1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (C) 2021, Intel Corporation. */
3
4#ifndef _ICE_PTP_HW_H_
5#define _ICE_PTP_HW_H_
6#include <linux/dpll.h>
7
8enum ice_ptp_tmr_cmd {
9 ICE_PTP_INIT_TIME,
10 ICE_PTP_INIT_INCVAL,
11 ICE_PTP_ADJ_TIME,
12 ICE_PTP_ADJ_TIME_AT_TIME,
13 ICE_PTP_READ_TIME,
14 ICE_PTP_NOP,
15};
16
17enum ice_ptp_serdes {
18 ICE_PTP_SERDES_1G,
19 ICE_PTP_SERDES_10G,
20 ICE_PTP_SERDES_25G,
21 ICE_PTP_SERDES_40G,
22 ICE_PTP_SERDES_50G,
23 ICE_PTP_SERDES_100G
24};
25
26enum ice_ptp_link_spd {
27 ICE_PTP_LNK_SPD_1G,
28 ICE_PTP_LNK_SPD_10G,
29 ICE_PTP_LNK_SPD_25G,
30 ICE_PTP_LNK_SPD_25G_RS,
31 ICE_PTP_LNK_SPD_40G,
32 ICE_PTP_LNK_SPD_50G,
33 ICE_PTP_LNK_SPD_50G_RS,
34 ICE_PTP_LNK_SPD_100G_RS,
35 NUM_ICE_PTP_LNK_SPD /* Must be last */
36};
37
38enum ice_ptp_fec_mode {
39 ICE_PTP_FEC_MODE_NONE,
40 ICE_PTP_FEC_MODE_CLAUSE74,
41 ICE_PTP_FEC_MODE_RS_FEC
42};
43
44/**
45 * struct ice_time_ref_info_e822
46 * @pll_freq: Frequency of PLL that drives timer ticks in Hz
47 * @nominal_incval: increment to generate nanoseconds in GLTSYN_TIME_L
48 * @pps_delay: propagation delay of the PPS output signal
49 *
50 * Characteristic information for the various TIME_REF sources possible in the
51 * E822 devices
52 */
53struct ice_time_ref_info_e822 {
54 u64 pll_freq;
55 u64 nominal_incval;
56 u8 pps_delay;
57};
58
59/**
60 * struct ice_vernier_info_e822
61 * @tx_par_clk: Frequency used to calculate P_REG_PAR_TX_TUS
62 * @rx_par_clk: Frequency used to calculate P_REG_PAR_RX_TUS
63 * @tx_pcs_clk: Frequency used to calculate P_REG_PCS_TX_TUS
64 * @rx_pcs_clk: Frequency used to calculate P_REG_PCS_RX_TUS
65 * @tx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_TX_TUS
66 * @rx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_RX_TUS
67 * @tx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_TX_TUS
68 * @rx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_RX_TUS
69 * @tx_fixed_delay: Fixed Tx latency measured in 1/100th nanoseconds
70 * @pmd_adj_divisor: Divisor used to calculate PDM alignment adjustment
71 * @rx_fixed_delay: Fixed Rx latency measured in 1/100th nanoseconds
72 *
73 * Table of constants used during as part of the Vernier calibration of the Tx
74 * and Rx timestamps. This includes frequency values used to compute TUs per
75 * PAR/PCS clock cycle, and static delay values measured during hardware
76 * design.
77 *
78 * Note that some values are not used for all link speeds, and the
79 * P_REG_DESK_PAR* registers may represent different clock markers at
80 * different link speeds, either the deskew marker for multi-lane link speeds
81 * or the Reed Solomon gearbox marker for RS-FEC.
82 */
83struct ice_vernier_info_e822 {
84 u32 tx_par_clk;
85 u32 rx_par_clk;
86 u32 tx_pcs_clk;
87 u32 rx_pcs_clk;
88 u32 tx_desk_rsgb_par;
89 u32 rx_desk_rsgb_par;
90 u32 tx_desk_rsgb_pcs;
91 u32 rx_desk_rsgb_pcs;
92 u32 tx_fixed_delay;
93 u32 pmd_adj_divisor;
94 u32 rx_fixed_delay;
95};
96
97/**
98 * struct ice_cgu_pll_params_e822
99 * @refclk_pre_div: Reference clock pre-divisor
100 * @feedback_div: Feedback divisor
101 * @frac_n_div: Fractional divisor
102 * @post_pll_div: Post PLL divisor
103 *
104 * Clock Generation Unit parameters used to program the PLL based on the
105 * selected TIME_REF frequency.
106 */
107struct ice_cgu_pll_params_e822 {
108 u32 refclk_pre_div;
109 u32 feedback_div;
110 u32 frac_n_div;
111 u32 post_pll_div;
112};
113
114#define E810C_QSFP_C827_0_HANDLE 2
115#define E810C_QSFP_C827_1_HANDLE 3
116enum ice_e810_c827_idx {
117 C827_0,
118 C827_1
119};
120
121enum ice_phy_rclk_pins {
122 ICE_RCLKA_PIN = 0, /* SCL pin */
123 ICE_RCLKB_PIN, /* SDA pin */
124};
125
126#define ICE_E810_RCLK_PINS_NUM (ICE_RCLKB_PIN + 1)
127#define ICE_E822_RCLK_PINS_NUM (ICE_RCLKA_PIN + 1)
128#define E810T_CGU_INPUT_C827(_phy, _pin) ((_phy) * ICE_E810_RCLK_PINS_NUM + \
129 (_pin) + ZL_REF1P)
130
131enum ice_zl_cgu_in_pins {
132 ZL_REF0P = 0,
133 ZL_REF0N,
134 ZL_REF1P,
135 ZL_REF1N,
136 ZL_REF2P,
137 ZL_REF2N,
138 ZL_REF3P,
139 ZL_REF3N,
140 ZL_REF4P,
141 ZL_REF4N,
142 NUM_ZL_CGU_INPUT_PINS
143};
144
145enum ice_zl_cgu_out_pins {
146 ZL_OUT0 = 0,
147 ZL_OUT1,
148 ZL_OUT2,
149 ZL_OUT3,
150 ZL_OUT4,
151 ZL_OUT5,
152 ZL_OUT6,
153 NUM_ZL_CGU_OUTPUT_PINS
154};
155
156enum ice_si_cgu_in_pins {
157 SI_REF0P = 0,
158 SI_REF0N,
159 SI_REF1P,
160 SI_REF1N,
161 SI_REF2P,
162 SI_REF2N,
163 SI_REF3,
164 SI_REF4,
165 NUM_SI_CGU_INPUT_PINS
166};
167
168enum ice_si_cgu_out_pins {
169 SI_OUT0 = 0,
170 SI_OUT1,
171 SI_OUT2,
172 SI_OUT3,
173 SI_OUT4,
174 NUM_SI_CGU_OUTPUT_PINS
175};
176
177struct ice_cgu_pin_desc {
178 char *name;
179 u8 index;
180 enum dpll_pin_type type;
181 u32 freq_supp_num;
182 struct dpll_pin_frequency *freq_supp;
183};
184
185extern const struct
186ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ];
187
188#define E810C_QSFP_C827_0_HANDLE 2
189#define E810C_QSFP_C827_1_HANDLE 3
190
191/* Table of constants related to possible TIME_REF sources */
192extern const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ];
193
194/* Table of constants for Vernier calibration on E822 */
195extern const struct ice_vernier_info_e822 e822_vernier[NUM_ICE_PTP_LNK_SPD];
196
197/* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for
198 * the E810 devices. Based off of a PLL with an 812.5 MHz frequency.
199 */
200#define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
201
202/* Device agnostic functions */
203u8 ice_get_ptp_src_clock_index(struct ice_hw *hw);
204bool ice_ptp_lock(struct ice_hw *hw);
205void ice_ptp_unlock(struct ice_hw *hw);
206void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd);
207int ice_ptp_init_time(struct ice_hw *hw, u64 time);
208int ice_ptp_write_incval(struct ice_hw *hw, u64 incval);
209int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval);
210int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj);
211int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);
212int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);
213void ice_ptp_reset_ts_memory(struct ice_hw *hw);
214int ice_ptp_init_phc(struct ice_hw *hw);
215int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready);
216
217/* E822 family functions */
218int ice_read_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 *val);
219int ice_write_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 val);
220void ice_ptp_reset_ts_memory_quad_e822(struct ice_hw *hw, u8 quad);
221
222/**
223 * ice_e822_time_ref - Get the current TIME_REF from capabilities
224 * @hw: pointer to the HW structure
225 *
226 * Returns the current TIME_REF from the capabilities structure.
227 */
228static inline enum ice_time_ref_freq ice_e822_time_ref(struct ice_hw *hw)
229{
230 return hw->func_caps.ts_func_info.time_ref;
231}
232
233/**
234 * ice_set_e822_time_ref - Set new TIME_REF
235 * @hw: pointer to the HW structure
236 * @time_ref: new TIME_REF to set
237 *
238 * Update the TIME_REF in the capabilities structure in response to some
239 * change, such as an update to the CGU registers.
240 */
241static inline void
242ice_set_e822_time_ref(struct ice_hw *hw, enum ice_time_ref_freq time_ref)
243{
244 hw->func_caps.ts_func_info.time_ref = time_ref;
245}
246
247static inline u64 ice_e822_pll_freq(enum ice_time_ref_freq time_ref)
248{
249 return e822_time_ref[time_ref].pll_freq;
250}
251
252static inline u64 ice_e822_nominal_incval(enum ice_time_ref_freq time_ref)
253{
254 return e822_time_ref[time_ref].nominal_incval;
255}
256
257static inline u64 ice_e822_pps_delay(enum ice_time_ref_freq time_ref)
258{
259 return e822_time_ref[time_ref].pps_delay;
260}
261
262/* E822 Vernier calibration functions */
263int ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset);
264int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port);
265int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port);
266int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port);
267
268/* E810 family functions */
269int ice_ptp_init_phy_e810(struct ice_hw *hw);
270int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);
271int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data);
272int ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data);
273bool ice_is_pca9575_present(struct ice_hw *hw);
274enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input);
275struct dpll_pin_frequency *
276ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num);
277const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input);
278int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx,
279 enum dpll_lock_status last_dpll_state, u8 *pin,
280 u8 *ref_state, u8 *eec_mode, s64 *phase_offset,
281 enum dpll_lock_status *dpll_state);
282int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num);
283
284void ice_ptp_init_phy_model(struct ice_hw *hw);
285
286#define PFTSYN_SEM_BYTES 4
287
288#define ICE_PTP_CLOCK_INDEX_0 0x00
289#define ICE_PTP_CLOCK_INDEX_1 0x01
290
291/* PHY timer commands */
292#define SEL_CPK_SRC 8
293#define SEL_PHY_SRC 3
294
295/* Time Sync command Definitions */
296#define GLTSYN_CMD_INIT_TIME BIT(0)
297#define GLTSYN_CMD_INIT_INCVAL BIT(1)
298#define GLTSYN_CMD_INIT_TIME_INCVAL (BIT(0) | BIT(1))
299#define GLTSYN_CMD_ADJ_TIME BIT(2)
300#define GLTSYN_CMD_ADJ_INIT_TIME (BIT(2) | BIT(3))
301#define GLTSYN_CMD_READ_TIME BIT(7)
302
303/* PHY port Time Sync command definitions */
304#define PHY_CMD_INIT_TIME BIT(0)
305#define PHY_CMD_INIT_INCVAL BIT(1)
306#define PHY_CMD_ADJ_TIME (BIT(0) | BIT(1))
307#define PHY_CMD_ADJ_TIME_AT_TIME (BIT(0) | BIT(2))
308#define PHY_CMD_READ_TIME (BIT(0) | BIT(1) | BIT(2))
309
310#define TS_CMD_MASK_E810 0xFF
311#define TS_CMD_MASK 0xF
312#define SYNC_EXEC_CMD 0x3
313
314/* Macros to derive port low and high addresses on both quads */
315#define P_Q0_L(a, p) ((((a) + (0x2000 * (p)))) & 0xFFFF)
316#define P_Q0_H(a, p) ((((a) + (0x2000 * (p)))) >> 16)
317#define P_Q1_L(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) & 0xFFFF)
318#define P_Q1_H(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) >> 16)
319
320/* PHY QUAD register base addresses */
321#define Q_0_BASE 0x94000
322#define Q_1_BASE 0x114000
323
324/* Timestamp memory reset registers */
325#define Q_REG_TS_CTRL 0x618
326#define Q_REG_TS_CTRL_S 0
327#define Q_REG_TS_CTRL_M BIT(0)
328
329/* Timestamp availability status registers */
330#define Q_REG_TX_MEMORY_STATUS_L 0xCF0
331#define Q_REG_TX_MEMORY_STATUS_U 0xCF4
332
333/* Tx FIFO status registers */
334#define Q_REG_FIFO23_STATUS 0xCF8
335#define Q_REG_FIFO01_STATUS 0xCFC
336#define Q_REG_FIFO02_S 0
337#define Q_REG_FIFO02_M ICE_M(0x3FF, 0)
338#define Q_REG_FIFO13_S 10
339#define Q_REG_FIFO13_M ICE_M(0x3FF, 10)
340
341/* Interrupt control Config registers */
342#define Q_REG_TX_MEM_GBL_CFG 0xC08
343#define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S 0
344#define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M BIT(0)
345#define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_S 1
346#define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M ICE_M(0xFF, 1)
347#define Q_REG_TX_MEM_GBL_CFG_INTR_THR_S 9
348#define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M ICE_M(0x3F, 9)
349#define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_S 15
350#define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M BIT(15)
351
352/* Tx Timestamp data registers */
353#define Q_REG_TX_MEMORY_BANK_START 0xA00
354
355/* PHY port register base addresses */
356#define P_0_BASE 0x80000
357#define P_4_BASE 0x106000
358
359/* Timestamp init registers */
360#define P_REG_RX_TIMER_INC_PRE_L 0x46C
361#define P_REG_RX_TIMER_INC_PRE_U 0x470
362#define P_REG_TX_TIMER_INC_PRE_L 0x44C
363#define P_REG_TX_TIMER_INC_PRE_U 0x450
364
365/* Timestamp match and adjust target registers */
366#define P_REG_RX_TIMER_CNT_ADJ_L 0x474
367#define P_REG_RX_TIMER_CNT_ADJ_U 0x478
368#define P_REG_TX_TIMER_CNT_ADJ_L 0x454
369#define P_REG_TX_TIMER_CNT_ADJ_U 0x458
370
371/* Timestamp capture registers */
372#define P_REG_RX_CAPTURE_L 0x4D8
373#define P_REG_RX_CAPTURE_U 0x4DC
374#define P_REG_TX_CAPTURE_L 0x4B4
375#define P_REG_TX_CAPTURE_U 0x4B8
376
377/* Timestamp PHY incval registers */
378#define P_REG_TIMETUS_L 0x410
379#define P_REG_TIMETUS_U 0x414
380
381#define P_REG_40B_LOW_M 0xFF
382#define P_REG_40B_HIGH_S 8
383
384/* PHY window length registers */
385#define P_REG_WL 0x40C
386
387#define PTP_VERNIER_WL 0x111ed
388
389/* PHY start registers */
390#define P_REG_PS 0x408
391#define P_REG_PS_START_S 0
392#define P_REG_PS_START_M BIT(0)
393#define P_REG_PS_BYPASS_MODE_S 1
394#define P_REG_PS_BYPASS_MODE_M BIT(1)
395#define P_REG_PS_ENA_CLK_S 2
396#define P_REG_PS_ENA_CLK_M BIT(2)
397#define P_REG_PS_LOAD_OFFSET_S 3
398#define P_REG_PS_LOAD_OFFSET_M BIT(3)
399#define P_REG_PS_SFT_RESET_S 11
400#define P_REG_PS_SFT_RESET_M BIT(11)
401
402/* PHY offset valid registers */
403#define P_REG_TX_OV_STATUS 0x4D4
404#define P_REG_TX_OV_STATUS_OV_S 0
405#define P_REG_TX_OV_STATUS_OV_M BIT(0)
406#define P_REG_RX_OV_STATUS 0x4F8
407#define P_REG_RX_OV_STATUS_OV_S 0
408#define P_REG_RX_OV_STATUS_OV_M BIT(0)
409
410/* PHY offset ready registers */
411#define P_REG_TX_OR 0x45C
412#define P_REG_RX_OR 0x47C
413
414/* PHY total offset registers */
415#define P_REG_TOTAL_RX_OFFSET_L 0x460
416#define P_REG_TOTAL_RX_OFFSET_U 0x464
417#define P_REG_TOTAL_TX_OFFSET_L 0x440
418#define P_REG_TOTAL_TX_OFFSET_U 0x444
419
420/* Timestamp PAR/PCS registers */
421#define P_REG_UIX66_10G_40G_L 0x480
422#define P_REG_UIX66_10G_40G_U 0x484
423#define P_REG_UIX66_25G_100G_L 0x488
424#define P_REG_UIX66_25G_100G_U 0x48C
425#define P_REG_DESK_PAR_RX_TUS_L 0x490
426#define P_REG_DESK_PAR_RX_TUS_U 0x494
427#define P_REG_DESK_PAR_TX_TUS_L 0x498
428#define P_REG_DESK_PAR_TX_TUS_U 0x49C
429#define P_REG_DESK_PCS_RX_TUS_L 0x4A0
430#define P_REG_DESK_PCS_RX_TUS_U 0x4A4
431#define P_REG_DESK_PCS_TX_TUS_L 0x4A8
432#define P_REG_DESK_PCS_TX_TUS_U 0x4AC
433#define P_REG_PAR_RX_TUS_L 0x420
434#define P_REG_PAR_RX_TUS_U 0x424
435#define P_REG_PAR_TX_TUS_L 0x428
436#define P_REG_PAR_TX_TUS_U 0x42C
437#define P_REG_PCS_RX_TUS_L 0x430
438#define P_REG_PCS_RX_TUS_U 0x434
439#define P_REG_PCS_TX_TUS_L 0x438
440#define P_REG_PCS_TX_TUS_U 0x43C
441#define P_REG_PAR_RX_TIME_L 0x4F0
442#define P_REG_PAR_RX_TIME_U 0x4F4
443#define P_REG_PAR_TX_TIME_L 0x4CC
444#define P_REG_PAR_TX_TIME_U 0x4D0
445#define P_REG_PAR_PCS_RX_OFFSET_L 0x4E8
446#define P_REG_PAR_PCS_RX_OFFSET_U 0x4EC
447#define P_REG_PAR_PCS_TX_OFFSET_L 0x4C4
448#define P_REG_PAR_PCS_TX_OFFSET_U 0x4C8
449#define P_REG_LINK_SPEED 0x4FC
450#define P_REG_LINK_SPEED_SERDES_S 0
451#define P_REG_LINK_SPEED_SERDES_M ICE_M(0x7, 0)
452#define P_REG_LINK_SPEED_FEC_MODE_S 3
453#define P_REG_LINK_SPEED_FEC_MODE_M ICE_M(0x3, 3)
454#define P_REG_LINK_SPEED_FEC_MODE(reg) \
455 (((reg) & P_REG_LINK_SPEED_FEC_MODE_M) >> \
456 P_REG_LINK_SPEED_FEC_MODE_S)
457
458/* PHY timestamp related registers */
459#define P_REG_PMD_ALIGNMENT 0x0FC
460#define P_REG_RX_80_TO_160_CNT 0x6FC
461#define P_REG_RX_80_TO_160_CNT_RXCYC_S 0
462#define P_REG_RX_80_TO_160_CNT_RXCYC_M BIT(0)
463#define P_REG_RX_40_TO_160_CNT 0x8FC
464#define P_REG_RX_40_TO_160_CNT_RXCYC_S 0
465#define P_REG_RX_40_TO_160_CNT_RXCYC_M ICE_M(0x3, 0)
466
467/* Rx FIFO status registers */
468#define P_REG_RX_OV_FS 0x4F8
469#define P_REG_RX_OV_FS_FIFO_STATUS_S 2
470#define P_REG_RX_OV_FS_FIFO_STATUS_M ICE_M(0x3FF, 2)
471
472/* Timestamp command registers */
473#define P_REG_TX_TMR_CMD 0x448
474#define P_REG_RX_TMR_CMD 0x468
475
476/* E810 timesync enable register */
477#define ETH_GLTSYN_ENA(_i) (0x03000348 + ((_i) * 4))
478
479/* E810 shadow init time registers */
480#define ETH_GLTSYN_SHTIME_0(i) (0x03000368 + ((i) * 32))
481#define ETH_GLTSYN_SHTIME_L(i) (0x0300036C + ((i) * 32))
482
483/* E810 shadow time adjust registers */
484#define ETH_GLTSYN_SHADJ_L(_i) (0x03000378 + ((_i) * 32))
485#define ETH_GLTSYN_SHADJ_H(_i) (0x0300037C + ((_i) * 32))
486
487/* E810 timer command register */
488#define ETH_GLTSYN_CMD 0x03000344
489
490/* Source timer incval macros */
491#define INCVAL_HIGH_M 0xFF
492
493/* Timestamp block macros */
494#define TS_VALID BIT(0)
495#define TS_LOW_M 0xFFFFFFFF
496#define TS_HIGH_M 0xFF
497#define TS_HIGH_S 32
498
499#define TS_PHY_LOW_M 0xFF
500#define TS_PHY_HIGH_M 0xFFFFFFFF
501#define TS_PHY_HIGH_S 8
502
503#define BYTES_PER_IDX_ADDR_L_U 8
504#define BYTES_PER_IDX_ADDR_L 4
505
506/* Tx timestamp low latency read definitions */
507#define TS_LL_READ_RETRIES 200
508#define TS_LL_READ_TS_HIGH GENMASK(23, 16)
509#define TS_LL_READ_TS_IDX GENMASK(29, 24)
510#define TS_LL_READ_TS BIT(31)
511
512/* Internal PHY timestamp address */
513#define TS_L(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U))
514#define TS_H(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U + \
515 BYTES_PER_IDX_ADDR_L))
516
517/* External PHY timestamp address */
518#define TS_EXT(a, port, idx) ((a) + (0x1000 * (port)) + \
519 ((idx) * BYTES_PER_IDX_ADDR_L_U))
520
521#define LOW_TX_MEMORY_BANK_START 0x03090000
522#define HIGH_TX_MEMORY_BANK_START 0x03090004
523
524/* E810T SMA controller pin control */
525#define ICE_SMA1_DIR_EN_E810T BIT(4)
526#define ICE_SMA1_TX_EN_E810T BIT(5)
527#define ICE_SMA2_UFL2_RX_DIS_E810T BIT(3)
528#define ICE_SMA2_DIR_EN_E810T BIT(6)
529#define ICE_SMA2_TX_EN_E810T BIT(7)
530
531#define ICE_SMA1_MASK_E810T (ICE_SMA1_DIR_EN_E810T | \
532 ICE_SMA1_TX_EN_E810T)
533#define ICE_SMA2_MASK_E810T (ICE_SMA2_UFL2_RX_DIS_E810T | \
534 ICE_SMA2_DIR_EN_E810T | \
535 ICE_SMA2_TX_EN_E810T)
536#define ICE_ALL_SMA_MASK_E810T (ICE_SMA1_MASK_E810T | \
537 ICE_SMA2_MASK_E810T)
538
539#define ICE_SMA_MIN_BIT_E810T 3
540#define ICE_SMA_MAX_BIT_E810T 7
541#define ICE_PCA9575_P1_OFFSET 8
542
543/* E810T PCA9575 IO controller registers */
544#define ICE_PCA9575_P0_IN 0x0
545
546/* E810T PCA9575 IO controller pin control */
547#define ICE_E810T_P0_GNSS_PRSNT_N BIT(4)
548
549#endif /* _ICE_PTP_HW_H_ */
550

source code of linux/drivers/net/ethernet/intel/ice/ice_ptp_hw.h