| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* Copyright (c) 2020 Intel Corporation */ |
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| 3 | |
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| 4 | bool igc_reg_test(struct igc_adapter *adapter, u64 *data); |
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| 5 | bool igc_eeprom_test(struct igc_adapter *adapter, u64 *data); |
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| 6 | bool igc_link_test(struct igc_adapter *adapter, u64 *data); |
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| 7 | |
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| 8 | struct igc_reg_test { |
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| 9 | u16 reg; |
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| 10 | u8 array_len; |
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| 11 | u8 test_type; |
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| 12 | u32 mask; |
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| 13 | u32 write; |
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| 14 | }; |
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| 15 | |
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| 16 | /* In the hardware, registers are laid out either singly, in arrays |
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| 17 | * spaced 0x40 bytes apart, or in contiguous tables. We assume |
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| 18 | * most tests take place on arrays or single registers (handled |
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| 19 | * as a single-element array) and special-case the tables. |
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| 20 | * Table tests are always pattern tests. |
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| 21 | * |
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| 22 | * We also make provision for some required setup steps by specifying |
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| 23 | * registers to be written without any read-back testing. |
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| 24 | */ |
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| 25 | |
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| 26 | #define PATTERN_TEST 1 |
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| 27 | #define SET_READ_TEST 2 |
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| 28 | #define TABLE32_TEST 3 |
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| 29 | #define TABLE64_TEST_LO 4 |
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| 30 | #define TABLE64_TEST_HI 5 |
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| 31 | |
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