1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018 Intel Corporation */
3
4#ifndef _IGC_H_
5#define _IGC_H_
6
7#include <linux/kobject.h>
8#include <linux/pci.h>
9#include <linux/netdevice.h>
10#include <linux/vmalloc.h>
11#include <linux/ethtool.h>
12#include <linux/sctp.h>
13#include <linux/ptp_clock_kernel.h>
14#include <linux/timecounter.h>
15#include <linux/net_tstamp.h>
16#include <linux/bitfield.h>
17#include <linux/hrtimer.h>
18#include <net/xdp.h>
19
20#include "igc_hw.h"
21
22void igc_ethtool_set_ops(struct net_device *);
23
24/* Transmit and receive queues */
25#define IGC_MAX_RX_QUEUES 4
26#define IGC_MAX_TX_QUEUES 4
27
28#define MAX_Q_VECTORS 8
29#define MAX_STD_JUMBO_FRAME_SIZE 9216
30
31#define MAX_ETYPE_FILTER 8
32#define IGC_RETA_SIZE 128
33
34/* SDP support */
35#define IGC_N_EXTTS 2
36#define IGC_N_PEROUT 2
37#define IGC_N_SDP 4
38
39#define MAX_FLEX_FILTER 32
40
41#define IGC_MAX_TX_TSTAMP_REGS 4
42
43enum igc_mac_filter_type {
44 IGC_MAC_FILTER_TYPE_DST = 0,
45 IGC_MAC_FILTER_TYPE_SRC
46};
47
48struct igc_tx_queue_stats {
49 u64 packets;
50 u64 bytes;
51 u64 restart_queue;
52 u64 restart_queue2;
53};
54
55struct igc_rx_queue_stats {
56 u64 packets;
57 u64 bytes;
58 u64 drops;
59 u64 csum_err;
60 u64 alloc_failed;
61};
62
63struct igc_rx_packet_stats {
64 u64 ipv4_packets; /* IPv4 headers processed */
65 u64 ipv4e_packets; /* IPv4E headers with extensions processed */
66 u64 ipv6_packets; /* IPv6 headers processed */
67 u64 ipv6e_packets; /* IPv6E headers with extensions processed */
68 u64 tcp_packets; /* TCP headers processed */
69 u64 udp_packets; /* UDP headers processed */
70 u64 sctp_packets; /* SCTP headers processed */
71 u64 nfs_packets; /* NFS headers processe */
72 u64 other_packets;
73};
74
75struct igc_tx_timestamp_request {
76 struct sk_buff *skb; /* reference to the packet being timestamped */
77 unsigned long start; /* when the tstamp request started (jiffies) */
78 u32 mask; /* _TSYNCTXCTL_TXTT_{X} bit for this request */
79 u32 regl; /* which TXSTMPL_{X} register should be used */
80 u32 regh; /* which TXSTMPH_{X} register should be used */
81 u32 flags; /* flags that should be added to the tx_buffer */
82};
83
84struct igc_inline_rx_tstamps {
85 /* Timestamps are saved in little endian at the beginning of the packet
86 * buffer following the layout:
87 *
88 * DWORD: | 0 | 1 | 2 | 3 |
89 * Field: | Timer1 SYSTIML | Timer1 SYSTIMH | Timer0 SYSTIML | Timer0 SYSTIMH |
90 *
91 * SYSTIML holds the nanoseconds part while SYSTIMH holds the seconds
92 * part of the timestamp.
93 *
94 */
95 __le32 timer1[2];
96 __le32 timer0[2];
97};
98
99struct igc_ring_container {
100 struct igc_ring *ring; /* pointer to linked list of rings */
101 unsigned int total_bytes; /* total bytes processed this int */
102 unsigned int total_packets; /* total packets processed this int */
103 u16 work_limit; /* total work allowed per interrupt */
104 u8 count; /* total number of rings in vector */
105 u8 itr; /* current ITR setting for ring */
106};
107
108struct igc_ring {
109 struct igc_q_vector *q_vector; /* backlink to q_vector */
110 struct net_device *netdev; /* back pointer to net_device */
111 struct device *dev; /* device for dma mapping */
112 union { /* array of buffer info structs */
113 struct igc_tx_buffer *tx_buffer_info;
114 struct igc_rx_buffer *rx_buffer_info;
115 };
116 void *desc; /* descriptor ring memory */
117 unsigned long flags; /* ring specific flags */
118 void __iomem *tail; /* pointer to ring tail register */
119 dma_addr_t dma; /* phys address of the ring */
120 unsigned int size; /* length of desc. ring in bytes */
121
122 u16 count; /* number of desc. in the ring */
123 u8 queue_index; /* logical index of the ring*/
124 u8 reg_idx; /* physical index of the ring */
125 bool launchtime_enable; /* true if LaunchTime is enabled */
126 ktime_t last_tx_cycle; /* end of the cycle with a launchtime transmission */
127 ktime_t last_ff_cycle; /* Last cycle with an active first flag */
128
129 u32 start_time;
130 u32 end_time;
131 u32 max_sdu;
132 bool oper_gate_closed; /* Operating gate. True if the TX Queue is closed */
133 bool admin_gate_closed; /* Future gate. True if the TX Queue will be closed */
134
135 /* CBS parameters */
136 bool cbs_enable; /* indicates if CBS is enabled */
137 s32 idleslope; /* idleSlope in kbps */
138 s32 sendslope; /* sendSlope in kbps */
139 s32 hicredit; /* hiCredit in bytes */
140 s32 locredit; /* loCredit in bytes */
141
142 /* everything past this point are written often */
143 u16 next_to_clean;
144 u16 next_to_use;
145 u16 next_to_alloc;
146
147 union {
148 /* TX */
149 struct {
150 struct igc_tx_queue_stats tx_stats;
151 struct u64_stats_sync tx_syncp;
152 struct u64_stats_sync tx_syncp2;
153 };
154 /* RX */
155 struct {
156 struct igc_rx_queue_stats rx_stats;
157 struct igc_rx_packet_stats pkt_stats;
158 struct u64_stats_sync rx_syncp;
159 struct sk_buff *skb;
160 };
161 };
162
163 struct xdp_rxq_info xdp_rxq;
164 struct xsk_buff_pool *xsk_pool;
165} ____cacheline_internodealigned_in_smp;
166
167/* Board specific private data structure */
168struct igc_adapter {
169 struct net_device *netdev;
170
171 struct ethtool_keee eee;
172 u16 eee_advert;
173
174 unsigned long state;
175 unsigned int flags;
176 unsigned int num_q_vectors;
177
178 struct msix_entry *msix_entries;
179
180 /* TX */
181 u16 tx_work_limit;
182 u32 tx_timeout_count;
183 int num_tx_queues;
184 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];
185
186 /* RX */
187 int num_rx_queues;
188 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES];
189
190 struct timer_list watchdog_timer;
191 struct timer_list dma_err_timer;
192 struct timer_list phy_info_timer;
193 struct hrtimer hrtimer;
194
195 u32 wol;
196 u32 en_mng_pt;
197 u16 link_speed;
198 u16 link_duplex;
199
200 u8 port_num;
201
202 u8 __iomem *io_addr;
203 /* Interrupt Throttle Rate */
204 u32 rx_itr_setting;
205 u32 tx_itr_setting;
206
207 struct work_struct reset_task;
208 struct work_struct watchdog_task;
209 struct work_struct dma_err_task;
210 bool fc_autoneg;
211
212 u8 tx_timeout_factor;
213
214 int msg_enable;
215 u32 max_frame_size;
216 u32 min_frame_size;
217
218 int tc_setup_type;
219 ktime_t base_time;
220 ktime_t cycle_time;
221 bool taprio_offload_enable;
222 u32 qbv_config_change_errors;
223 bool qbv_transition;
224 unsigned int qbv_count;
225 /* Access to oper_gate_closed, admin_gate_closed and qbv_transition
226 * are protected by the qbv_tx_lock.
227 */
228 spinlock_t qbv_tx_lock;
229
230 /* OS defined structs */
231 struct pci_dev *pdev;
232 /* lock for statistics */
233 spinlock_t stats64_lock;
234 struct rtnl_link_stats64 stats64;
235
236 /* structs defined in igc_hw.h */
237 struct igc_hw hw;
238 struct igc_hw_stats stats;
239
240 struct igc_q_vector *q_vector[MAX_Q_VECTORS];
241 u32 eims_enable_mask;
242 u32 eims_other;
243
244 u16 tx_ring_count;
245 u16 rx_ring_count;
246
247 u32 tx_hwtstamp_timeouts;
248 u32 tx_hwtstamp_skipped;
249 u32 rx_hwtstamp_cleared;
250
251 u32 rss_queues;
252 u32 rss_indir_tbl_init;
253
254 /* Any access to elements in nfc_rule_list is protected by the
255 * nfc_rule_lock.
256 */
257 struct mutex nfc_rule_lock;
258 struct list_head nfc_rule_list;
259 unsigned int nfc_rule_count;
260
261 u8 rss_indir_tbl[IGC_RETA_SIZE];
262
263 unsigned long link_check_timeout;
264 struct igc_info ei;
265
266 u32 test_icr;
267
268 struct ptp_clock *ptp_clock;
269 struct ptp_clock_info ptp_caps;
270 /* Access to ptp_tx_skb and ptp_tx_start are protected by the
271 * ptp_tx_lock.
272 */
273 spinlock_t ptp_tx_lock;
274 struct igc_tx_timestamp_request tx_tstamp[IGC_MAX_TX_TSTAMP_REGS];
275 struct hwtstamp_config tstamp_config;
276 unsigned int ptp_flags;
277 /* System time value lock */
278 spinlock_t tmreg_lock;
279 /* Free-running timer lock */
280 spinlock_t free_timer_lock;
281 struct cyclecounter cc;
282 struct timecounter tc;
283 struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */
284 ktime_t ptp_reset_start; /* Reset time in clock mono */
285 struct system_time_snapshot snapshot;
286
287 char fw_version[32];
288
289 struct bpf_prog *xdp_prog;
290
291 bool pps_sys_wrap_on;
292
293 struct ptp_pin_desc sdp_config[IGC_N_SDP];
294 struct {
295 struct timespec64 start;
296 struct timespec64 period;
297 } perout[IGC_N_PEROUT];
298
299 /* LEDs */
300 struct mutex led_mutex;
301};
302
303void igc_up(struct igc_adapter *adapter);
304void igc_down(struct igc_adapter *adapter);
305int igc_open(struct net_device *netdev);
306int igc_close(struct net_device *netdev);
307int igc_setup_tx_resources(struct igc_ring *ring);
308int igc_setup_rx_resources(struct igc_ring *ring);
309void igc_free_tx_resources(struct igc_ring *ring);
310void igc_free_rx_resources(struct igc_ring *ring);
311unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter);
312void igc_set_flag_queue_pairs(struct igc_adapter *adapter,
313 const u32 max_rss_queues);
314int igc_reinit_queues(struct igc_adapter *adapter);
315void igc_write_rss_indir_tbl(struct igc_adapter *adapter);
316bool igc_has_link(struct igc_adapter *adapter);
317void igc_reset(struct igc_adapter *adapter);
318void igc_update_stats(struct igc_adapter *adapter);
319void igc_disable_rx_ring(struct igc_ring *ring);
320void igc_enable_rx_ring(struct igc_ring *ring);
321void igc_disable_tx_ring(struct igc_ring *ring);
322void igc_enable_tx_ring(struct igc_ring *ring);
323int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags);
324
325/* igc_dump declarations */
326void igc_rings_dump(struct igc_adapter *adapter);
327void igc_regs_dump(struct igc_adapter *adapter);
328
329extern char igc_driver_name[];
330
331#define IGC_REGS_LEN 740
332
333/* flags controlling PTP/1588 function */
334#define IGC_PTP_ENABLED BIT(0)
335
336/* Flags definitions */
337#define IGC_FLAG_HAS_MSI BIT(0)
338#define IGC_FLAG_QUEUE_PAIRS BIT(3)
339#define IGC_FLAG_DMAC BIT(4)
340#define IGC_FLAG_PTP BIT(8)
341#define IGC_FLAG_WOL_SUPPORTED BIT(8)
342#define IGC_FLAG_NEED_LINK_UPDATE BIT(9)
343#define IGC_FLAG_HAS_MSIX BIT(13)
344#define IGC_FLAG_EEE BIT(14)
345#define IGC_FLAG_VLAN_PROMISC BIT(15)
346#define IGC_FLAG_RX_LEGACY BIT(16)
347#define IGC_FLAG_TSN_QBV_ENABLED BIT(17)
348#define IGC_FLAG_TSN_QAV_ENABLED BIT(18)
349
350#define IGC_FLAG_TSN_ANY_ENABLED \
351 (IGC_FLAG_TSN_QBV_ENABLED | IGC_FLAG_TSN_QAV_ENABLED)
352
353#define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
354#define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
355
356#define IGC_MRQC_ENABLE_RSS_MQ 0x00000002
357#define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
358#define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
359
360/* RX-desc Write-Back format RSS Type's */
361enum igc_rss_type_num {
362 IGC_RSS_TYPE_NO_HASH = 0,
363 IGC_RSS_TYPE_HASH_TCP_IPV4 = 1,
364 IGC_RSS_TYPE_HASH_IPV4 = 2,
365 IGC_RSS_TYPE_HASH_TCP_IPV6 = 3,
366 IGC_RSS_TYPE_HASH_IPV6_EX = 4,
367 IGC_RSS_TYPE_HASH_IPV6 = 5,
368 IGC_RSS_TYPE_HASH_TCP_IPV6_EX = 6,
369 IGC_RSS_TYPE_HASH_UDP_IPV4 = 7,
370 IGC_RSS_TYPE_HASH_UDP_IPV6 = 8,
371 IGC_RSS_TYPE_HASH_UDP_IPV6_EX = 9,
372 IGC_RSS_TYPE_MAX = 10,
373};
374#define IGC_RSS_TYPE_MAX_TABLE 16
375#define IGC_RSS_TYPE_MASK GENMASK(3,0) /* 4-bits (3:0) = mask 0x0F */
376
377/* igc_rss_type - Rx descriptor RSS type field */
378static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc)
379{
380 /* RSS Type 4-bits (3:0) number: 0-9 (above 9 is reserved)
381 * Accessing the same bits via u16 (wb.lower.lo_dword.hs_rss.pkt_info)
382 * is slightly slower than via u32 (wb.lower.lo_dword.data)
383 */
384 return le32_get_bits(v: rx_desc->wb.lower.lo_dword.data, IGC_RSS_TYPE_MASK);
385}
386
387/* Interrupt defines */
388#define IGC_START_ITR 648 /* ~6000 ints/sec */
389#define IGC_4K_ITR 980
390#define IGC_20K_ITR 196
391#define IGC_70K_ITR 56
392
393#define IGC_DEFAULT_ITR 3 /* dynamic */
394#define IGC_MAX_ITR_USECS 10000
395#define IGC_MIN_ITR_USECS 10
396#define NON_Q_VECTORS 1
397#define MAX_MSIX_ENTRIES 10
398
399/* TX/RX descriptor defines */
400#define IGC_DEFAULT_TXD 256
401#define IGC_DEFAULT_TX_WORK 128
402#define IGC_MIN_TXD 64
403#define IGC_MAX_TXD 4096
404
405#define IGC_DEFAULT_RXD 256
406#define IGC_MIN_RXD 64
407#define IGC_MAX_RXD 4096
408
409/* Supported Rx Buffer Sizes */
410#define IGC_RXBUFFER_256 256
411#define IGC_RXBUFFER_2048 2048
412#define IGC_RXBUFFER_3072 3072
413
414#define AUTO_ALL_MODES 0
415#define IGC_RX_HDR_LEN IGC_RXBUFFER_256
416
417/* Transmit and receive latency (for PTP timestamps) */
418#define IGC_I225_TX_LATENCY_10 240
419#define IGC_I225_TX_LATENCY_100 58
420#define IGC_I225_TX_LATENCY_1000 80
421#define IGC_I225_TX_LATENCY_2500 1325
422#define IGC_I225_RX_LATENCY_10 6450
423#define IGC_I225_RX_LATENCY_100 185
424#define IGC_I225_RX_LATENCY_1000 300
425#define IGC_I225_RX_LATENCY_2500 1485
426
427/* RX and TX descriptor control thresholds.
428 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
429 * descriptors available in its onboard memory.
430 * Setting this to 0 disables RX descriptor prefetch.
431 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
432 * available in host memory.
433 * If PTHRESH is 0, this should also be 0.
434 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
435 * descriptors until either it has this many to write back, or the
436 * ITR timer expires.
437 */
438#define IGC_RX_PTHRESH 8
439#define IGC_RX_HTHRESH 8
440#define IGC_TX_PTHRESH 8
441#define IGC_TX_HTHRESH 1
442#define IGC_RX_WTHRESH 4
443#define IGC_TX_WTHRESH 16
444
445#define IGC_RX_DMA_ATTR \
446 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
447
448#define IGC_TS_HDR_LEN 16
449
450#define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
451
452#if (PAGE_SIZE < 8192)
453#define IGC_MAX_FRAME_BUILD_SKB \
454 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN)
455#else
456#define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN)
457#endif
458
459/* How many Rx Buffers do we bundle into one write to the hardware ? */
460#define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */
461
462/* VLAN info */
463#define IGC_TX_FLAGS_VLAN_MASK 0xffff0000
464#define IGC_TX_FLAGS_VLAN_SHIFT 16
465
466/* igc_test_staterr - tests bits within Rx descriptor status and error fields */
467static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc,
468 const u32 stat_err_bits)
469{
470 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
471}
472
473enum igc_state_t {
474 __IGC_TESTING,
475 __IGC_RESETTING,
476 __IGC_DOWN,
477};
478
479enum igc_tx_flags {
480 /* cmd_type flags */
481 IGC_TX_FLAGS_VLAN = 0x01,
482 IGC_TX_FLAGS_TSO = 0x02,
483 IGC_TX_FLAGS_TSTAMP = 0x04,
484
485 /* olinfo flags */
486 IGC_TX_FLAGS_IPV4 = 0x10,
487 IGC_TX_FLAGS_CSUM = 0x20,
488
489 IGC_TX_FLAGS_TSTAMP_1 = 0x100,
490 IGC_TX_FLAGS_TSTAMP_2 = 0x200,
491 IGC_TX_FLAGS_TSTAMP_3 = 0x400,
492
493 IGC_TX_FLAGS_TSTAMP_TIMER_1 = 0x800,
494};
495
496enum igc_boards {
497 board_base,
498};
499
500/* The largest size we can write to the descriptor is 65535. In order to
501 * maintain a power of two alignment we have to limit ourselves to 32K.
502 */
503#define IGC_MAX_TXD_PWR 15
504#define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR)
505
506/* Tx Descriptors needed, worst case */
507#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD)
508#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
509
510enum igc_tx_buffer_type {
511 IGC_TX_BUFFER_TYPE_SKB,
512 IGC_TX_BUFFER_TYPE_XDP,
513 IGC_TX_BUFFER_TYPE_XSK,
514};
515
516/* wrapper around a pointer to a socket buffer,
517 * so a DMA handle can be stored along with the buffer
518 */
519struct igc_tx_buffer {
520 union igc_adv_tx_desc *next_to_watch;
521 unsigned long time_stamp;
522 enum igc_tx_buffer_type type;
523 union {
524 struct sk_buff *skb;
525 struct xdp_frame *xdpf;
526 };
527 unsigned int bytecount;
528 u16 gso_segs;
529 __be16 protocol;
530
531 DEFINE_DMA_UNMAP_ADDR(dma);
532 DEFINE_DMA_UNMAP_LEN(len);
533 u32 tx_flags;
534};
535
536struct igc_rx_buffer {
537 union {
538 struct {
539 dma_addr_t dma;
540 struct page *page;
541#if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
542 __u32 page_offset;
543#else
544 __u16 page_offset;
545#endif
546 __u16 pagecnt_bias;
547 };
548 struct xdp_buff *xdp;
549 };
550};
551
552/* context wrapper around xdp_buff to provide access to descriptor metadata */
553struct igc_xdp_buff {
554 struct xdp_buff xdp;
555 union igc_adv_rx_desc *rx_desc;
556 struct igc_inline_rx_tstamps *rx_ts; /* data indication bit IGC_RXDADV_STAT_TSIP */
557};
558
559struct igc_q_vector {
560 struct igc_adapter *adapter; /* backlink */
561 void __iomem *itr_register;
562 u32 eims_value; /* EIMS mask value */
563
564 u16 itr_val;
565 u8 set_itr;
566
567 struct igc_ring_container rx, tx;
568
569 struct napi_struct napi;
570
571 struct rcu_head rcu; /* to avoid race with update stats on free */
572 char name[IFNAMSIZ + 9];
573
574 /* for dynamic allocation of rings associated with this q_vector */
575 struct igc_ring ring[] ____cacheline_internodealigned_in_smp;
576};
577
578enum igc_filter_match_flags {
579 IGC_FILTER_FLAG_ETHER_TYPE = BIT(0),
580 IGC_FILTER_FLAG_VLAN_TCI = BIT(1),
581 IGC_FILTER_FLAG_SRC_MAC_ADDR = BIT(2),
582 IGC_FILTER_FLAG_DST_MAC_ADDR = BIT(3),
583 IGC_FILTER_FLAG_USER_DATA = BIT(4),
584 IGC_FILTER_FLAG_VLAN_ETYPE = BIT(5),
585};
586
587struct igc_nfc_filter {
588 u8 match_flags;
589 u16 etype;
590 u16 vlan_etype;
591 u16 vlan_tci;
592 u16 vlan_tci_mask;
593 u8 src_addr[ETH_ALEN];
594 u8 dst_addr[ETH_ALEN];
595 u8 user_data[8];
596 u8 user_mask[8];
597 u8 flex_index;
598 u8 rx_queue;
599 u8 prio;
600 u8 immediate_irq;
601 u8 drop;
602};
603
604struct igc_nfc_rule {
605 struct list_head list;
606 struct igc_nfc_filter filter;
607 u32 location;
608 u16 action;
609 bool flex;
610};
611
612/* IGC supports a total of 32 NFC rules: 16 MAC address based, 8 VLAN priority
613 * based, 8 ethertype based and 32 Flex filter based rules.
614 */
615#define IGC_MAX_RXNFC_RULES 64
616
617struct igc_flex_filter {
618 u8 index;
619 u8 data[128];
620 u8 mask[16];
621 u8 length;
622 u8 rx_queue;
623 u8 prio;
624 u8 immediate_irq;
625 u8 drop;
626};
627
628/* igc_desc_unused - calculate if we have unused descriptors */
629static inline u16 igc_desc_unused(const struct igc_ring *ring)
630{
631 u16 ntc = ring->next_to_clean;
632 u16 ntu = ring->next_to_use;
633
634 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
635}
636
637static inline s32 igc_get_phy_info(struct igc_hw *hw)
638{
639 if (hw->phy.ops.get_phy_info)
640 return hw->phy.ops.get_phy_info(hw);
641
642 return 0;
643}
644
645static inline s32 igc_reset_phy(struct igc_hw *hw)
646{
647 if (hw->phy.ops.reset)
648 return hw->phy.ops.reset(hw);
649
650 return 0;
651}
652
653static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring)
654{
655 return netdev_get_tx_queue(dev: tx_ring->netdev, index: tx_ring->queue_index);
656}
657
658enum igc_ring_flags_t {
659 IGC_RING_FLAG_RX_3K_BUFFER,
660 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED,
661 IGC_RING_FLAG_RX_SCTP_CSUM,
662 IGC_RING_FLAG_RX_LB_VLAN_BSWAP,
663 IGC_RING_FLAG_TX_CTX_IDX,
664 IGC_RING_FLAG_TX_DETECT_HANG,
665 IGC_RING_FLAG_AF_XDP_ZC,
666 IGC_RING_FLAG_TX_HWTSTAMP,
667};
668
669#define ring_uses_large_buffer(ring) \
670 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
671#define set_ring_uses_large_buffer(ring) \
672 set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
673#define clear_ring_uses_large_buffer(ring) \
674 clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
675
676#define ring_uses_build_skb(ring) \
677 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
678
679static inline unsigned int igc_rx_bufsz(struct igc_ring *ring)
680{
681#if (PAGE_SIZE < 8192)
682 if (ring_uses_large_buffer(ring))
683 return IGC_RXBUFFER_3072;
684
685 if (ring_uses_build_skb(ring))
686 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN;
687#endif
688 return IGC_RXBUFFER_2048;
689}
690
691static inline unsigned int igc_rx_pg_order(struct igc_ring *ring)
692{
693#if (PAGE_SIZE < 8192)
694 if (ring_uses_large_buffer(ring))
695 return 1;
696#endif
697 return 0;
698}
699
700static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data)
701{
702 if (hw->phy.ops.read_reg)
703 return hw->phy.ops.read_reg(hw, offset, data);
704
705 return -EOPNOTSUPP;
706}
707
708void igc_reinit_locked(struct igc_adapter *);
709struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter,
710 u32 location);
711int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
712void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
713
714void igc_ptp_init(struct igc_adapter *adapter);
715void igc_ptp_reset(struct igc_adapter *adapter);
716void igc_ptp_suspend(struct igc_adapter *adapter);
717void igc_ptp_stop(struct igc_adapter *adapter);
718ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf);
719int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
720int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
721void igc_ptp_tx_hang(struct igc_adapter *adapter);
722void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts);
723void igc_ptp_tx_tstamp_event(struct igc_adapter *adapter);
724
725int igc_led_setup(struct igc_adapter *adapter);
726
727#define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring))
728
729#define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS)
730
731#define IGC_RX_DESC(R, i) \
732 (&(((union igc_adv_rx_desc *)((R)->desc))[i]))
733#define IGC_TX_DESC(R, i) \
734 (&(((union igc_adv_tx_desc *)((R)->desc))[i]))
735#define IGC_TX_CTXTDESC(R, i) \
736 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i]))
737
738#endif /* _IGC_H_ */
739

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source code of linux/drivers/net/ethernet/intel/igc/igc.h