| 1 | // SPDX-License-Identifier: GPL-2.0-only |
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| 2 | /* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */ |
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| 3 | |
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| 4 | #ifndef __MTK_WED_REGS_H |
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| 5 | #define __MTK_WED_REGS_H |
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| 6 | |
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| 7 | #define MTK_WFDMA_DESC_CTRL_TO_HOST BIT(8) |
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| 8 | #define MTK_WDMA_DESC_CTRL_LEN1 GENMASK(14, 0) |
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| 9 | #define MTK_WDMA_DESC_CTRL_LEN1_V2 GENMASK(13, 0) |
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| 10 | #define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(15) |
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| 11 | #define MTK_WDMA_DESC_CTRL_BURST BIT(16) |
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| 12 | #define MTK_WDMA_DESC_CTRL_LEN0 GENMASK(29, 16) |
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| 13 | #define MTK_WDMA_DESC_CTRL_LAST_SEG0 BIT(30) |
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| 14 | #define MTK_WDMA_DESC_CTRL_DMA_DONE BIT(31) |
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| 15 | |
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| 16 | #define MTK_WDMA_TXD0_DESC_INFO_DMA_DONE BIT(29) |
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| 17 | #define MTK_WDMA_TXD1_DESC_INFO_DMA_DONE BIT(31) |
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| 18 | |
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| 19 | struct mtk_wdma_desc { |
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| 20 | __le32 buf0; |
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| 21 | __le32 ctrl; |
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| 22 | __le32 buf1; |
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| 23 | __le32 info; |
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| 24 | } __packed __aligned(4); |
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| 25 | |
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| 26 | #define MTK_WED_REV_ID 0x004 |
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| 27 | |
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| 28 | #define MTK_WED_RESET 0x008 |
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| 29 | #define MTK_WED_RESET_TX_BM BIT(0) |
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| 30 | #define MTK_WED_RESET_RX_BM BIT(1) |
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| 31 | #define MTK_WED_RESET_RX_PG_BM BIT(2) |
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| 32 | #define MTK_WED_RESET_RRO_RX_TO_PG BIT(3) |
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| 33 | #define MTK_WED_RESET_TX_FREE_AGENT BIT(4) |
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| 34 | #define MTK_WED_RESET_WPDMA_TX_DRV BIT(8) |
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| 35 | #define MTK_WED_RESET_WPDMA_RX_DRV BIT(9) |
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| 36 | #define MTK_WED_RESET_WPDMA_RX_D_DRV BIT(10) |
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| 37 | #define MTK_WED_RESET_WPDMA_INT_AGENT BIT(11) |
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| 38 | #define MTK_WED_RESET_WED_TX_DMA BIT(12) |
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| 39 | #define MTK_WED_RESET_WED_RX_DMA BIT(13) |
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| 40 | #define MTK_WED_RESET_WDMA_TX_DRV BIT(16) |
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| 41 | #define MTK_WED_RESET_WDMA_RX_DRV BIT(17) |
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| 42 | #define MTK_WED_RESET_WDMA_INT_AGENT BIT(19) |
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| 43 | #define MTK_WED_RESET_RX_RRO_QM BIT(20) |
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| 44 | #define MTK_WED_RESET_RX_ROUTE_QM BIT(21) |
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| 45 | #define MTK_WED_RESET_TX_AMSDU BIT(22) |
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| 46 | #define MTK_WED_RESET_WED BIT(31) |
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| 47 | |
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| 48 | #define MTK_WED_CTRL 0x00c |
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| 49 | #define MTK_WED_CTRL_WPDMA_INT_AGENT_EN BIT(0) |
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| 50 | #define MTK_WED_CTRL_WPDMA_INT_AGENT_BUSY BIT(1) |
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| 51 | #define MTK_WED_CTRL_WDMA_INT_AGENT_EN BIT(2) |
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| 52 | #define MTK_WED_CTRL_WDMA_INT_AGENT_BUSY BIT(3) |
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| 53 | #define MTK_WED_CTRL_WED_RX_IND_CMD_EN BIT(5) |
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| 54 | #define MTK_WED_CTRL_WED_RX_PG_BM_EN BIT(6) |
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| 55 | #define MTK_WED_CTRL_WED_RX_PG_BM_BUSY BIT(7) |
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| 56 | #define MTK_WED_CTRL_WED_TX_BM_EN BIT(8) |
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| 57 | #define MTK_WED_CTRL_WED_TX_BM_BUSY BIT(9) |
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| 58 | #define MTK_WED_CTRL_WED_TX_FREE_AGENT_EN BIT(10) |
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| 59 | #define MTK_WED_CTRL_WED_TX_FREE_AGENT_BUSY BIT(11) |
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| 60 | #define MTK_WED_CTRL_WED_RX_BM_EN BIT(12) |
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| 61 | #define MTK_WED_CTRL_WED_RX_BM_BUSY BIT(13) |
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| 62 | #define MTK_WED_CTRL_RX_RRO_QM_EN BIT(14) |
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| 63 | #define MTK_WED_CTRL_RX_RRO_QM_BUSY BIT(15) |
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| 64 | #define MTK_WED_CTRL_RX_ROUTE_QM_EN BIT(16) |
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| 65 | #define MTK_WED_CTRL_RX_ROUTE_QM_BUSY BIT(17) |
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| 66 | #define MTK_WED_CTRL_TX_TKID_ALI_EN BIT(20) |
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| 67 | #define MTK_WED_CTRL_TX_TKID_ALI_BUSY BIT(21) |
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| 68 | #define MTK_WED_CTRL_TX_AMSDU_EN BIT(22) |
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| 69 | #define MTK_WED_CTRL_TX_AMSDU_BUSY BIT(23) |
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| 70 | #define MTK_WED_CTRL_FINAL_DIDX_READ BIT(24) |
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| 71 | #define MTK_WED_CTRL_ETH_DMAD_FMT BIT(25) |
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| 72 | #define MTK_WED_CTRL_MIB_READ_CLEAR BIT(28) |
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| 73 | #define MTK_WED_CTRL_FLD_MIB_RD_CLR BIT(28) |
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| 74 | |
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| 75 | #define MTK_WED_EXT_INT_STATUS 0x020 |
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| 76 | #define MTK_WED_EXT_INT_STATUS_TF_LEN_ERR BIT(0) |
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| 77 | #define MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD BIT(1) |
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| 78 | #define MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID BIT(4) |
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| 79 | #define MTK_WED_EXT_INT_STATUS_TX_FBUF_LO_TH BIT(8) |
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| 80 | #define MTK_WED_EXT_INT_STATUS_TX_FBUF_HI_TH BIT(9) |
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| 81 | #define MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH BIT(10) /* wed v2 */ |
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| 82 | #define MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH BIT(11) /* wed v2 */ |
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| 83 | #define MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR BIT(16) |
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| 84 | #define MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR BIT(17) |
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| 85 | #define MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT BIT(18) |
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| 86 | #define MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN BIT(19) |
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| 87 | #define MTK_WED_EXT_INT_STATUS_RX_DRV_BM_DMAD_COHERENT BIT(20) |
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| 88 | #define MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR BIT(21) |
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| 89 | #define MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR BIT(22) |
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| 90 | #define MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR BIT(23) |
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| 91 | #define MTK_WED_EXT_INT_STATUS_RX_DRV_DMA_RECYCLE BIT(24) |
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| 92 | #define MTK_WED_EXT_INT_STATUS_RX_DRV_GET_BM_DMAD_SKIP BIT(25) |
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| 93 | #define MTK_WED_EXT_INT_STATUS_WPDMA_RX_D_DRV_ERR BIT(26) |
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| 94 | #define MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY BIT(27) |
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| 95 | #define MTK_WED_EXT_INT_STATUS_ERROR_MASK (MTK_WED_EXT_INT_STATUS_TF_LEN_ERR | \ |
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| 96 | MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD | \ |
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| 97 | MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID | \ |
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| 98 | MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR | \ |
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| 99 | MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR | \ |
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| 100 | MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN | \ |
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| 101 | MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR) |
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| 102 | |
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| 103 | #define MTK_WED_EXT_INT_MASK 0x028 |
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| 104 | #define MTK_WED_EXT_INT_MASK1 0x02c |
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| 105 | #define MTK_WED_EXT_INT_MASK2 0x030 |
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| 106 | #define MTK_WED_EXT_INT_MASK3 0x034 |
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| 107 | |
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| 108 | #define MTK_WED_STATUS 0x060 |
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| 109 | #define MTK_WED_STATUS_TX GENMASK(15, 8) |
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| 110 | |
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| 111 | #define MTK_WED_WPDMA_STATUS 0x068 |
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| 112 | #define MTK_WED_WPDMA_STATUS_TX_DRV GENMASK(15, 8) |
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| 113 | |
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| 114 | #define MTK_WED_TX_BM_CTRL 0x080 |
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| 115 | #define MTK_WED_TX_BM_CTRL_VLD_GRP_NUM GENMASK(6, 0) |
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| 116 | #define MTK_WED_TX_BM_CTRL_RSV_GRP_NUM GENMASK(22, 16) |
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| 117 | #define MTK_WED_TX_BM_CTRL_LEGACY_EN BIT(26) |
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| 118 | #define MTK_WED_TX_TKID_CTRL_FREE_FORMAT BIT(27) |
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| 119 | #define MTK_WED_TX_BM_CTRL_PAUSE BIT(28) |
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| 120 | |
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| 121 | #define MTK_WED_TX_BM_BASE 0x084 |
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| 122 | #define MTK_WED_TX_BM_INIT_PTR 0x088 |
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| 123 | #define MTK_WED_TX_BM_SW_TAIL_IDX GENMASK(16, 0) |
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| 124 | #define MTK_WED_TX_BM_INIT_SW_TAIL_IDX BIT(16) |
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| 125 | |
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| 126 | #define MTK_WED_TX_BM_TKID_START GENMASK(15, 0) |
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| 127 | #define MTK_WED_TX_BM_TKID_END GENMASK(31, 16) |
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| 128 | |
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| 129 | #define MTK_WED_TX_BM_BUF_LEN 0x08c |
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| 130 | |
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| 131 | #define MTK_WED_TX_BM_INTF 0x09c |
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| 132 | #define MTK_WED_TX_BM_INTF_TKID GENMASK(15, 0) |
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| 133 | #define MTK_WED_TX_BM_INTF_TKFIFO_FDEP GENMASK(23, 16) |
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| 134 | #define MTK_WED_TX_BM_INTF_TKID_VALID BIT(28) |
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| 135 | #define MTK_WED_TX_BM_INTF_TKID_READ BIT(29) |
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| 136 | |
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| 137 | #define MTK_WED_TX_BM_DYN_THR 0x0a0 |
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| 138 | #define MTK_WED_TX_BM_DYN_THR_LO GENMASK(6, 0) |
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| 139 | #define MTK_WED_TX_BM_DYN_THR_LO_V2 GENMASK(8, 0) |
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| 140 | #define MTK_WED_TX_BM_DYN_THR_HI GENMASK(22, 16) |
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| 141 | #define MTK_WED_TX_BM_DYN_THR_HI_V2 GENMASK(24, 16) |
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| 142 | |
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| 143 | #define MTK_WED_TX_TKID_CTRL 0x0c0 |
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| 144 | #define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM GENMASK(6, 0) |
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| 145 | #define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM GENMASK(22, 16) |
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| 146 | #define MTK_WED_TX_TKID_CTRL_PAUSE BIT(28) |
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| 147 | |
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| 148 | #define MTK_WED_TX_TKID_INTF 0x0dc |
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| 149 | #define MTK_WED_TX_TKID_INTF_TKFIFO_FDEP GENMASK(25, 16) |
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| 150 | |
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| 151 | #define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM_V3 GENMASK(7, 0) |
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| 152 | #define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM_V3 GENMASK(23, 16) |
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| 153 | |
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| 154 | #define MTK_WED_TX_TKID_DYN_THR 0x0e0 |
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| 155 | #define MTK_WED_TX_TKID_DYN_THR_LO GENMASK(6, 0) |
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| 156 | #define MTK_WED_TX_TKID_DYN_THR_HI GENMASK(22, 16) |
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| 157 | |
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| 158 | #define MTK_WED_TXP_DW0 0x120 |
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| 159 | #define MTK_WED_TXP_DW1 0x124 |
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| 160 | #define MTK_WED_WPDMA_WRITE_TXP GENMASK(31, 16) |
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| 161 | #define MTK_WED_TXDP_CTRL 0x130 |
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| 162 | #define MTK_WED_TXDP_DW9_OVERWR BIT(9) |
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| 163 | #define MTK_WED_RX_BM_TKID_MIB 0x1cc |
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| 164 | |
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| 165 | #define MTK_WED_INT_STATUS 0x200 |
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| 166 | #define MTK_WED_INT_MASK 0x204 |
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| 167 | |
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| 168 | #define MTK_WED_GLO_CFG 0x208 |
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| 169 | #define MTK_WED_GLO_CFG_TX_DMA_EN BIT(0) |
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| 170 | #define MTK_WED_GLO_CFG_TX_DMA_BUSY BIT(1) |
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| 171 | #define MTK_WED_GLO_CFG_RX_DMA_EN BIT(2) |
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| 172 | #define MTK_WED_GLO_CFG_RX_DMA_BUSY BIT(3) |
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| 173 | #define MTK_WED_GLO_CFG_RX_BT_SIZE GENMASK(5, 4) |
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| 174 | #define MTK_WED_GLO_CFG_TX_WB_DDONE BIT(6) |
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| 175 | #define MTK_WED_GLO_CFG_BIG_ENDIAN BIT(7) |
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| 176 | #define MTK_WED_GLO_CFG_DIS_BT_SIZE_ALIGN BIT(8) |
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| 177 | #define MTK_WED_GLO_CFG_TX_BT_SIZE_LO BIT(9) |
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| 178 | #define MTK_WED_GLO_CFG_MULTI_DMA_EN GENMASK(11, 10) |
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| 179 | #define MTK_WED_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12) |
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| 180 | #define MTK_WED_GLO_CFG_MI_DEPTH_RD GENMASK(21, 13) |
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| 181 | #define MTK_WED_GLO_CFG_TX_BT_SIZE_HI GENMASK(23, 22) |
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| 182 | #define MTK_WED_GLO_CFG_SW_RESET BIT(24) |
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| 183 | #define MTK_WED_GLO_CFG_FIRST_TOKEN_ONLY BIT(26) |
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| 184 | #define MTK_WED_GLO_CFG_OMIT_RX_INFO BIT(27) |
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| 185 | #define MTK_WED_GLO_CFG_OMIT_TX_INFO BIT(28) |
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| 186 | #define MTK_WED_GLO_CFG_BYTE_SWAP BIT(29) |
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| 187 | #define MTK_WED_GLO_CFG_RX_2B_OFFSET BIT(31) |
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| 188 | |
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| 189 | #define MTK_WED_RESET_IDX 0x20c |
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| 190 | #define MTK_WED_RESET_WPDMA_IDX_RX GENMASK(31, 30) |
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| 191 | |
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| 192 | #define MTK_WED_TX_MIB(_n) (0x2a0 + (_n) * 4) |
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| 193 | #define MTK_WED_RX_MIB(_n) (0x2e0 + (_n) * 4) |
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| 194 | |
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| 195 | #define MTK_WED_RING_TX(_n) (0x300 + (_n) * 0x10) |
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| 196 | |
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| 197 | #define MTK_WED_RING_RX(_n) (0x400 + (_n) * 0x10) |
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| 198 | #define MTK_WED_RING_RX_DATA(_n) (0x420 + (_n) * 0x10) |
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| 199 | |
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| 200 | #define MTK_WED_SCR0 0x3c0 |
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| 201 | #define MTK_WED_RX1_CTRL2 0x418 |
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| 202 | #define MTK_WED_WPDMA_INT_TRIGGER 0x504 |
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| 203 | #define MTK_WED_WPDMA_INT_TRIGGER_RX_DONE BIT(1) |
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| 204 | #define MTK_WED_WPDMA_INT_TRIGGER_TX_DONE GENMASK(5, 4) |
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| 205 | |
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| 206 | #define MTK_WED_WPDMA_GLO_CFG 0x508 |
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| 207 | #define MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN BIT(0) |
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| 208 | #define MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY BIT(1) |
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| 209 | #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN BIT(2) |
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| 210 | #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_BUSY BIT(3) |
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| 211 | #define MTK_WED_WPDMA_GLO_CFG_RX_BT_SIZE GENMASK(5, 4) |
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| 212 | #define MTK_WED_WPDMA_GLO_CFG_TX_WB_DDONE BIT(6) |
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| 213 | #define MTK_WED_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7) |
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| 214 | #define MTK_WED_WPDMA_GLO_CFG_DIS_BT_SIZE_ALIGN BIT(8) |
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| 215 | #define MTK_WED_WPDMA_GLO_CFG_TX_BT_SIZE_LO BIT(9) |
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| 216 | #define MTK_WED_WPDMA_GLO_CFG_MULTI_DMA_EN GENMASK(11, 10) |
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| 217 | #define MTK_WED_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12) |
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| 218 | #define MTK_WED_WPDMA_GLO_CFG_MI_DEPTH_RD GENMASK(21, 13) |
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| 219 | #define MTK_WED_WPDMA_GLO_CFG_TX_BT_SIZE_HI GENMASK(23, 22) |
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| 220 | #define MTK_WED_WPDMA_GLO_CFG_SW_RESET BIT(24) |
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| 221 | #define MTK_WED_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY BIT(26) |
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| 222 | #define MTK_WED_WPDMA_GLO_CFG_OMIT_RX_INFO BIT(27) |
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| 223 | #define MTK_WED_WPDMA_GLO_CFG_OMIT_TX_INFO BIT(28) |
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| 224 | #define MTK_WED_WPDMA_GLO_CFG_BYTE_SWAP BIT(29) |
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| 225 | #define MTK_WED_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31) |
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| 226 | |
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| 227 | /* CONFIG_MEDIATEK_NETSYS_V2 */ |
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| 228 | #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC BIT(4) |
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| 229 | #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_PKT_PROC BIT(5) |
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| 230 | #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC BIT(6) |
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| 231 | #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_CRX_SYNC BIT(7) |
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| 232 | #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_VER GENMASK(15, 12) |
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| 233 | #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNS_VER_FORCE_4 BIT(18) |
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| 234 | #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNSUPPORT_FMT BIT(19) |
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| 235 | #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_CHK BIT(20) |
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| 236 | #define MTK_WED_WPDMA_GLO_CFG_RX_DDONE2_WR BIT(21) |
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| 237 | #define MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP BIT(24) |
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| 238 | #define MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK_LAST BIT(25) |
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| 239 | #define MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV BIT(28) |
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| 240 | #define MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK BIT(30) |
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| 241 | |
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| 242 | #define MTK_WED_WPDMA_RESET_IDX 0x50c |
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| 243 | #define MTK_WED_WPDMA_RESET_IDX_TX GENMASK(3, 0) |
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| 244 | #define MTK_WED_WPDMA_RESET_IDX_RX GENMASK(17, 16) |
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| 245 | |
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| 246 | #define MTK_WED_WPDMA_CTRL 0x518 |
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| 247 | #define MTK_WED_WPDMA_CTRL_SDL1_FIXED BIT(31) |
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| 248 | |
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| 249 | #define MTK_WED_WPDMA_INT_CTRL 0x520 |
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| 250 | #define MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV BIT(21) |
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| 251 | #define MTK_WED_WPDMA_INT_CTRL_SIG_SRC BIT(22) |
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| 252 | #define MTK_WED_WPDMA_INT_CTRL_SRC_SEL GENMASK(17, 16) |
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| 253 | |
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| 254 | #define MTK_WED_WPDMA_INT_MASK 0x524 |
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| 255 | |
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| 256 | #define MTK_WED_WPDMA_INT_CTRL_TX 0x530 |
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| 257 | #define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN BIT(0) |
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| 258 | #define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_CLR BIT(1) |
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| 259 | #define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_TRIG GENMASK(6, 2) |
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| 260 | #define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_EN BIT(8) |
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| 261 | #define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_CLR BIT(9) |
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| 262 | #define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_TRIG GENMASK(14, 10) |
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| 263 | |
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| 264 | #define MTK_WED_WPDMA_INT_CTRL_RX 0x534 |
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| 265 | #define MTK_WED_WPDMA_INT_CTRL_RX0_EN BIT(0) |
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| 266 | #define MTK_WED_WPDMA_INT_CTRL_RX0_CLR BIT(1) |
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| 267 | #define MTK_WED_WPDMA_INT_CTRL_RX0_DONE_TRIG GENMASK(6, 2) |
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| 268 | #define MTK_WED_WPDMA_INT_CTRL_RX1_EN BIT(8) |
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| 269 | #define MTK_WED_WPDMA_INT_CTRL_RX1_CLR BIT(9) |
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| 270 | #define MTK_WED_WPDMA_INT_CTRL_RX1_DONE_TRIG GENMASK(14, 10) |
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| 271 | |
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| 272 | #define MTK_WED_WPDMA_INT_CTRL_TX_FREE 0x538 |
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| 273 | #define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN BIT(0) |
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| 274 | #define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_CLR BIT(1) |
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| 275 | #define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG GENMASK(6, 2) |
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| 276 | |
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| 277 | #define MTK_WED_PCIE_CFG_BASE 0x560 |
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| 278 | |
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| 279 | #define MTK_WED_PCIE_CFG_BASE 0x560 |
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| 280 | #define MTK_WED_PCIE_CFG_INTM 0x564 |
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| 281 | #define MTK_WED_PCIE_CFG_MSIS 0x568 |
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| 282 | #define MTK_WED_PCIE_INT_TRIGGER 0x570 |
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| 283 | #define MTK_WED_PCIE_INT_TRIGGER_STATUS BIT(16) |
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| 284 | |
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| 285 | #define MTK_WED_PCIE_INT_CTRL 0x57c |
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| 286 | #define MTK_WED_PCIE_INT_CTRL_POLL_EN GENMASK(13, 12) |
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| 287 | #define MTK_WED_PCIE_INT_CTRL_SRC_SEL GENMASK(17, 16) |
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| 288 | #define MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA BIT(20) |
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| 289 | #define MTK_WED_PCIE_INT_CTRL_MSK_IRQ_FILTER BIT(21) |
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| 290 | |
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| 291 | #define MTK_WED_WPDMA_CFG_BASE 0x580 |
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| 292 | #define MTK_WED_WPDMA_CFG_INT_MASK 0x584 |
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| 293 | #define MTK_WED_WPDMA_CFG_TX 0x588 |
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| 294 | #define MTK_WED_WPDMA_CFG_TX_FREE 0x58c |
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| 295 | |
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| 296 | #define MTK_WED_WPDMA_TX_MIB(_n) (0x5a0 + (_n) * 4) |
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| 297 | #define MTK_WED_WPDMA_TX_COHERENT_MIB(_n) (0x5d0 + (_n) * 4) |
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| 298 | #define MTK_WED_WPDMA_RX_MIB(_n) (0x5e0 + (_n) * 4) |
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| 299 | #define MTK_WED_WPDMA_RX_COHERENT_MIB(_n) (0x5f0 + (_n) * 4) |
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| 300 | |
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| 301 | #define MTK_WED_WPDMA_RING_TX(_n) (0x600 + (_n) * 0x10) |
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| 302 | #define MTK_WED_WPDMA_RING_RX(_n) (0x700 + (_n) * 0x10) |
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| 303 | #define MTK_WED_WPDMA_RING_RX_DATA(_n) (0x730 + (_n) * 0x10) |
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| 304 | |
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| 305 | #define MTK_WED_WPDMA_RX_D_GLO_CFG 0x75c |
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| 306 | #define MTK_WED_WPDMA_RX_D_RX_DRV_EN BIT(0) |
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| 307 | #define MTK_WED_WPDMA_RX_D_RX_DRV_BUSY BIT(1) |
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| 308 | #define MTK_WED_WPDMA_RX_D_FSM_RETURN_IDLE BIT(3) |
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| 309 | #define MTK_WED_WPDMA_RX_D_RST_INIT_COMPLETE BIT(4) |
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| 310 | #define MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL GENMASK(11, 7) |
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| 311 | #define MTK_WED_WPDMA_RX_D_RXD_READ_LEN GENMASK(31, 24) |
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| 312 | |
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| 313 | #define MTK_WED_WPDMA_RX_D_RST_IDX 0x760 |
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| 314 | #define MTK_WED_WPDMA_RX_D_RST_CRX_IDX GENMASK(17, 16) |
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| 315 | #define MTK_WED_WPDMA_RX_D_RST_DRV_IDX_ALL BIT(20) |
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| 316 | #define MTK_WED_WPDMA_RX_D_RST_DRV_IDX GENMASK(25, 24) |
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| 317 | |
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| 318 | #define MTK_WED_WPDMA_RX_GLO_CFG 0x76c |
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| 319 | |
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| 320 | #define MTK_WED_WPDMA_RX_D_MIB(_n) (0x774 + (_n) * 4) |
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| 321 | #define MTK_WED_WPDMA_RX_D_PROCESSED_MIB(_n) (0x784 + (_n) * 4) |
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| 322 | #define MTK_WED_WPDMA_RX_D_COHERENT_MIB 0x78c |
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| 323 | |
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| 324 | #define MTK_WED_WPDMA_RX_D_PREF_CFG 0x7b4 |
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| 325 | #define MTK_WED_WPDMA_RX_D_PREF_EN BIT(0) |
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| 326 | #define MTK_WED_WPDMA_RX_D_PREF_BUSY BIT(1) |
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| 327 | #define MTK_WED_WPDMA_RX_D_PREF_BURST_SIZE GENMASK(12, 8) |
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| 328 | #define MTK_WED_WPDMA_RX_D_PREF_LOW_THRES GENMASK(21, 16) |
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| 329 | |
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| 330 | #define MTK_WED_WPDMA_RX_D_PREF_RX0_SIDX 0x7b8 |
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| 331 | #define MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR BIT(15) |
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| 332 | |
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| 333 | #define MTK_WED_WPDMA_RX_D_PREF_RX1_SIDX 0x7bc |
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| 334 | |
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| 335 | #define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG 0x7c0 |
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| 336 | #define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R0_CLR BIT(0) |
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| 337 | #define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R1_CLR BIT(16) |
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| 338 | |
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| 339 | #define MTK_WED_WDMA_RING_TX 0x800 |
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| 340 | |
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| 341 | #define MTK_WED_WDMA_TX_MIB 0x810 |
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| 342 | |
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| 343 | #define MTK_WED_WDMA_RING_RX(_n) (0x900 + (_n) * 0x10) |
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| 344 | #define MTK_WED_WDMA_RX_THRES(_n) (0x940 + (_n) * 0x4) |
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| 345 | |
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| 346 | #define MTK_WED_WDMA_RX_PREF_CFG 0x950 |
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| 347 | #define MTK_WED_WDMA_RX_PREF_EN BIT(0) |
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| 348 | #define MTK_WED_WDMA_RX_PREF_BUSY BIT(1) |
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| 349 | #define MTK_WED_WDMA_RX_PREF_BURST_SIZE GENMASK(12, 8) |
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| 350 | #define MTK_WED_WDMA_RX_PREF_LOW_THRES GENMASK(21, 16) |
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| 351 | #define MTK_WED_WDMA_RX_PREF_RX0_SIDX_CLR BIT(24) |
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| 352 | #define MTK_WED_WDMA_RX_PREF_RX1_SIDX_CLR BIT(25) |
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| 353 | #define MTK_WED_WDMA_RX_PREF_DDONE2_EN BIT(26) |
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| 354 | #define MTK_WED_WDMA_RX_PREF_DDONE2_BUSY BIT(27) |
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| 355 | |
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| 356 | #define MTK_WED_WDMA_RX_PREF_FIFO_CFG 0x95C |
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| 357 | #define MTK_WED_WDMA_RX_PREF_FIFO_RX0_CLR BIT(0) |
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| 358 | #define MTK_WED_WDMA_RX_PREF_FIFO_RX1_CLR BIT(16) |
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| 359 | |
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| 360 | #define MTK_WED_WDMA_GLO_CFG 0xa04 |
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| 361 | #define MTK_WED_WDMA_GLO_CFG_TX_DRV_EN BIT(0) |
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| 362 | #define MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK BIT(1) |
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| 363 | #define MTK_WED_WDMA_GLO_CFG_RX_DRV_EN BIT(2) |
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| 364 | #define MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY BIT(3) |
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| 365 | #define MTK_WED_WDMA_GLO_CFG_BT_SIZE GENMASK(5, 4) |
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| 366 | #define MTK_WED_WDMA_GLO_CFG_TX_WB_DDONE BIT(6) |
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| 367 | #define MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE BIT(13) |
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| 368 | #define MTK_WED_WDMA_GLO_CFG_WCOMPLETE_SEL BIT(16) |
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| 369 | #define MTK_WED_WDMA_GLO_CFG_INIT_PHASE_RXDMA_BYPASS BIT(17) |
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| 370 | #define MTK_WED_WDMA_GLO_CFG_INIT_PHASE_BYPASS BIT(18) |
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| 371 | #define MTK_WED_WDMA_GLO_CFG_FSM_RETURN_IDLE BIT(19) |
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| 372 | #define MTK_WED_WDMA_GLO_CFG_WAIT_COHERENT BIT(20) |
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| 373 | #define MTK_WED_WDMA_GLO_CFG_AXI_W_AFTER_AW BIT(21) |
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| 374 | #define MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY_SINGLE_W BIT(22) |
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| 375 | #define MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY BIT(23) |
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| 376 | #define MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP BIT(24) |
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| 377 | #define MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE BIT(25) |
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| 378 | #define MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE BIT(26) |
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| 379 | #define MTK_WED_WDMA_GLO_CFG_RXDRV_CLKGATE_BYPASS BIT(30) |
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| 380 | |
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| 381 | #define MTK_WED_WDMA_RESET_IDX 0xa08 |
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| 382 | #define MTK_WED_WDMA_RESET_IDX_RX GENMASK(17, 16) |
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| 383 | #define MTK_WED_WDMA_RESET_IDX_RX_ALL BIT(20) |
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| 384 | #define MTK_WED_WDMA_RESET_IDX_DRV GENMASK(25, 24) |
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| 385 | |
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| 386 | #define MTK_WED_WDMA_INT_CLR 0xa24 |
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| 387 | #define MTK_WED_WDMA_INT_CLR_RX_DONE GENMASK(17, 16) |
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| 388 | |
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| 389 | #define MTK_WED_WDMA_INT_TRIGGER 0xa28 |
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| 390 | #define MTK_WED_WDMA_INT_TRIGGER_RX_DONE GENMASK(17, 16) |
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| 391 | |
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| 392 | #define MTK_WED_WDMA_INT_CTRL 0xa2c |
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| 393 | #define MTK_WED_WDMA_INT_POLL_PRD GENMASK(7, 0) |
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| 394 | #define MTK_WED_WDMA_INT_CTRL_POLL_SRC_SEL GENMASK(17, 16) |
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| 395 | |
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| 396 | #define MTK_WED_WDMA_CFG_BASE 0xaa0 |
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| 397 | #define MTK_WED_WDMA_OFFSET0 0xaa4 |
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| 398 | #define MTK_WED_WDMA_OFFSET1 0xaa8 |
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| 399 | |
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| 400 | #define MTK_WED_WDMA_OFST0_GLO_INTS GENMASK(15, 0) |
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| 401 | #define MTK_WED_WDMA_OFST0_GLO_CFG GENMASK(31, 16) |
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| 402 | #define MTK_WED_WDMA_OFST1_TX_CTRL GENMASK(15, 0) |
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| 403 | #define MTK_WED_WDMA_OFST1_RX_CTRL GENMASK(31, 16) |
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| 404 | |
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| 405 | #define MTK_WED_WDMA_RX_MIB(_n) (0xae0 + (_n) * 4) |
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| 406 | #define MTK_WED_WDMA_RX_RECYCLE_MIB(_n) (0xae8 + (_n) * 4) |
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| 407 | #define MTK_WED_WDMA_RX_PROCESSED_MIB(_n) (0xaf0 + (_n) * 4) |
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| 408 | |
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| 409 | #define MTK_WED_RX_BM_RX_DMAD 0xd80 |
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| 410 | #define MTK_WED_RX_BM_RX_DMAD_SDL0 GENMASK(13, 0) |
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| 411 | |
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| 412 | #define MTK_WED_RX_BM_BASE 0xd84 |
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| 413 | #define MTK_WED_RX_BM_INIT_PTR 0xd88 |
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| 414 | #define MTK_WED_RX_BM_SW_TAIL GENMASK(15, 0) |
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| 415 | #define MTK_WED_RX_BM_INIT_SW_TAIL BIT(16) |
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| 416 | |
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| 417 | #define MTK_WED_RX_PTR 0xd8c |
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| 418 | |
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| 419 | #define MTK_WED_RX_BM_DYN_ALLOC_TH 0xdb4 |
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| 420 | #define MTK_WED_RX_BM_DYN_ALLOC_TH_H GENMASK(31, 16) |
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| 421 | #define MTK_WED_RX_BM_DYN_ALLOC_TH_L GENMASK(15, 0) |
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| 422 | |
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| 423 | #define MTK_WED_RING_OFS_BASE 0x00 |
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| 424 | #define MTK_WED_RING_OFS_COUNT 0x04 |
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| 425 | #define MTK_WED_RING_OFS_CPU_IDX 0x08 |
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| 426 | #define MTK_WED_RING_OFS_DMA_IDX 0x0c |
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| 427 | |
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| 428 | #define MTK_WDMA_RING_TX(_n) (0x000 + (_n) * 0x10) |
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| 429 | #define MTK_WDMA_RING_RX(_n) (0x100 + (_n) * 0x10) |
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| 430 | |
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| 431 | #define MTK_WDMA_GLO_CFG 0x204 |
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| 432 | #define MTK_WDMA_GLO_CFG_TX_DMA_EN BIT(0) |
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| 433 | #define MTK_WDMA_GLO_CFG_TX_DMA_BUSY BIT(1) |
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| 434 | #define MTK_WDMA_GLO_CFG_RX_DMA_EN BIT(2) |
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| 435 | #define MTK_WDMA_GLO_CFG_RX_DMA_BUSY BIT(3) |
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| 436 | #define MTK_WDMA_GLO_CFG_RX_INFO3_PRERES BIT(26) |
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| 437 | #define MTK_WDMA_GLO_CFG_RX_INFO2_PRERES BIT(27) |
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| 438 | #define MTK_WDMA_GLO_CFG_RX_INFO1_PRERES BIT(28) |
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| 439 | |
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| 440 | #define MTK_WDMA_RESET_IDX 0x208 |
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| 441 | #define MTK_WDMA_RESET_IDX_TX GENMASK(3, 0) |
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| 442 | #define MTK_WDMA_RESET_IDX_RX GENMASK(17, 16) |
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| 443 | |
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| 444 | #define MTK_WDMA_INT_STATUS 0x220 |
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| 445 | |
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| 446 | #define MTK_WDMA_INT_MASK 0x228 |
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| 447 | #define MTK_WDMA_INT_MASK_TX_DONE GENMASK(3, 0) |
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| 448 | #define MTK_WDMA_INT_MASK_RX_DONE GENMASK(17, 16) |
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| 449 | #define MTK_WDMA_INT_MASK_TX_DELAY BIT(28) |
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| 450 | #define MTK_WDMA_INT_MASK_TX_COHERENT BIT(29) |
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| 451 | #define MTK_WDMA_INT_MASK_RX_DELAY BIT(30) |
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| 452 | #define MTK_WDMA_INT_MASK_RX_COHERENT BIT(31) |
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| 453 | |
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| 454 | #define MTK_WDMA_XDMA_TX_FIFO_CFG 0x238 |
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| 455 | #define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_PAR_FIFO_CLEAR BIT(0) |
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| 456 | #define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_CMD_FIFO_CLEAR BIT(4) |
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| 457 | #define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_DMAD_FIFO_CLEAR BIT(8) |
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| 458 | #define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_ARR_FIFO_CLEAR BIT(12) |
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| 459 | |
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| 460 | #define MTK_WDMA_XDMA_RX_FIFO_CFG 0x23c |
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| 461 | #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_PAR_FIFO_CLEAR BIT(0) |
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| 462 | #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_CMD_FIFO_CLEAR BIT(4) |
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| 463 | #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_DMAD_FIFO_CLEAR BIT(8) |
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| 464 | #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_ARR_FIFO_CLEAR BIT(12) |
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| 465 | #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_LEN_FIFO_CLEAR BIT(15) |
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| 466 | #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_WID_FIFO_CLEAR BIT(18) |
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| 467 | #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_BID_FIFO_CLEAR BIT(21) |
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| 468 | |
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| 469 | #define MTK_WDMA_INT_GRP1 0x250 |
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| 470 | #define MTK_WDMA_INT_GRP2 0x254 |
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| 471 | |
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| 472 | #define MTK_WDMA_PREF_TX_CFG 0x2d0 |
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| 473 | #define MTK_WDMA_PREF_TX_CFG_PREF_EN BIT(0) |
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| 474 | #define MTK_WDMA_PREF_TX_CFG_PREF_BUSY BIT(1) |
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| 475 | |
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| 476 | #define MTK_WDMA_PREF_RX_CFG 0x2dc |
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| 477 | #define MTK_WDMA_PREF_RX_CFG_PREF_EN BIT(0) |
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| 478 | #define MTK_WDMA_PREF_RX_CFG_PREF_BUSY BIT(1) |
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| 479 | |
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| 480 | #define MTK_WDMA_PREF_RX_FIFO_CFG 0x2e0 |
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| 481 | #define MTK_WDMA_PREF_RX_FIFO_CFG_RING0_CLEAR BIT(0) |
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| 482 | #define MTK_WDMA_PREF_RX_FIFO_CFG_RING1_CLEAR BIT(16) |
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| 483 | |
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| 484 | #define MTK_WDMA_PREF_TX_FIFO_CFG 0x2d4 |
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| 485 | #define MTK_WDMA_PREF_TX_FIFO_CFG_RING0_CLEAR BIT(0) |
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| 486 | #define MTK_WDMA_PREF_TX_FIFO_CFG_RING1_CLEAR BIT(16) |
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| 487 | |
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| 488 | #define MTK_WDMA_PREF_SIDX_CFG 0x2e4 |
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| 489 | #define MTK_WDMA_PREF_SIDX_CFG_TX_RING_CLEAR GENMASK(3, 0) |
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| 490 | #define MTK_WDMA_PREF_SIDX_CFG_RX_RING_CLEAR GENMASK(5, 4) |
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| 491 | |
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| 492 | #define MTK_WDMA_WRBK_TX_CFG 0x300 |
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| 493 | #define MTK_WDMA_WRBK_TX_CFG_WRBK_BUSY BIT(0) |
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| 494 | #define MTK_WDMA_WRBK_TX_CFG_WRBK_EN BIT(30) |
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| 495 | |
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| 496 | #define MTK_WDMA_WRBK_TX_FIFO_CFG(_n) (0x304 + (_n) * 0x4) |
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| 497 | #define MTK_WDMA_WRBK_TX_FIFO_CFG_RING_CLEAR BIT(0) |
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| 498 | |
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| 499 | #define MTK_WDMA_WRBK_RX_CFG 0x344 |
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| 500 | #define MTK_WDMA_WRBK_RX_CFG_WRBK_BUSY BIT(0) |
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| 501 | #define MTK_WDMA_WRBK_RX_CFG_WRBK_EN BIT(30) |
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| 502 | |
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| 503 | #define MTK_WDMA_WRBK_RX_FIFO_CFG(_n) (0x348 + (_n) * 0x4) |
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| 504 | #define MTK_WDMA_WRBK_RX_FIFO_CFG_RING_CLEAR BIT(0) |
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| 505 | |
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| 506 | #define MTK_WDMA_WRBK_SIDX_CFG 0x388 |
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| 507 | #define MTK_WDMA_WRBK_SIDX_CFG_TX_RING_CLEAR GENMASK(3, 0) |
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| 508 | #define MTK_WDMA_WRBK_SIDX_CFG_RX_RING_CLEAR GENMASK(5, 4) |
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| 509 | |
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| 510 | #define MTK_PCIE_MIRROR_MAP(n) ((n) ? 0x4 : 0x0) |
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| 511 | #define MTK_PCIE_MIRROR_MAP_EN BIT(0) |
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| 512 | #define MTK_PCIE_MIRROR_MAP_WED_ID BIT(1) |
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| 513 | |
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| 514 | /* DMA channel mapping */ |
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| 515 | #define HIFSYS_DMA_AG_MAP 0x008 |
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| 516 | |
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| 517 | #define MTK_WED_RTQM_GLO_CFG 0xb00 |
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| 518 | #define MTK_WED_RTQM_BUSY BIT(1) |
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| 519 | #define MTK_WED_RTQM_Q_RST BIT(2) |
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| 520 | #define MTK_WED_RTQM_Q_DBG_BYPASS BIT(5) |
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| 521 | #define MTK_WED_RTQM_TXDMAD_FPORT GENMASK(23, 20) |
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| 522 | |
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| 523 | #define MTK_WED_RTQM_RST 0xb04 |
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| 524 | |
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| 525 | #define MTK_WED_RTQM_IGRS0_I2HW_DMAD_CNT 0xb1c |
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| 526 | #define MTK_WED_RTQM_IGRS0_I2H_DMAD_CNT(_n) (0xb20 + (_n) * 0x4) |
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| 527 | #define MTK_WED_RTQM_IGRS0_I2HW_PKT_CNT 0xb28 |
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| 528 | #define MTK_WED_RTQM_IGRS0_I2H_PKT_CNT(_n) (0xb2c + (_n) * 0x4) |
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| 529 | #define MTK_WED_RTQM_IGRS0_FDROP_CNT 0xb34 |
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| 530 | |
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| 531 | #define MTK_WED_RTQM_IGRS1_I2HW_DMAD_CNT 0xb44 |
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| 532 | #define MTK_WED_RTQM_IGRS1_I2H_DMAD_CNT(_n) (0xb48 + (_n) * 0x4) |
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| 533 | #define MTK_WED_RTQM_IGRS1_I2HW_PKT_CNT 0xb50 |
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| 534 | #define MTK_WED_RTQM_IGRS1_I2H_PKT_CNT(_n) (0xb54 + (_n) * 0x4) |
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| 535 | #define MTK_WED_RTQM_IGRS1_FDROP_CNT 0xb5c |
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| 536 | |
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| 537 | #define MTK_WED_RTQM_IGRS2_I2HW_DMAD_CNT 0xb6c |
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| 538 | #define MTK_WED_RTQM_IGRS2_I2H_DMAD_CNT(_n) (0xb70 + (_n) * 0x4) |
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| 539 | #define MTK_WED_RTQM_IGRS2_I2HW_PKT_CNT 0xb78 |
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| 540 | #define MTK_WED_RTQM_IGRS2_I2H_PKT_CNT(_n) (0xb7c + (_n) * 0x4) |
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| 541 | #define MTK_WED_RTQM_IGRS2_FDROP_CNT 0xb84 |
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| 542 | |
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| 543 | #define MTK_WED_RTQM_IGRS3_I2HW_DMAD_CNT 0xb94 |
|---|
| 544 | #define MTK_WED_RTQM_IGRS3_I2H_DMAD_CNT(_n) (0xb98 + (_n) * 0x4) |
|---|
| 545 | #define MTK_WED_RTQM_IGRS3_I2HW_PKT_CNT 0xba0 |
|---|
| 546 | #define MTK_WED_RTQM_IGRS3_I2H_PKT_CNT(_n) (0xba4 + (_n) * 0x4) |
|---|
| 547 | #define MTK_WED_RTQM_IGRS3_FDROP_CNT 0xbac |
|---|
| 548 | |
|---|
| 549 | #define MTK_WED_RTQM_R2H_MIB(_n) (0xb70 + (_n) * 0x4) |
|---|
| 550 | #define MTK_WED_RTQM_R2Q_MIB(_n) (0xb78 + (_n) * 0x4) |
|---|
| 551 | #define MTK_WED_RTQM_Q2N_MIB 0xb80 |
|---|
| 552 | #define MTK_WED_RTQM_Q2H_MIB(_n) (0xb84 + (_n) * 0x4) |
|---|
| 553 | |
|---|
| 554 | #define MTK_WED_RTQM_Q2B_MIB 0xb8c |
|---|
| 555 | #define MTK_WED_RTQM_PFDBK_MIB 0xb90 |
|---|
| 556 | |
|---|
| 557 | #define MTK_WED_RTQM_ENQ_CFG0 0xbb8 |
|---|
| 558 | #define MTK_WED_RTQM_ENQ_CFG_TXDMAD_FPORT GENMASK(15, 12) |
|---|
| 559 | |
|---|
| 560 | #define MTK_WED_RTQM_FDROP_MIB 0xb84 |
|---|
| 561 | #define MTK_WED_RTQM_ENQ_I2Q_DMAD_CNT 0xbbc |
|---|
| 562 | #define MTK_WED_RTQM_ENQ_I2N_DMAD_CNT 0xbc0 |
|---|
| 563 | #define MTK_WED_RTQM_ENQ_I2Q_PKT_CNT 0xbc4 |
|---|
| 564 | #define MTK_WED_RTQM_ENQ_I2N_PKT_CNT 0xbc8 |
|---|
| 565 | #define MTK_WED_RTQM_ENQ_USED_ENTRY_CNT 0xbcc |
|---|
| 566 | #define MTK_WED_RTQM_ENQ_ERR_CNT 0xbd0 |
|---|
| 567 | |
|---|
| 568 | #define MTK_WED_RTQM_DEQ_DMAD_CNT 0xbd8 |
|---|
| 569 | #define MTK_WED_RTQM_DEQ_Q2I_DMAD_CNT 0xbdc |
|---|
| 570 | #define MTK_WED_RTQM_DEQ_PKT_CNT 0xbe0 |
|---|
| 571 | #define MTK_WED_RTQM_DEQ_Q2I_PKT_CNT 0xbe4 |
|---|
| 572 | #define MTK_WED_RTQM_DEQ_USED_PFDBK_CNT 0xbe8 |
|---|
| 573 | #define MTK_WED_RTQM_DEQ_ERR_CNT 0xbec |
|---|
| 574 | |
|---|
| 575 | #define MTK_WED_RROQM_GLO_CFG 0xc04 |
|---|
| 576 | #define MTK_WED_RROQM_RST_IDX 0xc08 |
|---|
| 577 | #define MTK_WED_RROQM_RST_IDX_MIOD BIT(0) |
|---|
| 578 | #define MTK_WED_RROQM_RST_IDX_FDBK BIT(4) |
|---|
| 579 | |
|---|
| 580 | #define MTK_WED_RROQM_MIOD_CTRL0 0xc40 |
|---|
| 581 | #define MTK_WED_RROQM_MIOD_CTRL1 0xc44 |
|---|
| 582 | #define MTK_WED_RROQM_MIOD_CNT GENMASK(11, 0) |
|---|
| 583 | |
|---|
| 584 | #define MTK_WED_RROQM_MIOD_CTRL2 0xc48 |
|---|
| 585 | #define MTK_WED_RROQM_MIOD_CTRL3 0xc4c |
|---|
| 586 | |
|---|
| 587 | #define MTK_WED_RROQM_FDBK_CTRL0 0xc50 |
|---|
| 588 | #define MTK_WED_RROQM_FDBK_CTRL1 0xc54 |
|---|
| 589 | #define MTK_WED_RROQM_FDBK_CNT GENMASK(11, 0) |
|---|
| 590 | |
|---|
| 591 | #define MTK_WED_RROQM_FDBK_CTRL2 0xc58 |
|---|
| 592 | |
|---|
| 593 | #define MTK_WED_RROQ_BASE_L 0xc80 |
|---|
| 594 | #define MTK_WED_RROQ_BASE_H 0xc84 |
|---|
| 595 | |
|---|
| 596 | #define MTK_WED_RROQM_MIOD_CFG 0xc8c |
|---|
| 597 | #define MTK_WED_RROQM_MIOD_MID_DW GENMASK(5, 0) |
|---|
| 598 | #define MTK_WED_RROQM_MIOD_MOD_DW GENMASK(13, 8) |
|---|
| 599 | #define MTK_WED_RROQM_MIOD_ENTRY_DW GENMASK(22, 16) |
|---|
| 600 | |
|---|
| 601 | #define MTK_WED_RROQM_MID_MIB 0xcc0 |
|---|
| 602 | #define MTK_WED_RROQM_MOD_MIB 0xcc4 |
|---|
| 603 | #define MTK_WED_RROQM_MOD_COHERENT_MIB 0xcc8 |
|---|
| 604 | #define MTK_WED_RROQM_FDBK_MIB 0xcd0 |
|---|
| 605 | #define MTK_WED_RROQM_FDBK_COHERENT_MIB 0xcd4 |
|---|
| 606 | #define MTK_WED_RROQM_FDBK_IND_MIB 0xce0 |
|---|
| 607 | #define MTK_WED_RROQM_FDBK_ENQ_MIB 0xce4 |
|---|
| 608 | #define MTK_WED_RROQM_FDBK_ANC_MIB 0xce8 |
|---|
| 609 | #define MTK_WED_RROQM_FDBK_ANC2H_MIB 0xcec |
|---|
| 610 | |
|---|
| 611 | #define MTK_WED_RX_BM_RX_DMAD 0xd80 |
|---|
| 612 | #define MTK_WED_RX_BM_BASE 0xd84 |
|---|
| 613 | #define MTK_WED_RX_BM_INIT_PTR 0xd88 |
|---|
| 614 | #define MTK_WED_RX_BM_PTR 0xd8c |
|---|
| 615 | #define MTK_WED_RX_BM_PTR_HEAD GENMASK(32, 16) |
|---|
| 616 | #define MTK_WED_RX_BM_PTR_TAIL GENMASK(15, 0) |
|---|
| 617 | |
|---|
| 618 | #define MTK_WED_RX_BM_BLEN 0xd90 |
|---|
| 619 | #define MTK_WED_RX_BM_STS 0xd94 |
|---|
| 620 | #define MTK_WED_RX_BM_INTF2 0xd98 |
|---|
| 621 | #define MTK_WED_RX_BM_INTF 0xd9c |
|---|
| 622 | #define MTK_WED_RX_BM_ERR_STS 0xda8 |
|---|
| 623 | |
|---|
| 624 | #define MTK_RRO_IND_CMD_SIGNATURE 0xe00 |
|---|
| 625 | #define MTK_RRO_IND_CMD_DMA_IDX GENMASK(11, 0) |
|---|
| 626 | #define MTK_RRO_IND_CMD_MAGIC_CNT GENMASK(30, 28) |
|---|
| 627 | |
|---|
| 628 | #define MTK_WED_IND_CMD_RX_CTRL0 0xe04 |
|---|
| 629 | #define MTK_WED_IND_CMD_PROC_IDX GENMASK(11, 0) |
|---|
| 630 | #define MTK_WED_IND_CMD_PREFETCH_FREE_CNT GENMASK(19, 16) |
|---|
| 631 | #define MTK_WED_IND_CMD_MAGIC_CNT GENMASK(30, 28) |
|---|
| 632 | |
|---|
| 633 | #define MTK_WED_IND_CMD_RX_CTRL1 0xe08 |
|---|
| 634 | #define MTK_WED_IND_CMD_RX_CTRL2 0xe0c |
|---|
| 635 | #define MTK_WED_IND_CMD_MAX_CNT GENMASK(11, 0) |
|---|
| 636 | #define MTK_WED_IND_CMD_BASE_M GENMASK(19, 16) |
|---|
| 637 | |
|---|
| 638 | #define MTK_WED_RRO_CFG0 0xe10 |
|---|
| 639 | #define MTK_WED_RRO_CFG1 0xe14 |
|---|
| 640 | #define MTK_WED_RRO_CFG1_MAX_WIN_SZ GENMASK(31, 29) |
|---|
| 641 | #define MTK_WED_RRO_CFG1_ACK_SN_BASE_M GENMASK(19, 16) |
|---|
| 642 | #define MTK_WED_RRO_CFG1_PARTICL_SE_ID GENMASK(11, 0) |
|---|
| 643 | |
|---|
| 644 | #define MTK_WED_ADDR_ELEM_CFG0 0xe18 |
|---|
| 645 | #define MTK_WED_ADDR_ELEM_CFG1 0xe1c |
|---|
| 646 | #define MTK_WED_ADDR_ELEM_PREFETCH_FREE_CNT GENMASK(19, 16) |
|---|
| 647 | |
|---|
| 648 | #define MTK_WED_ADDR_ELEM_TBL_CFG 0xe20 |
|---|
| 649 | #define MTK_WED_ADDR_ELEM_TBL_OFFSET GENMASK(6, 0) |
|---|
| 650 | #define MTK_WED_ADDR_ELEM_TBL_RD_RDY BIT(28) |
|---|
| 651 | #define MTK_WED_ADDR_ELEM_TBL_WR_RDY BIT(29) |
|---|
| 652 | #define MTK_WED_ADDR_ELEM_TBL_RD BIT(30) |
|---|
| 653 | #define MTK_WED_ADDR_ELEM_TBL_WR BIT(31) |
|---|
| 654 | |
|---|
| 655 | #define MTK_WED_RADDR_ELEM_TBL_WDATA 0xe24 |
|---|
| 656 | #define MTK_WED_RADDR_ELEM_TBL_RDATA 0xe28 |
|---|
| 657 | |
|---|
| 658 | #define MTK_WED_PN_CHECK_CFG 0xe30 |
|---|
| 659 | #define MTK_WED_PN_CHECK_SE_ID GENMASK(11, 0) |
|---|
| 660 | #define MTK_WED_PN_CHECK_RD_RDY BIT(28) |
|---|
| 661 | #define MTK_WED_PN_CHECK_WR_RDY BIT(29) |
|---|
| 662 | #define MTK_WED_PN_CHECK_RD BIT(30) |
|---|
| 663 | #define MTK_WED_PN_CHECK_WR BIT(31) |
|---|
| 664 | |
|---|
| 665 | #define MTK_WED_PN_CHECK_WDATA_M 0xe38 |
|---|
| 666 | #define MTK_WED_PN_CHECK_IS_FIRST BIT(17) |
|---|
| 667 | |
|---|
| 668 | #define MTK_WED_RRO_MSDU_PG_RING_CFG(_n) (0xe44 + (_n) * 0x8) |
|---|
| 669 | |
|---|
| 670 | #define MTK_WED_RRO_MSDU_PG_RING2_CFG 0xe58 |
|---|
| 671 | #define MTK_WED_RRO_MSDU_PG_DRV_CLR BIT(26) |
|---|
| 672 | #define MTK_WED_RRO_MSDU_PG_DRV_EN BIT(31) |
|---|
| 673 | |
|---|
| 674 | #define MTK_WED_RRO_MSDU_PG_CTRL0(_n) (0xe5c + (_n) * 0xc) |
|---|
| 675 | #define MTK_WED_RRO_MSDU_PG_CTRL1(_n) (0xe60 + (_n) * 0xc) |
|---|
| 676 | #define MTK_WED_RRO_MSDU_PG_CTRL2(_n) (0xe64 + (_n) * 0xc) |
|---|
| 677 | |
|---|
| 678 | #define MTK_WED_RRO_RX_D_RX(_n) (0xe80 + (_n) * 0x10) |
|---|
| 679 | |
|---|
| 680 | #define MTK_WED_RRO_RX_MAGIC_CNT BIT(13) |
|---|
| 681 | |
|---|
| 682 | #define MTK_WED_RRO_RX_D_CFG(_n) (0xea0 + (_n) * 0x4) |
|---|
| 683 | #define MTK_WED_RRO_RX_D_DRV_CLR BIT(26) |
|---|
| 684 | #define MTK_WED_RRO_RX_D_DRV_EN BIT(31) |
|---|
| 685 | |
|---|
| 686 | #define MTK_WED_RRO_PG_BM_RX_DMAM 0xeb0 |
|---|
| 687 | #define MTK_WED_RRO_PG_BM_RX_SDL0 GENMASK(13, 0) |
|---|
| 688 | |
|---|
| 689 | #define MTK_WED_RRO_PG_BM_BASE 0xeb4 |
|---|
| 690 | #define MTK_WED_RRO_PG_BM_INIT_PTR 0xeb8 |
|---|
| 691 | #define MTK_WED_RRO_PG_BM_SW_TAIL_IDX GENMASK(15, 0) |
|---|
| 692 | #define MTK_WED_RRO_PG_BM_INIT_SW_TAIL_IDX BIT(16) |
|---|
| 693 | |
|---|
| 694 | #define MTK_WED_WPDMA_INT_CTRL_RRO_RX 0xeec |
|---|
| 695 | #define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_EN BIT(0) |
|---|
| 696 | #define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_CLR BIT(1) |
|---|
| 697 | #define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_DONE_TRIG GENMASK(6, 2) |
|---|
| 698 | #define MTK_WED_WPDMA_INT_CTRL_RRO_RX1_EN BIT(8) |
|---|
| 699 | #define MTK_WED_WPDMA_INT_CTRL_RRO_RX1_CLR BIT(9) |
|---|
| 700 | #define MTK_WED_WPDMA_INT_CTRL_RRO_RX1_DONE_TRIG GENMASK(14, 10) |
|---|
| 701 | |
|---|
| 702 | #define MTK_WED_WPDMA_INT_CTRL_RRO_MSDU_PG 0xef4 |
|---|
| 703 | #define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_EN BIT(0) |
|---|
| 704 | #define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_CLR BIT(1) |
|---|
| 705 | #define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_DONE_TRIG GENMASK(6, 2) |
|---|
| 706 | #define MTK_WED_WPDMA_INT_CTRL_RRO_PG1_EN BIT(8) |
|---|
| 707 | #define MTK_WED_WPDMA_INT_CTRL_RRO_PG1_CLR BIT(9) |
|---|
| 708 | #define MTK_WED_WPDMA_INT_CTRL_RRO_PG1_DONE_TRIG GENMASK(14, 10) |
|---|
| 709 | #define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_EN BIT(16) |
|---|
| 710 | #define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_CLR BIT(17) |
|---|
| 711 | #define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_DONE_TRIG GENMASK(22, 18) |
|---|
| 712 | |
|---|
| 713 | #define MTK_WED_RRO_RX_HW_STS 0xf00 |
|---|
| 714 | #define MTK_WED_RX_IND_CMD_BUSY GENMASK(31, 0) |
|---|
| 715 | |
|---|
| 716 | #define MTK_WED_RX_IND_CMD_CNT0 0xf20 |
|---|
| 717 | #define MTK_WED_RX_IND_CMD_DBG_CNT_EN BIT(31) |
|---|
| 718 | |
|---|
| 719 | #define MTK_WED_RX_IND_CMD_CNT(_n) (0xf20 + (_n) * 0x4) |
|---|
| 720 | #define MTK_WED_IND_CMD_MAGIC_CNT_FAIL_CNT GENMASK(15, 0) |
|---|
| 721 | |
|---|
| 722 | #define MTK_WED_RX_ADDR_ELEM_CNT(_n) (0xf48 + (_n) * 0x4) |
|---|
| 723 | #define MTK_WED_ADDR_ELEM_SIG_FAIL_CNT GENMASK(15, 0) |
|---|
| 724 | #define MTK_WED_ADDR_ELEM_FIRST_SIG_FAIL_CNT GENMASK(31, 16) |
|---|
| 725 | #define MTK_WED_ADDR_ELEM_ACKSN_CNT GENMASK(27, 0) |
|---|
| 726 | |
|---|
| 727 | #define MTK_WED_RX_MSDU_PG_CNT(_n) (0xf5c + (_n) * 0x4) |
|---|
| 728 | |
|---|
| 729 | #define MTK_WED_RX_PN_CHK_CNT 0xf70 |
|---|
| 730 | #define MTK_WED_PN_CHK_FAIL_CNT GENMASK(15, 0) |
|---|
| 731 | |
|---|
| 732 | #define MTK_WED_WOCPU_VIEW_MIOD_BASE 0x8000 |
|---|
| 733 | #define MTK_WED_PCIE_INT_MASK 0x0 |
|---|
| 734 | |
|---|
| 735 | #define MTK_WED_AMSDU_FIFO 0x1800 |
|---|
| 736 | #define MTK_WED_AMSDU_IS_PRIOR0_RING BIT(10) |
|---|
| 737 | |
|---|
| 738 | #define MTK_WED_AMSDU_STA_INFO 0x01810 |
|---|
| 739 | #define MTK_WED_AMSDU_STA_INFO_DO_INIT BIT(0) |
|---|
| 740 | #define MTK_WED_AMSDU_STA_INFO_SET_INIT BIT(1) |
|---|
| 741 | |
|---|
| 742 | #define MTK_WED_AMSDU_STA_INFO_INIT 0x01814 |
|---|
| 743 | #define MTK_WED_AMSDU_STA_WTBL_HDRT_MODE BIT(0) |
|---|
| 744 | #define MTK_WED_AMSDU_STA_RMVL BIT(1) |
|---|
| 745 | #define MTK_WED_AMSDU_STA_MAX_AMSDU_LEN GENMASK(7, 2) |
|---|
| 746 | #define MTK_WED_AMSDU_STA_MAX_AMSDU_NUM GENMASK(11, 8) |
|---|
| 747 | |
|---|
| 748 | #define MTK_WED_AMSDU_HIFTXD_BASE_L(_n) (0x1980 + (_n) * 0x4) |
|---|
| 749 | |
|---|
| 750 | #define MTK_WED_AMSDU_PSE 0x1910 |
|---|
| 751 | #define MTK_WED_AMSDU_PSE_RESET BIT(16) |
|---|
| 752 | |
|---|
| 753 | #define MTK_WED_AMSDU_HIFTXD_CFG 0x1968 |
|---|
| 754 | #define MTK_WED_AMSDU_HIFTXD_SRC GENMASK(16, 15) |
|---|
| 755 | |
|---|
| 756 | #define MTK_WED_MON_AMSDU_FIFO_DMAD 0x1a34 |
|---|
| 757 | |
|---|
| 758 | #define MTK_WED_MON_AMSDU_ENG_DMAD(_n) (0x1a80 + (_n) * 0x50) |
|---|
| 759 | #define MTK_WED_MON_AMSDU_ENG_QFPL(_n) (0x1a84 + (_n) * 0x50) |
|---|
| 760 | #define MTK_WED_MON_AMSDU_ENG_QENI(_n) (0x1a88 + (_n) * 0x50) |
|---|
| 761 | #define MTK_WED_MON_AMSDU_ENG_QENO(_n) (0x1a8c + (_n) * 0x50) |
|---|
| 762 | #define MTK_WED_MON_AMSDU_ENG_MERG(_n) (0x1a90 + (_n) * 0x50) |
|---|
| 763 | |
|---|
| 764 | #define MTK_WED_MON_AMSDU_ENG_CNT8(_n) (0x1a94 + (_n) * 0x50) |
|---|
| 765 | #define MTK_WED_AMSDU_ENG_MAX_QGPP_CNT GENMASK(10, 0) |
|---|
| 766 | #define MTK_WED_AMSDU_ENG_MAX_PL_CNT GENMASK(27, 16) |
|---|
| 767 | |
|---|
| 768 | #define MTK_WED_MON_AMSDU_ENG_CNT9(_n) (0x1a98 + (_n) * 0x50) |
|---|
| 769 | #define MTK_WED_AMSDU_ENG_CUR_ENTRY GENMASK(10, 0) |
|---|
| 770 | #define MTK_WED_AMSDU_ENG_MAX_BUF_MERGED GENMASK(20, 16) |
|---|
| 771 | #define MTK_WED_AMSDU_ENG_MAX_MSDU_MERGED GENMASK(28, 24) |
|---|
| 772 | |
|---|
| 773 | #define MTK_WED_MON_AMSDU_QMEM_STS1 0x1e04 |
|---|
| 774 | |
|---|
| 775 | #define MTK_WED_MON_AMSDU_QMEM_CNT(_n) (0x1e0c + (_n) * 0x4) |
|---|
| 776 | #define MTK_WED_AMSDU_QMEM_FQ_CNT GENMASK(27, 16) |
|---|
| 777 | #define MTK_WED_AMSDU_QMEM_SP_QCNT GENMASK(11, 0) |
|---|
| 778 | #define MTK_WED_AMSDU_QMEM_TID0_QCNT GENMASK(27, 16) |
|---|
| 779 | #define MTK_WED_AMSDU_QMEM_TID1_QCNT GENMASK(11, 0) |
|---|
| 780 | #define MTK_WED_AMSDU_QMEM_TID2_QCNT GENMASK(27, 16) |
|---|
| 781 | #define MTK_WED_AMSDU_QMEM_TID3_QCNT GENMASK(11, 0) |
|---|
| 782 | #define MTK_WED_AMSDU_QMEM_TID4_QCNT GENMASK(27, 16) |
|---|
| 783 | #define MTK_WED_AMSDU_QMEM_TID5_QCNT GENMASK(11, 0) |
|---|
| 784 | #define MTK_WED_AMSDU_QMEM_TID6_QCNT GENMASK(27, 16) |
|---|
| 785 | #define MTK_WED_AMSDU_QMEM_TID7_QCNT GENMASK(11, 0) |
|---|
| 786 | |
|---|
| 787 | #define MTK_WED_MON_AMSDU_QMEM_PTR(_n) (0x1e20 + (_n) * 0x4) |
|---|
| 788 | #define MTK_WED_AMSDU_QMEM_FQ_HEAD GENMASK(27, 16) |
|---|
| 789 | #define MTK_WED_AMSDU_QMEM_SP_QHEAD GENMASK(11, 0) |
|---|
| 790 | #define MTK_WED_AMSDU_QMEM_TID0_QHEAD GENMASK(27, 16) |
|---|
| 791 | #define MTK_WED_AMSDU_QMEM_TID1_QHEAD GENMASK(11, 0) |
|---|
| 792 | #define MTK_WED_AMSDU_QMEM_TID2_QHEAD GENMASK(27, 16) |
|---|
| 793 | #define MTK_WED_AMSDU_QMEM_TID3_QHEAD GENMASK(11, 0) |
|---|
| 794 | #define MTK_WED_AMSDU_QMEM_TID4_QHEAD GENMASK(27, 16) |
|---|
| 795 | #define MTK_WED_AMSDU_QMEM_TID5_QHEAD GENMASK(11, 0) |
|---|
| 796 | #define MTK_WED_AMSDU_QMEM_TID6_QHEAD GENMASK(27, 16) |
|---|
| 797 | #define MTK_WED_AMSDU_QMEM_TID7_QHEAD GENMASK(11, 0) |
|---|
| 798 | #define MTK_WED_AMSDU_QMEM_FQ_TAIL GENMASK(27, 16) |
|---|
| 799 | #define MTK_WED_AMSDU_QMEM_SP_QTAIL GENMASK(11, 0) |
|---|
| 800 | #define MTK_WED_AMSDU_QMEM_TID0_QTAIL GENMASK(27, 16) |
|---|
| 801 | #define MTK_WED_AMSDU_QMEM_TID1_QTAIL GENMASK(11, 0) |
|---|
| 802 | #define MTK_WED_AMSDU_QMEM_TID2_QTAIL GENMASK(27, 16) |
|---|
| 803 | #define MTK_WED_AMSDU_QMEM_TID3_QTAIL GENMASK(11, 0) |
|---|
| 804 | #define MTK_WED_AMSDU_QMEM_TID4_QTAIL GENMASK(27, 16) |
|---|
| 805 | #define MTK_WED_AMSDU_QMEM_TID5_QTAIL GENMASK(11, 0) |
|---|
| 806 | #define MTK_WED_AMSDU_QMEM_TID6_QTAIL GENMASK(27, 16) |
|---|
| 807 | #define MTK_WED_AMSDU_QMEM_TID7_QTAIL GENMASK(11, 0) |
|---|
| 808 | |
|---|
| 809 | #define MTK_WED_MON_AMSDU_HIFTXD_FETCH_MSDU(_n) (0x1ec4 + (_n) * 0x4) |
|---|
| 810 | |
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| 811 | #define MTK_WED_PCIE_BASE 0x11280000 |
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| 812 | #define MTK_WED_PCIE_BASE0 0x11300000 |
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| 813 | #define MTK_WED_PCIE_BASE1 0x11310000 |
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| 814 | #define MTK_WED_PCIE_BASE2 0x11290000 |
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| 815 | #endif |
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| 816 | |
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