1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * |
4 | * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> |
5 | * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> |
6 | * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> |
7 | */ |
8 | |
9 | #include <linux/of.h> |
10 | #include <linux/of_mdio.h> |
11 | #include <linux/of_net.h> |
12 | #include <linux/of_address.h> |
13 | #include <linux/mfd/syscon.h> |
14 | #include <linux/platform_device.h> |
15 | #include <linux/regmap.h> |
16 | #include <linux/clk.h> |
17 | #include <linux/pm_runtime.h> |
18 | #include <linux/if_vlan.h> |
19 | #include <linux/reset.h> |
20 | #include <linux/tcp.h> |
21 | #include <linux/interrupt.h> |
22 | #include <linux/pinctrl/devinfo.h> |
23 | #include <linux/phylink.h> |
24 | #include <linux/pcs/pcs-mtk-lynxi.h> |
25 | #include <linux/jhash.h> |
26 | #include <linux/bitfield.h> |
27 | #include <net/dsa.h> |
28 | #include <net/dst_metadata.h> |
29 | #include <net/page_pool/helpers.h> |
30 | |
31 | #include "mtk_eth_soc.h" |
32 | #include "mtk_wed.h" |
33 | |
34 | static int mtk_msg_level = -1; |
35 | module_param_named(msg_level, mtk_msg_level, int, 0); |
36 | MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)" ); |
37 | |
38 | #define MTK_ETHTOOL_STAT(x) { #x, \ |
39 | offsetof(struct mtk_hw_stats, x) / sizeof(u64) } |
40 | |
41 | #define MTK_ETHTOOL_XDP_STAT(x) { #x, \ |
42 | offsetof(struct mtk_hw_stats, xdp_stats.x) / \ |
43 | sizeof(u64) } |
44 | |
45 | static const struct mtk_reg_map mtk_reg_map = { |
46 | .tx_irq_mask = 0x1a1c, |
47 | .tx_irq_status = 0x1a18, |
48 | .pdma = { |
49 | .rx_ptr = 0x0900, |
50 | .rx_cnt_cfg = 0x0904, |
51 | .pcrx_ptr = 0x0908, |
52 | .glo_cfg = 0x0a04, |
53 | .rst_idx = 0x0a08, |
54 | .delay_irq = 0x0a0c, |
55 | .irq_status = 0x0a20, |
56 | .irq_mask = 0x0a28, |
57 | .adma_rx_dbg0 = 0x0a38, |
58 | .int_grp = 0x0a50, |
59 | }, |
60 | .qdma = { |
61 | .qtx_cfg = 0x1800, |
62 | .qtx_sch = 0x1804, |
63 | .rx_ptr = 0x1900, |
64 | .rx_cnt_cfg = 0x1904, |
65 | .qcrx_ptr = 0x1908, |
66 | .glo_cfg = 0x1a04, |
67 | .rst_idx = 0x1a08, |
68 | .delay_irq = 0x1a0c, |
69 | .fc_th = 0x1a10, |
70 | .tx_sch_rate = 0x1a14, |
71 | .int_grp = 0x1a20, |
72 | .hred = 0x1a44, |
73 | .ctx_ptr = 0x1b00, |
74 | .dtx_ptr = 0x1b04, |
75 | .crx_ptr = 0x1b10, |
76 | .drx_ptr = 0x1b14, |
77 | .fq_head = 0x1b20, |
78 | .fq_tail = 0x1b24, |
79 | .fq_count = 0x1b28, |
80 | .fq_blen = 0x1b2c, |
81 | }, |
82 | .gdm1_cnt = 0x2400, |
83 | .gdma_to_ppe = 0x4444, |
84 | .ppe_base = 0x0c00, |
85 | .wdma_base = { |
86 | [0] = 0x2800, |
87 | [1] = 0x2c00, |
88 | }, |
89 | .pse_iq_sta = 0x0110, |
90 | .pse_oq_sta = 0x0118, |
91 | }; |
92 | |
93 | static const struct mtk_reg_map mt7628_reg_map = { |
94 | .tx_irq_mask = 0x0a28, |
95 | .tx_irq_status = 0x0a20, |
96 | .pdma = { |
97 | .rx_ptr = 0x0900, |
98 | .rx_cnt_cfg = 0x0904, |
99 | .pcrx_ptr = 0x0908, |
100 | .glo_cfg = 0x0a04, |
101 | .rst_idx = 0x0a08, |
102 | .delay_irq = 0x0a0c, |
103 | .irq_status = 0x0a20, |
104 | .irq_mask = 0x0a28, |
105 | .int_grp = 0x0a50, |
106 | }, |
107 | }; |
108 | |
109 | static const struct mtk_reg_map mt7986_reg_map = { |
110 | .tx_irq_mask = 0x461c, |
111 | .tx_irq_status = 0x4618, |
112 | .pdma = { |
113 | .rx_ptr = 0x6100, |
114 | .rx_cnt_cfg = 0x6104, |
115 | .pcrx_ptr = 0x6108, |
116 | .glo_cfg = 0x6204, |
117 | .rst_idx = 0x6208, |
118 | .delay_irq = 0x620c, |
119 | .irq_status = 0x6220, |
120 | .irq_mask = 0x6228, |
121 | .adma_rx_dbg0 = 0x6238, |
122 | .int_grp = 0x6250, |
123 | }, |
124 | .qdma = { |
125 | .qtx_cfg = 0x4400, |
126 | .qtx_sch = 0x4404, |
127 | .rx_ptr = 0x4500, |
128 | .rx_cnt_cfg = 0x4504, |
129 | .qcrx_ptr = 0x4508, |
130 | .glo_cfg = 0x4604, |
131 | .rst_idx = 0x4608, |
132 | .delay_irq = 0x460c, |
133 | .fc_th = 0x4610, |
134 | .int_grp = 0x4620, |
135 | .hred = 0x4644, |
136 | .ctx_ptr = 0x4700, |
137 | .dtx_ptr = 0x4704, |
138 | .crx_ptr = 0x4710, |
139 | .drx_ptr = 0x4714, |
140 | .fq_head = 0x4720, |
141 | .fq_tail = 0x4724, |
142 | .fq_count = 0x4728, |
143 | .fq_blen = 0x472c, |
144 | .tx_sch_rate = 0x4798, |
145 | }, |
146 | .gdm1_cnt = 0x1c00, |
147 | .gdma_to_ppe = 0x3333, |
148 | .ppe_base = 0x2000, |
149 | .wdma_base = { |
150 | [0] = 0x4800, |
151 | [1] = 0x4c00, |
152 | }, |
153 | .pse_iq_sta = 0x0180, |
154 | .pse_oq_sta = 0x01a0, |
155 | }; |
156 | |
157 | static const struct mtk_reg_map mt7988_reg_map = { |
158 | .tx_irq_mask = 0x461c, |
159 | .tx_irq_status = 0x4618, |
160 | .pdma = { |
161 | .rx_ptr = 0x6900, |
162 | .rx_cnt_cfg = 0x6904, |
163 | .pcrx_ptr = 0x6908, |
164 | .glo_cfg = 0x6a04, |
165 | .rst_idx = 0x6a08, |
166 | .delay_irq = 0x6a0c, |
167 | .irq_status = 0x6a20, |
168 | .irq_mask = 0x6a28, |
169 | .adma_rx_dbg0 = 0x6a38, |
170 | .int_grp = 0x6a50, |
171 | }, |
172 | .qdma = { |
173 | .qtx_cfg = 0x4400, |
174 | .qtx_sch = 0x4404, |
175 | .rx_ptr = 0x4500, |
176 | .rx_cnt_cfg = 0x4504, |
177 | .qcrx_ptr = 0x4508, |
178 | .glo_cfg = 0x4604, |
179 | .rst_idx = 0x4608, |
180 | .delay_irq = 0x460c, |
181 | .fc_th = 0x4610, |
182 | .int_grp = 0x4620, |
183 | .hred = 0x4644, |
184 | .ctx_ptr = 0x4700, |
185 | .dtx_ptr = 0x4704, |
186 | .crx_ptr = 0x4710, |
187 | .drx_ptr = 0x4714, |
188 | .fq_head = 0x4720, |
189 | .fq_tail = 0x4724, |
190 | .fq_count = 0x4728, |
191 | .fq_blen = 0x472c, |
192 | .tx_sch_rate = 0x4798, |
193 | }, |
194 | .gdm1_cnt = 0x1c00, |
195 | .gdma_to_ppe = 0x3333, |
196 | .ppe_base = 0x2000, |
197 | .wdma_base = { |
198 | [0] = 0x4800, |
199 | [1] = 0x4c00, |
200 | [2] = 0x5000, |
201 | }, |
202 | .pse_iq_sta = 0x0180, |
203 | .pse_oq_sta = 0x01a0, |
204 | }; |
205 | |
206 | /* strings used by ethtool */ |
207 | static const struct mtk_ethtool_stats { |
208 | char str[ETH_GSTRING_LEN]; |
209 | u32 offset; |
210 | } mtk_ethtool_stats[] = { |
211 | MTK_ETHTOOL_STAT(tx_bytes), |
212 | MTK_ETHTOOL_STAT(tx_packets), |
213 | MTK_ETHTOOL_STAT(tx_skip), |
214 | MTK_ETHTOOL_STAT(tx_collisions), |
215 | MTK_ETHTOOL_STAT(rx_bytes), |
216 | MTK_ETHTOOL_STAT(rx_packets), |
217 | MTK_ETHTOOL_STAT(rx_overflow), |
218 | MTK_ETHTOOL_STAT(rx_fcs_errors), |
219 | MTK_ETHTOOL_STAT(rx_short_errors), |
220 | MTK_ETHTOOL_STAT(rx_long_errors), |
221 | MTK_ETHTOOL_STAT(rx_checksum_errors), |
222 | MTK_ETHTOOL_STAT(rx_flow_control_packets), |
223 | MTK_ETHTOOL_XDP_STAT(rx_xdp_redirect), |
224 | MTK_ETHTOOL_XDP_STAT(rx_xdp_pass), |
225 | MTK_ETHTOOL_XDP_STAT(rx_xdp_drop), |
226 | MTK_ETHTOOL_XDP_STAT(rx_xdp_tx), |
227 | MTK_ETHTOOL_XDP_STAT(rx_xdp_tx_errors), |
228 | MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit), |
229 | MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit_errors), |
230 | }; |
231 | |
232 | static const char * const mtk_clks_source_name[] = { |
233 | "ethif" , |
234 | "sgmiitop" , |
235 | "esw" , |
236 | "gp0" , |
237 | "gp1" , |
238 | "gp2" , |
239 | "gp3" , |
240 | "xgp1" , |
241 | "xgp2" , |
242 | "xgp3" , |
243 | "crypto" , |
244 | "fe" , |
245 | "trgpll" , |
246 | "sgmii_tx250m" , |
247 | "sgmii_rx250m" , |
248 | "sgmii_cdr_ref" , |
249 | "sgmii_cdr_fb" , |
250 | "sgmii2_tx250m" , |
251 | "sgmii2_rx250m" , |
252 | "sgmii2_cdr_ref" , |
253 | "sgmii2_cdr_fb" , |
254 | "sgmii_ck" , |
255 | "eth2pll" , |
256 | "wocpu0" , |
257 | "wocpu1" , |
258 | "netsys0" , |
259 | "netsys1" , |
260 | "ethwarp_wocpu2" , |
261 | "ethwarp_wocpu1" , |
262 | "ethwarp_wocpu0" , |
263 | "top_usxgmii0_sel" , |
264 | "top_usxgmii1_sel" , |
265 | "top_sgm0_sel" , |
266 | "top_sgm1_sel" , |
267 | "top_xfi_phy0_xtal_sel" , |
268 | "top_xfi_phy1_xtal_sel" , |
269 | "top_eth_gmii_sel" , |
270 | "top_eth_refck_50m_sel" , |
271 | "top_eth_sys_200m_sel" , |
272 | "top_eth_sys_sel" , |
273 | "top_eth_xgmii_sel" , |
274 | "top_eth_mii_sel" , |
275 | "top_netsys_sel" , |
276 | "top_netsys_500m_sel" , |
277 | "top_netsys_pao_2x_sel" , |
278 | "top_netsys_sync_250m_sel" , |
279 | "top_netsys_ppefb_250m_sel" , |
280 | "top_netsys_warp_sel" , |
281 | }; |
282 | |
283 | void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) |
284 | { |
285 | __raw_writel(val, addr: eth->base + reg); |
286 | } |
287 | |
288 | u32 mtk_r32(struct mtk_eth *eth, unsigned reg) |
289 | { |
290 | return __raw_readl(addr: eth->base + reg); |
291 | } |
292 | |
293 | u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg) |
294 | { |
295 | u32 val; |
296 | |
297 | val = mtk_r32(eth, reg); |
298 | val &= ~mask; |
299 | val |= set; |
300 | mtk_w32(eth, val, reg); |
301 | return reg; |
302 | } |
303 | |
304 | static int mtk_mdio_busy_wait(struct mtk_eth *eth) |
305 | { |
306 | unsigned long t_start = jiffies; |
307 | |
308 | while (1) { |
309 | if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) |
310 | return 0; |
311 | if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) |
312 | break; |
313 | cond_resched(); |
314 | } |
315 | |
316 | dev_err(eth->dev, "mdio: MDIO timeout\n" ); |
317 | return -ETIMEDOUT; |
318 | } |
319 | |
320 | static int _mtk_mdio_write_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, |
321 | u32 write_data) |
322 | { |
323 | int ret; |
324 | |
325 | ret = mtk_mdio_busy_wait(eth); |
326 | if (ret < 0) |
327 | return ret; |
328 | |
329 | mtk_w32(eth, PHY_IAC_ACCESS | |
330 | PHY_IAC_START_C22 | |
331 | PHY_IAC_CMD_WRITE | |
332 | PHY_IAC_REG(phy_reg) | |
333 | PHY_IAC_ADDR(phy_addr) | |
334 | PHY_IAC_DATA(write_data), |
335 | MTK_PHY_IAC); |
336 | |
337 | ret = mtk_mdio_busy_wait(eth); |
338 | if (ret < 0) |
339 | return ret; |
340 | |
341 | return 0; |
342 | } |
343 | |
344 | static int _mtk_mdio_write_c45(struct mtk_eth *eth, u32 phy_addr, |
345 | u32 devad, u32 phy_reg, u32 write_data) |
346 | { |
347 | int ret; |
348 | |
349 | ret = mtk_mdio_busy_wait(eth); |
350 | if (ret < 0) |
351 | return ret; |
352 | |
353 | mtk_w32(eth, PHY_IAC_ACCESS | |
354 | PHY_IAC_START_C45 | |
355 | PHY_IAC_CMD_C45_ADDR | |
356 | PHY_IAC_REG(devad) | |
357 | PHY_IAC_ADDR(phy_addr) | |
358 | PHY_IAC_DATA(phy_reg), |
359 | MTK_PHY_IAC); |
360 | |
361 | ret = mtk_mdio_busy_wait(eth); |
362 | if (ret < 0) |
363 | return ret; |
364 | |
365 | mtk_w32(eth, PHY_IAC_ACCESS | |
366 | PHY_IAC_START_C45 | |
367 | PHY_IAC_CMD_WRITE | |
368 | PHY_IAC_REG(devad) | |
369 | PHY_IAC_ADDR(phy_addr) | |
370 | PHY_IAC_DATA(write_data), |
371 | MTK_PHY_IAC); |
372 | |
373 | ret = mtk_mdio_busy_wait(eth); |
374 | if (ret < 0) |
375 | return ret; |
376 | |
377 | return 0; |
378 | } |
379 | |
380 | static int _mtk_mdio_read_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) |
381 | { |
382 | int ret; |
383 | |
384 | ret = mtk_mdio_busy_wait(eth); |
385 | if (ret < 0) |
386 | return ret; |
387 | |
388 | mtk_w32(eth, PHY_IAC_ACCESS | |
389 | PHY_IAC_START_C22 | |
390 | PHY_IAC_CMD_C22_READ | |
391 | PHY_IAC_REG(phy_reg) | |
392 | PHY_IAC_ADDR(phy_addr), |
393 | MTK_PHY_IAC); |
394 | |
395 | ret = mtk_mdio_busy_wait(eth); |
396 | if (ret < 0) |
397 | return ret; |
398 | |
399 | return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; |
400 | } |
401 | |
402 | static int _mtk_mdio_read_c45(struct mtk_eth *eth, u32 phy_addr, |
403 | u32 devad, u32 phy_reg) |
404 | { |
405 | int ret; |
406 | |
407 | ret = mtk_mdio_busy_wait(eth); |
408 | if (ret < 0) |
409 | return ret; |
410 | |
411 | mtk_w32(eth, PHY_IAC_ACCESS | |
412 | PHY_IAC_START_C45 | |
413 | PHY_IAC_CMD_C45_ADDR | |
414 | PHY_IAC_REG(devad) | |
415 | PHY_IAC_ADDR(phy_addr) | |
416 | PHY_IAC_DATA(phy_reg), |
417 | MTK_PHY_IAC); |
418 | |
419 | ret = mtk_mdio_busy_wait(eth); |
420 | if (ret < 0) |
421 | return ret; |
422 | |
423 | mtk_w32(eth, PHY_IAC_ACCESS | |
424 | PHY_IAC_START_C45 | |
425 | PHY_IAC_CMD_C45_READ | |
426 | PHY_IAC_REG(devad) | |
427 | PHY_IAC_ADDR(phy_addr), |
428 | MTK_PHY_IAC); |
429 | |
430 | ret = mtk_mdio_busy_wait(eth); |
431 | if (ret < 0) |
432 | return ret; |
433 | |
434 | return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; |
435 | } |
436 | |
437 | static int mtk_mdio_write_c22(struct mii_bus *bus, int phy_addr, |
438 | int phy_reg, u16 val) |
439 | { |
440 | struct mtk_eth *eth = bus->priv; |
441 | |
442 | return _mtk_mdio_write_c22(eth, phy_addr, phy_reg, write_data: val); |
443 | } |
444 | |
445 | static int mtk_mdio_write_c45(struct mii_bus *bus, int phy_addr, |
446 | int devad, int phy_reg, u16 val) |
447 | { |
448 | struct mtk_eth *eth = bus->priv; |
449 | |
450 | return _mtk_mdio_write_c45(eth, phy_addr, devad, phy_reg, write_data: val); |
451 | } |
452 | |
453 | static int mtk_mdio_read_c22(struct mii_bus *bus, int phy_addr, int phy_reg) |
454 | { |
455 | struct mtk_eth *eth = bus->priv; |
456 | |
457 | return _mtk_mdio_read_c22(eth, phy_addr, phy_reg); |
458 | } |
459 | |
460 | static int mtk_mdio_read_c45(struct mii_bus *bus, int phy_addr, int devad, |
461 | int phy_reg) |
462 | { |
463 | struct mtk_eth *eth = bus->priv; |
464 | |
465 | return _mtk_mdio_read_c45(eth, phy_addr, devad, phy_reg); |
466 | } |
467 | |
468 | static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, |
469 | phy_interface_t interface) |
470 | { |
471 | u32 val; |
472 | |
473 | val = (interface == PHY_INTERFACE_MODE_TRGMII) ? |
474 | ETHSYS_TRGMII_MT7621_DDR_PLL : 0; |
475 | |
476 | regmap_update_bits(map: eth->ethsys, ETHSYS_CLKCFG0, |
477 | ETHSYS_TRGMII_MT7621_MASK, val); |
478 | |
479 | return 0; |
480 | } |
481 | |
482 | static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, |
483 | phy_interface_t interface) |
484 | { |
485 | int ret; |
486 | |
487 | if (interface == PHY_INTERFACE_MODE_TRGMII) { |
488 | mtk_w32(eth, TRGMII_MODE, INTF_MODE); |
489 | ret = clk_set_rate(clk: eth->clks[MTK_CLK_TRGPLL], rate: 500000000); |
490 | if (ret) |
491 | dev_err(eth->dev, "Failed to set trgmii pll: %d\n" , ret); |
492 | return; |
493 | } |
494 | |
495 | dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n" ); |
496 | } |
497 | |
498 | static void mtk_setup_bridge_switch(struct mtk_eth *eth) |
499 | { |
500 | /* Force Port1 XGMAC Link Up */ |
501 | mtk_m32(eth, mask: 0, MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID), |
502 | MTK_XGMAC_STS(MTK_GMAC1_ID)); |
503 | |
504 | /* Adjust GSW bridge IPG to 11 */ |
505 | mtk_m32(eth, GSWTX_IPG_MASK | GSWRX_IPG_MASK, |
506 | set: (GSW_IPG_11 << GSWTX_IPG_SHIFT) | |
507 | (GSW_IPG_11 << GSWRX_IPG_SHIFT), |
508 | MTK_GSW_CFG); |
509 | } |
510 | |
511 | static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, |
512 | phy_interface_t interface) |
513 | { |
514 | struct mtk_mac *mac = container_of(config, struct mtk_mac, |
515 | phylink_config); |
516 | struct mtk_eth *eth = mac->hw; |
517 | unsigned int sid; |
518 | |
519 | if (interface == PHY_INTERFACE_MODE_SGMII || |
520 | phy_interface_mode_is_8023z(mode: interface)) { |
521 | sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? |
522 | 0 : mac->id; |
523 | |
524 | return eth->sgmii_pcs[sid]; |
525 | } |
526 | |
527 | return NULL; |
528 | } |
529 | |
530 | static void mtk_mac_config(struct phylink_config *config, unsigned int mode, |
531 | const struct phylink_link_state *state) |
532 | { |
533 | struct mtk_mac *mac = container_of(config, struct mtk_mac, |
534 | phylink_config); |
535 | struct mtk_eth *eth = mac->hw; |
536 | int val, ge_mode, err = 0; |
537 | u32 i; |
538 | |
539 | /* MT76x8 has no hardware settings between for the MAC */ |
540 | if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && |
541 | mac->interface != state->interface) { |
542 | /* Setup soc pin functions */ |
543 | switch (state->interface) { |
544 | case PHY_INTERFACE_MODE_TRGMII: |
545 | case PHY_INTERFACE_MODE_RGMII_TXID: |
546 | case PHY_INTERFACE_MODE_RGMII_RXID: |
547 | case PHY_INTERFACE_MODE_RGMII_ID: |
548 | case PHY_INTERFACE_MODE_RGMII: |
549 | case PHY_INTERFACE_MODE_MII: |
550 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { |
551 | err = mtk_gmac_rgmii_path_setup(eth, mac_id: mac->id); |
552 | if (err) |
553 | goto init_err; |
554 | } |
555 | break; |
556 | case PHY_INTERFACE_MODE_1000BASEX: |
557 | case PHY_INTERFACE_MODE_2500BASEX: |
558 | case PHY_INTERFACE_MODE_SGMII: |
559 | err = mtk_gmac_sgmii_path_setup(eth, mac_id: mac->id); |
560 | if (err) |
561 | goto init_err; |
562 | break; |
563 | case PHY_INTERFACE_MODE_GMII: |
564 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { |
565 | err = mtk_gmac_gephy_path_setup(eth, mac_id: mac->id); |
566 | if (err) |
567 | goto init_err; |
568 | } |
569 | break; |
570 | case PHY_INTERFACE_MODE_INTERNAL: |
571 | break; |
572 | default: |
573 | goto err_phy; |
574 | } |
575 | |
576 | /* Setup clock for 1st gmac */ |
577 | if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && |
578 | !phy_interface_mode_is_8023z(mode: state->interface) && |
579 | MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { |
580 | if (MTK_HAS_CAPS(mac->hw->soc->caps, |
581 | MTK_TRGMII_MT7621_CLK)) { |
582 | if (mt7621_gmac0_rgmii_adjust(eth: mac->hw, |
583 | interface: state->interface)) |
584 | goto err_phy; |
585 | } else { |
586 | mtk_gmac0_rgmii_adjust(eth: mac->hw, |
587 | interface: state->interface); |
588 | |
589 | /* mt7623_pad_clk_setup */ |
590 | for (i = 0 ; i < NUM_TRGMII_CTRL; i++) |
591 | mtk_w32(eth: mac->hw, |
592 | TD_DM_DRVP(8) | TD_DM_DRVN(8), |
593 | TRGMII_TD_ODT(i)); |
594 | |
595 | /* Assert/release MT7623 RXC reset */ |
596 | mtk_m32(eth: mac->hw, mask: 0, RXC_RST | RXC_DQSISEL, |
597 | TRGMII_RCK_CTRL); |
598 | mtk_m32(eth: mac->hw, RXC_RST, set: 0, TRGMII_RCK_CTRL); |
599 | } |
600 | } |
601 | |
602 | switch (state->interface) { |
603 | case PHY_INTERFACE_MODE_MII: |
604 | case PHY_INTERFACE_MODE_GMII: |
605 | ge_mode = 1; |
606 | break; |
607 | default: |
608 | ge_mode = 0; |
609 | break; |
610 | } |
611 | |
612 | /* put the gmac into the right mode */ |
613 | regmap_read(map: eth->ethsys, ETHSYS_SYSCFG0, val: &val); |
614 | val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); |
615 | val |= SYSCFG0_GE_MODE(ge_mode, mac->id); |
616 | regmap_write(map: eth->ethsys, ETHSYS_SYSCFG0, val); |
617 | |
618 | mac->interface = state->interface; |
619 | } |
620 | |
621 | /* SGMII */ |
622 | if (state->interface == PHY_INTERFACE_MODE_SGMII || |
623 | phy_interface_mode_is_8023z(mode: state->interface)) { |
624 | /* The path GMAC to SGMII will be enabled once the SGMIISYS is |
625 | * being setup done. |
626 | */ |
627 | regmap_read(map: eth->ethsys, ETHSYS_SYSCFG0, val: &val); |
628 | |
629 | regmap_update_bits(map: eth->ethsys, ETHSYS_SYSCFG0, |
630 | SYSCFG0_SGMII_MASK, |
631 | val: ~(u32)SYSCFG0_SGMII_MASK); |
632 | |
633 | /* Save the syscfg0 value for mac_finish */ |
634 | mac->syscfg0 = val; |
635 | } else if (phylink_autoneg_inband(mode)) { |
636 | dev_err(eth->dev, |
637 | "In-band mode not supported in non SGMII mode!\n" ); |
638 | return; |
639 | } |
640 | |
641 | /* Setup gmac */ |
642 | if (mtk_is_netsys_v3_or_greater(eth) && |
643 | mac->interface == PHY_INTERFACE_MODE_INTERNAL) { |
644 | mtk_w32(eth: mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id)); |
645 | mtk_w32(eth: mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id)); |
646 | |
647 | mtk_setup_bridge_switch(eth); |
648 | } |
649 | |
650 | return; |
651 | |
652 | err_phy: |
653 | dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n" , __func__, |
654 | mac->id, phy_modes(state->interface)); |
655 | return; |
656 | |
657 | init_err: |
658 | dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n" , __func__, |
659 | mac->id, phy_modes(state->interface), err); |
660 | } |
661 | |
662 | static int mtk_mac_finish(struct phylink_config *config, unsigned int mode, |
663 | phy_interface_t interface) |
664 | { |
665 | struct mtk_mac *mac = container_of(config, struct mtk_mac, |
666 | phylink_config); |
667 | struct mtk_eth *eth = mac->hw; |
668 | u32 mcr_cur, mcr_new; |
669 | |
670 | /* Enable SGMII */ |
671 | if (interface == PHY_INTERFACE_MODE_SGMII || |
672 | phy_interface_mode_is_8023z(mode: interface)) |
673 | regmap_update_bits(map: eth->ethsys, ETHSYS_SYSCFG0, |
674 | SYSCFG0_SGMII_MASK, val: mac->syscfg0); |
675 | |
676 | /* Setup gmac */ |
677 | mcr_cur = mtk_r32(eth: mac->hw, MTK_MAC_MCR(mac->id)); |
678 | mcr_new = mcr_cur; |
679 | mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | |
680 | MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_RX_FIFO_CLR_DIS; |
681 | |
682 | /* Only update control register when needed! */ |
683 | if (mcr_new != mcr_cur) |
684 | mtk_w32(eth: mac->hw, val: mcr_new, MTK_MAC_MCR(mac->id)); |
685 | |
686 | return 0; |
687 | } |
688 | |
689 | static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, |
690 | phy_interface_t interface) |
691 | { |
692 | struct mtk_mac *mac = container_of(config, struct mtk_mac, |
693 | phylink_config); |
694 | u32 mcr = mtk_r32(eth: mac->hw, MTK_MAC_MCR(mac->id)); |
695 | |
696 | mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK); |
697 | mtk_w32(eth: mac->hw, val: mcr, MTK_MAC_MCR(mac->id)); |
698 | } |
699 | |
700 | static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx, |
701 | int speed) |
702 | { |
703 | const struct mtk_soc_data *soc = eth->soc; |
704 | u32 ofs, val; |
705 | |
706 | if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) |
707 | return; |
708 | |
709 | val = MTK_QTX_SCH_MIN_RATE_EN | |
710 | /* minimum: 10 Mbps */ |
711 | FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | |
712 | FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | |
713 | MTK_QTX_SCH_LEAKY_BUCKET_SIZE; |
714 | if (mtk_is_netsys_v1(eth)) |
715 | val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; |
716 | |
717 | if (IS_ENABLED(CONFIG_SOC_MT7621)) { |
718 | switch (speed) { |
719 | case SPEED_10: |
720 | val |= MTK_QTX_SCH_MAX_RATE_EN | |
721 | FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | |
722 | FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 2) | |
723 | FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); |
724 | break; |
725 | case SPEED_100: |
726 | val |= MTK_QTX_SCH_MAX_RATE_EN | |
727 | FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | |
728 | FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 3); |
729 | FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); |
730 | break; |
731 | case SPEED_1000: |
732 | val |= MTK_QTX_SCH_MAX_RATE_EN | |
733 | FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 105) | |
734 | FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | |
735 | FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); |
736 | break; |
737 | default: |
738 | break; |
739 | } |
740 | } else { |
741 | switch (speed) { |
742 | case SPEED_10: |
743 | val |= MTK_QTX_SCH_MAX_RATE_EN | |
744 | FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | |
745 | FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | |
746 | FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); |
747 | break; |
748 | case SPEED_100: |
749 | val |= MTK_QTX_SCH_MAX_RATE_EN | |
750 | FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | |
751 | FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5); |
752 | FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); |
753 | break; |
754 | case SPEED_1000: |
755 | val |= MTK_QTX_SCH_MAX_RATE_EN | |
756 | FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 10) | |
757 | FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5) | |
758 | FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); |
759 | break; |
760 | default: |
761 | break; |
762 | } |
763 | } |
764 | |
765 | ofs = MTK_QTX_OFFSET * idx; |
766 | mtk_w32(eth, val, reg: soc->reg_map->qdma.qtx_sch + ofs); |
767 | } |
768 | |
769 | static void mtk_mac_link_up(struct phylink_config *config, |
770 | struct phy_device *phy, |
771 | unsigned int mode, phy_interface_t interface, |
772 | int speed, int duplex, bool tx_pause, bool rx_pause) |
773 | { |
774 | struct mtk_mac *mac = container_of(config, struct mtk_mac, |
775 | phylink_config); |
776 | u32 mcr; |
777 | |
778 | mcr = mtk_r32(eth: mac->hw, MTK_MAC_MCR(mac->id)); |
779 | mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | |
780 | MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | |
781 | MAC_MCR_FORCE_RX_FC); |
782 | |
783 | /* Configure speed */ |
784 | mac->speed = speed; |
785 | switch (speed) { |
786 | case SPEED_2500: |
787 | case SPEED_1000: |
788 | mcr |= MAC_MCR_SPEED_1000; |
789 | break; |
790 | case SPEED_100: |
791 | mcr |= MAC_MCR_SPEED_100; |
792 | break; |
793 | } |
794 | |
795 | /* Configure duplex */ |
796 | if (duplex == DUPLEX_FULL) |
797 | mcr |= MAC_MCR_FORCE_DPX; |
798 | |
799 | /* Configure pause modes - phylink will avoid these for half duplex */ |
800 | if (tx_pause) |
801 | mcr |= MAC_MCR_FORCE_TX_FC; |
802 | if (rx_pause) |
803 | mcr |= MAC_MCR_FORCE_RX_FC; |
804 | |
805 | mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK; |
806 | mtk_w32(eth: mac->hw, val: mcr, MTK_MAC_MCR(mac->id)); |
807 | } |
808 | |
809 | static const struct phylink_mac_ops mtk_phylink_ops = { |
810 | .mac_select_pcs = mtk_mac_select_pcs, |
811 | .mac_config = mtk_mac_config, |
812 | .mac_finish = mtk_mac_finish, |
813 | .mac_link_down = mtk_mac_link_down, |
814 | .mac_link_up = mtk_mac_link_up, |
815 | }; |
816 | |
817 | static int mtk_mdio_init(struct mtk_eth *eth) |
818 | { |
819 | unsigned int max_clk = 2500000, divider; |
820 | struct device_node *mii_np; |
821 | int ret; |
822 | u32 val; |
823 | |
824 | mii_np = of_get_child_by_name(node: eth->dev->of_node, name: "mdio-bus" ); |
825 | if (!mii_np) { |
826 | dev_err(eth->dev, "no %s child node found" , "mdio-bus" ); |
827 | return -ENODEV; |
828 | } |
829 | |
830 | if (!of_device_is_available(device: mii_np)) { |
831 | ret = -ENODEV; |
832 | goto err_put_node; |
833 | } |
834 | |
835 | eth->mii_bus = devm_mdiobus_alloc(dev: eth->dev); |
836 | if (!eth->mii_bus) { |
837 | ret = -ENOMEM; |
838 | goto err_put_node; |
839 | } |
840 | |
841 | eth->mii_bus->name = "mdio" ; |
842 | eth->mii_bus->read = mtk_mdio_read_c22; |
843 | eth->mii_bus->write = mtk_mdio_write_c22; |
844 | eth->mii_bus->read_c45 = mtk_mdio_read_c45; |
845 | eth->mii_bus->write_c45 = mtk_mdio_write_c45; |
846 | eth->mii_bus->priv = eth; |
847 | eth->mii_bus->parent = eth->dev; |
848 | |
849 | snprintf(buf: eth->mii_bus->id, MII_BUS_ID_SIZE, fmt: "%pOFn" , mii_np); |
850 | |
851 | if (!of_property_read_u32(np: mii_np, propname: "clock-frequency" , out_value: &val)) { |
852 | if (val > MDC_MAX_FREQ || val < MDC_MAX_FREQ / MDC_MAX_DIVIDER) { |
853 | dev_err(eth->dev, "MDIO clock frequency out of range" ); |
854 | ret = -EINVAL; |
855 | goto err_put_node; |
856 | } |
857 | max_clk = val; |
858 | } |
859 | divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63); |
860 | |
861 | /* Configure MDC Turbo Mode */ |
862 | if (mtk_is_netsys_v3_or_greater(eth)) |
863 | mtk_m32(eth, mask: 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3); |
864 | |
865 | /* Configure MDC Divider */ |
866 | val = FIELD_PREP(PPSC_MDC_CFG, divider); |
867 | if (!mtk_is_netsys_v3_or_greater(eth)) |
868 | val |= PPSC_MDC_TURBO; |
869 | mtk_m32(eth, PPSC_MDC_CFG, set: val, MTK_PPSC); |
870 | |
871 | dev_dbg(eth->dev, "MDC is running on %d Hz\n" , MDC_MAX_FREQ / divider); |
872 | |
873 | ret = of_mdiobus_register(mdio: eth->mii_bus, np: mii_np); |
874 | |
875 | err_put_node: |
876 | of_node_put(node: mii_np); |
877 | return ret; |
878 | } |
879 | |
880 | static void mtk_mdio_cleanup(struct mtk_eth *eth) |
881 | { |
882 | if (!eth->mii_bus) |
883 | return; |
884 | |
885 | mdiobus_unregister(bus: eth->mii_bus); |
886 | } |
887 | |
888 | static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) |
889 | { |
890 | unsigned long flags; |
891 | u32 val; |
892 | |
893 | spin_lock_irqsave(ð->tx_irq_lock, flags); |
894 | val = mtk_r32(eth, reg: eth->soc->reg_map->tx_irq_mask); |
895 | mtk_w32(eth, val: val & ~mask, reg: eth->soc->reg_map->tx_irq_mask); |
896 | spin_unlock_irqrestore(lock: ð->tx_irq_lock, flags); |
897 | } |
898 | |
899 | static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) |
900 | { |
901 | unsigned long flags; |
902 | u32 val; |
903 | |
904 | spin_lock_irqsave(ð->tx_irq_lock, flags); |
905 | val = mtk_r32(eth, reg: eth->soc->reg_map->tx_irq_mask); |
906 | mtk_w32(eth, val: val | mask, reg: eth->soc->reg_map->tx_irq_mask); |
907 | spin_unlock_irqrestore(lock: ð->tx_irq_lock, flags); |
908 | } |
909 | |
910 | static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) |
911 | { |
912 | unsigned long flags; |
913 | u32 val; |
914 | |
915 | spin_lock_irqsave(ð->rx_irq_lock, flags); |
916 | val = mtk_r32(eth, reg: eth->soc->reg_map->pdma.irq_mask); |
917 | mtk_w32(eth, val: val & ~mask, reg: eth->soc->reg_map->pdma.irq_mask); |
918 | spin_unlock_irqrestore(lock: ð->rx_irq_lock, flags); |
919 | } |
920 | |
921 | static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) |
922 | { |
923 | unsigned long flags; |
924 | u32 val; |
925 | |
926 | spin_lock_irqsave(ð->rx_irq_lock, flags); |
927 | val = mtk_r32(eth, reg: eth->soc->reg_map->pdma.irq_mask); |
928 | mtk_w32(eth, val: val | mask, reg: eth->soc->reg_map->pdma.irq_mask); |
929 | spin_unlock_irqrestore(lock: ð->rx_irq_lock, flags); |
930 | } |
931 | |
932 | static int mtk_set_mac_address(struct net_device *dev, void *p) |
933 | { |
934 | int ret = eth_mac_addr(dev, p); |
935 | struct mtk_mac *mac = netdev_priv(dev); |
936 | struct mtk_eth *eth = mac->hw; |
937 | const char *macaddr = dev->dev_addr; |
938 | |
939 | if (ret) |
940 | return ret; |
941 | |
942 | if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) |
943 | return -EBUSY; |
944 | |
945 | spin_lock_bh(lock: &mac->hw->page_lock); |
946 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { |
947 | mtk_w32(eth: mac->hw, val: (macaddr[0] << 8) | macaddr[1], |
948 | MT7628_SDM_MAC_ADRH); |
949 | mtk_w32(eth: mac->hw, val: (macaddr[2] << 24) | (macaddr[3] << 16) | |
950 | (macaddr[4] << 8) | macaddr[5], |
951 | MT7628_SDM_MAC_ADRL); |
952 | } else { |
953 | mtk_w32(eth: mac->hw, val: (macaddr[0] << 8) | macaddr[1], |
954 | MTK_GDMA_MAC_ADRH(mac->id)); |
955 | mtk_w32(eth: mac->hw, val: (macaddr[2] << 24) | (macaddr[3] << 16) | |
956 | (macaddr[4] << 8) | macaddr[5], |
957 | MTK_GDMA_MAC_ADRL(mac->id)); |
958 | } |
959 | spin_unlock_bh(lock: &mac->hw->page_lock); |
960 | |
961 | return 0; |
962 | } |
963 | |
964 | void mtk_stats_update_mac(struct mtk_mac *mac) |
965 | { |
966 | struct mtk_hw_stats *hw_stats = mac->hw_stats; |
967 | struct mtk_eth *eth = mac->hw; |
968 | |
969 | u64_stats_update_begin(syncp: &hw_stats->syncp); |
970 | |
971 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { |
972 | hw_stats->tx_packets += mtk_r32(eth: mac->hw, MT7628_SDM_TPCNT); |
973 | hw_stats->tx_bytes += mtk_r32(eth: mac->hw, MT7628_SDM_TBCNT); |
974 | hw_stats->rx_packets += mtk_r32(eth: mac->hw, MT7628_SDM_RPCNT); |
975 | hw_stats->rx_bytes += mtk_r32(eth: mac->hw, MT7628_SDM_RBCNT); |
976 | hw_stats->rx_checksum_errors += |
977 | mtk_r32(eth: mac->hw, MT7628_SDM_CS_ERR); |
978 | } else { |
979 | const struct mtk_reg_map *reg_map = eth->soc->reg_map; |
980 | unsigned int offs = hw_stats->reg_offset; |
981 | u64 stats; |
982 | |
983 | hw_stats->rx_bytes += mtk_r32(eth: mac->hw, reg: reg_map->gdm1_cnt + offs); |
984 | stats = mtk_r32(eth: mac->hw, reg: reg_map->gdm1_cnt + 0x4 + offs); |
985 | if (stats) |
986 | hw_stats->rx_bytes += (stats << 32); |
987 | hw_stats->rx_packets += |
988 | mtk_r32(eth: mac->hw, reg: reg_map->gdm1_cnt + 0x8 + offs); |
989 | hw_stats->rx_overflow += |
990 | mtk_r32(eth: mac->hw, reg: reg_map->gdm1_cnt + 0x10 + offs); |
991 | hw_stats->rx_fcs_errors += |
992 | mtk_r32(eth: mac->hw, reg: reg_map->gdm1_cnt + 0x14 + offs); |
993 | hw_stats->rx_short_errors += |
994 | mtk_r32(eth: mac->hw, reg: reg_map->gdm1_cnt + 0x18 + offs); |
995 | hw_stats->rx_long_errors += |
996 | mtk_r32(eth: mac->hw, reg: reg_map->gdm1_cnt + 0x1c + offs); |
997 | hw_stats->rx_checksum_errors += |
998 | mtk_r32(eth: mac->hw, reg: reg_map->gdm1_cnt + 0x20 + offs); |
999 | hw_stats->rx_flow_control_packets += |
1000 | mtk_r32(eth: mac->hw, reg: reg_map->gdm1_cnt + 0x24 + offs); |
1001 | |
1002 | if (mtk_is_netsys_v3_or_greater(eth)) { |
1003 | hw_stats->tx_skip += |
1004 | mtk_r32(eth: mac->hw, reg: reg_map->gdm1_cnt + 0x50 + offs); |
1005 | hw_stats->tx_collisions += |
1006 | mtk_r32(eth: mac->hw, reg: reg_map->gdm1_cnt + 0x54 + offs); |
1007 | hw_stats->tx_bytes += |
1008 | mtk_r32(eth: mac->hw, reg: reg_map->gdm1_cnt + 0x40 + offs); |
1009 | stats = mtk_r32(eth: mac->hw, reg: reg_map->gdm1_cnt + 0x44 + offs); |
1010 | if (stats) |
1011 | hw_stats->tx_bytes += (stats << 32); |
1012 | hw_stats->tx_packets += |
1013 | mtk_r32(eth: mac->hw, reg: reg_map->gdm1_cnt + 0x48 + offs); |
1014 | } else { |
1015 | hw_stats->tx_skip += |
1016 | mtk_r32(eth: mac->hw, reg: reg_map->gdm1_cnt + 0x28 + offs); |
1017 | hw_stats->tx_collisions += |
1018 | mtk_r32(eth: mac->hw, reg: reg_map->gdm1_cnt + 0x2c + offs); |
1019 | hw_stats->tx_bytes += |
1020 | mtk_r32(eth: mac->hw, reg: reg_map->gdm1_cnt + 0x30 + offs); |
1021 | stats = mtk_r32(eth: mac->hw, reg: reg_map->gdm1_cnt + 0x34 + offs); |
1022 | if (stats) |
1023 | hw_stats->tx_bytes += (stats << 32); |
1024 | hw_stats->tx_packets += |
1025 | mtk_r32(eth: mac->hw, reg: reg_map->gdm1_cnt + 0x38 + offs); |
1026 | } |
1027 | } |
1028 | |
1029 | u64_stats_update_end(syncp: &hw_stats->syncp); |
1030 | } |
1031 | |
1032 | static void mtk_stats_update(struct mtk_eth *eth) |
1033 | { |
1034 | int i; |
1035 | |
1036 | for (i = 0; i < MTK_MAX_DEVS; i++) { |
1037 | if (!eth->mac[i] || !eth->mac[i]->hw_stats) |
1038 | continue; |
1039 | if (spin_trylock(lock: ð->mac[i]->hw_stats->stats_lock)) { |
1040 | mtk_stats_update_mac(mac: eth->mac[i]); |
1041 | spin_unlock(lock: ð->mac[i]->hw_stats->stats_lock); |
1042 | } |
1043 | } |
1044 | } |
1045 | |
1046 | static void mtk_get_stats64(struct net_device *dev, |
1047 | struct rtnl_link_stats64 *storage) |
1048 | { |
1049 | struct mtk_mac *mac = netdev_priv(dev); |
1050 | struct mtk_hw_stats *hw_stats = mac->hw_stats; |
1051 | unsigned int start; |
1052 | |
1053 | if (netif_running(dev) && netif_device_present(dev)) { |
1054 | if (spin_trylock_bh(lock: &hw_stats->stats_lock)) { |
1055 | mtk_stats_update_mac(mac); |
1056 | spin_unlock_bh(lock: &hw_stats->stats_lock); |
1057 | } |
1058 | } |
1059 | |
1060 | do { |
1061 | start = u64_stats_fetch_begin(syncp: &hw_stats->syncp); |
1062 | storage->rx_packets = hw_stats->rx_packets; |
1063 | storage->tx_packets = hw_stats->tx_packets; |
1064 | storage->rx_bytes = hw_stats->rx_bytes; |
1065 | storage->tx_bytes = hw_stats->tx_bytes; |
1066 | storage->collisions = hw_stats->tx_collisions; |
1067 | storage->rx_length_errors = hw_stats->rx_short_errors + |
1068 | hw_stats->rx_long_errors; |
1069 | storage->rx_over_errors = hw_stats->rx_overflow; |
1070 | storage->rx_crc_errors = hw_stats->rx_fcs_errors; |
1071 | storage->rx_errors = hw_stats->rx_checksum_errors; |
1072 | storage->tx_aborted_errors = hw_stats->tx_skip; |
1073 | } while (u64_stats_fetch_retry(syncp: &hw_stats->syncp, start)); |
1074 | |
1075 | storage->tx_errors = dev->stats.tx_errors; |
1076 | storage->rx_dropped = dev->stats.rx_dropped; |
1077 | storage->tx_dropped = dev->stats.tx_dropped; |
1078 | } |
1079 | |
1080 | static inline int mtk_max_frag_size(int mtu) |
1081 | { |
1082 | /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ |
1083 | if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K) |
1084 | mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; |
1085 | |
1086 | return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + |
1087 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); |
1088 | } |
1089 | |
1090 | static inline int mtk_max_buf_size(int frag_size) |
1091 | { |
1092 | int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - |
1093 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); |
1094 | |
1095 | WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K); |
1096 | |
1097 | return buf_size; |
1098 | } |
1099 | |
1100 | static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd, |
1101 | struct mtk_rx_dma_v2 *dma_rxd) |
1102 | { |
1103 | rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); |
1104 | if (!(rxd->rxd2 & RX_DMA_DONE)) |
1105 | return false; |
1106 | |
1107 | rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); |
1108 | rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); |
1109 | rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); |
1110 | if (mtk_is_netsys_v2_or_greater(eth)) { |
1111 | rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); |
1112 | rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); |
1113 | } |
1114 | |
1115 | return true; |
1116 | } |
1117 | |
1118 | static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask) |
1119 | { |
1120 | unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH); |
1121 | unsigned long data; |
1122 | |
1123 | data = __get_free_pages(gfp_mask: gfp_mask | __GFP_COMP | __GFP_NOWARN, |
1124 | order: get_order(size)); |
1125 | |
1126 | return (void *)data; |
1127 | } |
1128 | |
1129 | /* the qdma core needs scratch memory to be setup */ |
1130 | static int mtk_init_fq_dma(struct mtk_eth *eth) |
1131 | { |
1132 | const struct mtk_soc_data *soc = eth->soc; |
1133 | dma_addr_t phy_ring_tail; |
1134 | int cnt = MTK_QDMA_RING_SIZE; |
1135 | dma_addr_t dma_addr; |
1136 | int i; |
1137 | |
1138 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) |
1139 | eth->scratch_ring = eth->sram_base; |
1140 | else |
1141 | eth->scratch_ring = dma_alloc_coherent(dev: eth->dma_dev, |
1142 | size: cnt * soc->txrx.txd_size, |
1143 | dma_handle: ð->phy_scratch_ring, |
1144 | GFP_KERNEL); |
1145 | if (unlikely(!eth->scratch_ring)) |
1146 | return -ENOMEM; |
1147 | |
1148 | eth->scratch_head = kcalloc(n: cnt, MTK_QDMA_PAGE_SIZE, GFP_KERNEL); |
1149 | if (unlikely(!eth->scratch_head)) |
1150 | return -ENOMEM; |
1151 | |
1152 | dma_addr = dma_map_single(eth->dma_dev, |
1153 | eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, |
1154 | DMA_FROM_DEVICE); |
1155 | if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) |
1156 | return -ENOMEM; |
1157 | |
1158 | phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1); |
1159 | |
1160 | for (i = 0; i < cnt; i++) { |
1161 | dma_addr_t addr = dma_addr + i * MTK_QDMA_PAGE_SIZE; |
1162 | struct mtk_tx_dma_v2 *txd; |
1163 | |
1164 | txd = eth->scratch_ring + i * soc->txrx.txd_size; |
1165 | txd->txd1 = addr; |
1166 | if (i < cnt - 1) |
1167 | txd->txd2 = eth->phy_scratch_ring + |
1168 | (i + 1) * soc->txrx.txd_size; |
1169 | |
1170 | txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); |
1171 | if (MTK_HAS_CAPS(soc->caps, MTK_36BIT_DMA)) |
1172 | txd->txd3 |= TX_DMA_PREP_ADDR64(addr); |
1173 | txd->txd4 = 0; |
1174 | if (mtk_is_netsys_v2_or_greater(eth)) { |
1175 | txd->txd5 = 0; |
1176 | txd->txd6 = 0; |
1177 | txd->txd7 = 0; |
1178 | txd->txd8 = 0; |
1179 | } |
1180 | } |
1181 | |
1182 | mtk_w32(eth, val: eth->phy_scratch_ring, reg: soc->reg_map->qdma.fq_head); |
1183 | mtk_w32(eth, val: phy_ring_tail, reg: soc->reg_map->qdma.fq_tail); |
1184 | mtk_w32(eth, val: (cnt << 16) | cnt, reg: soc->reg_map->qdma.fq_count); |
1185 | mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, reg: soc->reg_map->qdma.fq_blen); |
1186 | |
1187 | return 0; |
1188 | } |
1189 | |
1190 | static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) |
1191 | { |
1192 | return ring->dma + (desc - ring->phys); |
1193 | } |
1194 | |
1195 | static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, |
1196 | void *txd, u32 txd_size) |
1197 | { |
1198 | int idx = (txd - ring->dma) / txd_size; |
1199 | |
1200 | return &ring->buf[idx]; |
1201 | } |
1202 | |
1203 | static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, |
1204 | struct mtk_tx_dma *dma) |
1205 | { |
1206 | return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma; |
1207 | } |
1208 | |
1209 | static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size) |
1210 | { |
1211 | return (dma - ring->dma) / txd_size; |
1212 | } |
1213 | |
1214 | static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, |
1215 | struct xdp_frame_bulk *bq, bool napi) |
1216 | { |
1217 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
1218 | if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { |
1219 | dma_unmap_single(eth->dma_dev, |
1220 | dma_unmap_addr(tx_buf, dma_addr0), |
1221 | dma_unmap_len(tx_buf, dma_len0), |
1222 | DMA_TO_DEVICE); |
1223 | } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { |
1224 | dma_unmap_page(eth->dma_dev, |
1225 | dma_unmap_addr(tx_buf, dma_addr0), |
1226 | dma_unmap_len(tx_buf, dma_len0), |
1227 | DMA_TO_DEVICE); |
1228 | } |
1229 | } else { |
1230 | if (dma_unmap_len(tx_buf, dma_len0)) { |
1231 | dma_unmap_page(eth->dma_dev, |
1232 | dma_unmap_addr(tx_buf, dma_addr0), |
1233 | dma_unmap_len(tx_buf, dma_len0), |
1234 | DMA_TO_DEVICE); |
1235 | } |
1236 | |
1237 | if (dma_unmap_len(tx_buf, dma_len1)) { |
1238 | dma_unmap_page(eth->dma_dev, |
1239 | dma_unmap_addr(tx_buf, dma_addr1), |
1240 | dma_unmap_len(tx_buf, dma_len1), |
1241 | DMA_TO_DEVICE); |
1242 | } |
1243 | } |
1244 | |
1245 | if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { |
1246 | if (tx_buf->type == MTK_TYPE_SKB) { |
1247 | struct sk_buff *skb = tx_buf->data; |
1248 | |
1249 | if (napi) |
1250 | napi_consume_skb(skb, budget: napi); |
1251 | else |
1252 | dev_kfree_skb_any(skb); |
1253 | } else { |
1254 | struct xdp_frame *xdpf = tx_buf->data; |
1255 | |
1256 | if (napi && tx_buf->type == MTK_TYPE_XDP_TX) |
1257 | xdp_return_frame_rx_napi(xdpf); |
1258 | else if (bq) |
1259 | xdp_return_frame_bulk(xdpf, bq); |
1260 | else |
1261 | xdp_return_frame(xdpf); |
1262 | } |
1263 | } |
1264 | tx_buf->flags = 0; |
1265 | tx_buf->data = NULL; |
1266 | } |
1267 | |
1268 | static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, |
1269 | struct mtk_tx_dma *txd, dma_addr_t mapped_addr, |
1270 | size_t size, int idx) |
1271 | { |
1272 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
1273 | dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); |
1274 | dma_unmap_len_set(tx_buf, dma_len0, size); |
1275 | } else { |
1276 | if (idx & 1) { |
1277 | txd->txd3 = mapped_addr; |
1278 | txd->txd2 |= TX_DMA_PLEN1(size); |
1279 | dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); |
1280 | dma_unmap_len_set(tx_buf, dma_len1, size); |
1281 | } else { |
1282 | tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; |
1283 | txd->txd1 = mapped_addr; |
1284 | txd->txd2 = TX_DMA_PLEN0(size); |
1285 | dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); |
1286 | dma_unmap_len_set(tx_buf, dma_len0, size); |
1287 | } |
1288 | } |
1289 | } |
1290 | |
1291 | static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd, |
1292 | struct mtk_tx_dma_desc_info *info) |
1293 | { |
1294 | struct mtk_mac *mac = netdev_priv(dev); |
1295 | struct mtk_eth *eth = mac->hw; |
1296 | struct mtk_tx_dma *desc = txd; |
1297 | u32 data; |
1298 | |
1299 | WRITE_ONCE(desc->txd1, info->addr); |
1300 | |
1301 | data = TX_DMA_SWC | TX_DMA_PLEN0(info->size) | |
1302 | FIELD_PREP(TX_DMA_PQID, info->qid); |
1303 | if (info->last) |
1304 | data |= TX_DMA_LS0; |
1305 | WRITE_ONCE(desc->txd3, data); |
1306 | |
1307 | data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */ |
1308 | if (info->first) { |
1309 | if (info->gso) |
1310 | data |= TX_DMA_TSO; |
1311 | /* tx checksum offload */ |
1312 | if (info->csum) |
1313 | data |= TX_DMA_CHKSUM; |
1314 | /* vlan header offload */ |
1315 | if (info->vlan) |
1316 | data |= TX_DMA_INS_VLAN | info->vlan_tci; |
1317 | } |
1318 | WRITE_ONCE(desc->txd4, data); |
1319 | } |
1320 | |
1321 | static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd, |
1322 | struct mtk_tx_dma_desc_info *info) |
1323 | { |
1324 | struct mtk_mac *mac = netdev_priv(dev); |
1325 | struct mtk_tx_dma_v2 *desc = txd; |
1326 | struct mtk_eth *eth = mac->hw; |
1327 | u32 data; |
1328 | |
1329 | WRITE_ONCE(desc->txd1, info->addr); |
1330 | |
1331 | data = TX_DMA_PLEN0(info->size); |
1332 | if (info->last) |
1333 | data |= TX_DMA_LS0; |
1334 | |
1335 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) |
1336 | data |= TX_DMA_PREP_ADDR64(info->addr); |
1337 | |
1338 | WRITE_ONCE(desc->txd3, data); |
1339 | |
1340 | /* set forward port */ |
1341 | switch (mac->id) { |
1342 | case MTK_GMAC1_ID: |
1343 | data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2; |
1344 | break; |
1345 | case MTK_GMAC2_ID: |
1346 | data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2; |
1347 | break; |
1348 | case MTK_GMAC3_ID: |
1349 | data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2; |
1350 | break; |
1351 | } |
1352 | |
1353 | data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); |
1354 | WRITE_ONCE(desc->txd4, data); |
1355 | |
1356 | data = 0; |
1357 | if (info->first) { |
1358 | if (info->gso) |
1359 | data |= TX_DMA_TSO_V2; |
1360 | /* tx checksum offload */ |
1361 | if (info->csum) |
1362 | data |= TX_DMA_CHKSUM_V2; |
1363 | if (mtk_is_netsys_v3_or_greater(eth) && netdev_uses_dsa(dev)) |
1364 | data |= TX_DMA_SPTAG_V3; |
1365 | } |
1366 | WRITE_ONCE(desc->txd5, data); |
1367 | |
1368 | data = 0; |
1369 | if (info->first && info->vlan) |
1370 | data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci; |
1371 | WRITE_ONCE(desc->txd6, data); |
1372 | |
1373 | WRITE_ONCE(desc->txd7, 0); |
1374 | WRITE_ONCE(desc->txd8, 0); |
1375 | } |
1376 | |
1377 | static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd, |
1378 | struct mtk_tx_dma_desc_info *info) |
1379 | { |
1380 | struct mtk_mac *mac = netdev_priv(dev); |
1381 | struct mtk_eth *eth = mac->hw; |
1382 | |
1383 | if (mtk_is_netsys_v2_or_greater(eth)) |
1384 | mtk_tx_set_dma_desc_v2(dev, txd, info); |
1385 | else |
1386 | mtk_tx_set_dma_desc_v1(dev, txd, info); |
1387 | } |
1388 | |
1389 | static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, |
1390 | int tx_num, struct mtk_tx_ring *ring, bool gso) |
1391 | { |
1392 | struct mtk_tx_dma_desc_info txd_info = { |
1393 | .size = skb_headlen(skb), |
1394 | .gso = gso, |
1395 | .csum = skb->ip_summed == CHECKSUM_PARTIAL, |
1396 | .vlan = skb_vlan_tag_present(skb), |
1397 | .qid = skb_get_queue_mapping(skb), |
1398 | .vlan_tci = skb_vlan_tag_get(skb), |
1399 | .first = true, |
1400 | .last = !skb_is_nonlinear(skb), |
1401 | }; |
1402 | struct netdev_queue *txq; |
1403 | struct mtk_mac *mac = netdev_priv(dev); |
1404 | struct mtk_eth *eth = mac->hw; |
1405 | const struct mtk_soc_data *soc = eth->soc; |
1406 | struct mtk_tx_dma *itxd, *txd; |
1407 | struct mtk_tx_dma *itxd_pdma, *txd_pdma; |
1408 | struct mtk_tx_buf *itx_buf, *tx_buf; |
1409 | int i, n_desc = 1; |
1410 | int queue = skb_get_queue_mapping(skb); |
1411 | int k = 0; |
1412 | |
1413 | txq = netdev_get_tx_queue(dev, index: queue); |
1414 | itxd = ring->next_free; |
1415 | itxd_pdma = qdma_to_pdma(ring, dma: itxd); |
1416 | if (itxd == ring->last_free) |
1417 | return -ENOMEM; |
1418 | |
1419 | itx_buf = mtk_desc_to_tx_buf(ring, txd: itxd, txd_size: soc->txrx.txd_size); |
1420 | memset(itx_buf, 0, sizeof(*itx_buf)); |
1421 | |
1422 | txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size, |
1423 | DMA_TO_DEVICE); |
1424 | if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) |
1425 | return -ENOMEM; |
1426 | |
1427 | mtk_tx_set_dma_desc(dev, txd: itxd, info: &txd_info); |
1428 | |
1429 | itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; |
1430 | itx_buf->mac_id = mac->id; |
1431 | setup_tx_buf(eth, tx_buf: itx_buf, txd: itxd_pdma, mapped_addr: txd_info.addr, size: txd_info.size, |
1432 | idx: k++); |
1433 | |
1434 | /* TX SG offload */ |
1435 | txd = itxd; |
1436 | txd_pdma = qdma_to_pdma(ring, dma: txd); |
1437 | |
1438 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { |
1439 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
1440 | unsigned int offset = 0; |
1441 | int frag_size = skb_frag_size(frag); |
1442 | |
1443 | while (frag_size) { |
1444 | bool new_desc = true; |
1445 | |
1446 | if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || |
1447 | (i & 0x1)) { |
1448 | txd = mtk_qdma_phys_to_virt(ring, desc: txd->txd2); |
1449 | txd_pdma = qdma_to_pdma(ring, dma: txd); |
1450 | if (txd == ring->last_free) |
1451 | goto err_dma; |
1452 | |
1453 | n_desc++; |
1454 | } else { |
1455 | new_desc = false; |
1456 | } |
1457 | |
1458 | memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); |
1459 | txd_info.size = min_t(unsigned int, frag_size, |
1460 | soc->txrx.dma_max_len); |
1461 | txd_info.qid = queue; |
1462 | txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && |
1463 | !(frag_size - txd_info.size); |
1464 | txd_info.addr = skb_frag_dma_map(dev: eth->dma_dev, frag, |
1465 | offset, size: txd_info.size, |
1466 | dir: DMA_TO_DEVICE); |
1467 | if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) |
1468 | goto err_dma; |
1469 | |
1470 | mtk_tx_set_dma_desc(dev, txd, info: &txd_info); |
1471 | |
1472 | tx_buf = mtk_desc_to_tx_buf(ring, txd, |
1473 | txd_size: soc->txrx.txd_size); |
1474 | if (new_desc) |
1475 | memset(tx_buf, 0, sizeof(*tx_buf)); |
1476 | tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; |
1477 | tx_buf->flags |= MTK_TX_FLAGS_PAGE0; |
1478 | tx_buf->mac_id = mac->id; |
1479 | |
1480 | setup_tx_buf(eth, tx_buf, txd: txd_pdma, mapped_addr: txd_info.addr, |
1481 | size: txd_info.size, idx: k++); |
1482 | |
1483 | frag_size -= txd_info.size; |
1484 | offset += txd_info.size; |
1485 | } |
1486 | } |
1487 | |
1488 | /* store skb to cleanup */ |
1489 | itx_buf->type = MTK_TYPE_SKB; |
1490 | itx_buf->data = skb; |
1491 | |
1492 | if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { |
1493 | if (k & 0x1) |
1494 | txd_pdma->txd2 |= TX_DMA_LS0; |
1495 | else |
1496 | txd_pdma->txd2 |= TX_DMA_LS1; |
1497 | } |
1498 | |
1499 | netdev_tx_sent_queue(dev_queue: txq, bytes: skb->len); |
1500 | skb_tx_timestamp(skb); |
1501 | |
1502 | ring->next_free = mtk_qdma_phys_to_virt(ring, desc: txd->txd2); |
1503 | atomic_sub(i: n_desc, v: &ring->free_count); |
1504 | |
1505 | /* make sure that all changes to the dma ring are flushed before we |
1506 | * continue |
1507 | */ |
1508 | wmb(); |
1509 | |
1510 | if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { |
1511 | if (netif_xmit_stopped(dev_queue: txq) || !netdev_xmit_more()) |
1512 | mtk_w32(eth, val: txd->txd2, reg: soc->reg_map->qdma.ctx_ptr); |
1513 | } else { |
1514 | int next_idx; |
1515 | |
1516 | next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size), |
1517 | ring->dma_size); |
1518 | mtk_w32(eth, val: next_idx, MT7628_TX_CTX_IDX0); |
1519 | } |
1520 | |
1521 | return 0; |
1522 | |
1523 | err_dma: |
1524 | do { |
1525 | tx_buf = mtk_desc_to_tx_buf(ring, txd: itxd, txd_size: soc->txrx.txd_size); |
1526 | |
1527 | /* unmap dma */ |
1528 | mtk_tx_unmap(eth, tx_buf, NULL, napi: false); |
1529 | |
1530 | itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; |
1531 | if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) |
1532 | itxd_pdma->txd2 = TX_DMA_DESP2_DEF; |
1533 | |
1534 | itxd = mtk_qdma_phys_to_virt(ring, desc: itxd->txd2); |
1535 | itxd_pdma = qdma_to_pdma(ring, dma: itxd); |
1536 | } while (itxd != txd); |
1537 | |
1538 | return -ENOMEM; |
1539 | } |
1540 | |
1541 | static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb) |
1542 | { |
1543 | int i, nfrags = 1; |
1544 | skb_frag_t *frag; |
1545 | |
1546 | if (skb_is_gso(skb)) { |
1547 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { |
1548 | frag = &skb_shinfo(skb)->frags[i]; |
1549 | nfrags += DIV_ROUND_UP(skb_frag_size(frag), |
1550 | eth->soc->txrx.dma_max_len); |
1551 | } |
1552 | } else { |
1553 | nfrags += skb_shinfo(skb)->nr_frags; |
1554 | } |
1555 | |
1556 | return nfrags; |
1557 | } |
1558 | |
1559 | static int mtk_queue_stopped(struct mtk_eth *eth) |
1560 | { |
1561 | int i; |
1562 | |
1563 | for (i = 0; i < MTK_MAX_DEVS; i++) { |
1564 | if (!eth->netdev[i]) |
1565 | continue; |
1566 | if (netif_queue_stopped(dev: eth->netdev[i])) |
1567 | return 1; |
1568 | } |
1569 | |
1570 | return 0; |
1571 | } |
1572 | |
1573 | static void mtk_wake_queue(struct mtk_eth *eth) |
1574 | { |
1575 | int i; |
1576 | |
1577 | for (i = 0; i < MTK_MAX_DEVS; i++) { |
1578 | if (!eth->netdev[i]) |
1579 | continue; |
1580 | netif_tx_wake_all_queues(dev: eth->netdev[i]); |
1581 | } |
1582 | } |
1583 | |
1584 | static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1585 | { |
1586 | struct mtk_mac *mac = netdev_priv(dev); |
1587 | struct mtk_eth *eth = mac->hw; |
1588 | struct mtk_tx_ring *ring = ð->tx_ring; |
1589 | struct net_device_stats *stats = &dev->stats; |
1590 | bool gso = false; |
1591 | int tx_num; |
1592 | |
1593 | /* normally we can rely on the stack not calling this more than once, |
1594 | * however we have 2 queues running on the same ring so we need to lock |
1595 | * the ring access |
1596 | */ |
1597 | spin_lock(lock: ð->page_lock); |
1598 | |
1599 | if (unlikely(test_bit(MTK_RESETTING, ð->state))) |
1600 | goto drop; |
1601 | |
1602 | tx_num = mtk_cal_txd_req(eth, skb); |
1603 | if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { |
1604 | netif_tx_stop_all_queues(dev); |
1605 | netif_err(eth, tx_queued, dev, |
1606 | "Tx Ring full when queue awake!\n" ); |
1607 | spin_unlock(lock: ð->page_lock); |
1608 | return NETDEV_TX_BUSY; |
1609 | } |
1610 | |
1611 | /* TSO: fill MSS info in tcp checksum field */ |
1612 | if (skb_is_gso(skb)) { |
1613 | if (skb_cow_head(skb, headroom: 0)) { |
1614 | netif_warn(eth, tx_err, dev, |
1615 | "GSO expand head fail.\n" ); |
1616 | goto drop; |
1617 | } |
1618 | |
1619 | if (skb_shinfo(skb)->gso_type & |
1620 | (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { |
1621 | gso = true; |
1622 | tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); |
1623 | } |
1624 | } |
1625 | |
1626 | if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) |
1627 | goto drop; |
1628 | |
1629 | if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) |
1630 | netif_tx_stop_all_queues(dev); |
1631 | |
1632 | spin_unlock(lock: ð->page_lock); |
1633 | |
1634 | return NETDEV_TX_OK; |
1635 | |
1636 | drop: |
1637 | spin_unlock(lock: ð->page_lock); |
1638 | stats->tx_dropped++; |
1639 | dev_kfree_skb_any(skb); |
1640 | return NETDEV_TX_OK; |
1641 | } |
1642 | |
1643 | static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) |
1644 | { |
1645 | int i; |
1646 | struct mtk_rx_ring *ring; |
1647 | int idx; |
1648 | |
1649 | if (!eth->hwlro) |
1650 | return ð->rx_ring[0]; |
1651 | |
1652 | for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { |
1653 | struct mtk_rx_dma *rxd; |
1654 | |
1655 | ring = ð->rx_ring[i]; |
1656 | idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); |
1657 | rxd = ring->dma + idx * eth->soc->txrx.rxd_size; |
1658 | if (rxd->rxd2 & RX_DMA_DONE) { |
1659 | ring->calc_idx_update = true; |
1660 | return ring; |
1661 | } |
1662 | } |
1663 | |
1664 | return NULL; |
1665 | } |
1666 | |
1667 | static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) |
1668 | { |
1669 | struct mtk_rx_ring *ring; |
1670 | int i; |
1671 | |
1672 | if (!eth->hwlro) { |
1673 | ring = ð->rx_ring[0]; |
1674 | mtk_w32(eth, val: ring->calc_idx, reg: ring->crx_idx_reg); |
1675 | } else { |
1676 | for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { |
1677 | ring = ð->rx_ring[i]; |
1678 | if (ring->calc_idx_update) { |
1679 | ring->calc_idx_update = false; |
1680 | mtk_w32(eth, val: ring->calc_idx, reg: ring->crx_idx_reg); |
1681 | } |
1682 | } |
1683 | } |
1684 | } |
1685 | |
1686 | static bool mtk_page_pool_enabled(struct mtk_eth *eth) |
1687 | { |
1688 | return mtk_is_netsys_v2_or_greater(eth); |
1689 | } |
1690 | |
1691 | static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth, |
1692 | struct xdp_rxq_info *xdp_q, |
1693 | int id, int size) |
1694 | { |
1695 | struct page_pool_params pp_params = { |
1696 | .order = 0, |
1697 | .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, |
1698 | .pool_size = size, |
1699 | .nid = NUMA_NO_NODE, |
1700 | .dev = eth->dma_dev, |
1701 | .offset = MTK_PP_HEADROOM, |
1702 | .max_len = MTK_PP_MAX_BUF_SIZE, |
1703 | }; |
1704 | struct page_pool *pp; |
1705 | int err; |
1706 | |
1707 | pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL |
1708 | : DMA_FROM_DEVICE; |
1709 | pp = page_pool_create(params: &pp_params); |
1710 | if (IS_ERR(ptr: pp)) |
1711 | return pp; |
1712 | |
1713 | err = __xdp_rxq_info_reg(xdp_rxq: xdp_q, dev: ð->dummy_dev, queue_index: id, |
1714 | napi_id: eth->rx_napi.napi_id, PAGE_SIZE); |
1715 | if (err < 0) |
1716 | goto err_free_pp; |
1717 | |
1718 | err = xdp_rxq_info_reg_mem_model(xdp_rxq: xdp_q, type: MEM_TYPE_PAGE_POOL, allocator: pp); |
1719 | if (err) |
1720 | goto err_unregister_rxq; |
1721 | |
1722 | return pp; |
1723 | |
1724 | err_unregister_rxq: |
1725 | xdp_rxq_info_unreg(xdp_rxq: xdp_q); |
1726 | err_free_pp: |
1727 | page_pool_destroy(pool: pp); |
1728 | |
1729 | return ERR_PTR(error: err); |
1730 | } |
1731 | |
1732 | static void *mtk_page_pool_get_buff(struct page_pool *pp, dma_addr_t *dma_addr, |
1733 | gfp_t gfp_mask) |
1734 | { |
1735 | struct page *page; |
1736 | |
1737 | page = page_pool_alloc_pages(pool: pp, gfp: gfp_mask | __GFP_NOWARN); |
1738 | if (!page) |
1739 | return NULL; |
1740 | |
1741 | *dma_addr = page_pool_get_dma_addr(page) + MTK_PP_HEADROOM; |
1742 | return page_address(page); |
1743 | } |
1744 | |
1745 | static void mtk_rx_put_buff(struct mtk_rx_ring *ring, void *data, bool napi) |
1746 | { |
1747 | if (ring->page_pool) |
1748 | page_pool_put_full_page(pool: ring->page_pool, |
1749 | page: virt_to_head_page(x: data), allow_direct: napi); |
1750 | else |
1751 | skb_free_frag(addr: data); |
1752 | } |
1753 | |
1754 | static int mtk_xdp_frame_map(struct mtk_eth *eth, struct net_device *dev, |
1755 | struct mtk_tx_dma_desc_info *txd_info, |
1756 | struct mtk_tx_dma *txd, struct mtk_tx_buf *tx_buf, |
1757 | void *data, u16 headroom, int index, bool dma_map) |
1758 | { |
1759 | struct mtk_tx_ring *ring = ð->tx_ring; |
1760 | struct mtk_mac *mac = netdev_priv(dev); |
1761 | struct mtk_tx_dma *txd_pdma; |
1762 | |
1763 | if (dma_map) { /* ndo_xdp_xmit */ |
1764 | txd_info->addr = dma_map_single(eth->dma_dev, data, |
1765 | txd_info->size, DMA_TO_DEVICE); |
1766 | if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr))) |
1767 | return -ENOMEM; |
1768 | |
1769 | tx_buf->flags |= MTK_TX_FLAGS_SINGLE0; |
1770 | } else { |
1771 | struct page *page = virt_to_head_page(x: data); |
1772 | |
1773 | txd_info->addr = page_pool_get_dma_addr(page) + |
1774 | sizeof(struct xdp_frame) + headroom; |
1775 | dma_sync_single_for_device(dev: eth->dma_dev, addr: txd_info->addr, |
1776 | size: txd_info->size, dir: DMA_BIDIRECTIONAL); |
1777 | } |
1778 | mtk_tx_set_dma_desc(dev, txd, info: txd_info); |
1779 | |
1780 | tx_buf->mac_id = mac->id; |
1781 | tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX; |
1782 | tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; |
1783 | |
1784 | txd_pdma = qdma_to_pdma(ring, dma: txd); |
1785 | setup_tx_buf(eth, tx_buf, txd: txd_pdma, mapped_addr: txd_info->addr, size: txd_info->size, |
1786 | idx: index); |
1787 | |
1788 | return 0; |
1789 | } |
1790 | |
1791 | static int mtk_xdp_submit_frame(struct mtk_eth *eth, struct xdp_frame *xdpf, |
1792 | struct net_device *dev, bool dma_map) |
1793 | { |
1794 | struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(frame: xdpf); |
1795 | const struct mtk_soc_data *soc = eth->soc; |
1796 | struct mtk_tx_ring *ring = ð->tx_ring; |
1797 | struct mtk_mac *mac = netdev_priv(dev); |
1798 | struct mtk_tx_dma_desc_info txd_info = { |
1799 | .size = xdpf->len, |
1800 | .first = true, |
1801 | .last = !xdp_frame_has_frags(frame: xdpf), |
1802 | .qid = mac->id, |
1803 | }; |
1804 | int err, index = 0, n_desc = 1, nr_frags; |
1805 | struct mtk_tx_buf *htx_buf, *tx_buf; |
1806 | struct mtk_tx_dma *htxd, *txd; |
1807 | void *data = xdpf->data; |
1808 | |
1809 | if (unlikely(test_bit(MTK_RESETTING, ð->state))) |
1810 | return -EBUSY; |
1811 | |
1812 | nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; |
1813 | if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags)) |
1814 | return -EBUSY; |
1815 | |
1816 | spin_lock(lock: ð->page_lock); |
1817 | |
1818 | txd = ring->next_free; |
1819 | if (txd == ring->last_free) { |
1820 | spin_unlock(lock: ð->page_lock); |
1821 | return -ENOMEM; |
1822 | } |
1823 | htxd = txd; |
1824 | |
1825 | tx_buf = mtk_desc_to_tx_buf(ring, txd, txd_size: soc->txrx.txd_size); |
1826 | memset(tx_buf, 0, sizeof(*tx_buf)); |
1827 | htx_buf = tx_buf; |
1828 | |
1829 | for (;;) { |
1830 | err = mtk_xdp_frame_map(eth, dev, txd_info: &txd_info, txd, tx_buf, |
1831 | data, headroom: xdpf->headroom, index, dma_map); |
1832 | if (err < 0) |
1833 | goto unmap; |
1834 | |
1835 | if (txd_info.last) |
1836 | break; |
1837 | |
1838 | if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) { |
1839 | txd = mtk_qdma_phys_to_virt(ring, desc: txd->txd2); |
1840 | if (txd == ring->last_free) |
1841 | goto unmap; |
1842 | |
1843 | tx_buf = mtk_desc_to_tx_buf(ring, txd, |
1844 | txd_size: soc->txrx.txd_size); |
1845 | memset(tx_buf, 0, sizeof(*tx_buf)); |
1846 | n_desc++; |
1847 | } |
1848 | |
1849 | memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); |
1850 | txd_info.size = skb_frag_size(frag: &sinfo->frags[index]); |
1851 | txd_info.last = index + 1 == nr_frags; |
1852 | txd_info.qid = mac->id; |
1853 | data = skb_frag_address(frag: &sinfo->frags[index]); |
1854 | |
1855 | index++; |
1856 | } |
1857 | /* store xdpf for cleanup */ |
1858 | htx_buf->data = xdpf; |
1859 | |
1860 | if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { |
1861 | struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, dma: txd); |
1862 | |
1863 | if (index & 1) |
1864 | txd_pdma->txd2 |= TX_DMA_LS0; |
1865 | else |
1866 | txd_pdma->txd2 |= TX_DMA_LS1; |
1867 | } |
1868 | |
1869 | ring->next_free = mtk_qdma_phys_to_virt(ring, desc: txd->txd2); |
1870 | atomic_sub(i: n_desc, v: &ring->free_count); |
1871 | |
1872 | /* make sure that all changes to the dma ring are flushed before we |
1873 | * continue |
1874 | */ |
1875 | wmb(); |
1876 | |
1877 | if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { |
1878 | mtk_w32(eth, val: txd->txd2, reg: soc->reg_map->qdma.ctx_ptr); |
1879 | } else { |
1880 | int idx; |
1881 | |
1882 | idx = txd_to_idx(ring, dma: txd, txd_size: soc->txrx.txd_size); |
1883 | mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size), |
1884 | MT7628_TX_CTX_IDX0); |
1885 | } |
1886 | |
1887 | spin_unlock(lock: ð->page_lock); |
1888 | |
1889 | return 0; |
1890 | |
1891 | unmap: |
1892 | while (htxd != txd) { |
1893 | tx_buf = mtk_desc_to_tx_buf(ring, txd: htxd, txd_size: soc->txrx.txd_size); |
1894 | mtk_tx_unmap(eth, tx_buf, NULL, napi: false); |
1895 | |
1896 | htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; |
1897 | if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { |
1898 | struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, dma: htxd); |
1899 | |
1900 | txd_pdma->txd2 = TX_DMA_DESP2_DEF; |
1901 | } |
1902 | |
1903 | htxd = mtk_qdma_phys_to_virt(ring, desc: htxd->txd2); |
1904 | } |
1905 | |
1906 | spin_unlock(lock: ð->page_lock); |
1907 | |
1908 | return err; |
1909 | } |
1910 | |
1911 | static int mtk_xdp_xmit(struct net_device *dev, int num_frame, |
1912 | struct xdp_frame **frames, u32 flags) |
1913 | { |
1914 | struct mtk_mac *mac = netdev_priv(dev); |
1915 | struct mtk_hw_stats *hw_stats = mac->hw_stats; |
1916 | struct mtk_eth *eth = mac->hw; |
1917 | int i, nxmit = 0; |
1918 | |
1919 | if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) |
1920 | return -EINVAL; |
1921 | |
1922 | for (i = 0; i < num_frame; i++) { |
1923 | if (mtk_xdp_submit_frame(eth, xdpf: frames[i], dev, dma_map: true)) |
1924 | break; |
1925 | nxmit++; |
1926 | } |
1927 | |
1928 | u64_stats_update_begin(syncp: &hw_stats->syncp); |
1929 | hw_stats->xdp_stats.tx_xdp_xmit += nxmit; |
1930 | hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit; |
1931 | u64_stats_update_end(syncp: &hw_stats->syncp); |
1932 | |
1933 | return nxmit; |
1934 | } |
1935 | |
1936 | static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring, |
1937 | struct xdp_buff *xdp, struct net_device *dev) |
1938 | { |
1939 | struct mtk_mac *mac = netdev_priv(dev); |
1940 | struct mtk_hw_stats *hw_stats = mac->hw_stats; |
1941 | u64 *count = &hw_stats->xdp_stats.rx_xdp_drop; |
1942 | struct bpf_prog *prog; |
1943 | u32 act = XDP_PASS; |
1944 | |
1945 | rcu_read_lock(); |
1946 | |
1947 | prog = rcu_dereference(eth->prog); |
1948 | if (!prog) |
1949 | goto out; |
1950 | |
1951 | act = bpf_prog_run_xdp(prog, xdp); |
1952 | switch (act) { |
1953 | case XDP_PASS: |
1954 | count = &hw_stats->xdp_stats.rx_xdp_pass; |
1955 | goto update_stats; |
1956 | case XDP_REDIRECT: |
1957 | if (unlikely(xdp_do_redirect(dev, xdp, prog))) { |
1958 | act = XDP_DROP; |
1959 | break; |
1960 | } |
1961 | |
1962 | count = &hw_stats->xdp_stats.rx_xdp_redirect; |
1963 | goto update_stats; |
1964 | case XDP_TX: { |
1965 | struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); |
1966 | |
1967 | if (!xdpf || mtk_xdp_submit_frame(eth, xdpf, dev, dma_map: false)) { |
1968 | count = &hw_stats->xdp_stats.rx_xdp_tx_errors; |
1969 | act = XDP_DROP; |
1970 | break; |
1971 | } |
1972 | |
1973 | count = &hw_stats->xdp_stats.rx_xdp_tx; |
1974 | goto update_stats; |
1975 | } |
1976 | default: |
1977 | bpf_warn_invalid_xdp_action(dev, prog, act); |
1978 | fallthrough; |
1979 | case XDP_ABORTED: |
1980 | trace_xdp_exception(dev, xdp: prog, act); |
1981 | fallthrough; |
1982 | case XDP_DROP: |
1983 | break; |
1984 | } |
1985 | |
1986 | page_pool_put_full_page(pool: ring->page_pool, |
1987 | page: virt_to_head_page(x: xdp->data), allow_direct: true); |
1988 | |
1989 | update_stats: |
1990 | u64_stats_update_begin(syncp: &hw_stats->syncp); |
1991 | *count = *count + 1; |
1992 | u64_stats_update_end(syncp: &hw_stats->syncp); |
1993 | out: |
1994 | rcu_read_unlock(); |
1995 | |
1996 | return act; |
1997 | } |
1998 | |
1999 | static int mtk_poll_rx(struct napi_struct *napi, int budget, |
2000 | struct mtk_eth *eth) |
2001 | { |
2002 | struct dim_sample dim_sample = {}; |
2003 | struct mtk_rx_ring *ring; |
2004 | bool xdp_flush = false; |
2005 | int idx; |
2006 | struct sk_buff *skb; |
2007 | u64 addr64 = 0; |
2008 | u8 *data, *new_data; |
2009 | struct mtk_rx_dma_v2 *rxd, trxd; |
2010 | int done = 0, bytes = 0; |
2011 | dma_addr_t dma_addr = DMA_MAPPING_ERROR; |
2012 | |
2013 | while (done < budget) { |
2014 | unsigned int pktlen, *rxdcsum; |
2015 | struct net_device *netdev; |
2016 | u32 hash, reason; |
2017 | int mac = 0; |
2018 | |
2019 | ring = mtk_get_rx_ring(eth); |
2020 | if (unlikely(!ring)) |
2021 | goto rx_done; |
2022 | |
2023 | idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); |
2024 | rxd = ring->dma + idx * eth->soc->txrx.rxd_size; |
2025 | data = ring->data[idx]; |
2026 | |
2027 | if (!mtk_rx_get_desc(eth, rxd: &trxd, dma_rxd: rxd)) |
2028 | break; |
2029 | |
2030 | /* find out which mac the packet come from. values start at 1 */ |
2031 | if (mtk_is_netsys_v2_or_greater(eth)) { |
2032 | u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5); |
2033 | |
2034 | switch (val) { |
2035 | case PSE_GDM1_PORT: |
2036 | case PSE_GDM2_PORT: |
2037 | mac = val - 1; |
2038 | break; |
2039 | case PSE_GDM3_PORT: |
2040 | mac = MTK_GMAC3_ID; |
2041 | break; |
2042 | default: |
2043 | break; |
2044 | } |
2045 | } else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && |
2046 | !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) { |
2047 | mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; |
2048 | } |
2049 | |
2050 | if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS || |
2051 | !eth->netdev[mac])) |
2052 | goto release_desc; |
2053 | |
2054 | netdev = eth->netdev[mac]; |
2055 | |
2056 | if (unlikely(test_bit(MTK_RESETTING, ð->state))) |
2057 | goto release_desc; |
2058 | |
2059 | pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); |
2060 | |
2061 | /* alloc new buffer */ |
2062 | if (ring->page_pool) { |
2063 | struct page *page = virt_to_head_page(x: data); |
2064 | struct xdp_buff xdp; |
2065 | u32 ret; |
2066 | |
2067 | new_data = mtk_page_pool_get_buff(pp: ring->page_pool, |
2068 | dma_addr: &dma_addr, |
2069 | GFP_ATOMIC); |
2070 | if (unlikely(!new_data)) { |
2071 | netdev->stats.rx_dropped++; |
2072 | goto release_desc; |
2073 | } |
2074 | |
2075 | dma_sync_single_for_cpu(dev: eth->dma_dev, |
2076 | addr: page_pool_get_dma_addr(page) + MTK_PP_HEADROOM, |
2077 | size: pktlen, dir: page_pool_get_dma_dir(pool: ring->page_pool)); |
2078 | |
2079 | xdp_init_buff(xdp: &xdp, PAGE_SIZE, rxq: &ring->xdp_q); |
2080 | xdp_prepare_buff(xdp: &xdp, hard_start: data, MTK_PP_HEADROOM, data_len: pktlen, |
2081 | meta_valid: false); |
2082 | xdp_buff_clear_frags_flag(xdp: &xdp); |
2083 | |
2084 | ret = mtk_xdp_run(eth, ring, xdp: &xdp, dev: netdev); |
2085 | if (ret == XDP_REDIRECT) |
2086 | xdp_flush = true; |
2087 | |
2088 | if (ret != XDP_PASS) |
2089 | goto skip_rx; |
2090 | |
2091 | skb = build_skb(data, PAGE_SIZE); |
2092 | if (unlikely(!skb)) { |
2093 | page_pool_put_full_page(pool: ring->page_pool, |
2094 | page, allow_direct: true); |
2095 | netdev->stats.rx_dropped++; |
2096 | goto skip_rx; |
2097 | } |
2098 | |
2099 | skb_reserve(skb, len: xdp.data - xdp.data_hard_start); |
2100 | skb_put(skb, len: xdp.data_end - xdp.data); |
2101 | skb_mark_for_recycle(skb); |
2102 | } else { |
2103 | if (ring->frag_size <= PAGE_SIZE) |
2104 | new_data = napi_alloc_frag(fragsz: ring->frag_size); |
2105 | else |
2106 | new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC); |
2107 | |
2108 | if (unlikely(!new_data)) { |
2109 | netdev->stats.rx_dropped++; |
2110 | goto release_desc; |
2111 | } |
2112 | |
2113 | dma_addr = dma_map_single(eth->dma_dev, |
2114 | new_data + NET_SKB_PAD + eth->ip_align, |
2115 | ring->buf_size, DMA_FROM_DEVICE); |
2116 | if (unlikely(dma_mapping_error(eth->dma_dev, |
2117 | dma_addr))) { |
2118 | skb_free_frag(addr: new_data); |
2119 | netdev->stats.rx_dropped++; |
2120 | goto release_desc; |
2121 | } |
2122 | |
2123 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) |
2124 | addr64 = RX_DMA_GET_ADDR64(trxd.rxd2); |
2125 | |
2126 | dma_unmap_single(eth->dma_dev, ((u64)trxd.rxd1 | addr64), |
2127 | ring->buf_size, DMA_FROM_DEVICE); |
2128 | |
2129 | skb = build_skb(data, frag_size: ring->frag_size); |
2130 | if (unlikely(!skb)) { |
2131 | netdev->stats.rx_dropped++; |
2132 | skb_free_frag(addr: data); |
2133 | goto skip_rx; |
2134 | } |
2135 | |
2136 | skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); |
2137 | skb_put(skb, len: pktlen); |
2138 | } |
2139 | |
2140 | skb->dev = netdev; |
2141 | bytes += skb->len; |
2142 | |
2143 | if (mtk_is_netsys_v2_or_greater(eth)) { |
2144 | reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); |
2145 | hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; |
2146 | if (hash != MTK_RXD5_FOE_ENTRY) |
2147 | skb_set_hash(skb, hash: jhash_1word(a: hash, initval: 0), |
2148 | type: PKT_HASH_TYPE_L4); |
2149 | rxdcsum = &trxd.rxd3; |
2150 | } else { |
2151 | reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4); |
2152 | hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; |
2153 | if (hash != MTK_RXD4_FOE_ENTRY) |
2154 | skb_set_hash(skb, hash: jhash_1word(a: hash, initval: 0), |
2155 | type: PKT_HASH_TYPE_L4); |
2156 | rxdcsum = &trxd.rxd4; |
2157 | } |
2158 | |
2159 | if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid) |
2160 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
2161 | else |
2162 | skb_checksum_none_assert(skb); |
2163 | skb->protocol = eth_type_trans(skb, dev: netdev); |
2164 | |
2165 | /* When using VLAN untagging in combination with DSA, the |
2166 | * hardware treats the MTK special tag as a VLAN and untags it. |
2167 | */ |
2168 | if (mtk_is_netsys_v1(eth) && (trxd.rxd2 & RX_DMA_VTAG) && |
2169 | netdev_uses_dsa(dev: netdev)) { |
2170 | unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0); |
2171 | |
2172 | if (port < ARRAY_SIZE(eth->dsa_meta) && |
2173 | eth->dsa_meta[port]) |
2174 | skb_dst_set_noref(skb, dst: ð->dsa_meta[port]->dst); |
2175 | } |
2176 | |
2177 | if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) |
2178 | mtk_ppe_check_skb(ppe: eth->ppe[0], skb, hash); |
2179 | |
2180 | skb_record_rx_queue(skb, rx_queue: 0); |
2181 | napi_gro_receive(napi, skb); |
2182 | |
2183 | skip_rx: |
2184 | ring->data[idx] = new_data; |
2185 | rxd->rxd1 = (unsigned int)dma_addr; |
2186 | release_desc: |
2187 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) |
2188 | rxd->rxd2 = RX_DMA_LSO; |
2189 | else |
2190 | rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); |
2191 | |
2192 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA) && |
2193 | likely(dma_addr != DMA_MAPPING_ERROR)) |
2194 | rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr); |
2195 | |
2196 | ring->calc_idx = idx; |
2197 | done++; |
2198 | } |
2199 | |
2200 | rx_done: |
2201 | if (done) { |
2202 | /* make sure that all changes to the dma ring are flushed before |
2203 | * we continue |
2204 | */ |
2205 | wmb(); |
2206 | mtk_update_rx_cpu_idx(eth); |
2207 | } |
2208 | |
2209 | eth->rx_packets += done; |
2210 | eth->rx_bytes += bytes; |
2211 | dim_update_sample(event_ctr: eth->rx_events, packets: eth->rx_packets, bytes: eth->rx_bytes, |
2212 | s: &dim_sample); |
2213 | net_dim(dim: ð->rx_dim, end_sample: dim_sample); |
2214 | |
2215 | if (xdp_flush) |
2216 | xdp_do_flush(); |
2217 | |
2218 | return done; |
2219 | } |
2220 | |
2221 | struct mtk_poll_state { |
2222 | struct netdev_queue *txq; |
2223 | unsigned int total; |
2224 | unsigned int done; |
2225 | unsigned int bytes; |
2226 | }; |
2227 | |
2228 | static void |
2229 | mtk_poll_tx_done(struct mtk_eth *eth, struct mtk_poll_state *state, u8 mac, |
2230 | struct sk_buff *skb) |
2231 | { |
2232 | struct netdev_queue *txq; |
2233 | struct net_device *dev; |
2234 | unsigned int bytes = skb->len; |
2235 | |
2236 | state->total++; |
2237 | eth->tx_packets++; |
2238 | eth->tx_bytes += bytes; |
2239 | |
2240 | dev = eth->netdev[mac]; |
2241 | if (!dev) |
2242 | return; |
2243 | |
2244 | txq = netdev_get_tx_queue(dev, index: skb_get_queue_mapping(skb)); |
2245 | if (state->txq == txq) { |
2246 | state->done++; |
2247 | state->bytes += bytes; |
2248 | return; |
2249 | } |
2250 | |
2251 | if (state->txq) |
2252 | netdev_tx_completed_queue(dev_queue: state->txq, pkts: state->done, bytes: state->bytes); |
2253 | |
2254 | state->txq = txq; |
2255 | state->done = 1; |
2256 | state->bytes = bytes; |
2257 | } |
2258 | |
2259 | static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, |
2260 | struct mtk_poll_state *state) |
2261 | { |
2262 | const struct mtk_reg_map *reg_map = eth->soc->reg_map; |
2263 | struct mtk_tx_ring *ring = ð->tx_ring; |
2264 | struct mtk_tx_buf *tx_buf; |
2265 | struct xdp_frame_bulk bq; |
2266 | struct mtk_tx_dma *desc; |
2267 | u32 cpu, dma; |
2268 | |
2269 | cpu = ring->last_free_ptr; |
2270 | dma = mtk_r32(eth, reg: reg_map->qdma.drx_ptr); |
2271 | |
2272 | desc = mtk_qdma_phys_to_virt(ring, desc: cpu); |
2273 | xdp_frame_bulk_init(bq: &bq); |
2274 | |
2275 | while ((cpu != dma) && budget) { |
2276 | u32 next_cpu = desc->txd2; |
2277 | |
2278 | desc = mtk_qdma_phys_to_virt(ring, desc: desc->txd2); |
2279 | if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) |
2280 | break; |
2281 | |
2282 | tx_buf = mtk_desc_to_tx_buf(ring, txd: desc, |
2283 | txd_size: eth->soc->txrx.txd_size); |
2284 | if (!tx_buf->data) |
2285 | break; |
2286 | |
2287 | if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { |
2288 | if (tx_buf->type == MTK_TYPE_SKB) |
2289 | mtk_poll_tx_done(eth, state, mac: tx_buf->mac_id, |
2290 | skb: tx_buf->data); |
2291 | |
2292 | budget--; |
2293 | } |
2294 | mtk_tx_unmap(eth, tx_buf, bq: &bq, napi: true); |
2295 | |
2296 | ring->last_free = desc; |
2297 | atomic_inc(v: &ring->free_count); |
2298 | |
2299 | cpu = next_cpu; |
2300 | } |
2301 | xdp_flush_frame_bulk(bq: &bq); |
2302 | |
2303 | ring->last_free_ptr = cpu; |
2304 | mtk_w32(eth, val: cpu, reg: reg_map->qdma.crx_ptr); |
2305 | |
2306 | return budget; |
2307 | } |
2308 | |
2309 | static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, |
2310 | struct mtk_poll_state *state) |
2311 | { |
2312 | struct mtk_tx_ring *ring = ð->tx_ring; |
2313 | struct mtk_tx_buf *tx_buf; |
2314 | struct xdp_frame_bulk bq; |
2315 | struct mtk_tx_dma *desc; |
2316 | u32 cpu, dma; |
2317 | |
2318 | cpu = ring->cpu_idx; |
2319 | dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); |
2320 | xdp_frame_bulk_init(bq: &bq); |
2321 | |
2322 | while ((cpu != dma) && budget) { |
2323 | tx_buf = &ring->buf[cpu]; |
2324 | if (!tx_buf->data) |
2325 | break; |
2326 | |
2327 | if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { |
2328 | if (tx_buf->type == MTK_TYPE_SKB) |
2329 | mtk_poll_tx_done(eth, state, mac: 0, skb: tx_buf->data); |
2330 | budget--; |
2331 | } |
2332 | mtk_tx_unmap(eth, tx_buf, bq: &bq, napi: true); |
2333 | |
2334 | desc = ring->dma + cpu * eth->soc->txrx.txd_size; |
2335 | ring->last_free = desc; |
2336 | atomic_inc(v: &ring->free_count); |
2337 | |
2338 | cpu = NEXT_DESP_IDX(cpu, ring->dma_size); |
2339 | } |
2340 | xdp_flush_frame_bulk(bq: &bq); |
2341 | |
2342 | ring->cpu_idx = cpu; |
2343 | |
2344 | return budget; |
2345 | } |
2346 | |
2347 | static int mtk_poll_tx(struct mtk_eth *eth, int budget) |
2348 | { |
2349 | struct mtk_tx_ring *ring = ð->tx_ring; |
2350 | struct dim_sample dim_sample = {}; |
2351 | struct mtk_poll_state state = {}; |
2352 | |
2353 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) |
2354 | budget = mtk_poll_tx_qdma(eth, budget, state: &state); |
2355 | else |
2356 | budget = mtk_poll_tx_pdma(eth, budget, state: &state); |
2357 | |
2358 | if (state.txq) |
2359 | netdev_tx_completed_queue(dev_queue: state.txq, pkts: state.done, bytes: state.bytes); |
2360 | |
2361 | dim_update_sample(event_ctr: eth->tx_events, packets: eth->tx_packets, bytes: eth->tx_bytes, |
2362 | s: &dim_sample); |
2363 | net_dim(dim: ð->tx_dim, end_sample: dim_sample); |
2364 | |
2365 | if (mtk_queue_stopped(eth) && |
2366 | (atomic_read(v: &ring->free_count) > ring->thresh)) |
2367 | mtk_wake_queue(eth); |
2368 | |
2369 | return state.total; |
2370 | } |
2371 | |
2372 | static void mtk_handle_status_irq(struct mtk_eth *eth) |
2373 | { |
2374 | u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); |
2375 | |
2376 | if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { |
2377 | mtk_stats_update(eth); |
2378 | mtk_w32(eth, val: (MTK_GDM1_AF | MTK_GDM2_AF), |
2379 | MTK_INT_STATUS2); |
2380 | } |
2381 | } |
2382 | |
2383 | static int mtk_napi_tx(struct napi_struct *napi, int budget) |
2384 | { |
2385 | struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); |
2386 | const struct mtk_reg_map *reg_map = eth->soc->reg_map; |
2387 | int tx_done = 0; |
2388 | |
2389 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) |
2390 | mtk_handle_status_irq(eth); |
2391 | mtk_w32(eth, MTK_TX_DONE_INT, reg: reg_map->tx_irq_status); |
2392 | tx_done = mtk_poll_tx(eth, budget); |
2393 | |
2394 | if (unlikely(netif_msg_intr(eth))) { |
2395 | dev_info(eth->dev, |
2396 | "done tx %d, intr 0x%08x/0x%x\n" , tx_done, |
2397 | mtk_r32(eth, reg_map->tx_irq_status), |
2398 | mtk_r32(eth, reg_map->tx_irq_mask)); |
2399 | } |
2400 | |
2401 | if (tx_done == budget) |
2402 | return budget; |
2403 | |
2404 | if (mtk_r32(eth, reg: reg_map->tx_irq_status) & MTK_TX_DONE_INT) |
2405 | return budget; |
2406 | |
2407 | if (napi_complete_done(n: napi, work_done: tx_done)) |
2408 | mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); |
2409 | |
2410 | return tx_done; |
2411 | } |
2412 | |
2413 | static int mtk_napi_rx(struct napi_struct *napi, int budget) |
2414 | { |
2415 | struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); |
2416 | const struct mtk_reg_map *reg_map = eth->soc->reg_map; |
2417 | int rx_done_total = 0; |
2418 | |
2419 | mtk_handle_status_irq(eth); |
2420 | |
2421 | do { |
2422 | int rx_done; |
2423 | |
2424 | mtk_w32(eth, val: eth->soc->txrx.rx_irq_done_mask, |
2425 | reg: reg_map->pdma.irq_status); |
2426 | rx_done = mtk_poll_rx(napi, budget: budget - rx_done_total, eth); |
2427 | rx_done_total += rx_done; |
2428 | |
2429 | if (unlikely(netif_msg_intr(eth))) { |
2430 | dev_info(eth->dev, |
2431 | "done rx %d, intr 0x%08x/0x%x\n" , rx_done, |
2432 | mtk_r32(eth, reg_map->pdma.irq_status), |
2433 | mtk_r32(eth, reg_map->pdma.irq_mask)); |
2434 | } |
2435 | |
2436 | if (rx_done_total == budget) |
2437 | return budget; |
2438 | |
2439 | } while (mtk_r32(eth, reg: reg_map->pdma.irq_status) & |
2440 | eth->soc->txrx.rx_irq_done_mask); |
2441 | |
2442 | if (napi_complete_done(n: napi, work_done: rx_done_total)) |
2443 | mtk_rx_irq_enable(eth, mask: eth->soc->txrx.rx_irq_done_mask); |
2444 | |
2445 | return rx_done_total; |
2446 | } |
2447 | |
2448 | static int mtk_tx_alloc(struct mtk_eth *eth) |
2449 | { |
2450 | const struct mtk_soc_data *soc = eth->soc; |
2451 | struct mtk_tx_ring *ring = ð->tx_ring; |
2452 | int i, sz = soc->txrx.txd_size; |
2453 | struct mtk_tx_dma_v2 *txd; |
2454 | int ring_size; |
2455 | u32 ofs, val; |
2456 | |
2457 | if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) |
2458 | ring_size = MTK_QDMA_RING_SIZE; |
2459 | else |
2460 | ring_size = MTK_DMA_SIZE; |
2461 | |
2462 | ring->buf = kcalloc(n: ring_size, size: sizeof(*ring->buf), |
2463 | GFP_KERNEL); |
2464 | if (!ring->buf) |
2465 | goto no_tx_mem; |
2466 | |
2467 | if (MTK_HAS_CAPS(soc->caps, MTK_SRAM)) { |
2468 | ring->dma = eth->sram_base + ring_size * sz; |
2469 | ring->phys = eth->phy_scratch_ring + ring_size * (dma_addr_t)sz; |
2470 | } else { |
2471 | ring->dma = dma_alloc_coherent(dev: eth->dma_dev, size: ring_size * sz, |
2472 | dma_handle: &ring->phys, GFP_KERNEL); |
2473 | } |
2474 | |
2475 | if (!ring->dma) |
2476 | goto no_tx_mem; |
2477 | |
2478 | for (i = 0; i < ring_size; i++) { |
2479 | int next = (i + 1) % ring_size; |
2480 | u32 next_ptr = ring->phys + next * sz; |
2481 | |
2482 | txd = ring->dma + i * sz; |
2483 | txd->txd2 = next_ptr; |
2484 | txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; |
2485 | txd->txd4 = 0; |
2486 | if (mtk_is_netsys_v2_or_greater(eth)) { |
2487 | txd->txd5 = 0; |
2488 | txd->txd6 = 0; |
2489 | txd->txd7 = 0; |
2490 | txd->txd8 = 0; |
2491 | } |
2492 | } |
2493 | |
2494 | /* On MT7688 (PDMA only) this driver uses the ring->dma structs |
2495 | * only as the framework. The real HW descriptors are the PDMA |
2496 | * descriptors in ring->dma_pdma. |
2497 | */ |
2498 | if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { |
2499 | ring->dma_pdma = dma_alloc_coherent(dev: eth->dma_dev, size: ring_size * sz, |
2500 | dma_handle: &ring->phys_pdma, GFP_KERNEL); |
2501 | if (!ring->dma_pdma) |
2502 | goto no_tx_mem; |
2503 | |
2504 | for (i = 0; i < ring_size; i++) { |
2505 | ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; |
2506 | ring->dma_pdma[i].txd4 = 0; |
2507 | } |
2508 | } |
2509 | |
2510 | ring->dma_size = ring_size; |
2511 | atomic_set(v: &ring->free_count, i: ring_size - 2); |
2512 | ring->next_free = ring->dma; |
2513 | ring->last_free = (void *)txd; |
2514 | ring->last_free_ptr = (u32)(ring->phys + ((ring_size - 1) * sz)); |
2515 | ring->thresh = MAX_SKB_FRAGS; |
2516 | |
2517 | /* make sure that all changes to the dma ring are flushed before we |
2518 | * continue |
2519 | */ |
2520 | wmb(); |
2521 | |
2522 | if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { |
2523 | mtk_w32(eth, val: ring->phys, reg: soc->reg_map->qdma.ctx_ptr); |
2524 | mtk_w32(eth, val: ring->phys, reg: soc->reg_map->qdma.dtx_ptr); |
2525 | mtk_w32(eth, |
2526 | val: ring->phys + ((ring_size - 1) * sz), |
2527 | reg: soc->reg_map->qdma.crx_ptr); |
2528 | mtk_w32(eth, val: ring->last_free_ptr, reg: soc->reg_map->qdma.drx_ptr); |
2529 | |
2530 | for (i = 0, ofs = 0; i < MTK_QDMA_NUM_QUEUES; i++) { |
2531 | val = (QDMA_RES_THRES << 8) | QDMA_RES_THRES; |
2532 | mtk_w32(eth, val, reg: soc->reg_map->qdma.qtx_cfg + ofs); |
2533 | |
2534 | val = MTK_QTX_SCH_MIN_RATE_EN | |
2535 | /* minimum: 10 Mbps */ |
2536 | FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | |
2537 | FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | |
2538 | MTK_QTX_SCH_LEAKY_BUCKET_SIZE; |
2539 | if (mtk_is_netsys_v1(eth)) |
2540 | val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; |
2541 | mtk_w32(eth, val, reg: soc->reg_map->qdma.qtx_sch + ofs); |
2542 | ofs += MTK_QTX_OFFSET; |
2543 | } |
2544 | val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16); |
2545 | mtk_w32(eth, val, reg: soc->reg_map->qdma.tx_sch_rate); |
2546 | if (mtk_is_netsys_v2_or_greater(eth)) |
2547 | mtk_w32(eth, val, reg: soc->reg_map->qdma.tx_sch_rate + 4); |
2548 | } else { |
2549 | mtk_w32(eth, val: ring->phys_pdma, MT7628_TX_BASE_PTR0); |
2550 | mtk_w32(eth, val: ring_size, MT7628_TX_MAX_CNT0); |
2551 | mtk_w32(eth, val: 0, MT7628_TX_CTX_IDX0); |
2552 | mtk_w32(eth, MT7628_PST_DTX_IDX0, reg: soc->reg_map->pdma.rst_idx); |
2553 | } |
2554 | |
2555 | return 0; |
2556 | |
2557 | no_tx_mem: |
2558 | return -ENOMEM; |
2559 | } |
2560 | |
2561 | static void mtk_tx_clean(struct mtk_eth *eth) |
2562 | { |
2563 | const struct mtk_soc_data *soc = eth->soc; |
2564 | struct mtk_tx_ring *ring = ð->tx_ring; |
2565 | int i; |
2566 | |
2567 | if (ring->buf) { |
2568 | for (i = 0; i < ring->dma_size; i++) |
2569 | mtk_tx_unmap(eth, tx_buf: &ring->buf[i], NULL, napi: false); |
2570 | kfree(objp: ring->buf); |
2571 | ring->buf = NULL; |
2572 | } |
2573 | if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) { |
2574 | dma_free_coherent(dev: eth->dma_dev, |
2575 | size: ring->dma_size * soc->txrx.txd_size, |
2576 | cpu_addr: ring->dma, dma_handle: ring->phys); |
2577 | ring->dma = NULL; |
2578 | } |
2579 | |
2580 | if (ring->dma_pdma) { |
2581 | dma_free_coherent(dev: eth->dma_dev, |
2582 | size: ring->dma_size * soc->txrx.txd_size, |
2583 | cpu_addr: ring->dma_pdma, dma_handle: ring->phys_pdma); |
2584 | ring->dma_pdma = NULL; |
2585 | } |
2586 | } |
2587 | |
2588 | static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) |
2589 | { |
2590 | const struct mtk_reg_map *reg_map = eth->soc->reg_map; |
2591 | struct mtk_rx_ring *ring; |
2592 | int rx_data_len, rx_dma_size, tx_ring_size; |
2593 | int i; |
2594 | |
2595 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) |
2596 | tx_ring_size = MTK_QDMA_RING_SIZE; |
2597 | else |
2598 | tx_ring_size = MTK_DMA_SIZE; |
2599 | |
2600 | if (rx_flag == MTK_RX_FLAGS_QDMA) { |
2601 | if (ring_no) |
2602 | return -EINVAL; |
2603 | ring = ð->rx_ring_qdma; |
2604 | } else { |
2605 | ring = ð->rx_ring[ring_no]; |
2606 | } |
2607 | |
2608 | if (rx_flag == MTK_RX_FLAGS_HWLRO) { |
2609 | rx_data_len = MTK_MAX_LRO_RX_LENGTH; |
2610 | rx_dma_size = MTK_HW_LRO_DMA_SIZE; |
2611 | } else { |
2612 | rx_data_len = ETH_DATA_LEN; |
2613 | rx_dma_size = MTK_DMA_SIZE; |
2614 | } |
2615 | |
2616 | ring->frag_size = mtk_max_frag_size(mtu: rx_data_len); |
2617 | ring->buf_size = mtk_max_buf_size(frag_size: ring->frag_size); |
2618 | ring->data = kcalloc(n: rx_dma_size, size: sizeof(*ring->data), |
2619 | GFP_KERNEL); |
2620 | if (!ring->data) |
2621 | return -ENOMEM; |
2622 | |
2623 | if (mtk_page_pool_enabled(eth)) { |
2624 | struct page_pool *pp; |
2625 | |
2626 | pp = mtk_create_page_pool(eth, xdp_q: &ring->xdp_q, id: ring_no, |
2627 | size: rx_dma_size); |
2628 | if (IS_ERR(ptr: pp)) |
2629 | return PTR_ERR(ptr: pp); |
2630 | |
2631 | ring->page_pool = pp; |
2632 | } |
2633 | |
2634 | if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) || |
2635 | rx_flag != MTK_RX_FLAGS_NORMAL) { |
2636 | ring->dma = dma_alloc_coherent(dev: eth->dma_dev, |
2637 | size: rx_dma_size * eth->soc->txrx.rxd_size, |
2638 | dma_handle: &ring->phys, GFP_KERNEL); |
2639 | } else { |
2640 | struct mtk_tx_ring *tx_ring = ð->tx_ring; |
2641 | |
2642 | ring->dma = tx_ring->dma + tx_ring_size * |
2643 | eth->soc->txrx.txd_size * (ring_no + 1); |
2644 | ring->phys = tx_ring->phys + tx_ring_size * |
2645 | eth->soc->txrx.txd_size * (ring_no + 1); |
2646 | } |
2647 | |
2648 | if (!ring->dma) |
2649 | return -ENOMEM; |
2650 | |
2651 | for (i = 0; i < rx_dma_size; i++) { |
2652 | struct mtk_rx_dma_v2 *rxd; |
2653 | dma_addr_t dma_addr; |
2654 | void *data; |
2655 | |
2656 | rxd = ring->dma + i * eth->soc->txrx.rxd_size; |
2657 | if (ring->page_pool) { |
2658 | data = mtk_page_pool_get_buff(pp: ring->page_pool, |
2659 | dma_addr: &dma_addr, GFP_KERNEL); |
2660 | if (!data) |
2661 | return -ENOMEM; |
2662 | } else { |
2663 | if (ring->frag_size <= PAGE_SIZE) |
2664 | data = netdev_alloc_frag(fragsz: ring->frag_size); |
2665 | else |
2666 | data = mtk_max_lro_buf_alloc(GFP_KERNEL); |
2667 | |
2668 | if (!data) |
2669 | return -ENOMEM; |
2670 | |
2671 | dma_addr = dma_map_single(eth->dma_dev, |
2672 | data + NET_SKB_PAD + eth->ip_align, |
2673 | ring->buf_size, DMA_FROM_DEVICE); |
2674 | if (unlikely(dma_mapping_error(eth->dma_dev, |
2675 | dma_addr))) { |
2676 | skb_free_frag(addr: data); |
2677 | return -ENOMEM; |
2678 | } |
2679 | } |
2680 | rxd->rxd1 = (unsigned int)dma_addr; |
2681 | ring->data[i] = data; |
2682 | |
2683 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) |
2684 | rxd->rxd2 = RX_DMA_LSO; |
2685 | else |
2686 | rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); |
2687 | |
2688 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) |
2689 | rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr); |
2690 | |
2691 | rxd->rxd3 = 0; |
2692 | rxd->rxd4 = 0; |
2693 | if (mtk_is_netsys_v2_or_greater(eth)) { |
2694 | rxd->rxd5 = 0; |
2695 | rxd->rxd6 = 0; |
2696 | rxd->rxd7 = 0; |
2697 | rxd->rxd8 = 0; |
2698 | } |
2699 | } |
2700 | |
2701 | ring->dma_size = rx_dma_size; |
2702 | ring->calc_idx_update = false; |
2703 | ring->calc_idx = rx_dma_size - 1; |
2704 | if (rx_flag == MTK_RX_FLAGS_QDMA) |
2705 | ring->crx_idx_reg = reg_map->qdma.qcrx_ptr + |
2706 | ring_no * MTK_QRX_OFFSET; |
2707 | else |
2708 | ring->crx_idx_reg = reg_map->pdma.pcrx_ptr + |
2709 | ring_no * MTK_QRX_OFFSET; |
2710 | /* make sure that all changes to the dma ring are flushed before we |
2711 | * continue |
2712 | */ |
2713 | wmb(); |
2714 | |
2715 | if (rx_flag == MTK_RX_FLAGS_QDMA) { |
2716 | mtk_w32(eth, val: ring->phys, |
2717 | reg: reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET); |
2718 | mtk_w32(eth, val: rx_dma_size, |
2719 | reg: reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); |
2720 | mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), |
2721 | reg: reg_map->qdma.rst_idx); |
2722 | } else { |
2723 | mtk_w32(eth, val: ring->phys, |
2724 | reg: reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET); |
2725 | mtk_w32(eth, val: rx_dma_size, |
2726 | reg: reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); |
2727 | mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), |
2728 | reg: reg_map->pdma.rst_idx); |
2729 | } |
2730 | mtk_w32(eth, val: ring->calc_idx, reg: ring->crx_idx_reg); |
2731 | |
2732 | return 0; |
2733 | } |
2734 | |
2735 | static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram) |
2736 | { |
2737 | u64 addr64 = 0; |
2738 | int i; |
2739 | |
2740 | if (ring->data && ring->dma) { |
2741 | for (i = 0; i < ring->dma_size; i++) { |
2742 | struct mtk_rx_dma *rxd; |
2743 | |
2744 | if (!ring->data[i]) |
2745 | continue; |
2746 | |
2747 | rxd = ring->dma + i * eth->soc->txrx.rxd_size; |
2748 | if (!rxd->rxd1) |
2749 | continue; |
2750 | |
2751 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) |
2752 | addr64 = RX_DMA_GET_ADDR64(rxd->rxd2); |
2753 | |
2754 | dma_unmap_single(eth->dma_dev, ((u64)rxd->rxd1 | addr64), |
2755 | ring->buf_size, DMA_FROM_DEVICE); |
2756 | mtk_rx_put_buff(ring, data: ring->data[i], napi: false); |
2757 | } |
2758 | kfree(objp: ring->data); |
2759 | ring->data = NULL; |
2760 | } |
2761 | |
2762 | if (!in_sram && ring->dma) { |
2763 | dma_free_coherent(dev: eth->dma_dev, |
2764 | size: ring->dma_size * eth->soc->txrx.rxd_size, |
2765 | cpu_addr: ring->dma, dma_handle: ring->phys); |
2766 | ring->dma = NULL; |
2767 | } |
2768 | |
2769 | if (ring->page_pool) { |
2770 | if (xdp_rxq_info_is_reg(xdp_rxq: &ring->xdp_q)) |
2771 | xdp_rxq_info_unreg(xdp_rxq: &ring->xdp_q); |
2772 | page_pool_destroy(pool: ring->page_pool); |
2773 | ring->page_pool = NULL; |
2774 | } |
2775 | } |
2776 | |
2777 | static int mtk_hwlro_rx_init(struct mtk_eth *eth) |
2778 | { |
2779 | int i; |
2780 | u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; |
2781 | u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; |
2782 | |
2783 | /* set LRO rings to auto-learn modes */ |
2784 | ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; |
2785 | |
2786 | /* validate LRO ring */ |
2787 | ring_ctrl_dw2 |= MTK_RING_VLD; |
2788 | |
2789 | /* set AGE timer (unit: 20us) */ |
2790 | ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; |
2791 | ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; |
2792 | |
2793 | /* set max AGG timer (unit: 20us) */ |
2794 | ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; |
2795 | |
2796 | /* set max LRO AGG count */ |
2797 | ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; |
2798 | ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; |
2799 | |
2800 | for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { |
2801 | mtk_w32(eth, val: ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); |
2802 | mtk_w32(eth, val: ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); |
2803 | mtk_w32(eth, val: ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); |
2804 | } |
2805 | |
2806 | /* IPv4 checksum update enable */ |
2807 | lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; |
2808 | |
2809 | /* switch priority comparison to packet count mode */ |
2810 | lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; |
2811 | |
2812 | /* bandwidth threshold setting */ |
2813 | mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); |
2814 | |
2815 | /* auto-learn score delta setting */ |
2816 | mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); |
2817 | |
2818 | /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ |
2819 | mtk_w32(eth, val: (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, |
2820 | MTK_PDMA_LRO_ALT_REFRESH_TIMER); |
2821 | |
2822 | /* set HW LRO mode & the max aggregation count for rx packets */ |
2823 | lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); |
2824 | |
2825 | /* the minimal remaining room of SDL0 in RXD for lro aggregation */ |
2826 | lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; |
2827 | |
2828 | /* enable HW LRO */ |
2829 | lro_ctrl_dw0 |= MTK_LRO_EN; |
2830 | |
2831 | mtk_w32(eth, val: lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); |
2832 | mtk_w32(eth, val: lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); |
2833 | |
2834 | return 0; |
2835 | } |
2836 | |
2837 | static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) |
2838 | { |
2839 | int i; |
2840 | u32 val; |
2841 | |
2842 | /* relinquish lro rings, flush aggregated packets */ |
2843 | mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); |
2844 | |
2845 | /* wait for relinquishments done */ |
2846 | for (i = 0; i < 10; i++) { |
2847 | val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); |
2848 | if (val & MTK_LRO_RING_RELINQUISH_DONE) { |
2849 | msleep(msecs: 20); |
2850 | continue; |
2851 | } |
2852 | break; |
2853 | } |
2854 | |
2855 | /* invalidate lro rings */ |
2856 | for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) |
2857 | mtk_w32(eth, val: 0, MTK_LRO_CTRL_DW2_CFG(i)); |
2858 | |
2859 | /* disable HW LRO */ |
2860 | mtk_w32(eth, val: 0, MTK_PDMA_LRO_CTRL_DW0); |
2861 | } |
2862 | |
2863 | static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) |
2864 | { |
2865 | u32 reg_val; |
2866 | |
2867 | reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); |
2868 | |
2869 | /* invalidate the IP setting */ |
2870 | mtk_w32(eth, val: (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); |
2871 | |
2872 | mtk_w32(eth, val: ip, MTK_LRO_DIP_DW0_CFG(idx)); |
2873 | |
2874 | /* validate the IP setting */ |
2875 | mtk_w32(eth, val: (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); |
2876 | } |
2877 | |
2878 | static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) |
2879 | { |
2880 | u32 reg_val; |
2881 | |
2882 | reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); |
2883 | |
2884 | /* invalidate the IP setting */ |
2885 | mtk_w32(eth, val: (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); |
2886 | |
2887 | mtk_w32(eth, val: 0, MTK_LRO_DIP_DW0_CFG(idx)); |
2888 | } |
2889 | |
2890 | static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) |
2891 | { |
2892 | int cnt = 0; |
2893 | int i; |
2894 | |
2895 | for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { |
2896 | if (mac->hwlro_ip[i]) |
2897 | cnt++; |
2898 | } |
2899 | |
2900 | return cnt; |
2901 | } |
2902 | |
2903 | static int mtk_hwlro_add_ipaddr(struct net_device *dev, |
2904 | struct ethtool_rxnfc *cmd) |
2905 | { |
2906 | struct ethtool_rx_flow_spec *fsp = |
2907 | (struct ethtool_rx_flow_spec *)&cmd->fs; |
2908 | struct mtk_mac *mac = netdev_priv(dev); |
2909 | struct mtk_eth *eth = mac->hw; |
2910 | int hwlro_idx; |
2911 | |
2912 | if ((fsp->flow_type != TCP_V4_FLOW) || |
2913 | (!fsp->h_u.tcp_ip4_spec.ip4dst) || |
2914 | (fsp->location > 1)) |
2915 | return -EINVAL; |
2916 | |
2917 | mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); |
2918 | hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; |
2919 | |
2920 | mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); |
2921 | |
2922 | mtk_hwlro_val_ipaddr(eth, idx: hwlro_idx, ip: mac->hwlro_ip[fsp->location]); |
2923 | |
2924 | return 0; |
2925 | } |
2926 | |
2927 | static int mtk_hwlro_del_ipaddr(struct net_device *dev, |
2928 | struct ethtool_rxnfc *cmd) |
2929 | { |
2930 | struct ethtool_rx_flow_spec *fsp = |
2931 | (struct ethtool_rx_flow_spec *)&cmd->fs; |
2932 | struct mtk_mac *mac = netdev_priv(dev); |
2933 | struct mtk_eth *eth = mac->hw; |
2934 | int hwlro_idx; |
2935 | |
2936 | if (fsp->location > 1) |
2937 | return -EINVAL; |
2938 | |
2939 | mac->hwlro_ip[fsp->location] = 0; |
2940 | hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; |
2941 | |
2942 | mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); |
2943 | |
2944 | mtk_hwlro_inval_ipaddr(eth, idx: hwlro_idx); |
2945 | |
2946 | return 0; |
2947 | } |
2948 | |
2949 | static void mtk_hwlro_netdev_disable(struct net_device *dev) |
2950 | { |
2951 | struct mtk_mac *mac = netdev_priv(dev); |
2952 | struct mtk_eth *eth = mac->hw; |
2953 | int i, hwlro_idx; |
2954 | |
2955 | for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { |
2956 | mac->hwlro_ip[i] = 0; |
2957 | hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; |
2958 | |
2959 | mtk_hwlro_inval_ipaddr(eth, idx: hwlro_idx); |
2960 | } |
2961 | |
2962 | mac->hwlro_ip_cnt = 0; |
2963 | } |
2964 | |
2965 | static int mtk_hwlro_get_fdir_entry(struct net_device *dev, |
2966 | struct ethtool_rxnfc *cmd) |
2967 | { |
2968 | struct mtk_mac *mac = netdev_priv(dev); |
2969 | struct ethtool_rx_flow_spec *fsp = |
2970 | (struct ethtool_rx_flow_spec *)&cmd->fs; |
2971 | |
2972 | if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip)) |
2973 | return -EINVAL; |
2974 | |
2975 | /* only tcp dst ipv4 is meaningful, others are meaningless */ |
2976 | fsp->flow_type = TCP_V4_FLOW; |
2977 | fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); |
2978 | fsp->m_u.tcp_ip4_spec.ip4dst = 0; |
2979 | |
2980 | fsp->h_u.tcp_ip4_spec.ip4src = 0; |
2981 | fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; |
2982 | fsp->h_u.tcp_ip4_spec.psrc = 0; |
2983 | fsp->m_u.tcp_ip4_spec.psrc = 0xffff; |
2984 | fsp->h_u.tcp_ip4_spec.pdst = 0; |
2985 | fsp->m_u.tcp_ip4_spec.pdst = 0xffff; |
2986 | fsp->h_u.tcp_ip4_spec.tos = 0; |
2987 | fsp->m_u.tcp_ip4_spec.tos = 0xff; |
2988 | |
2989 | return 0; |
2990 | } |
2991 | |
2992 | static int mtk_hwlro_get_fdir_all(struct net_device *dev, |
2993 | struct ethtool_rxnfc *cmd, |
2994 | u32 *rule_locs) |
2995 | { |
2996 | struct mtk_mac *mac = netdev_priv(dev); |
2997 | int cnt = 0; |
2998 | int i; |
2999 | |
3000 | for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { |
3001 | if (cnt == cmd->rule_cnt) |
3002 | return -EMSGSIZE; |
3003 | |
3004 | if (mac->hwlro_ip[i]) { |
3005 | rule_locs[cnt] = i; |
3006 | cnt++; |
3007 | } |
3008 | } |
3009 | |
3010 | cmd->rule_cnt = cnt; |
3011 | |
3012 | return 0; |
3013 | } |
3014 | |
3015 | static netdev_features_t mtk_fix_features(struct net_device *dev, |
3016 | netdev_features_t features) |
3017 | { |
3018 | if (!(features & NETIF_F_LRO)) { |
3019 | struct mtk_mac *mac = netdev_priv(dev); |
3020 | int ip_cnt = mtk_hwlro_get_ip_cnt(mac); |
3021 | |
3022 | if (ip_cnt) { |
3023 | netdev_info(dev, format: "RX flow is programmed, LRO should keep on\n" ); |
3024 | |
3025 | features |= NETIF_F_LRO; |
3026 | } |
3027 | } |
3028 | |
3029 | return features; |
3030 | } |
3031 | |
3032 | static int mtk_set_features(struct net_device *dev, netdev_features_t features) |
3033 | { |
3034 | netdev_features_t diff = dev->features ^ features; |
3035 | |
3036 | if ((diff & NETIF_F_LRO) && !(features & NETIF_F_LRO)) |
3037 | mtk_hwlro_netdev_disable(dev); |
3038 | |
3039 | return 0; |
3040 | } |
3041 | |
3042 | /* wait for DMA to finish whatever it is doing before we start using it again */ |
3043 | static int mtk_dma_busy_wait(struct mtk_eth *eth) |
3044 | { |
3045 | unsigned int reg; |
3046 | int ret; |
3047 | u32 val; |
3048 | |
3049 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) |
3050 | reg = eth->soc->reg_map->qdma.glo_cfg; |
3051 | else |
3052 | reg = eth->soc->reg_map->pdma.glo_cfg; |
3053 | |
3054 | ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val, |
3055 | !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)), |
3056 | 5, MTK_DMA_BUSY_TIMEOUT_US); |
3057 | if (ret) |
3058 | dev_err(eth->dev, "DMA init timeout\n" ); |
3059 | |
3060 | return ret; |
3061 | } |
3062 | |
3063 | static int mtk_dma_init(struct mtk_eth *eth) |
3064 | { |
3065 | int err; |
3066 | u32 i; |
3067 | |
3068 | if (mtk_dma_busy_wait(eth)) |
3069 | return -EBUSY; |
3070 | |
3071 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
3072 | /* QDMA needs scratch memory for internal reordering of the |
3073 | * descriptors |
3074 | */ |
3075 | err = mtk_init_fq_dma(eth); |
3076 | if (err) |
3077 | return err; |
3078 | } |
3079 | |
3080 | err = mtk_tx_alloc(eth); |
3081 | if (err) |
3082 | return err; |
3083 | |
3084 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
3085 | err = mtk_rx_alloc(eth, ring_no: 0, rx_flag: MTK_RX_FLAGS_QDMA); |
3086 | if (err) |
3087 | return err; |
3088 | } |
3089 | |
3090 | err = mtk_rx_alloc(eth, ring_no: 0, rx_flag: MTK_RX_FLAGS_NORMAL); |
3091 | if (err) |
3092 | return err; |
3093 | |
3094 | if (eth->hwlro) { |
3095 | for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { |
3096 | err = mtk_rx_alloc(eth, ring_no: i, rx_flag: MTK_RX_FLAGS_HWLRO); |
3097 | if (err) |
3098 | return err; |
3099 | } |
3100 | err = mtk_hwlro_rx_init(eth); |
3101 | if (err) |
3102 | return err; |
3103 | } |
3104 | |
3105 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
3106 | /* Enable random early drop and set drop threshold |
3107 | * automatically |
3108 | */ |
3109 | mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | |
3110 | FC_THRES_MIN, reg: eth->soc->reg_map->qdma.fc_th); |
3111 | mtk_w32(eth, val: 0x0, reg: eth->soc->reg_map->qdma.hred); |
3112 | } |
3113 | |
3114 | return 0; |
3115 | } |
3116 | |
3117 | static void mtk_dma_free(struct mtk_eth *eth) |
3118 | { |
3119 | const struct mtk_soc_data *soc = eth->soc; |
3120 | int i; |
3121 | |
3122 | for (i = 0; i < MTK_MAX_DEVS; i++) |
3123 | if (eth->netdev[i]) |
3124 | netdev_reset_queue(dev_queue: eth->netdev[i]); |
3125 | if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) { |
3126 | dma_free_coherent(dev: eth->dma_dev, |
3127 | MTK_QDMA_RING_SIZE * soc->txrx.txd_size, |
3128 | cpu_addr: eth->scratch_ring, dma_handle: eth->phy_scratch_ring); |
3129 | eth->scratch_ring = NULL; |
3130 | eth->phy_scratch_ring = 0; |
3131 | } |
3132 | mtk_tx_clean(eth); |
3133 | mtk_rx_clean(eth, ring: ð->rx_ring[0], MTK_HAS_CAPS(soc->caps, MTK_SRAM)); |
3134 | mtk_rx_clean(eth, ring: ð->rx_ring_qdma, in_sram: false); |
3135 | |
3136 | if (eth->hwlro) { |
3137 | mtk_hwlro_rx_uninit(eth); |
3138 | for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) |
3139 | mtk_rx_clean(eth, ring: ð->rx_ring[i], in_sram: false); |
3140 | } |
3141 | |
3142 | kfree(objp: eth->scratch_head); |
3143 | } |
3144 | |
3145 | static bool mtk_hw_reset_check(struct mtk_eth *eth) |
3146 | { |
3147 | u32 val = mtk_r32(eth, MTK_INT_STATUS2); |
3148 | |
3149 | return (val & MTK_FE_INT_FQ_EMPTY) || (val & MTK_FE_INT_RFIFO_UF) || |
3150 | (val & MTK_FE_INT_RFIFO_OV) || (val & MTK_FE_INT_TSO_FAIL) || |
3151 | (val & MTK_FE_INT_TSO_ALIGN) || (val & MTK_FE_INT_TSO_ILLEGAL); |
3152 | } |
3153 | |
3154 | static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue) |
3155 | { |
3156 | struct mtk_mac *mac = netdev_priv(dev); |
3157 | struct mtk_eth *eth = mac->hw; |
3158 | |
3159 | if (test_bit(MTK_RESETTING, ð->state)) |
3160 | return; |
3161 | |
3162 | if (!mtk_hw_reset_check(eth)) |
3163 | return; |
3164 | |
3165 | eth->netdev[mac->id]->stats.tx_errors++; |
3166 | netif_err(eth, tx_err, dev, "transmit timed out\n" ); |
3167 | |
3168 | schedule_work(work: ð->pending_work); |
3169 | } |
3170 | |
3171 | static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) |
3172 | { |
3173 | struct mtk_eth *eth = _eth; |
3174 | |
3175 | eth->rx_events++; |
3176 | if (likely(napi_schedule_prep(ð->rx_napi))) { |
3177 | mtk_rx_irq_disable(eth, mask: eth->soc->txrx.rx_irq_done_mask); |
3178 | __napi_schedule(n: ð->rx_napi); |
3179 | } |
3180 | |
3181 | return IRQ_HANDLED; |
3182 | } |
3183 | |
3184 | static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) |
3185 | { |
3186 | struct mtk_eth *eth = _eth; |
3187 | |
3188 | eth->tx_events++; |
3189 | if (likely(napi_schedule_prep(ð->tx_napi))) { |
3190 | mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); |
3191 | __napi_schedule(n: ð->tx_napi); |
3192 | } |
3193 | |
3194 | return IRQ_HANDLED; |
3195 | } |
3196 | |
3197 | static irqreturn_t mtk_handle_irq(int irq, void *_eth) |
3198 | { |
3199 | struct mtk_eth *eth = _eth; |
3200 | const struct mtk_reg_map *reg_map = eth->soc->reg_map; |
3201 | |
3202 | if (mtk_r32(eth, reg: reg_map->pdma.irq_mask) & |
3203 | eth->soc->txrx.rx_irq_done_mask) { |
3204 | if (mtk_r32(eth, reg: reg_map->pdma.irq_status) & |
3205 | eth->soc->txrx.rx_irq_done_mask) |
3206 | mtk_handle_irq_rx(irq, _eth); |
3207 | } |
3208 | if (mtk_r32(eth, reg: reg_map->tx_irq_mask) & MTK_TX_DONE_INT) { |
3209 | if (mtk_r32(eth, reg: reg_map->tx_irq_status) & MTK_TX_DONE_INT) |
3210 | mtk_handle_irq_tx(irq, _eth); |
3211 | } |
3212 | |
3213 | return IRQ_HANDLED; |
3214 | } |
3215 | |
3216 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3217 | static void mtk_poll_controller(struct net_device *dev) |
3218 | { |
3219 | struct mtk_mac *mac = netdev_priv(dev); |
3220 | struct mtk_eth *eth = mac->hw; |
3221 | |
3222 | mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); |
3223 | mtk_rx_irq_disable(eth, mask: eth->soc->txrx.rx_irq_done_mask); |
3224 | mtk_handle_irq_rx(irq: eth->irq[2], eth: dev); |
3225 | mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); |
3226 | mtk_rx_irq_enable(eth, mask: eth->soc->txrx.rx_irq_done_mask); |
3227 | } |
3228 | #endif |
3229 | |
3230 | static int mtk_start_dma(struct mtk_eth *eth) |
3231 | { |
3232 | u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; |
3233 | const struct mtk_reg_map *reg_map = eth->soc->reg_map; |
3234 | int err; |
3235 | |
3236 | err = mtk_dma_init(eth); |
3237 | if (err) { |
3238 | mtk_dma_free(eth); |
3239 | return err; |
3240 | } |
3241 | |
3242 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
3243 | val = mtk_r32(eth, reg: reg_map->qdma.glo_cfg); |
3244 | val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN | |
3245 | MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | |
3246 | MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; |
3247 | |
3248 | if (mtk_is_netsys_v2_or_greater(eth)) |
3249 | val |= MTK_MUTLI_CNT | MTK_RESV_BUF | |
3250 | MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | |
3251 | MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN; |
3252 | else |
3253 | val |= MTK_RX_BT_32DWORDS; |
3254 | mtk_w32(eth, val, reg: reg_map->qdma.glo_cfg); |
3255 | |
3256 | mtk_w32(eth, |
3257 | MTK_RX_DMA_EN | rx_2b_offset | |
3258 | MTK_RX_BT_32DWORDS | MTK_MULTI_EN, |
3259 | reg: reg_map->pdma.glo_cfg); |
3260 | } else { |
3261 | mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | |
3262 | MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, |
3263 | reg: reg_map->pdma.glo_cfg); |
3264 | } |
3265 | |
3266 | return 0; |
3267 | } |
3268 | |
3269 | static void mtk_gdm_config(struct mtk_eth *eth, u32 config) |
3270 | { |
3271 | int i; |
3272 | |
3273 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) |
3274 | return; |
3275 | |
3276 | for (i = 0; i < MTK_MAX_DEVS; i++) { |
3277 | u32 val; |
3278 | |
3279 | if (!eth->netdev[i]) |
3280 | continue; |
3281 | |
3282 | val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); |
3283 | |
3284 | /* default setup the forward port to send frame to PDMA */ |
3285 | val &= ~0xffff; |
3286 | |
3287 | /* Enable RX checksum */ |
3288 | val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; |
3289 | |
3290 | val |= config; |
3291 | |
3292 | if (netdev_uses_dsa(dev: eth->netdev[i])) |
3293 | val |= MTK_GDMA_SPECIAL_TAG; |
3294 | |
3295 | mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); |
3296 | } |
3297 | /* Reset and enable PSE */ |
3298 | mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); |
3299 | mtk_w32(eth, val: 0, MTK_RST_GL); |
3300 | } |
3301 | |
3302 | |
3303 | static bool mtk_uses_dsa(struct net_device *dev) |
3304 | { |
3305 | #if IS_ENABLED(CONFIG_NET_DSA) |
3306 | return netdev_uses_dsa(dev) && |
3307 | dev->dsa_ptr->tag_ops->proto == DSA_TAG_PROTO_MTK; |
3308 | #else |
3309 | return false; |
3310 | #endif |
3311 | } |
3312 | |
3313 | static int mtk_device_event(struct notifier_block *n, unsigned long event, void *ptr) |
3314 | { |
3315 | struct mtk_mac *mac = container_of(n, struct mtk_mac, device_notifier); |
3316 | struct mtk_eth *eth = mac->hw; |
3317 | struct net_device *dev = netdev_notifier_info_to_dev(info: ptr); |
3318 | struct ethtool_link_ksettings s; |
3319 | struct net_device *ldev; |
3320 | struct list_head *iter; |
3321 | struct dsa_port *dp; |
3322 | |
3323 | if (event != NETDEV_CHANGE) |
3324 | return NOTIFY_DONE; |
3325 | |
3326 | netdev_for_each_lower_dev(dev, ldev, iter) { |
3327 | if (netdev_priv(dev: ldev) == mac) |
3328 | goto found; |
3329 | } |
3330 | |
3331 | return NOTIFY_DONE; |
3332 | |
3333 | found: |
3334 | if (!dsa_user_dev_check(dev)) |
3335 | return NOTIFY_DONE; |
3336 | |
3337 | if (__ethtool_get_link_ksettings(dev, link_ksettings: &s)) |
3338 | return NOTIFY_DONE; |
3339 | |
3340 | if (s.base.speed == 0 || s.base.speed == ((__u32)-1)) |
3341 | return NOTIFY_DONE; |
3342 | |
3343 | dp = dsa_port_from_netdev(netdev: dev); |
3344 | if (dp->index >= MTK_QDMA_NUM_QUEUES) |
3345 | return NOTIFY_DONE; |
3346 | |
3347 | if (mac->speed > 0 && mac->speed <= s.base.speed) |
3348 | s.base.speed = 0; |
3349 | |
3350 | mtk_set_queue_speed(eth, idx: dp->index + 3, speed: s.base.speed); |
3351 | |
3352 | return NOTIFY_DONE; |
3353 | } |
3354 | |
3355 | static int mtk_open(struct net_device *dev) |
3356 | { |
3357 | struct mtk_mac *mac = netdev_priv(dev); |
3358 | struct mtk_eth *eth = mac->hw; |
3359 | int i, err; |
3360 | |
3361 | err = phylink_of_phy_connect(mac->phylink, mac->of_node, flags: 0); |
3362 | if (err) { |
3363 | netdev_err(dev, format: "%s: could not attach PHY: %d\n" , __func__, |
3364 | err); |
3365 | return err; |
3366 | } |
3367 | |
3368 | /* we run 2 netdevs on the same dma ring so we only bring it up once */ |
3369 | if (!refcount_read(r: ð->dma_refcnt)) { |
3370 | const struct mtk_soc_data *soc = eth->soc; |
3371 | u32 gdm_config; |
3372 | int i; |
3373 | |
3374 | err = mtk_start_dma(eth); |
3375 | if (err) { |
3376 | phylink_disconnect_phy(mac->phylink); |
3377 | return err; |
3378 | } |
3379 | |
3380 | for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) |
3381 | mtk_ppe_start(ppe: eth->ppe[i]); |
3382 | |
3383 | gdm_config = soc->offload_version ? soc->reg_map->gdma_to_ppe |
3384 | : MTK_GDMA_TO_PDMA; |
3385 | mtk_gdm_config(eth, config: gdm_config); |
3386 | |
3387 | napi_enable(n: ð->tx_napi); |
3388 | napi_enable(n: ð->rx_napi); |
3389 | mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); |
3390 | mtk_rx_irq_enable(eth, mask: soc->txrx.rx_irq_done_mask); |
3391 | refcount_set(r: ð->dma_refcnt, n: 1); |
3392 | } |
3393 | else |
3394 | refcount_inc(r: ð->dma_refcnt); |
3395 | |
3396 | phylink_start(mac->phylink); |
3397 | netif_tx_start_all_queues(dev); |
3398 | |
3399 | if (mtk_is_netsys_v2_or_greater(eth)) |
3400 | return 0; |
3401 | |
3402 | if (mtk_uses_dsa(dev) && !eth->prog) { |
3403 | for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { |
3404 | struct metadata_dst *md_dst = eth->dsa_meta[i]; |
3405 | |
3406 | if (md_dst) |
3407 | continue; |
3408 | |
3409 | md_dst = metadata_dst_alloc(optslen: 0, type: METADATA_HW_PORT_MUX, |
3410 | GFP_KERNEL); |
3411 | if (!md_dst) |
3412 | return -ENOMEM; |
3413 | |
3414 | md_dst->u.port_info.port_id = i; |
3415 | eth->dsa_meta[i] = md_dst; |
3416 | } |
3417 | } else { |
3418 | /* Hardware DSA untagging and VLAN RX offloading need to be |
3419 | * disabled if at least one MAC does not use DSA. |
3420 | */ |
3421 | u32 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); |
3422 | |
3423 | val &= ~MTK_CDMP_STAG_EN; |
3424 | mtk_w32(eth, val, MTK_CDMP_IG_CTRL); |
3425 | |
3426 | mtk_w32(eth, val: 0, MTK_CDMP_EG_CTRL); |
3427 | } |
3428 | |
3429 | return 0; |
3430 | } |
3431 | |
3432 | static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) |
3433 | { |
3434 | u32 val; |
3435 | int i; |
3436 | |
3437 | /* stop the dma engine */ |
3438 | spin_lock_bh(lock: ð->page_lock); |
3439 | val = mtk_r32(eth, reg: glo_cfg); |
3440 | mtk_w32(eth, val: val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), |
3441 | reg: glo_cfg); |
3442 | spin_unlock_bh(lock: ð->page_lock); |
3443 | |
3444 | /* wait for dma stop */ |
3445 | for (i = 0; i < 10; i++) { |
3446 | val = mtk_r32(eth, reg: glo_cfg); |
3447 | if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { |
3448 | msleep(msecs: 20); |
3449 | continue; |
3450 | } |
3451 | break; |
3452 | } |
3453 | } |
3454 | |
3455 | static int mtk_stop(struct net_device *dev) |
3456 | { |
3457 | struct mtk_mac *mac = netdev_priv(dev); |
3458 | struct mtk_eth *eth = mac->hw; |
3459 | int i; |
3460 | |
3461 | phylink_stop(mac->phylink); |
3462 | |
3463 | netif_tx_disable(dev); |
3464 | |
3465 | phylink_disconnect_phy(mac->phylink); |
3466 | |
3467 | /* only shutdown DMA if this is the last user */ |
3468 | if (!refcount_dec_and_test(r: ð->dma_refcnt)) |
3469 | return 0; |
3470 | |
3471 | mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); |
3472 | |
3473 | mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); |
3474 | mtk_rx_irq_disable(eth, mask: eth->soc->txrx.rx_irq_done_mask); |
3475 | napi_disable(n: ð->tx_napi); |
3476 | napi_disable(n: ð->rx_napi); |
3477 | |
3478 | cancel_work_sync(work: ð->rx_dim.work); |
3479 | cancel_work_sync(work: ð->tx_dim.work); |
3480 | |
3481 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) |
3482 | mtk_stop_dma(eth, glo_cfg: eth->soc->reg_map->qdma.glo_cfg); |
3483 | mtk_stop_dma(eth, glo_cfg: eth->soc->reg_map->pdma.glo_cfg); |
3484 | |
3485 | mtk_dma_free(eth); |
3486 | |
3487 | for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) |
3488 | mtk_ppe_stop(ppe: eth->ppe[i]); |
3489 | |
3490 | return 0; |
3491 | } |
3492 | |
3493 | static int mtk_xdp_setup(struct net_device *dev, struct bpf_prog *prog, |
3494 | struct netlink_ext_ack *extack) |
3495 | { |
3496 | struct mtk_mac *mac = netdev_priv(dev); |
3497 | struct mtk_eth *eth = mac->hw; |
3498 | struct bpf_prog *old_prog; |
3499 | bool need_update; |
3500 | |
3501 | if (eth->hwlro) { |
3502 | NL_SET_ERR_MSG_MOD(extack, "XDP not supported with HWLRO" ); |
3503 | return -EOPNOTSUPP; |
3504 | } |
3505 | |
3506 | if (dev->mtu > MTK_PP_MAX_BUF_SIZE) { |
3507 | NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP" ); |
3508 | return -EOPNOTSUPP; |
3509 | } |
3510 | |
3511 | need_update = !!eth->prog != !!prog; |
3512 | if (netif_running(dev) && need_update) |
3513 | mtk_stop(dev); |
3514 | |
3515 | old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held()); |
3516 | if (old_prog) |
3517 | bpf_prog_put(prog: old_prog); |
3518 | |
3519 | if (netif_running(dev) && need_update) |
3520 | return mtk_open(dev); |
3521 | |
3522 | return 0; |
3523 | } |
3524 | |
3525 | static int mtk_xdp(struct net_device *dev, struct netdev_bpf *xdp) |
3526 | { |
3527 | switch (xdp->command) { |
3528 | case XDP_SETUP_PROG: |
3529 | return mtk_xdp_setup(dev, prog: xdp->prog, extack: xdp->extack); |
3530 | default: |
3531 | return -EINVAL; |
3532 | } |
3533 | } |
3534 | |
3535 | static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) |
3536 | { |
3537 | regmap_update_bits(map: eth->ethsys, ETHSYS_RSTCTRL, |
3538 | mask: reset_bits, |
3539 | val: reset_bits); |
3540 | |
3541 | usleep_range(min: 1000, max: 1100); |
3542 | regmap_update_bits(map: eth->ethsys, ETHSYS_RSTCTRL, |
3543 | mask: reset_bits, |
3544 | val: ~reset_bits); |
3545 | mdelay(10); |
3546 | } |
3547 | |
3548 | static void mtk_clk_disable(struct mtk_eth *eth) |
3549 | { |
3550 | int clk; |
3551 | |
3552 | for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) |
3553 | clk_disable_unprepare(clk: eth->clks[clk]); |
3554 | } |
3555 | |
3556 | static int mtk_clk_enable(struct mtk_eth *eth) |
3557 | { |
3558 | int clk, ret; |
3559 | |
3560 | for (clk = 0; clk < MTK_CLK_MAX ; clk++) { |
3561 | ret = clk_prepare_enable(clk: eth->clks[clk]); |
3562 | if (ret) |
3563 | goto err_disable_clks; |
3564 | } |
3565 | |
3566 | return 0; |
3567 | |
3568 | err_disable_clks: |
3569 | while (--clk >= 0) |
3570 | clk_disable_unprepare(clk: eth->clks[clk]); |
3571 | |
3572 | return ret; |
3573 | } |
3574 | |
3575 | static void mtk_dim_rx(struct work_struct *work) |
3576 | { |
3577 | struct dim *dim = container_of(work, struct dim, work); |
3578 | struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim); |
3579 | const struct mtk_reg_map *reg_map = eth->soc->reg_map; |
3580 | struct dim_cq_moder cur_profile; |
3581 | u32 val, cur; |
3582 | |
3583 | cur_profile = net_dim_get_rx_moderation(cq_period_mode: eth->rx_dim.mode, |
3584 | ix: dim->profile_ix); |
3585 | spin_lock_bh(lock: ð->dim_lock); |
3586 | |
3587 | val = mtk_r32(eth, reg: reg_map->pdma.delay_irq); |
3588 | val &= MTK_PDMA_DELAY_TX_MASK; |
3589 | val |= MTK_PDMA_DELAY_RX_EN; |
3590 | |
3591 | cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); |
3592 | val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT; |
3593 | |
3594 | cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); |
3595 | val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT; |
3596 | |
3597 | mtk_w32(eth, val, reg: reg_map->pdma.delay_irq); |
3598 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) |
3599 | mtk_w32(eth, val, reg: reg_map->qdma.delay_irq); |
3600 | |
3601 | spin_unlock_bh(lock: ð->dim_lock); |
3602 | |
3603 | dim->state = DIM_START_MEASURE; |
3604 | } |
3605 | |
3606 | static void mtk_dim_tx(struct work_struct *work) |
3607 | { |
3608 | struct dim *dim = container_of(work, struct dim, work); |
3609 | struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim); |
3610 | const struct mtk_reg_map *reg_map = eth->soc->reg_map; |
3611 | struct dim_cq_moder cur_profile; |
3612 | u32 val, cur; |
3613 | |
3614 | cur_profile = net_dim_get_tx_moderation(cq_period_mode: eth->tx_dim.mode, |
3615 | ix: dim->profile_ix); |
3616 | spin_lock_bh(lock: ð->dim_lock); |
3617 | |
3618 | val = mtk_r32(eth, reg: reg_map->pdma.delay_irq); |
3619 | val &= MTK_PDMA_DELAY_RX_MASK; |
3620 | val |= MTK_PDMA_DELAY_TX_EN; |
3621 | |
3622 | cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); |
3623 | val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT; |
3624 | |
3625 | cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); |
3626 | val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT; |
3627 | |
3628 | mtk_w32(eth, val, reg: reg_map->pdma.delay_irq); |
3629 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) |
3630 | mtk_w32(eth, val, reg: reg_map->qdma.delay_irq); |
3631 | |
3632 | spin_unlock_bh(lock: ð->dim_lock); |
3633 | |
3634 | dim->state = DIM_START_MEASURE; |
3635 | } |
3636 | |
3637 | static void mtk_set_mcr_max_rx(struct mtk_mac *mac, u32 val) |
3638 | { |
3639 | struct mtk_eth *eth = mac->hw; |
3640 | u32 mcr_cur, mcr_new; |
3641 | |
3642 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) |
3643 | return; |
3644 | |
3645 | mcr_cur = mtk_r32(eth: mac->hw, MTK_MAC_MCR(mac->id)); |
3646 | mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK; |
3647 | |
3648 | if (val <= 1518) |
3649 | mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518); |
3650 | else if (val <= 1536) |
3651 | mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536); |
3652 | else if (val <= 1552) |
3653 | mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552); |
3654 | else |
3655 | mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048); |
3656 | |
3657 | if (mcr_new != mcr_cur) |
3658 | mtk_w32(eth: mac->hw, val: mcr_new, MTK_MAC_MCR(mac->id)); |
3659 | } |
3660 | |
3661 | static void mtk_hw_reset(struct mtk_eth *eth) |
3662 | { |
3663 | u32 val; |
3664 | |
3665 | if (mtk_is_netsys_v2_or_greater(eth)) |
3666 | regmap_write(map: eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, val: 0); |
3667 | |
3668 | if (mtk_is_netsys_v3_or_greater(eth)) { |
3669 | val = RSTCTRL_PPE0_V3; |
3670 | |
3671 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) |
3672 | val |= RSTCTRL_PPE1_V3; |
3673 | |
3674 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) |
3675 | val |= RSTCTRL_PPE2; |
3676 | |
3677 | val |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2; |
3678 | } else if (mtk_is_netsys_v2_or_greater(eth)) { |
3679 | val = RSTCTRL_PPE0_V2; |
3680 | |
3681 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) |
3682 | val |= RSTCTRL_PPE1; |
3683 | } else { |
3684 | val = RSTCTRL_PPE0; |
3685 | } |
3686 | |
3687 | ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); |
3688 | |
3689 | if (mtk_is_netsys_v3_or_greater(eth)) |
3690 | regmap_write(map: eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, |
3691 | val: 0x6f8ff); |
3692 | else if (mtk_is_netsys_v2_or_greater(eth)) |
3693 | regmap_write(map: eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, |
3694 | val: 0x3ffffff); |
3695 | } |
3696 | |
3697 | static u32 mtk_hw_reset_read(struct mtk_eth *eth) |
3698 | { |
3699 | u32 val; |
3700 | |
3701 | regmap_read(map: eth->ethsys, ETHSYS_RSTCTRL, val: &val); |
3702 | return val; |
3703 | } |
3704 | |
3705 | static void mtk_hw_warm_reset(struct mtk_eth *eth) |
3706 | { |
3707 | u32 rst_mask, val; |
3708 | |
3709 | regmap_update_bits(map: eth->ethsys, ETHSYS_RSTCTRL, RSTCTRL_FE, |
3710 | RSTCTRL_FE); |
3711 | if (readx_poll_timeout_atomic(mtk_hw_reset_read, eth, val, |
3712 | val & RSTCTRL_FE, 1, 1000)) { |
3713 | dev_err(eth->dev, "warm reset failed\n" ); |
3714 | mtk_hw_reset(eth); |
3715 | return; |
3716 | } |
3717 | |
3718 | if (mtk_is_netsys_v3_or_greater(eth)) { |
3719 | rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V3; |
3720 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) |
3721 | rst_mask |= RSTCTRL_PPE1_V3; |
3722 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) |
3723 | rst_mask |= RSTCTRL_PPE2; |
3724 | |
3725 | rst_mask |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2; |
3726 | } else if (mtk_is_netsys_v2_or_greater(eth)) { |
3727 | rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2; |
3728 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) |
3729 | rst_mask |= RSTCTRL_PPE1; |
3730 | } else { |
3731 | rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0; |
3732 | } |
3733 | |
3734 | regmap_update_bits(map: eth->ethsys, ETHSYS_RSTCTRL, mask: rst_mask, val: rst_mask); |
3735 | |
3736 | udelay(1); |
3737 | val = mtk_hw_reset_read(eth); |
3738 | if (!(val & rst_mask)) |
3739 | dev_err(eth->dev, "warm reset stage0 failed %08x (%08x)\n" , |
3740 | val, rst_mask); |
3741 | |
3742 | rst_mask |= RSTCTRL_FE; |
3743 | regmap_update_bits(map: eth->ethsys, ETHSYS_RSTCTRL, mask: rst_mask, val: ~rst_mask); |
3744 | |
3745 | udelay(1); |
3746 | val = mtk_hw_reset_read(eth); |
3747 | if (val & rst_mask) |
3748 | dev_err(eth->dev, "warm reset stage1 failed %08x (%08x)\n" , |
3749 | val, rst_mask); |
3750 | } |
3751 | |
3752 | static bool mtk_hw_check_dma_hang(struct mtk_eth *eth) |
3753 | { |
3754 | const struct mtk_reg_map *reg_map = eth->soc->reg_map; |
3755 | bool gmac1_tx, gmac2_tx, gdm1_tx, gdm2_tx; |
3756 | bool oq_hang, cdm1_busy, adma_busy; |
3757 | bool wtx_busy, cdm_full, oq_free; |
3758 | u32 wdidx, val, gdm1_fc, gdm2_fc; |
3759 | bool qfsm_hang, qfwd_hang; |
3760 | bool ret = false; |
3761 | |
3762 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) |
3763 | return false; |
3764 | |
3765 | /* WDMA sanity checks */ |
3766 | wdidx = mtk_r32(eth, reg: reg_map->wdma_base[0] + 0xc); |
3767 | |
3768 | val = mtk_r32(eth, reg: reg_map->wdma_base[0] + 0x204); |
3769 | wtx_busy = FIELD_GET(MTK_TX_DMA_BUSY, val); |
3770 | |
3771 | val = mtk_r32(eth, reg: reg_map->wdma_base[0] + 0x230); |
3772 | cdm_full = !FIELD_GET(MTK_CDM_TXFIFO_RDY, val); |
3773 | |
3774 | oq_free = (!(mtk_r32(eth, reg: reg_map->pse_oq_sta) & GENMASK(24, 16)) && |
3775 | !(mtk_r32(eth, reg: reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) && |
3776 | !(mtk_r32(eth, reg: reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16))); |
3777 | |
3778 | if (wdidx == eth->reset.wdidx && wtx_busy && cdm_full && oq_free) { |
3779 | if (++eth->reset.wdma_hang_count > 2) { |
3780 | eth->reset.wdma_hang_count = 0; |
3781 | ret = true; |
3782 | } |
3783 | goto out; |
3784 | } |
3785 | |
3786 | /* QDMA sanity checks */ |
3787 | qfsm_hang = !!mtk_r32(eth, reg: reg_map->qdma.qtx_cfg + 0x234); |
3788 | qfwd_hang = !mtk_r32(eth, reg: reg_map->qdma.qtx_cfg + 0x308); |
3789 | |
3790 | gdm1_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM1_FSM)) > 0; |
3791 | gdm2_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM2_FSM)) > 0; |
3792 | gmac1_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(0))) != 1; |
3793 | gmac2_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(1))) != 1; |
3794 | gdm1_fc = mtk_r32(eth, reg: reg_map->gdm1_cnt + 0x24); |
3795 | gdm2_fc = mtk_r32(eth, reg: reg_map->gdm1_cnt + 0x64); |
3796 | |
3797 | if (qfsm_hang && qfwd_hang && |
3798 | ((gdm1_tx && gmac1_tx && gdm1_fc < 1) || |
3799 | (gdm2_tx && gmac2_tx && gdm2_fc < 1))) { |
3800 | if (++eth->reset.qdma_hang_count > 2) { |
3801 | eth->reset.qdma_hang_count = 0; |
3802 | ret = true; |
3803 | } |
3804 | goto out; |
3805 | } |
3806 | |
3807 | /* ADMA sanity checks */ |
3808 | oq_hang = !!(mtk_r32(eth, reg: reg_map->pse_oq_sta) & GENMASK(8, 0)); |
3809 | cdm1_busy = !!(mtk_r32(eth, MTK_FE_CDM1_FSM) & GENMASK(31, 16)); |
3810 | adma_busy = !(mtk_r32(eth, reg: reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) && |
3811 | !(mtk_r32(eth, reg: reg_map->pdma.adma_rx_dbg0) & BIT(6)); |
3812 | |
3813 | if (oq_hang && cdm1_busy && adma_busy) { |
3814 | if (++eth->reset.adma_hang_count > 2) { |
3815 | eth->reset.adma_hang_count = 0; |
3816 | ret = true; |
3817 | } |
3818 | goto out; |
3819 | } |
3820 | |
3821 | eth->reset.wdma_hang_count = 0; |
3822 | eth->reset.qdma_hang_count = 0; |
3823 | eth->reset.adma_hang_count = 0; |
3824 | out: |
3825 | eth->reset.wdidx = wdidx; |
3826 | |
3827 | return ret; |
3828 | } |
3829 | |
3830 | static void mtk_hw_reset_monitor_work(struct work_struct *work) |
3831 | { |
3832 | struct delayed_work *del_work = to_delayed_work(work); |
3833 | struct mtk_eth *eth = container_of(del_work, struct mtk_eth, |
3834 | reset.monitor_work); |
3835 | |
3836 | if (test_bit(MTK_RESETTING, ð->state)) |
3837 | goto out; |
3838 | |
3839 | /* DMA stuck checks */ |
3840 | if (mtk_hw_check_dma_hang(eth)) |
3841 | schedule_work(work: ð->pending_work); |
3842 | |
3843 | out: |
3844 | schedule_delayed_work(dwork: ð->reset.monitor_work, |
3845 | MTK_DMA_MONITOR_TIMEOUT); |
3846 | } |
3847 | |
3848 | static int mtk_hw_init(struct mtk_eth *eth, bool reset) |
3849 | { |
3850 | u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA | |
3851 | ETHSYS_DMA_AG_MAP_PPE; |
3852 | const struct mtk_reg_map *reg_map = eth->soc->reg_map; |
3853 | int i, val, ret; |
3854 | |
3855 | if (!reset && test_and_set_bit(nr: MTK_HW_INIT, addr: ð->state)) |
3856 | return 0; |
3857 | |
3858 | if (!reset) { |
3859 | pm_runtime_enable(dev: eth->dev); |
3860 | pm_runtime_get_sync(dev: eth->dev); |
3861 | |
3862 | ret = mtk_clk_enable(eth); |
3863 | if (ret) |
3864 | goto err_disable_pm; |
3865 | } |
3866 | |
3867 | if (eth->ethsys) |
3868 | regmap_update_bits(map: eth->ethsys, ETHSYS_DMA_AG_MAP, mask: dma_mask, |
3869 | val: of_dma_is_coherent(np: eth->dma_dev->of_node) * dma_mask); |
3870 | |
3871 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { |
3872 | ret = device_reset(dev: eth->dev); |
3873 | if (ret) { |
3874 | dev_err(eth->dev, "MAC reset failed!\n" ); |
3875 | goto err_disable_pm; |
3876 | } |
3877 | |
3878 | /* set interrupt delays based on current Net DIM sample */ |
3879 | mtk_dim_rx(work: ð->rx_dim.work); |
3880 | mtk_dim_tx(work: ð->tx_dim.work); |
3881 | |
3882 | /* disable delay and normal interrupt */ |
3883 | mtk_tx_irq_disable(eth, mask: ~0); |
3884 | mtk_rx_irq_disable(eth, mask: ~0); |
3885 | |
3886 | return 0; |
3887 | } |
3888 | |
3889 | msleep(msecs: 100); |
3890 | |
3891 | if (reset) |
3892 | mtk_hw_warm_reset(eth); |
3893 | else |
3894 | mtk_hw_reset(eth); |
3895 | |
3896 | if (mtk_is_netsys_v2_or_greater(eth)) { |
3897 | /* Set FE to PDMAv2 if necessary */ |
3898 | val = mtk_r32(eth, MTK_FE_GLO_MISC); |
3899 | mtk_w32(eth, val: val | BIT(4), MTK_FE_GLO_MISC); |
3900 | } |
3901 | |
3902 | if (eth->pctl) { |
3903 | /* Set GE2 driving and slew rate */ |
3904 | regmap_write(map: eth->pctl, GPIO_DRV_SEL10, val: 0xa00); |
3905 | |
3906 | /* set GE2 TDSEL */ |
3907 | regmap_write(map: eth->pctl, GPIO_OD33_CTRL8, val: 0x5); |
3908 | |
3909 | /* set GE2 TUNE */ |
3910 | regmap_write(map: eth->pctl, GPIO_BIAS_CTRL, val: 0x0); |
3911 | } |
3912 | |
3913 | /* Set linkdown as the default for each GMAC. Its own MCR would be set |
3914 | * up with the more appropriate value when mtk_mac_config call is being |
3915 | * invoked. |
3916 | */ |
3917 | for (i = 0; i < MTK_MAX_DEVS; i++) { |
3918 | struct net_device *dev = eth->netdev[i]; |
3919 | |
3920 | if (!dev) |
3921 | continue; |
3922 | |
3923 | mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); |
3924 | mtk_set_mcr_max_rx(mac: netdev_priv(dev), |
3925 | val: dev->mtu + MTK_RX_ETH_HLEN); |
3926 | } |
3927 | |
3928 | /* Indicates CDM to parse the MTK special tag from CPU |
3929 | * which also is working out for untag packets. |
3930 | */ |
3931 | val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); |
3932 | mtk_w32(eth, val: val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); |
3933 | if (mtk_is_netsys_v1(eth)) { |
3934 | val = mtk_r32(eth, MTK_CDMP_IG_CTRL); |
3935 | mtk_w32(eth, val: val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); |
3936 | |
3937 | mtk_w32(eth, val: 1, MTK_CDMP_EG_CTRL); |
3938 | } |
3939 | |
3940 | /* set interrupt delays based on current Net DIM sample */ |
3941 | mtk_dim_rx(work: ð->rx_dim.work); |
3942 | mtk_dim_tx(work: ð->tx_dim.work); |
3943 | |
3944 | /* disable delay and normal interrupt */ |
3945 | mtk_tx_irq_disable(eth, mask: ~0); |
3946 | mtk_rx_irq_disable(eth, mask: ~0); |
3947 | |
3948 | /* FE int grouping */ |
3949 | mtk_w32(eth, MTK_TX_DONE_INT, reg: reg_map->pdma.int_grp); |
3950 | mtk_w32(eth, val: eth->soc->txrx.rx_irq_done_mask, reg: reg_map->pdma.int_grp + 4); |
3951 | mtk_w32(eth, MTK_TX_DONE_INT, reg: reg_map->qdma.int_grp); |
3952 | mtk_w32(eth, val: eth->soc->txrx.rx_irq_done_mask, reg: reg_map->qdma.int_grp + 4); |
3953 | mtk_w32(eth, val: 0x21021000, MTK_FE_INT_GRP); |
3954 | |
3955 | if (mtk_is_netsys_v3_or_greater(eth)) { |
3956 | /* PSE should not drop port1, port8 and port9 packets */ |
3957 | mtk_w32(eth, val: 0x00000302, PSE_DROP_CFG); |
3958 | |
3959 | /* GDM and CDM Threshold */ |
3960 | mtk_w32(eth, val: 0x00000707, MTK_CDMW0_THRES); |
3961 | mtk_w32(eth, val: 0x00000077, MTK_CDMW1_THRES); |
3962 | |
3963 | /* Disable GDM1 RX CRC stripping */ |
3964 | mtk_m32(eth, MTK_GDMA_STRP_CRC, set: 0, MTK_GDMA_FWD_CFG(0)); |
3965 | |
3966 | /* PSE GDM3 MIB counter has incorrect hw default values, |
3967 | * so the driver ought to read clear the values beforehand |
3968 | * in case ethtool retrieve wrong mib values. |
3969 | */ |
3970 | for (i = 0; i < 0x80; i += 0x4) |
3971 | mtk_r32(eth, reg: reg_map->gdm1_cnt + 0x100 + i); |
3972 | } else if (!mtk_is_netsys_v1(eth)) { |
3973 | /* PSE should not drop port8 and port9 packets from WDMA Tx */ |
3974 | mtk_w32(eth, val: 0x00000300, PSE_DROP_CFG); |
3975 | |
3976 | /* PSE should drop packets to port 8/9 on WDMA Rx ring full */ |
3977 | mtk_w32(eth, val: 0x00000300, PSE_PPE0_DROP); |
3978 | |
3979 | /* PSE Free Queue Flow Control */ |
3980 | mtk_w32(eth, val: 0x01fa01f4, PSE_FQFC_CFG2); |
3981 | |
3982 | /* PSE config input queue threshold */ |
3983 | mtk_w32(eth, val: 0x001a000e, PSE_IQ_REV(1)); |
3984 | mtk_w32(eth, val: 0x01ff001a, PSE_IQ_REV(2)); |
3985 | mtk_w32(eth, val: 0x000e01ff, PSE_IQ_REV(3)); |
3986 | mtk_w32(eth, val: 0x000e000e, PSE_IQ_REV(4)); |
3987 | mtk_w32(eth, val: 0x000e000e, PSE_IQ_REV(5)); |
3988 | mtk_w32(eth, val: 0x000e000e, PSE_IQ_REV(6)); |
3989 | mtk_w32(eth, val: 0x000e000e, PSE_IQ_REV(7)); |
3990 | mtk_w32(eth, val: 0x000e000e, PSE_IQ_REV(8)); |
3991 | |
3992 | /* PSE config output queue threshold */ |
3993 | mtk_w32(eth, val: 0x000f000a, PSE_OQ_TH(1)); |
3994 | mtk_w32(eth, val: 0x001a000f, PSE_OQ_TH(2)); |
3995 | mtk_w32(eth, val: 0x000f001a, PSE_OQ_TH(3)); |
3996 | mtk_w32(eth, val: 0x01ff000f, PSE_OQ_TH(4)); |
3997 | mtk_w32(eth, val: 0x000f000f, PSE_OQ_TH(5)); |
3998 | mtk_w32(eth, val: 0x0006000f, PSE_OQ_TH(6)); |
3999 | mtk_w32(eth, val: 0x00060006, PSE_OQ_TH(7)); |
4000 | mtk_w32(eth, val: 0x00060006, PSE_OQ_TH(8)); |
4001 | |
4002 | /* GDM and CDM Threshold */ |
4003 | mtk_w32(eth, val: 0x00000004, MTK_GDM2_THRES); |
4004 | mtk_w32(eth, val: 0x00000004, MTK_CDMW0_THRES); |
4005 | mtk_w32(eth, val: 0x00000004, MTK_CDMW1_THRES); |
4006 | mtk_w32(eth, val: 0x00000004, MTK_CDME0_THRES); |
4007 | mtk_w32(eth, val: 0x00000004, MTK_CDME1_THRES); |
4008 | mtk_w32(eth, val: 0x00000004, MTK_CDMM_THRES); |
4009 | } |
4010 | |
4011 | return 0; |
4012 | |
4013 | err_disable_pm: |
4014 | if (!reset) { |
4015 | pm_runtime_put_sync(dev: eth->dev); |
4016 | pm_runtime_disable(dev: eth->dev); |
4017 | } |
4018 | |
4019 | return ret; |
4020 | } |
4021 | |
4022 | static int mtk_hw_deinit(struct mtk_eth *eth) |
4023 | { |
4024 | if (!test_and_clear_bit(nr: MTK_HW_INIT, addr: ð->state)) |
4025 | return 0; |
4026 | |
4027 | mtk_clk_disable(eth); |
4028 | |
4029 | pm_runtime_put_sync(dev: eth->dev); |
4030 | pm_runtime_disable(dev: eth->dev); |
4031 | |
4032 | return 0; |
4033 | } |
4034 | |
4035 | static void mtk_uninit(struct net_device *dev) |
4036 | { |
4037 | struct mtk_mac *mac = netdev_priv(dev); |
4038 | struct mtk_eth *eth = mac->hw; |
4039 | |
4040 | phylink_disconnect_phy(mac->phylink); |
4041 | mtk_tx_irq_disable(eth, mask: ~0); |
4042 | mtk_rx_irq_disable(eth, mask: ~0); |
4043 | } |
4044 | |
4045 | static int mtk_change_mtu(struct net_device *dev, int new_mtu) |
4046 | { |
4047 | int length = new_mtu + MTK_RX_ETH_HLEN; |
4048 | struct mtk_mac *mac = netdev_priv(dev); |
4049 | struct mtk_eth *eth = mac->hw; |
4050 | |
4051 | if (rcu_access_pointer(eth->prog) && |
4052 | length > MTK_PP_MAX_BUF_SIZE) { |
4053 | netdev_err(dev, format: "Invalid MTU for XDP mode\n" ); |
4054 | return -EINVAL; |
4055 | } |
4056 | |
4057 | mtk_set_mcr_max_rx(mac, val: length); |
4058 | dev->mtu = new_mtu; |
4059 | |
4060 | return 0; |
4061 | } |
4062 | |
4063 | static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
4064 | { |
4065 | struct mtk_mac *mac = netdev_priv(dev); |
4066 | |
4067 | switch (cmd) { |
4068 | case SIOCGMIIPHY: |
4069 | case SIOCGMIIREG: |
4070 | case SIOCSMIIREG: |
4071 | return phylink_mii_ioctl(mac->phylink, ifr, cmd); |
4072 | default: |
4073 | break; |
4074 | } |
4075 | |
4076 | return -EOPNOTSUPP; |
4077 | } |
4078 | |
4079 | static void mtk_prepare_for_reset(struct mtk_eth *eth) |
4080 | { |
4081 | u32 val; |
4082 | int i; |
4083 | |
4084 | /* set FE PPE ports link down */ |
4085 | for (i = MTK_GMAC1_ID; |
4086 | i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID); |
4087 | i += 2) { |
4088 | val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) | MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT); |
4089 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) |
4090 | val |= MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT); |
4091 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) |
4092 | val |= MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT); |
4093 | mtk_w32(eth, val, MTK_FE_GLO_CFG(i)); |
4094 | } |
4095 | |
4096 | /* adjust PPE configurations to prepare for reset */ |
4097 | for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) |
4098 | mtk_ppe_prepare_reset(ppe: eth->ppe[i]); |
4099 | |
4100 | /* disable NETSYS interrupts */ |
4101 | mtk_w32(eth, val: 0, MTK_FE_INT_ENABLE); |
4102 | |
4103 | /* force link down GMAC */ |
4104 | for (i = 0; i < 2; i++) { |
4105 | val = mtk_r32(eth, MTK_MAC_MCR(i)) & ~MAC_MCR_FORCE_LINK; |
4106 | mtk_w32(eth, val, MTK_MAC_MCR(i)); |
4107 | } |
4108 | } |
4109 | |
4110 | static void mtk_pending_work(struct work_struct *work) |
4111 | { |
4112 | struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); |
4113 | unsigned long restart = 0; |
4114 | u32 val; |
4115 | int i; |
4116 | |
4117 | rtnl_lock(); |
4118 | set_bit(nr: MTK_RESETTING, addr: ð->state); |
4119 | |
4120 | mtk_prepare_for_reset(eth); |
4121 | mtk_wed_fe_reset(); |
4122 | /* Run again reset preliminary configuration in order to avoid any |
4123 | * possible race during FE reset since it can run releasing RTNL lock. |
4124 | */ |
4125 | mtk_prepare_for_reset(eth); |
4126 | |
4127 | /* stop all devices to make sure that dma is properly shut down */ |
4128 | for (i = 0; i < MTK_MAX_DEVS; i++) { |
4129 | if (!eth->netdev[i] || !netif_running(dev: eth->netdev[i])) |
4130 | continue; |
4131 | |
4132 | mtk_stop(dev: eth->netdev[i]); |
4133 | __set_bit(i, &restart); |
4134 | } |
4135 | |
4136 | usleep_range(min: 15000, max: 16000); |
4137 | |
4138 | if (eth->dev->pins) |
4139 | pinctrl_select_state(p: eth->dev->pins->p, |
4140 | s: eth->dev->pins->default_state); |
4141 | mtk_hw_init(eth, reset: true); |
4142 | |
4143 | /* restart DMA and enable IRQs */ |
4144 | for (i = 0; i < MTK_MAX_DEVS; i++) { |
4145 | if (!eth->netdev[i] || !test_bit(i, &restart)) |
4146 | continue; |
4147 | |
4148 | if (mtk_open(dev: eth->netdev[i])) { |
4149 | netif_alert(eth, ifup, eth->netdev[i], |
4150 | "Driver up/down cycle failed\n" ); |
4151 | dev_close(dev: eth->netdev[i]); |
4152 | } |
4153 | } |
4154 | |
4155 | /* set FE PPE ports link up */ |
4156 | for (i = MTK_GMAC1_ID; |
4157 | i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID); |
4158 | i += 2) { |
4159 | val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) & ~MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT); |
4160 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) |
4161 | val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT); |
4162 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) |
4163 | val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT); |
4164 | |
4165 | mtk_w32(eth, val, MTK_FE_GLO_CFG(i)); |
4166 | } |
4167 | |
4168 | clear_bit(nr: MTK_RESETTING, addr: ð->state); |
4169 | |
4170 | mtk_wed_fe_reset_complete(); |
4171 | |
4172 | rtnl_unlock(); |
4173 | } |
4174 | |
4175 | static int mtk_free_dev(struct mtk_eth *eth) |
4176 | { |
4177 | int i; |
4178 | |
4179 | for (i = 0; i < MTK_MAX_DEVS; i++) { |
4180 | if (!eth->netdev[i]) |
4181 | continue; |
4182 | free_netdev(dev: eth->netdev[i]); |
4183 | } |
4184 | |
4185 | for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { |
4186 | if (!eth->dsa_meta[i]) |
4187 | break; |
4188 | metadata_dst_free(eth->dsa_meta[i]); |
4189 | } |
4190 | |
4191 | return 0; |
4192 | } |
4193 | |
4194 | static int mtk_unreg_dev(struct mtk_eth *eth) |
4195 | { |
4196 | int i; |
4197 | |
4198 | for (i = 0; i < MTK_MAX_DEVS; i++) { |
4199 | struct mtk_mac *mac; |
4200 | if (!eth->netdev[i]) |
4201 | continue; |
4202 | mac = netdev_priv(dev: eth->netdev[i]); |
4203 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) |
4204 | unregister_netdevice_notifier(nb: &mac->device_notifier); |
4205 | unregister_netdev(dev: eth->netdev[i]); |
4206 | } |
4207 | |
4208 | return 0; |
4209 | } |
4210 | |
4211 | static void mtk_sgmii_destroy(struct mtk_eth *eth) |
4212 | { |
4213 | int i; |
4214 | |
4215 | for (i = 0; i < MTK_MAX_DEVS; i++) |
4216 | mtk_pcs_lynxi_destroy(pcs: eth->sgmii_pcs[i]); |
4217 | } |
4218 | |
4219 | static int mtk_cleanup(struct mtk_eth *eth) |
4220 | { |
4221 | mtk_sgmii_destroy(eth); |
4222 | mtk_unreg_dev(eth); |
4223 | mtk_free_dev(eth); |
4224 | cancel_work_sync(work: ð->pending_work); |
4225 | cancel_delayed_work_sync(dwork: ð->reset.monitor_work); |
4226 | |
4227 | return 0; |
4228 | } |
4229 | |
4230 | static int mtk_get_link_ksettings(struct net_device *ndev, |
4231 | struct ethtool_link_ksettings *cmd) |
4232 | { |
4233 | struct mtk_mac *mac = netdev_priv(dev: ndev); |
4234 | |
4235 | if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) |
4236 | return -EBUSY; |
4237 | |
4238 | return phylink_ethtool_ksettings_get(mac->phylink, cmd); |
4239 | } |
4240 | |
4241 | static int mtk_set_link_ksettings(struct net_device *ndev, |
4242 | const struct ethtool_link_ksettings *cmd) |
4243 | { |
4244 | struct mtk_mac *mac = netdev_priv(dev: ndev); |
4245 | |
4246 | if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) |
4247 | return -EBUSY; |
4248 | |
4249 | return phylink_ethtool_ksettings_set(mac->phylink, cmd); |
4250 | } |
4251 | |
4252 | static void mtk_get_drvinfo(struct net_device *dev, |
4253 | struct ethtool_drvinfo *info) |
4254 | { |
4255 | struct mtk_mac *mac = netdev_priv(dev); |
4256 | |
4257 | strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); |
4258 | strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); |
4259 | info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); |
4260 | } |
4261 | |
4262 | static u32 mtk_get_msglevel(struct net_device *dev) |
4263 | { |
4264 | struct mtk_mac *mac = netdev_priv(dev); |
4265 | |
4266 | return mac->hw->msg_enable; |
4267 | } |
4268 | |
4269 | static void mtk_set_msglevel(struct net_device *dev, u32 value) |
4270 | { |
4271 | struct mtk_mac *mac = netdev_priv(dev); |
4272 | |
4273 | mac->hw->msg_enable = value; |
4274 | } |
4275 | |
4276 | static int mtk_nway_reset(struct net_device *dev) |
4277 | { |
4278 | struct mtk_mac *mac = netdev_priv(dev); |
4279 | |
4280 | if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) |
4281 | return -EBUSY; |
4282 | |
4283 | if (!mac->phylink) |
4284 | return -ENOTSUPP; |
4285 | |
4286 | return phylink_ethtool_nway_reset(mac->phylink); |
4287 | } |
4288 | |
4289 | static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
4290 | { |
4291 | int i; |
4292 | |
4293 | switch (stringset) { |
4294 | case ETH_SS_STATS: { |
4295 | struct mtk_mac *mac = netdev_priv(dev); |
4296 | |
4297 | for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { |
4298 | memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); |
4299 | data += ETH_GSTRING_LEN; |
4300 | } |
4301 | if (mtk_page_pool_enabled(eth: mac->hw)) |
4302 | page_pool_ethtool_stats_get_strings(data); |
4303 | break; |
4304 | } |
4305 | default: |
4306 | break; |
4307 | } |
4308 | } |
4309 | |
4310 | static int mtk_get_sset_count(struct net_device *dev, int sset) |
4311 | { |
4312 | switch (sset) { |
4313 | case ETH_SS_STATS: { |
4314 | int count = ARRAY_SIZE(mtk_ethtool_stats); |
4315 | struct mtk_mac *mac = netdev_priv(dev); |
4316 | |
4317 | if (mtk_page_pool_enabled(eth: mac->hw)) |
4318 | count += page_pool_ethtool_stats_get_count(); |
4319 | return count; |
4320 | } |
4321 | default: |
4322 | return -EOPNOTSUPP; |
4323 | } |
4324 | } |
4325 | |
4326 | static void mtk_ethtool_pp_stats(struct mtk_eth *eth, u64 *data) |
4327 | { |
4328 | struct page_pool_stats stats = {}; |
4329 | int i; |
4330 | |
4331 | for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) { |
4332 | struct mtk_rx_ring *ring = ð->rx_ring[i]; |
4333 | |
4334 | if (!ring->page_pool) |
4335 | continue; |
4336 | |
4337 | page_pool_get_stats(pool: ring->page_pool, stats: &stats); |
4338 | } |
4339 | page_pool_ethtool_stats_get(data, stats: &stats); |
4340 | } |
4341 | |
4342 | static void mtk_get_ethtool_stats(struct net_device *dev, |
4343 | struct ethtool_stats *stats, u64 *data) |
4344 | { |
4345 | struct mtk_mac *mac = netdev_priv(dev); |
4346 | struct mtk_hw_stats *hwstats = mac->hw_stats; |
4347 | u64 *data_src, *data_dst; |
4348 | unsigned int start; |
4349 | int i; |
4350 | |
4351 | if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) |
4352 | return; |
4353 | |
4354 | if (netif_running(dev) && netif_device_present(dev)) { |
4355 | if (spin_trylock_bh(lock: &hwstats->stats_lock)) { |
4356 | mtk_stats_update_mac(mac); |
4357 | spin_unlock_bh(lock: &hwstats->stats_lock); |
4358 | } |
4359 | } |
4360 | |
4361 | data_src = (u64 *)hwstats; |
4362 | |
4363 | do { |
4364 | data_dst = data; |
4365 | start = u64_stats_fetch_begin(syncp: &hwstats->syncp); |
4366 | |
4367 | for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) |
4368 | *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); |
4369 | if (mtk_page_pool_enabled(eth: mac->hw)) |
4370 | mtk_ethtool_pp_stats(eth: mac->hw, data: data_dst); |
4371 | } while (u64_stats_fetch_retry(syncp: &hwstats->syncp, start)); |
4372 | } |
4373 | |
4374 | static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, |
4375 | u32 *rule_locs) |
4376 | { |
4377 | int ret = -EOPNOTSUPP; |
4378 | |
4379 | switch (cmd->cmd) { |
4380 | case ETHTOOL_GRXRINGS: |
4381 | if (dev->hw_features & NETIF_F_LRO) { |
4382 | cmd->data = MTK_MAX_RX_RING_NUM; |
4383 | ret = 0; |
4384 | } |
4385 | break; |
4386 | case ETHTOOL_GRXCLSRLCNT: |
4387 | if (dev->hw_features & NETIF_F_LRO) { |
4388 | struct mtk_mac *mac = netdev_priv(dev); |
4389 | |
4390 | cmd->rule_cnt = mac->hwlro_ip_cnt; |
4391 | ret = 0; |
4392 | } |
4393 | break; |
4394 | case ETHTOOL_GRXCLSRULE: |
4395 | if (dev->hw_features & NETIF_F_LRO) |
4396 | ret = mtk_hwlro_get_fdir_entry(dev, cmd); |
4397 | break; |
4398 | case ETHTOOL_GRXCLSRLALL: |
4399 | if (dev->hw_features & NETIF_F_LRO) |
4400 | ret = mtk_hwlro_get_fdir_all(dev, cmd, |
4401 | rule_locs); |
4402 | break; |
4403 | default: |
4404 | break; |
4405 | } |
4406 | |
4407 | return ret; |
4408 | } |
4409 | |
4410 | static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) |
4411 | { |
4412 | int ret = -EOPNOTSUPP; |
4413 | |
4414 | switch (cmd->cmd) { |
4415 | case ETHTOOL_SRXCLSRLINS: |
4416 | if (dev->hw_features & NETIF_F_LRO) |
4417 | ret = mtk_hwlro_add_ipaddr(dev, cmd); |
4418 | break; |
4419 | case ETHTOOL_SRXCLSRLDEL: |
4420 | if (dev->hw_features & NETIF_F_LRO) |
4421 | ret = mtk_hwlro_del_ipaddr(dev, cmd); |
4422 | break; |
4423 | default: |
4424 | break; |
4425 | } |
4426 | |
4427 | return ret; |
4428 | } |
4429 | |
4430 | static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb, |
4431 | struct net_device *sb_dev) |
4432 | { |
4433 | struct mtk_mac *mac = netdev_priv(dev); |
4434 | unsigned int queue = 0; |
4435 | |
4436 | if (netdev_uses_dsa(dev)) |
4437 | queue = skb_get_queue_mapping(skb) + 3; |
4438 | else |
4439 | queue = mac->id; |
4440 | |
4441 | if (queue >= dev->num_tx_queues) |
4442 | queue = 0; |
4443 | |
4444 | return queue; |
4445 | } |
4446 | |
4447 | static const struct ethtool_ops mtk_ethtool_ops = { |
4448 | .get_link_ksettings = mtk_get_link_ksettings, |
4449 | .set_link_ksettings = mtk_set_link_ksettings, |
4450 | .get_drvinfo = mtk_get_drvinfo, |
4451 | .get_msglevel = mtk_get_msglevel, |
4452 | .set_msglevel = mtk_set_msglevel, |
4453 | .nway_reset = mtk_nway_reset, |
4454 | .get_link = ethtool_op_get_link, |
4455 | .get_strings = mtk_get_strings, |
4456 | .get_sset_count = mtk_get_sset_count, |
4457 | .get_ethtool_stats = mtk_get_ethtool_stats, |
4458 | .get_rxnfc = mtk_get_rxnfc, |
4459 | .set_rxnfc = mtk_set_rxnfc, |
4460 | }; |
4461 | |
4462 | static const struct net_device_ops mtk_netdev_ops = { |
4463 | .ndo_uninit = mtk_uninit, |
4464 | .ndo_open = mtk_open, |
4465 | .ndo_stop = mtk_stop, |
4466 | .ndo_start_xmit = mtk_start_xmit, |
4467 | .ndo_set_mac_address = mtk_set_mac_address, |
4468 | .ndo_validate_addr = eth_validate_addr, |
4469 | .ndo_eth_ioctl = mtk_do_ioctl, |
4470 | .ndo_change_mtu = mtk_change_mtu, |
4471 | .ndo_tx_timeout = mtk_tx_timeout, |
4472 | .ndo_get_stats64 = mtk_get_stats64, |
4473 | .ndo_fix_features = mtk_fix_features, |
4474 | .ndo_set_features = mtk_set_features, |
4475 | #ifdef CONFIG_NET_POLL_CONTROLLER |
4476 | .ndo_poll_controller = mtk_poll_controller, |
4477 | #endif |
4478 | .ndo_setup_tc = mtk_eth_setup_tc, |
4479 | .ndo_bpf = mtk_xdp, |
4480 | .ndo_xdp_xmit = mtk_xdp_xmit, |
4481 | .ndo_select_queue = mtk_select_queue, |
4482 | }; |
4483 | |
4484 | static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) |
4485 | { |
4486 | const __be32 *_id = of_get_property(node: np, name: "reg" , NULL); |
4487 | phy_interface_t phy_mode; |
4488 | struct phylink *phylink; |
4489 | struct mtk_mac *mac; |
4490 | int id, err; |
4491 | int txqs = 1; |
4492 | u32 val; |
4493 | |
4494 | if (!_id) { |
4495 | dev_err(eth->dev, "missing mac id\n" ); |
4496 | return -EINVAL; |
4497 | } |
4498 | |
4499 | id = be32_to_cpup(p: _id); |
4500 | if (id >= MTK_MAX_DEVS) { |
4501 | dev_err(eth->dev, "%d is not a valid mac id\n" , id); |
4502 | return -EINVAL; |
4503 | } |
4504 | |
4505 | if (eth->netdev[id]) { |
4506 | dev_err(eth->dev, "duplicate mac id found: %d\n" , id); |
4507 | return -EINVAL; |
4508 | } |
4509 | |
4510 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) |
4511 | txqs = MTK_QDMA_NUM_QUEUES; |
4512 | |
4513 | eth->netdev[id] = alloc_etherdev_mqs(sizeof_priv: sizeof(*mac), txqs, rxqs: 1); |
4514 | if (!eth->netdev[id]) { |
4515 | dev_err(eth->dev, "alloc_etherdev failed\n" ); |
4516 | return -ENOMEM; |
4517 | } |
4518 | mac = netdev_priv(dev: eth->netdev[id]); |
4519 | eth->mac[id] = mac; |
4520 | mac->id = id; |
4521 | mac->hw = eth; |
4522 | mac->of_node = np; |
4523 | |
4524 | err = of_get_ethdev_address(np: mac->of_node, dev: eth->netdev[id]); |
4525 | if (err == -EPROBE_DEFER) |
4526 | return err; |
4527 | |
4528 | if (err) { |
4529 | /* If the mac address is invalid, use random mac address */ |
4530 | eth_hw_addr_random(dev: eth->netdev[id]); |
4531 | dev_err(eth->dev, "generated random MAC address %pM\n" , |
4532 | eth->netdev[id]->dev_addr); |
4533 | } |
4534 | |
4535 | memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); |
4536 | mac->hwlro_ip_cnt = 0; |
4537 | |
4538 | mac->hw_stats = devm_kzalloc(dev: eth->dev, |
4539 | size: sizeof(*mac->hw_stats), |
4540 | GFP_KERNEL); |
4541 | if (!mac->hw_stats) { |
4542 | dev_err(eth->dev, "failed to allocate counter memory\n" ); |
4543 | err = -ENOMEM; |
4544 | goto free_netdev; |
4545 | } |
4546 | spin_lock_init(&mac->hw_stats->stats_lock); |
4547 | u64_stats_init(syncp: &mac->hw_stats->syncp); |
4548 | |
4549 | if (mtk_is_netsys_v3_or_greater(eth)) |
4550 | mac->hw_stats->reg_offset = id * 0x80; |
4551 | else |
4552 | mac->hw_stats->reg_offset = id * 0x40; |
4553 | |
4554 | /* phylink create */ |
4555 | err = of_get_phy_mode(np, interface: &phy_mode); |
4556 | if (err) { |
4557 | dev_err(eth->dev, "incorrect phy-mode\n" ); |
4558 | goto free_netdev; |
4559 | } |
4560 | |
4561 | /* mac config is not set */ |
4562 | mac->interface = PHY_INTERFACE_MODE_NA; |
4563 | mac->speed = SPEED_UNKNOWN; |
4564 | |
4565 | mac->phylink_config.dev = ð->netdev[id]->dev; |
4566 | mac->phylink_config.type = PHYLINK_NETDEV; |
4567 | mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | |
4568 | MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; |
4569 | |
4570 | /* MT7623 gmac0 is now missing its speed-specific PLL configuration |
4571 | * in its .mac_config method (since state->speed is not valid there. |
4572 | * Disable support for MII, GMII and RGMII. |
4573 | */ |
4574 | if (!mac->hw->soc->disable_pll_modes || mac->id != 0) { |
4575 | __set_bit(PHY_INTERFACE_MODE_MII, |
4576 | mac->phylink_config.supported_interfaces); |
4577 | __set_bit(PHY_INTERFACE_MODE_GMII, |
4578 | mac->phylink_config.supported_interfaces); |
4579 | |
4580 | if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) |
4581 | phy_interface_set_rgmii(intf: mac->phylink_config.supported_interfaces); |
4582 | } |
4583 | |
4584 | if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id) |
4585 | __set_bit(PHY_INTERFACE_MODE_TRGMII, |
4586 | mac->phylink_config.supported_interfaces); |
4587 | |
4588 | /* TRGMII is not permitted on MT7621 if using DDR2 */ |
4589 | if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && |
4590 | MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) { |
4591 | regmap_read(map: eth->ethsys, ETHSYS_SYSCFG, val: &val); |
4592 | if (val & SYSCFG_DRAM_TYPE_DDR2) |
4593 | __clear_bit(PHY_INTERFACE_MODE_TRGMII, |
4594 | mac->phylink_config.supported_interfaces); |
4595 | } |
4596 | |
4597 | if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { |
4598 | __set_bit(PHY_INTERFACE_MODE_SGMII, |
4599 | mac->phylink_config.supported_interfaces); |
4600 | __set_bit(PHY_INTERFACE_MODE_1000BASEX, |
4601 | mac->phylink_config.supported_interfaces); |
4602 | __set_bit(PHY_INTERFACE_MODE_2500BASEX, |
4603 | mac->phylink_config.supported_interfaces); |
4604 | } |
4605 | |
4606 | if (mtk_is_netsys_v3_or_greater(eth: mac->hw) && |
4607 | MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW_BIT) && |
4608 | id == MTK_GMAC1_ID) { |
4609 | mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | |
4610 | MAC_SYM_PAUSE | |
4611 | MAC_10000FD; |
4612 | phy_interface_zero(intf: mac->phylink_config.supported_interfaces); |
4613 | __set_bit(PHY_INTERFACE_MODE_INTERNAL, |
4614 | mac->phylink_config.supported_interfaces); |
4615 | } |
4616 | |
4617 | phylink = phylink_create(&mac->phylink_config, |
4618 | of_fwnode_handle(mac->of_node), |
4619 | phy_mode, &mtk_phylink_ops); |
4620 | if (IS_ERR(ptr: phylink)) { |
4621 | err = PTR_ERR(ptr: phylink); |
4622 | goto free_netdev; |
4623 | } |
4624 | |
4625 | mac->phylink = phylink; |
4626 | |
4627 | SET_NETDEV_DEV(eth->netdev[id], eth->dev); |
4628 | eth->netdev[id]->watchdog_timeo = 5 * HZ; |
4629 | eth->netdev[id]->netdev_ops = &mtk_netdev_ops; |
4630 | eth->netdev[id]->base_addr = (unsigned long)eth->base; |
4631 | |
4632 | eth->netdev[id]->hw_features = eth->soc->hw_features; |
4633 | if (eth->hwlro) |
4634 | eth->netdev[id]->hw_features |= NETIF_F_LRO; |
4635 | |
4636 | eth->netdev[id]->vlan_features = eth->soc->hw_features & |
4637 | ~NETIF_F_HW_VLAN_CTAG_TX; |
4638 | eth->netdev[id]->features |= eth->soc->hw_features; |
4639 | eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; |
4640 | |
4641 | eth->netdev[id]->irq = eth->irq[0]; |
4642 | eth->netdev[id]->dev.of_node = np; |
4643 | |
4644 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) |
4645 | eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; |
4646 | else |
4647 | eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; |
4648 | |
4649 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
4650 | mac->device_notifier.notifier_call = mtk_device_event; |
4651 | register_netdevice_notifier(nb: &mac->device_notifier); |
4652 | } |
4653 | |
4654 | if (mtk_page_pool_enabled(eth)) |
4655 | eth->netdev[id]->xdp_features = NETDEV_XDP_ACT_BASIC | |
4656 | NETDEV_XDP_ACT_REDIRECT | |
4657 | NETDEV_XDP_ACT_NDO_XMIT | |
4658 | NETDEV_XDP_ACT_NDO_XMIT_SG; |
4659 | |
4660 | return 0; |
4661 | |
4662 | free_netdev: |
4663 | free_netdev(dev: eth->netdev[id]); |
4664 | return err; |
4665 | } |
4666 | |
4667 | void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev) |
4668 | { |
4669 | struct net_device *dev, *tmp; |
4670 | LIST_HEAD(dev_list); |
4671 | int i; |
4672 | |
4673 | rtnl_lock(); |
4674 | |
4675 | for (i = 0; i < MTK_MAX_DEVS; i++) { |
4676 | dev = eth->netdev[i]; |
4677 | |
4678 | if (!dev || !(dev->flags & IFF_UP)) |
4679 | continue; |
4680 | |
4681 | list_add_tail(new: &dev->close_list, head: &dev_list); |
4682 | } |
4683 | |
4684 | dev_close_many(head: &dev_list, unlink: false); |
4685 | |
4686 | eth->dma_dev = dma_dev; |
4687 | |
4688 | list_for_each_entry_safe(dev, tmp, &dev_list, close_list) { |
4689 | list_del_init(entry: &dev->close_list); |
4690 | dev_open(dev, NULL); |
4691 | } |
4692 | |
4693 | rtnl_unlock(); |
4694 | } |
4695 | |
4696 | static int mtk_sgmii_init(struct mtk_eth *eth) |
4697 | { |
4698 | struct device_node *np; |
4699 | struct regmap *regmap; |
4700 | u32 flags; |
4701 | int i; |
4702 | |
4703 | for (i = 0; i < MTK_MAX_DEVS; i++) { |
4704 | np = of_parse_phandle(np: eth->dev->of_node, phandle_name: "mediatek,sgmiisys" , index: i); |
4705 | if (!np) |
4706 | break; |
4707 | |
4708 | regmap = syscon_node_to_regmap(np); |
4709 | flags = 0; |
4710 | if (of_property_read_bool(np, propname: "mediatek,pnswap" )) |
4711 | flags |= MTK_SGMII_FLAG_PN_SWAP; |
4712 | |
4713 | of_node_put(node: np); |
4714 | |
4715 | if (IS_ERR(ptr: regmap)) |
4716 | return PTR_ERR(ptr: regmap); |
4717 | |
4718 | eth->sgmii_pcs[i] = mtk_pcs_lynxi_create(dev: eth->dev, regmap, |
4719 | ana_rgc3: eth->soc->ana_rgc3, |
4720 | flags); |
4721 | } |
4722 | |
4723 | return 0; |
4724 | } |
4725 | |
4726 | static int mtk_probe(struct platform_device *pdev) |
4727 | { |
4728 | struct resource *res = NULL, *res_sram; |
4729 | struct device_node *mac_np; |
4730 | struct mtk_eth *eth; |
4731 | int err, i; |
4732 | |
4733 | eth = devm_kzalloc(dev: &pdev->dev, size: sizeof(*eth), GFP_KERNEL); |
4734 | if (!eth) |
4735 | return -ENOMEM; |
4736 | |
4737 | eth->soc = of_device_get_match_data(dev: &pdev->dev); |
4738 | |
4739 | eth->dev = &pdev->dev; |
4740 | eth->dma_dev = &pdev->dev; |
4741 | eth->base = devm_platform_ioremap_resource(pdev, index: 0); |
4742 | if (IS_ERR(ptr: eth->base)) |
4743 | return PTR_ERR(ptr: eth->base); |
4744 | |
4745 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) |
4746 | eth->ip_align = NET_IP_ALIGN; |
4747 | |
4748 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) { |
4749 | /* SRAM is actual memory and supports transparent access just like DRAM. |
4750 | * Hence we don't require __iomem being set and don't need to use accessor |
4751 | * functions to read from or write to SRAM. |
4752 | */ |
4753 | if (mtk_is_netsys_v3_or_greater(eth)) { |
4754 | eth->sram_base = (void __force *)devm_platform_ioremap_resource(pdev, index: 1); |
4755 | if (IS_ERR(ptr: eth->sram_base)) |
4756 | return PTR_ERR(ptr: eth->sram_base); |
4757 | } else { |
4758 | eth->sram_base = (void __force *)eth->base + MTK_ETH_SRAM_OFFSET; |
4759 | } |
4760 | } |
4761 | |
4762 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) { |
4763 | err = dma_set_mask(dev: &pdev->dev, DMA_BIT_MASK(36)); |
4764 | if (!err) |
4765 | err = dma_set_coherent_mask(dev: &pdev->dev, DMA_BIT_MASK(32)); |
4766 | |
4767 | if (err) { |
4768 | dev_err(&pdev->dev, "Wrong DMA config\n" ); |
4769 | return -EINVAL; |
4770 | } |
4771 | } |
4772 | |
4773 | spin_lock_init(ð->page_lock); |
4774 | spin_lock_init(ð->tx_irq_lock); |
4775 | spin_lock_init(ð->rx_irq_lock); |
4776 | spin_lock_init(ð->dim_lock); |
4777 | |
4778 | eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; |
4779 | INIT_WORK(ð->rx_dim.work, mtk_dim_rx); |
4780 | INIT_DELAYED_WORK(ð->reset.monitor_work, mtk_hw_reset_monitor_work); |
4781 | |
4782 | eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; |
4783 | INIT_WORK(ð->tx_dim.work, mtk_dim_tx); |
4784 | |
4785 | if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { |
4786 | eth->ethsys = syscon_regmap_lookup_by_phandle(np: pdev->dev.of_node, |
4787 | property: "mediatek,ethsys" ); |
4788 | if (IS_ERR(ptr: eth->ethsys)) { |
4789 | dev_err(&pdev->dev, "no ethsys regmap found\n" ); |
4790 | return PTR_ERR(ptr: eth->ethsys); |
4791 | } |
4792 | } |
4793 | |
4794 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { |
4795 | eth->infra = syscon_regmap_lookup_by_phandle(np: pdev->dev.of_node, |
4796 | property: "mediatek,infracfg" ); |
4797 | if (IS_ERR(ptr: eth->infra)) { |
4798 | dev_err(&pdev->dev, "no infracfg regmap found\n" ); |
4799 | return PTR_ERR(ptr: eth->infra); |
4800 | } |
4801 | } |
4802 | |
4803 | if (of_dma_is_coherent(np: pdev->dev.of_node)) { |
4804 | struct regmap *cci; |
4805 | |
4806 | cci = syscon_regmap_lookup_by_phandle(np: pdev->dev.of_node, |
4807 | property: "cci-control-port" ); |
4808 | /* enable CPU/bus coherency */ |
4809 | if (!IS_ERR(ptr: cci)) |
4810 | regmap_write(map: cci, reg: 0, val: 3); |
4811 | } |
4812 | |
4813 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { |
4814 | err = mtk_sgmii_init(eth); |
4815 | |
4816 | if (err) |
4817 | return err; |
4818 | } |
4819 | |
4820 | if (eth->soc->required_pctl) { |
4821 | eth->pctl = syscon_regmap_lookup_by_phandle(np: pdev->dev.of_node, |
4822 | property: "mediatek,pctl" ); |
4823 | if (IS_ERR(ptr: eth->pctl)) { |
4824 | dev_err(&pdev->dev, "no pctl regmap found\n" ); |
4825 | err = PTR_ERR(ptr: eth->pctl); |
4826 | goto err_destroy_sgmii; |
4827 | } |
4828 | } |
4829 | |
4830 | if (mtk_is_netsys_v2_or_greater(eth)) { |
4831 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
4832 | if (!res) { |
4833 | err = -EINVAL; |
4834 | goto err_destroy_sgmii; |
4835 | } |
4836 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) { |
4837 | if (mtk_is_netsys_v3_or_greater(eth)) { |
4838 | res_sram = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
4839 | if (!res_sram) { |
4840 | err = -EINVAL; |
4841 | goto err_destroy_sgmii; |
4842 | } |
4843 | eth->phy_scratch_ring = res_sram->start; |
4844 | } else { |
4845 | eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET; |
4846 | } |
4847 | } |
4848 | } |
4849 | |
4850 | if (eth->soc->offload_version) { |
4851 | for (i = 0;; i++) { |
4852 | struct device_node *np; |
4853 | phys_addr_t wdma_phy; |
4854 | u32 wdma_base; |
4855 | |
4856 | if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base)) |
4857 | break; |
4858 | |
4859 | np = of_parse_phandle(np: pdev->dev.of_node, |
4860 | phandle_name: "mediatek,wed" , index: i); |
4861 | if (!np) |
4862 | break; |
4863 | |
4864 | wdma_base = eth->soc->reg_map->wdma_base[i]; |
4865 | wdma_phy = res ? res->start + wdma_base : 0; |
4866 | mtk_wed_add_hw(np, eth, wdma: eth->base + wdma_base, |
4867 | wdma_phy, index: i); |
4868 | } |
4869 | } |
4870 | |
4871 | for (i = 0; i < 3; i++) { |
4872 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) |
4873 | eth->irq[i] = eth->irq[0]; |
4874 | else |
4875 | eth->irq[i] = platform_get_irq(pdev, i); |
4876 | if (eth->irq[i] < 0) { |
4877 | dev_err(&pdev->dev, "no IRQ%d resource found\n" , i); |
4878 | err = -ENXIO; |
4879 | goto err_wed_exit; |
4880 | } |
4881 | } |
4882 | for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { |
4883 | eth->clks[i] = devm_clk_get(dev: eth->dev, |
4884 | id: mtk_clks_source_name[i]); |
4885 | if (IS_ERR(ptr: eth->clks[i])) { |
4886 | if (PTR_ERR(ptr: eth->clks[i]) == -EPROBE_DEFER) { |
4887 | err = -EPROBE_DEFER; |
4888 | goto err_wed_exit; |
4889 | } |
4890 | if (eth->soc->required_clks & BIT(i)) { |
4891 | dev_err(&pdev->dev, "clock %s not found\n" , |
4892 | mtk_clks_source_name[i]); |
4893 | err = -EINVAL; |
4894 | goto err_wed_exit; |
4895 | } |
4896 | eth->clks[i] = NULL; |
4897 | } |
4898 | } |
4899 | |
4900 | eth->msg_enable = netif_msg_init(debug_value: mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); |
4901 | INIT_WORK(ð->pending_work, mtk_pending_work); |
4902 | |
4903 | err = mtk_hw_init(eth, reset: false); |
4904 | if (err) |
4905 | goto err_wed_exit; |
4906 | |
4907 | eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); |
4908 | |
4909 | for_each_child_of_node(pdev->dev.of_node, mac_np) { |
4910 | if (!of_device_is_compatible(device: mac_np, |
4911 | "mediatek,eth-mac" )) |
4912 | continue; |
4913 | |
4914 | if (!of_device_is_available(device: mac_np)) |
4915 | continue; |
4916 | |
4917 | err = mtk_add_mac(eth, np: mac_np); |
4918 | if (err) { |
4919 | of_node_put(node: mac_np); |
4920 | goto err_deinit_hw; |
4921 | } |
4922 | } |
4923 | |
4924 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { |
4925 | err = devm_request_irq(dev: eth->dev, irq: eth->irq[0], |
4926 | handler: mtk_handle_irq, irqflags: 0, |
4927 | devname: dev_name(dev: eth->dev), dev_id: eth); |
4928 | } else { |
4929 | err = devm_request_irq(dev: eth->dev, irq: eth->irq[1], |
4930 | handler: mtk_handle_irq_tx, irqflags: 0, |
4931 | devname: dev_name(dev: eth->dev), dev_id: eth); |
4932 | if (err) |
4933 | goto err_free_dev; |
4934 | |
4935 | err = devm_request_irq(dev: eth->dev, irq: eth->irq[2], |
4936 | handler: mtk_handle_irq_rx, irqflags: 0, |
4937 | devname: dev_name(dev: eth->dev), dev_id: eth); |
4938 | } |
4939 | if (err) |
4940 | goto err_free_dev; |
4941 | |
4942 | /* No MT7628/88 support yet */ |
4943 | if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { |
4944 | err = mtk_mdio_init(eth); |
4945 | if (err) |
4946 | goto err_free_dev; |
4947 | } |
4948 | |
4949 | if (eth->soc->offload_version) { |
4950 | u32 num_ppe = mtk_is_netsys_v2_or_greater(eth) ? 2 : 1; |
4951 | |
4952 | num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe); |
4953 | for (i = 0; i < num_ppe; i++) { |
4954 | u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400; |
4955 | |
4956 | eth->ppe[i] = mtk_ppe_init(eth, base: eth->base + ppe_addr, index: i); |
4957 | |
4958 | if (!eth->ppe[i]) { |
4959 | err = -ENOMEM; |
4960 | goto err_deinit_ppe; |
4961 | } |
4962 | } |
4963 | |
4964 | err = mtk_eth_offload_init(eth); |
4965 | if (err) |
4966 | goto err_deinit_ppe; |
4967 | } |
4968 | |
4969 | for (i = 0; i < MTK_MAX_DEVS; i++) { |
4970 | if (!eth->netdev[i]) |
4971 | continue; |
4972 | |
4973 | err = register_netdev(dev: eth->netdev[i]); |
4974 | if (err) { |
4975 | dev_err(eth->dev, "error bringing up device\n" ); |
4976 | goto err_deinit_ppe; |
4977 | } else |
4978 | netif_info(eth, probe, eth->netdev[i], |
4979 | "mediatek frame engine at 0x%08lx, irq %d\n" , |
4980 | eth->netdev[i]->base_addr, eth->irq[0]); |
4981 | } |
4982 | |
4983 | /* we run 2 devices on the same DMA ring so we need a dummy device |
4984 | * for NAPI to work |
4985 | */ |
4986 | init_dummy_netdev(dev: ð->dummy_dev); |
4987 | netif_napi_add(dev: ð->dummy_dev, napi: ð->tx_napi, poll: mtk_napi_tx); |
4988 | netif_napi_add(dev: ð->dummy_dev, napi: ð->rx_napi, poll: mtk_napi_rx); |
4989 | |
4990 | platform_set_drvdata(pdev, data: eth); |
4991 | schedule_delayed_work(dwork: ð->reset.monitor_work, |
4992 | MTK_DMA_MONITOR_TIMEOUT); |
4993 | |
4994 | return 0; |
4995 | |
4996 | err_deinit_ppe: |
4997 | mtk_ppe_deinit(eth); |
4998 | mtk_mdio_cleanup(eth); |
4999 | err_free_dev: |
5000 | mtk_free_dev(eth); |
5001 | err_deinit_hw: |
5002 | mtk_hw_deinit(eth); |
5003 | err_wed_exit: |
5004 | mtk_wed_exit(); |
5005 | err_destroy_sgmii: |
5006 | mtk_sgmii_destroy(eth); |
5007 | |
5008 | return err; |
5009 | } |
5010 | |
5011 | static void mtk_remove(struct platform_device *pdev) |
5012 | { |
5013 | struct mtk_eth *eth = platform_get_drvdata(pdev); |
5014 | struct mtk_mac *mac; |
5015 | int i; |
5016 | |
5017 | /* stop all devices to make sure that dma is properly shut down */ |
5018 | for (i = 0; i < MTK_MAX_DEVS; i++) { |
5019 | if (!eth->netdev[i]) |
5020 | continue; |
5021 | mtk_stop(dev: eth->netdev[i]); |
5022 | mac = netdev_priv(dev: eth->netdev[i]); |
5023 | phylink_disconnect_phy(mac->phylink); |
5024 | } |
5025 | |
5026 | mtk_wed_exit(); |
5027 | mtk_hw_deinit(eth); |
5028 | |
5029 | netif_napi_del(napi: ð->tx_napi); |
5030 | netif_napi_del(napi: ð->rx_napi); |
5031 | mtk_cleanup(eth); |
5032 | mtk_mdio_cleanup(eth); |
5033 | } |
5034 | |
5035 | static const struct mtk_soc_data mt2701_data = { |
5036 | .reg_map = &mtk_reg_map, |
5037 | .caps = MT7623_CAPS | MTK_HWLRO, |
5038 | .hw_features = MTK_HW_FEATURES, |
5039 | .required_clks = MT7623_CLKS_BITMAP, |
5040 | .required_pctl = true, |
5041 | .version = 1, |
5042 | .txrx = { |
5043 | .txd_size = sizeof(struct mtk_tx_dma), |
5044 | .rxd_size = sizeof(struct mtk_rx_dma), |
5045 | .rx_irq_done_mask = MTK_RX_DONE_INT, |
5046 | .rx_dma_l4_valid = RX_DMA_L4_VALID, |
5047 | .dma_max_len = MTK_TX_DMA_BUF_LEN, |
5048 | .dma_len_offset = 16, |
5049 | }, |
5050 | }; |
5051 | |
5052 | static const struct mtk_soc_data mt7621_data = { |
5053 | .reg_map = &mtk_reg_map, |
5054 | .caps = MT7621_CAPS, |
5055 | .hw_features = MTK_HW_FEATURES, |
5056 | .required_clks = MT7621_CLKS_BITMAP, |
5057 | .required_pctl = false, |
5058 | .version = 1, |
5059 | .offload_version = 1, |
5060 | .hash_offset = 2, |
5061 | .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, |
5062 | .txrx = { |
5063 | .txd_size = sizeof(struct mtk_tx_dma), |
5064 | .rxd_size = sizeof(struct mtk_rx_dma), |
5065 | .rx_irq_done_mask = MTK_RX_DONE_INT, |
5066 | .rx_dma_l4_valid = RX_DMA_L4_VALID, |
5067 | .dma_max_len = MTK_TX_DMA_BUF_LEN, |
5068 | .dma_len_offset = 16, |
5069 | }, |
5070 | }; |
5071 | |
5072 | static const struct mtk_soc_data mt7622_data = { |
5073 | .reg_map = &mtk_reg_map, |
5074 | .ana_rgc3 = 0x2028, |
5075 | .caps = MT7622_CAPS | MTK_HWLRO, |
5076 | .hw_features = MTK_HW_FEATURES, |
5077 | .required_clks = MT7622_CLKS_BITMAP, |
5078 | .required_pctl = false, |
5079 | .version = 1, |
5080 | .offload_version = 2, |
5081 | .hash_offset = 2, |
5082 | .has_accounting = true, |
5083 | .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, |
5084 | .txrx = { |
5085 | .txd_size = sizeof(struct mtk_tx_dma), |
5086 | .rxd_size = sizeof(struct mtk_rx_dma), |
5087 | .rx_irq_done_mask = MTK_RX_DONE_INT, |
5088 | .rx_dma_l4_valid = RX_DMA_L4_VALID, |
5089 | .dma_max_len = MTK_TX_DMA_BUF_LEN, |
5090 | .dma_len_offset = 16, |
5091 | }, |
5092 | }; |
5093 | |
5094 | static const struct mtk_soc_data mt7623_data = { |
5095 | .reg_map = &mtk_reg_map, |
5096 | .caps = MT7623_CAPS | MTK_HWLRO, |
5097 | .hw_features = MTK_HW_FEATURES, |
5098 | .required_clks = MT7623_CLKS_BITMAP, |
5099 | .required_pctl = true, |
5100 | .version = 1, |
5101 | .offload_version = 1, |
5102 | .hash_offset = 2, |
5103 | .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, |
5104 | .disable_pll_modes = true, |
5105 | .txrx = { |
5106 | .txd_size = sizeof(struct mtk_tx_dma), |
5107 | .rxd_size = sizeof(struct mtk_rx_dma), |
5108 | .rx_irq_done_mask = MTK_RX_DONE_INT, |
5109 | .rx_dma_l4_valid = RX_DMA_L4_VALID, |
5110 | .dma_max_len = MTK_TX_DMA_BUF_LEN, |
5111 | .dma_len_offset = 16, |
5112 | }, |
5113 | }; |
5114 | |
5115 | static const struct mtk_soc_data mt7629_data = { |
5116 | .reg_map = &mtk_reg_map, |
5117 | .ana_rgc3 = 0x128, |
5118 | .caps = MT7629_CAPS | MTK_HWLRO, |
5119 | .hw_features = MTK_HW_FEATURES, |
5120 | .required_clks = MT7629_CLKS_BITMAP, |
5121 | .required_pctl = false, |
5122 | .has_accounting = true, |
5123 | .version = 1, |
5124 | .txrx = { |
5125 | .txd_size = sizeof(struct mtk_tx_dma), |
5126 | .rxd_size = sizeof(struct mtk_rx_dma), |
5127 | .rx_irq_done_mask = MTK_RX_DONE_INT, |
5128 | .rx_dma_l4_valid = RX_DMA_L4_VALID, |
5129 | .dma_max_len = MTK_TX_DMA_BUF_LEN, |
5130 | .dma_len_offset = 16, |
5131 | }, |
5132 | }; |
5133 | |
5134 | static const struct mtk_soc_data mt7981_data = { |
5135 | .reg_map = &mt7986_reg_map, |
5136 | .ana_rgc3 = 0x128, |
5137 | .caps = MT7981_CAPS, |
5138 | .hw_features = MTK_HW_FEATURES, |
5139 | .required_clks = MT7981_CLKS_BITMAP, |
5140 | .required_pctl = false, |
5141 | .version = 2, |
5142 | .offload_version = 2, |
5143 | .hash_offset = 4, |
5144 | .has_accounting = true, |
5145 | .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, |
5146 | .txrx = { |
5147 | .txd_size = sizeof(struct mtk_tx_dma_v2), |
5148 | .rxd_size = sizeof(struct mtk_rx_dma_v2), |
5149 | .rx_irq_done_mask = MTK_RX_DONE_INT_V2, |
5150 | .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, |
5151 | .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, |
5152 | .dma_len_offset = 8, |
5153 | }, |
5154 | }; |
5155 | |
5156 | static const struct mtk_soc_data mt7986_data = { |
5157 | .reg_map = &mt7986_reg_map, |
5158 | .ana_rgc3 = 0x128, |
5159 | .caps = MT7986_CAPS, |
5160 | .hw_features = MTK_HW_FEATURES, |
5161 | .required_clks = MT7986_CLKS_BITMAP, |
5162 | .required_pctl = false, |
5163 | .version = 2, |
5164 | .offload_version = 2, |
5165 | .hash_offset = 4, |
5166 | .has_accounting = true, |
5167 | .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, |
5168 | .txrx = { |
5169 | .txd_size = sizeof(struct mtk_tx_dma_v2), |
5170 | .rxd_size = sizeof(struct mtk_rx_dma_v2), |
5171 | .rx_irq_done_mask = MTK_RX_DONE_INT_V2, |
5172 | .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, |
5173 | .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, |
5174 | .dma_len_offset = 8, |
5175 | }, |
5176 | }; |
5177 | |
5178 | static const struct mtk_soc_data mt7988_data = { |
5179 | .reg_map = &mt7988_reg_map, |
5180 | .ana_rgc3 = 0x128, |
5181 | .caps = MT7988_CAPS, |
5182 | .hw_features = MTK_HW_FEATURES, |
5183 | .required_clks = MT7988_CLKS_BITMAP, |
5184 | .required_pctl = false, |
5185 | .version = 3, |
5186 | .offload_version = 2, |
5187 | .hash_offset = 4, |
5188 | .has_accounting = true, |
5189 | .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE, |
5190 | .txrx = { |
5191 | .txd_size = sizeof(struct mtk_tx_dma_v2), |
5192 | .rxd_size = sizeof(struct mtk_rx_dma_v2), |
5193 | .rx_irq_done_mask = MTK_RX_DONE_INT_V2, |
5194 | .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, |
5195 | .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, |
5196 | .dma_len_offset = 8, |
5197 | }, |
5198 | }; |
5199 | |
5200 | static const struct mtk_soc_data rt5350_data = { |
5201 | .reg_map = &mt7628_reg_map, |
5202 | .caps = MT7628_CAPS, |
5203 | .hw_features = MTK_HW_FEATURES_MT7628, |
5204 | .required_clks = MT7628_CLKS_BITMAP, |
5205 | .required_pctl = false, |
5206 | .version = 1, |
5207 | .txrx = { |
5208 | .txd_size = sizeof(struct mtk_tx_dma), |
5209 | .rxd_size = sizeof(struct mtk_rx_dma), |
5210 | .rx_irq_done_mask = MTK_RX_DONE_INT, |
5211 | .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA, |
5212 | .dma_max_len = MTK_TX_DMA_BUF_LEN, |
5213 | .dma_len_offset = 16, |
5214 | }, |
5215 | }; |
5216 | |
5217 | const struct of_device_id of_mtk_match[] = { |
5218 | { .compatible = "mediatek,mt2701-eth" , .data = &mt2701_data }, |
5219 | { .compatible = "mediatek,mt7621-eth" , .data = &mt7621_data }, |
5220 | { .compatible = "mediatek,mt7622-eth" , .data = &mt7622_data }, |
5221 | { .compatible = "mediatek,mt7623-eth" , .data = &mt7623_data }, |
5222 | { .compatible = "mediatek,mt7629-eth" , .data = &mt7629_data }, |
5223 | { .compatible = "mediatek,mt7981-eth" , .data = &mt7981_data }, |
5224 | { .compatible = "mediatek,mt7986-eth" , .data = &mt7986_data }, |
5225 | { .compatible = "mediatek,mt7988-eth" , .data = &mt7988_data }, |
5226 | { .compatible = "ralink,rt5350-eth" , .data = &rt5350_data }, |
5227 | {}, |
5228 | }; |
5229 | MODULE_DEVICE_TABLE(of, of_mtk_match); |
5230 | |
5231 | static struct platform_driver mtk_driver = { |
5232 | .probe = mtk_probe, |
5233 | .remove_new = mtk_remove, |
5234 | .driver = { |
5235 | .name = "mtk_soc_eth" , |
5236 | .of_match_table = of_mtk_match, |
5237 | }, |
5238 | }; |
5239 | |
5240 | module_platform_driver(mtk_driver); |
5241 | |
5242 | MODULE_LICENSE("GPL" ); |
5243 | MODULE_AUTHOR("John Crispin <blogic@openwrt.org>" ); |
5244 | MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC" ); |
5245 | |