| 1 | /* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ |
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| 2 | |
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| 3 | /* MDIO support for Mellanox Gigabit Ethernet driver |
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| 4 | * |
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| 5 | * Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES, ALL RIGHTS RESERVED. |
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| 6 | * |
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| 7 | * This software product is a proprietary product of NVIDIA CORPORATION & |
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| 8 | * AFFILIATES (the "Company") and all right, title, and interest in and to the |
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| 9 | * software product, including all associated intellectual property rights, are |
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| 10 | * and shall remain exclusively with the Company. |
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| 11 | * |
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| 12 | * This software product is governed by the End User License Agreement |
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| 13 | * provided with the software product. |
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| 14 | */ |
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| 15 | |
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| 16 | #ifndef __MLXBF_GIGE_MDIO_BF3_H__ |
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| 17 | #define __MLXBF_GIGE_MDIO_BF3_H__ |
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| 18 | |
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| 19 | #include <linux/bitfield.h> |
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| 20 | |
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| 21 | #define MLXBF3_GIGE_MDIO_GW_OFFSET 0x80 |
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| 22 | #define MLXBF3_GIGE_MDIO_DATA_READ 0x8c |
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| 23 | #define MLXBF3_GIGE_MDIO_CFG_REG0 0x100 |
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| 24 | #define MLXBF3_GIGE_MDIO_CFG_REG1 0x104 |
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| 25 | #define MLXBF3_GIGE_MDIO_CFG_REG2 0x108 |
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| 26 | |
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| 27 | /* MDIO GW register bits */ |
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| 28 | #define MLXBF3_GIGE_MDIO_GW_ST1_MASK GENMASK(1, 1) |
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| 29 | #define MLXBF3_GIGE_MDIO_GW_OPCODE_MASK GENMASK(3, 2) |
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| 30 | #define MLXBF3_GIGE_MDIO_GW_PARTAD_MASK GENMASK(8, 4) |
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| 31 | #define MLXBF3_GIGE_MDIO_GW_DEVAD_MASK GENMASK(13, 9) |
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| 32 | /* For BlueField-3, this field is only used for mdio write */ |
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| 33 | #define MLXBF3_GIGE_MDIO_GW_DATA_MASK GENMASK(29, 14) |
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| 34 | #define MLXBF3_GIGE_MDIO_GW_BUSY_MASK GENMASK(30, 30) |
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| 35 | |
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| 36 | #define MLXBF3_GIGE_MDIO_GW_DATA_READ_MASK GENMASK(15, 0) |
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| 37 | |
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| 38 | #define MLXBF3_GIGE_MDIO_GW_ST1_SHIFT 1 |
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| 39 | #define MLXBF3_GIGE_MDIO_GW_OPCODE_SHIFT 2 |
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| 40 | #define MLXBF3_GIGE_MDIO_GW_PARTAD_SHIFT 4 |
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| 41 | #define MLXBF3_GIGE_MDIO_GW_DEVAD_SHIFT 9 |
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| 42 | #define MLXBF3_GIGE_MDIO_GW_DATA_SHIFT 14 |
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| 43 | #define MLXBF3_GIGE_MDIO_GW_BUSY_SHIFT 30 |
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| 44 | |
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| 45 | #define MLXBF3_GIGE_MDIO_GW_DATA_READ_SHIFT 0 |
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| 46 | |
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| 47 | /* MDIO config register bits */ |
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| 48 | #define MLXBF3_GIGE_MDIO_CFG_MDIO_MODE_MASK GENMASK(1, 0) |
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| 49 | #define MLXBF3_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK GENMASK(2, 2) |
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| 50 | #define MLXBF3_GIGE_MDIO_CFG_MDC_PERIOD_MASK GENMASK(7, 0) |
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| 51 | #define MLXBF3_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK GENMASK(7, 0) |
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| 52 | #define MLXBF3_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK GENMASK(15, 8) |
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| 53 | |
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| 54 | #endif /* __MLXBF_GIGE_MDIO_BF3_H__ */ |
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| 55 | |
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