1 | // SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause |
2 | |
3 | /* MDIO support for Mellanox Gigabit Ethernet driver |
4 | * |
5 | * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES |
6 | */ |
7 | |
8 | #include <linux/acpi.h> |
9 | #include <linux/bitfield.h> |
10 | #include <linux/delay.h> |
11 | #include <linux/device.h> |
12 | #include <linux/err.h> |
13 | #include <linux/io.h> |
14 | #include <linux/iopoll.h> |
15 | #include <linux/ioport.h> |
16 | #include <linux/irqreturn.h> |
17 | #include <linux/jiffies.h> |
18 | #include <linux/module.h> |
19 | #include <linux/mod_devicetable.h> |
20 | #include <linux/phy.h> |
21 | #include <linux/platform_device.h> |
22 | #include <linux/property.h> |
23 | |
24 | #include "mlxbf_gige.h" |
25 | #include "mlxbf_gige_regs.h" |
26 | #include "mlxbf_gige_mdio_bf2.h" |
27 | #include "mlxbf_gige_mdio_bf3.h" |
28 | |
29 | static struct mlxbf_gige_mdio_gw mlxbf_gige_mdio_gw_t[] = { |
30 | [MLXBF_GIGE_VERSION_BF2] = { |
31 | .gw_address = MLXBF2_GIGE_MDIO_GW_OFFSET, |
32 | .read_data_address = MLXBF2_GIGE_MDIO_GW_OFFSET, |
33 | .busy = { |
34 | .mask = MLXBF2_GIGE_MDIO_GW_BUSY_MASK, |
35 | .shift = MLXBF2_GIGE_MDIO_GW_BUSY_SHIFT, |
36 | }, |
37 | .read_data = { |
38 | .mask = MLXBF2_GIGE_MDIO_GW_AD_MASK, |
39 | .shift = MLXBF2_GIGE_MDIO_GW_AD_SHIFT, |
40 | }, |
41 | .write_data = { |
42 | .mask = MLXBF2_GIGE_MDIO_GW_AD_MASK, |
43 | .shift = MLXBF2_GIGE_MDIO_GW_AD_SHIFT, |
44 | }, |
45 | .devad = { |
46 | .mask = MLXBF2_GIGE_MDIO_GW_DEVAD_MASK, |
47 | .shift = MLXBF2_GIGE_MDIO_GW_DEVAD_SHIFT, |
48 | }, |
49 | .partad = { |
50 | .mask = MLXBF2_GIGE_MDIO_GW_PARTAD_MASK, |
51 | .shift = MLXBF2_GIGE_MDIO_GW_PARTAD_SHIFT, |
52 | }, |
53 | .opcode = { |
54 | .mask = MLXBF2_GIGE_MDIO_GW_OPCODE_MASK, |
55 | .shift = MLXBF2_GIGE_MDIO_GW_OPCODE_SHIFT, |
56 | }, |
57 | .st1 = { |
58 | .mask = MLXBF2_GIGE_MDIO_GW_ST1_MASK, |
59 | .shift = MLXBF2_GIGE_MDIO_GW_ST1_SHIFT, |
60 | }, |
61 | }, |
62 | [MLXBF_GIGE_VERSION_BF3] = { |
63 | .gw_address = MLXBF3_GIGE_MDIO_GW_OFFSET, |
64 | .read_data_address = MLXBF3_GIGE_MDIO_DATA_READ, |
65 | .busy = { |
66 | .mask = MLXBF3_GIGE_MDIO_GW_BUSY_MASK, |
67 | .shift = MLXBF3_GIGE_MDIO_GW_BUSY_SHIFT, |
68 | }, |
69 | .read_data = { |
70 | .mask = MLXBF3_GIGE_MDIO_GW_DATA_READ_MASK, |
71 | .shift = MLXBF3_GIGE_MDIO_GW_DATA_READ_SHIFT, |
72 | }, |
73 | .write_data = { |
74 | .mask = MLXBF3_GIGE_MDIO_GW_DATA_MASK, |
75 | .shift = MLXBF3_GIGE_MDIO_GW_DATA_SHIFT, |
76 | }, |
77 | .devad = { |
78 | .mask = MLXBF3_GIGE_MDIO_GW_DEVAD_MASK, |
79 | .shift = MLXBF3_GIGE_MDIO_GW_DEVAD_SHIFT, |
80 | }, |
81 | .partad = { |
82 | .mask = MLXBF3_GIGE_MDIO_GW_PARTAD_MASK, |
83 | .shift = MLXBF3_GIGE_MDIO_GW_PARTAD_SHIFT, |
84 | }, |
85 | .opcode = { |
86 | .mask = MLXBF3_GIGE_MDIO_GW_OPCODE_MASK, |
87 | .shift = MLXBF3_GIGE_MDIO_GW_OPCODE_SHIFT, |
88 | }, |
89 | .st1 = { |
90 | .mask = MLXBF3_GIGE_MDIO_GW_ST1_MASK, |
91 | .shift = MLXBF3_GIGE_MDIO_GW_ST1_SHIFT, |
92 | }, |
93 | }, |
94 | }; |
95 | |
96 | #define MLXBF_GIGE_MDIO_FREQ_REFERENCE 156250000ULL |
97 | #define MLXBF_GIGE_MDIO_COREPLL_CONST 16384ULL |
98 | #define MLXBF_GIGE_MDC_CLK_NS 400 |
99 | #define MLXBF_GIGE_MDIO_PLL_I1CLK_REG1 0x4 |
100 | #define MLXBF_GIGE_MDIO_PLL_I1CLK_REG2 0x8 |
101 | #define MLXBF_GIGE_MDIO_CORE_F_SHIFT 0 |
102 | #define MLXBF_GIGE_MDIO_CORE_F_MASK GENMASK(25, 0) |
103 | #define MLXBF_GIGE_MDIO_CORE_R_SHIFT 26 |
104 | #define MLXBF_GIGE_MDIO_CORE_R_MASK GENMASK(31, 26) |
105 | #define MLXBF_GIGE_MDIO_CORE_OD_SHIFT 0 |
106 | #define MLXBF_GIGE_MDIO_CORE_OD_MASK GENMASK(3, 0) |
107 | |
108 | /* Support clause 22 */ |
109 | #define MLXBF_GIGE_MDIO_CL22_ST1 0x1 |
110 | #define MLXBF_GIGE_MDIO_CL22_WRITE 0x1 |
111 | #define MLXBF_GIGE_MDIO_CL22_READ 0x2 |
112 | |
113 | /* Busy bit is set by software and cleared by hardware */ |
114 | #define MLXBF_GIGE_MDIO_SET_BUSY 0x1 |
115 | |
116 | #define MLXBF_GIGE_BF2_COREPLL_ADDR 0x02800c30 |
117 | #define MLXBF_GIGE_BF2_COREPLL_SIZE 0x0000000c |
118 | #define MLXBF_GIGE_BF3_COREPLL_ADDR 0x13409824 |
119 | #define MLXBF_GIGE_BF3_COREPLL_SIZE 0x00000010 |
120 | |
121 | static struct resource corepll_params[] = { |
122 | [MLXBF_GIGE_VERSION_BF2] = { |
123 | .start = MLXBF_GIGE_BF2_COREPLL_ADDR, |
124 | .end = MLXBF_GIGE_BF2_COREPLL_ADDR + MLXBF_GIGE_BF2_COREPLL_SIZE - 1, |
125 | .name = "COREPLL_RES" |
126 | }, |
127 | [MLXBF_GIGE_VERSION_BF3] = { |
128 | .start = MLXBF_GIGE_BF3_COREPLL_ADDR, |
129 | .end = MLXBF_GIGE_BF3_COREPLL_ADDR + MLXBF_GIGE_BF3_COREPLL_SIZE - 1, |
130 | .name = "COREPLL_RES" |
131 | } |
132 | }; |
133 | |
134 | /* Returns core clock i1clk in Hz */ |
135 | static u64 calculate_i1clk(struct mlxbf_gige *priv) |
136 | { |
137 | u8 core_od, core_r; |
138 | u64 freq_output; |
139 | u32 reg1, reg2; |
140 | u32 core_f; |
141 | |
142 | reg1 = readl(addr: priv->clk_io + MLXBF_GIGE_MDIO_PLL_I1CLK_REG1); |
143 | reg2 = readl(addr: priv->clk_io + MLXBF_GIGE_MDIO_PLL_I1CLK_REG2); |
144 | |
145 | core_f = (reg1 & MLXBF_GIGE_MDIO_CORE_F_MASK) >> |
146 | MLXBF_GIGE_MDIO_CORE_F_SHIFT; |
147 | core_r = (reg1 & MLXBF_GIGE_MDIO_CORE_R_MASK) >> |
148 | MLXBF_GIGE_MDIO_CORE_R_SHIFT; |
149 | core_od = (reg2 & MLXBF_GIGE_MDIO_CORE_OD_MASK) >> |
150 | MLXBF_GIGE_MDIO_CORE_OD_SHIFT; |
151 | |
152 | /* Compute PLL output frequency as follow: |
153 | * |
154 | * CORE_F / 16384 |
155 | * freq_output = freq_reference * ---------------------------- |
156 | * (CORE_R + 1) * (CORE_OD + 1) |
157 | */ |
158 | freq_output = div_u64(dividend: (MLXBF_GIGE_MDIO_FREQ_REFERENCE * core_f), |
159 | MLXBF_GIGE_MDIO_COREPLL_CONST); |
160 | freq_output = div_u64(dividend: freq_output, divisor: (core_r + 1) * (core_od + 1)); |
161 | |
162 | return freq_output; |
163 | } |
164 | |
165 | /* Formula for encoding the MDIO period. The encoded value is |
166 | * passed to the MDIO config register. |
167 | * |
168 | * mdc_clk = 2*(val + 1)*(core clock in sec) |
169 | * |
170 | * i1clk is in Hz: |
171 | * 400 ns = 2*(val + 1)*(1/i1clk) |
172 | * |
173 | * val = (((400/10^9) / (1/i1clk) / 2) - 1) |
174 | * val = (400/2 * i1clk)/10^9 - 1 |
175 | */ |
176 | static u8 mdio_period_map(struct mlxbf_gige *priv) |
177 | { |
178 | u8 mdio_period; |
179 | u64 i1clk; |
180 | |
181 | i1clk = calculate_i1clk(priv); |
182 | |
183 | mdio_period = div_u64(dividend: (MLXBF_GIGE_MDC_CLK_NS >> 1) * i1clk, divisor: 1000000000) - 1; |
184 | |
185 | return mdio_period; |
186 | } |
187 | |
188 | static u32 mlxbf_gige_mdio_create_cmd(struct mlxbf_gige_mdio_gw *mdio_gw, u16 data, int phy_add, |
189 | int phy_reg, u32 opcode) |
190 | { |
191 | u32 gw_reg = 0; |
192 | |
193 | gw_reg |= ((data << mdio_gw->write_data.shift) & |
194 | mdio_gw->write_data.mask); |
195 | gw_reg |= ((phy_reg << mdio_gw->devad.shift) & |
196 | mdio_gw->devad.mask); |
197 | gw_reg |= ((phy_add << mdio_gw->partad.shift) & |
198 | mdio_gw->partad.mask); |
199 | gw_reg |= ((opcode << mdio_gw->opcode.shift) & |
200 | mdio_gw->opcode.mask); |
201 | gw_reg |= ((MLXBF_GIGE_MDIO_CL22_ST1 << mdio_gw->st1.shift) & |
202 | mdio_gw->st1.mask); |
203 | gw_reg |= ((MLXBF_GIGE_MDIO_SET_BUSY << mdio_gw->busy.shift) & |
204 | mdio_gw->busy.mask); |
205 | |
206 | return gw_reg; |
207 | } |
208 | |
209 | static int mlxbf_gige_mdio_read(struct mii_bus *bus, int phy_add, int phy_reg) |
210 | { |
211 | struct mlxbf_gige *priv = bus->priv; |
212 | u32 cmd; |
213 | int ret; |
214 | u32 val; |
215 | |
216 | /* Send mdio read request */ |
217 | cmd = mlxbf_gige_mdio_create_cmd(mdio_gw: priv->mdio_gw, data: 0, phy_add, phy_reg, |
218 | MLXBF_GIGE_MDIO_CL22_READ); |
219 | |
220 | writel(val: cmd, addr: priv->mdio_io + priv->mdio_gw->gw_address); |
221 | |
222 | ret = readl_poll_timeout_atomic(priv->mdio_io + priv->mdio_gw->gw_address, |
223 | val, !(val & priv->mdio_gw->busy.mask), |
224 | 5, 1000000); |
225 | |
226 | if (ret) { |
227 | writel(val: 0, addr: priv->mdio_io + priv->mdio_gw->gw_address); |
228 | return ret; |
229 | } |
230 | |
231 | ret = readl(addr: priv->mdio_io + priv->mdio_gw->read_data_address); |
232 | /* Only return ad bits of the gw register */ |
233 | ret &= priv->mdio_gw->read_data.mask; |
234 | |
235 | /* The MDIO lock is set on read. To release it, clear gw register */ |
236 | writel(val: 0, addr: priv->mdio_io + priv->mdio_gw->gw_address); |
237 | |
238 | return ret; |
239 | } |
240 | |
241 | static int mlxbf_gige_mdio_write(struct mii_bus *bus, int phy_add, |
242 | int phy_reg, u16 val) |
243 | { |
244 | struct mlxbf_gige *priv = bus->priv; |
245 | u32 temp; |
246 | u32 cmd; |
247 | int ret; |
248 | |
249 | /* Send mdio write request */ |
250 | cmd = mlxbf_gige_mdio_create_cmd(mdio_gw: priv->mdio_gw, data: val, phy_add, phy_reg, |
251 | MLXBF_GIGE_MDIO_CL22_WRITE); |
252 | writel(val: cmd, addr: priv->mdio_io + priv->mdio_gw->gw_address); |
253 | |
254 | /* If the poll timed out, drop the request */ |
255 | ret = readl_poll_timeout_atomic(priv->mdio_io + priv->mdio_gw->gw_address, |
256 | temp, !(temp & priv->mdio_gw->busy.mask), |
257 | 5, 1000000); |
258 | |
259 | /* The MDIO lock is set on read. To release it, clear gw register */ |
260 | writel(val: 0, addr: priv->mdio_io + priv->mdio_gw->gw_address); |
261 | |
262 | return ret; |
263 | } |
264 | |
265 | static void mlxbf_gige_mdio_cfg(struct mlxbf_gige *priv) |
266 | { |
267 | u8 mdio_period; |
268 | u32 val; |
269 | |
270 | mdio_period = mdio_period_map(priv); |
271 | |
272 | if (priv->hw_version == MLXBF_GIGE_VERSION_BF2) { |
273 | val = MLXBF2_GIGE_MDIO_CFG_VAL; |
274 | val |= FIELD_PREP(MLXBF2_GIGE_MDIO_CFG_MDC_PERIOD_MASK, mdio_period); |
275 | writel(val, addr: priv->mdio_io + MLXBF2_GIGE_MDIO_CFG_OFFSET); |
276 | } else { |
277 | val = FIELD_PREP(MLXBF3_GIGE_MDIO_CFG_MDIO_MODE_MASK, 1) | |
278 | FIELD_PREP(MLXBF3_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK, 1); |
279 | writel(val, addr: priv->mdio_io + MLXBF3_GIGE_MDIO_CFG_REG0); |
280 | val = FIELD_PREP(MLXBF3_GIGE_MDIO_CFG_MDC_PERIOD_MASK, mdio_period); |
281 | writel(val, addr: priv->mdio_io + MLXBF3_GIGE_MDIO_CFG_REG1); |
282 | val = FIELD_PREP(MLXBF3_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK, 6) | |
283 | FIELD_PREP(MLXBF3_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK, 13); |
284 | writel(val, addr: priv->mdio_io + MLXBF3_GIGE_MDIO_CFG_REG2); |
285 | } |
286 | } |
287 | |
288 | int mlxbf_gige_mdio_probe(struct platform_device *pdev, struct mlxbf_gige *priv) |
289 | { |
290 | struct device *dev = &pdev->dev; |
291 | struct resource *res; |
292 | int ret; |
293 | |
294 | if (priv->hw_version > MLXBF_GIGE_VERSION_BF3) |
295 | return -ENODEV; |
296 | |
297 | priv->mdio_io = devm_platform_ioremap_resource(pdev, index: MLXBF_GIGE_RES_MDIO9); |
298 | if (IS_ERR(ptr: priv->mdio_io)) |
299 | return PTR_ERR(ptr: priv->mdio_io); |
300 | |
301 | /* clk resource shared with other drivers so cannot use |
302 | * devm_platform_ioremap_resource |
303 | */ |
304 | res = platform_get_resource(pdev, IORESOURCE_MEM, MLXBF_GIGE_RES_CLK); |
305 | if (!res) { |
306 | /* For backward compatibility with older ACPI tables, also keep |
307 | * CLK resource internal to the driver. |
308 | */ |
309 | res = &corepll_params[priv->hw_version]; |
310 | } |
311 | |
312 | priv->clk_io = devm_ioremap(dev, offset: res->start, size: resource_size(res)); |
313 | if (!priv->clk_io) |
314 | return -ENOMEM; |
315 | |
316 | priv->mdio_gw = &mlxbf_gige_mdio_gw_t[priv->hw_version]; |
317 | |
318 | mlxbf_gige_mdio_cfg(priv); |
319 | |
320 | priv->mdiobus = devm_mdiobus_alloc(dev); |
321 | if (!priv->mdiobus) { |
322 | dev_err(dev, "Failed to alloc MDIO bus\n" ); |
323 | return -ENOMEM; |
324 | } |
325 | |
326 | priv->mdiobus->name = "mlxbf-mdio" ; |
327 | priv->mdiobus->read = mlxbf_gige_mdio_read; |
328 | priv->mdiobus->write = mlxbf_gige_mdio_write; |
329 | priv->mdiobus->parent = dev; |
330 | priv->mdiobus->priv = priv; |
331 | snprintf(buf: priv->mdiobus->id, MII_BUS_ID_SIZE, fmt: "%s" , |
332 | dev_name(dev)); |
333 | |
334 | ret = mdiobus_register(priv->mdiobus); |
335 | if (ret) |
336 | dev_err(dev, "Failed to register MDIO bus\n" ); |
337 | |
338 | return ret; |
339 | } |
340 | |
341 | void mlxbf_gige_mdio_remove(struct mlxbf_gige *priv) |
342 | { |
343 | mdiobus_unregister(bus: priv->mdiobus); |
344 | } |
345 | |