1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /* Microchip Sparx5 Switch driver |
3 | * |
4 | * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. |
5 | */ |
6 | |
7 | #ifndef __SPARX5_TC_H__ |
8 | #define __SPARX5_TC_H__ |
9 | |
10 | #include <net/flow_offload.h> |
11 | #include <net/pkt_cls.h> |
12 | #include <linux/netdevice.h> |
13 | |
14 | /* Controls how PORT_MASK is applied */ |
15 | enum SPX5_PORT_MASK_MODE { |
16 | SPX5_PMM_OR_DSTMASK, |
17 | SPX5_PMM_AND_VLANMASK, |
18 | SPX5_PMM_REPLACE_PGID, |
19 | SPX5_PMM_REPLACE_ALL, |
20 | SPX5_PMM_REDIR_PGID, |
21 | SPX5_PMM_OR_PGID_MASK, |
22 | }; |
23 | |
24 | /* Controls ES0 forwarding */ |
25 | enum SPX5_FORWARDING_SEL { |
26 | SPX5_FWSEL_NO_ACTION, |
27 | SPX5_FWSEL_COPY_TO_LOOPBACK, |
28 | SPX5_FWSEL_REDIRECT_TO_LOOPBACK, |
29 | SPX5_FWSEL_DISCARD, |
30 | }; |
31 | |
32 | /* Controls tag A (outer tagging) */ |
33 | enum SPX5_OUTER_TAG_SEL { |
34 | SPX5_OTAG_PORT, |
35 | SPX5_OTAG_TAG_A, |
36 | SPX5_OTAG_FORCED_PORT, |
37 | SPX5_OTAG_UNTAG, |
38 | }; |
39 | |
40 | /* Selects TPID for ES0 tag A */ |
41 | enum SPX5_TPID_A_SEL { |
42 | SPX5_TPID_A_8100, |
43 | SPX5_TPID_A_88A8, |
44 | SPX5_TPID_A_CUST1, |
45 | SPX5_TPID_A_CUST2, |
46 | SPX5_TPID_A_CUST3, |
47 | SPX5_TPID_A_CLASSIFIED, |
48 | }; |
49 | |
50 | /* Selects VID for ES0 tag A */ |
51 | enum SPX5_VID_A_SEL { |
52 | SPX5_VID_A_CLASSIFIED, |
53 | SPX5_VID_A_VAL, |
54 | SPX5_VID_A_IFH, |
55 | SPX5_VID_A_RESERVED, |
56 | }; |
57 | |
58 | /* Select PCP source for ES0 tag A */ |
59 | enum SPX5_PCP_A_SEL { |
60 | SPX5_PCP_A_CLASSIFIED, |
61 | SPX5_PCP_A_VAL, |
62 | SPX5_PCP_A_RESERVED, |
63 | SPX5_PCP_A_POPPED, |
64 | SPX5_PCP_A_MAPPED_0, |
65 | SPX5_PCP_A_MAPPED_1, |
66 | SPX5_PCP_A_MAPPED_2, |
67 | SPX5_PCP_A_MAPPED_3, |
68 | }; |
69 | |
70 | /* Select DEI source for ES0 tag A */ |
71 | enum SPX5_DEI_A_SEL { |
72 | SPX5_DEI_A_CLASSIFIED, |
73 | SPX5_DEI_A_VAL, |
74 | SPX5_DEI_A_REW, |
75 | SPX5_DEI_A_POPPED, |
76 | SPX5_DEI_A_MAPPED_0, |
77 | SPX5_DEI_A_MAPPED_1, |
78 | SPX5_DEI_A_MAPPED_2, |
79 | SPX5_DEI_A_MAPPED_3, |
80 | }; |
81 | |
82 | /* Controls tag B (inner tagging) */ |
83 | enum SPX5_INNER_TAG_SEL { |
84 | SPX5_ITAG_NO_PUSH, |
85 | SPX5_ITAG_PUSH_B_TAG, |
86 | }; |
87 | |
88 | /* Selects TPID for ES0 tag B. */ |
89 | enum SPX5_TPID_B_SEL { |
90 | SPX5_TPID_B_8100, |
91 | SPX5_TPID_B_88A8, |
92 | SPX5_TPID_B_CUST1, |
93 | SPX5_TPID_B_CUST2, |
94 | SPX5_TPID_B_CUST3, |
95 | SPX5_TPID_B_CLASSIFIED, |
96 | }; |
97 | |
98 | int sparx5_port_setup_tc(struct net_device *ndev, enum tc_setup_type type, |
99 | void *type_data); |
100 | |
101 | int sparx5_tc_matchall(struct net_device *ndev, |
102 | struct tc_cls_matchall_offload *tmo, |
103 | bool ingress); |
104 | |
105 | int sparx5_tc_flower(struct net_device *ndev, struct flow_cls_offload *fco, |
106 | bool ingress); |
107 | |
108 | #endif /* __SPARX5_TC_H__ */ |
109 | |