1 | // SPDX-License-Identifier: GPL-2.0 |
2 | |
3 | /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. |
4 | * Copyright (C) 2019-2021 Linaro Ltd. |
5 | */ |
6 | |
7 | #include <linux/log2.h> |
8 | |
9 | #include "../gsi.h" |
10 | #include "../ipa_data.h" |
11 | #include "../ipa_endpoint.h" |
12 | #include "../ipa_mem.h" |
13 | |
14 | /** enum ipa_resource_type - IPA resource types for an SoC having IPA v3.1 */ |
15 | enum ipa_resource_type { |
16 | /* Source resource types; first must have value 0 */ |
17 | IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, |
18 | IPA_RESOURCE_TYPE_SRC_HDR_SECTORS, |
19 | IPA_RESOURCE_TYPE_SRC_HDRI1_BUFFER, |
20 | IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, |
21 | IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, |
22 | IPA_RESOURCE_TYPE_SRC_HDRI2_BUFFERS, |
23 | IPA_RESOURCE_TYPE_SRC_HPS_DMARS, |
24 | IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, |
25 | |
26 | /* Destination resource types; first must have value 0 */ |
27 | IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, |
28 | IPA_RESOURCE_TYPE_DST_DATA_SECTOR_LISTS, |
29 | IPA_RESOURCE_TYPE_DST_DPS_DMARS, |
30 | }; |
31 | |
32 | /* Resource groups used for an SoC having IPA v3.1 */ |
33 | enum ipa_rsrc_group_id { |
34 | /* Source resource group identifiers */ |
35 | IPA_RSRC_GROUP_SRC_UL = 0, |
36 | IPA_RSRC_GROUP_SRC_DL, |
37 | IPA_RSRC_GROUP_SRC_DIAG, |
38 | IPA_RSRC_GROUP_SRC_DMA, |
39 | IPA_RSRC_GROUP_SRC_UNUSED, |
40 | IPA_RSRC_GROUP_SRC_UC_RX_Q, |
41 | IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ |
42 | |
43 | /* Destination resource group identifiers */ |
44 | IPA_RSRC_GROUP_DST_UL = 0, |
45 | IPA_RSRC_GROUP_DST_DL, |
46 | IPA_RSRC_GROUP_DST_DIAG_DPL, |
47 | IPA_RSRC_GROUP_DST_DMA, |
48 | IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL, |
49 | IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE, |
50 | IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ |
51 | }; |
52 | |
53 | /* QSB configuration data for an SoC having IPA v3.1 */ |
54 | static const struct ipa_qsb_data ipa_qsb_data[] = { |
55 | [IPA_QSB_MASTER_DDR] = { |
56 | .max_writes = 8, |
57 | .max_reads = 8, |
58 | }, |
59 | [IPA_QSB_MASTER_PCIE] = { |
60 | .max_writes = 2, |
61 | .max_reads = 8, |
62 | }, |
63 | }; |
64 | |
65 | /* Endpoint data for an SoC having IPA v3.1 */ |
66 | static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { |
67 | [IPA_ENDPOINT_AP_COMMAND_TX] = { |
68 | .ee_id = GSI_EE_AP, |
69 | .channel_id = 6, |
70 | .endpoint_id = 22, |
71 | .toward_ipa = true, |
72 | .channel = { |
73 | .tre_count = 256, |
74 | .event_count = 256, |
75 | .tlv_count = 18, |
76 | }, |
77 | .endpoint = { |
78 | .config = { |
79 | .resource_group = IPA_RSRC_GROUP_SRC_UL, |
80 | .dma_mode = true, |
81 | .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, |
82 | .tx = { |
83 | .seq_type = IPA_SEQ_DMA, |
84 | }, |
85 | }, |
86 | }, |
87 | }, |
88 | [IPA_ENDPOINT_AP_LAN_RX] = { |
89 | .ee_id = GSI_EE_AP, |
90 | .channel_id = 7, |
91 | .endpoint_id = 15, |
92 | .toward_ipa = false, |
93 | .channel = { |
94 | .tre_count = 256, |
95 | .event_count = 256, |
96 | .tlv_count = 8, |
97 | }, |
98 | .endpoint = { |
99 | .config = { |
100 | .resource_group = IPA_RSRC_GROUP_SRC_UL, |
101 | .aggregation = true, |
102 | .status_enable = true, |
103 | .rx = { |
104 | .buffer_size = 8192, |
105 | .pad_align = ilog2(sizeof(u32)), |
106 | .aggr_time_limit = 500, |
107 | }, |
108 | }, |
109 | }, |
110 | }, |
111 | [IPA_ENDPOINT_AP_MODEM_TX] = { |
112 | .ee_id = GSI_EE_AP, |
113 | .channel_id = 5, |
114 | .endpoint_id = 3, |
115 | .toward_ipa = true, |
116 | .channel = { |
117 | .tre_count = 512, |
118 | .event_count = 512, |
119 | .tlv_count = 16, |
120 | }, |
121 | .endpoint = { |
122 | .filter_support = true, |
123 | .config = { |
124 | .resource_group = IPA_RSRC_GROUP_SRC_UL, |
125 | .checksum = true, |
126 | .qmap = true, |
127 | .status_enable = true, |
128 | .tx = { |
129 | .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, |
130 | .status_endpoint = |
131 | IPA_ENDPOINT_MODEM_AP_RX, |
132 | }, |
133 | }, |
134 | }, |
135 | }, |
136 | [IPA_ENDPOINT_AP_MODEM_RX] = { |
137 | .ee_id = GSI_EE_AP, |
138 | .channel_id = 8, |
139 | .endpoint_id = 16, |
140 | .toward_ipa = false, |
141 | .channel = { |
142 | .tre_count = 256, |
143 | .event_count = 256, |
144 | .tlv_count = 8, |
145 | }, |
146 | .endpoint = { |
147 | .config = { |
148 | .resource_group = IPA_RSRC_GROUP_DST_DL, |
149 | .checksum = true, |
150 | .qmap = true, |
151 | .aggregation = true, |
152 | .rx = { |
153 | .buffer_size = 8192, |
154 | .aggr_time_limit = 500, |
155 | .aggr_close_eof = true, |
156 | }, |
157 | }, |
158 | }, |
159 | }, |
160 | [IPA_ENDPOINT_MODEM_LAN_TX] = { |
161 | .ee_id = GSI_EE_MODEM, |
162 | .channel_id = 4, |
163 | .endpoint_id = 9, |
164 | .toward_ipa = true, |
165 | .endpoint = { |
166 | .filter_support = true, |
167 | }, |
168 | }, |
169 | [IPA_ENDPOINT_MODEM_AP_TX] = { |
170 | .ee_id = GSI_EE_MODEM, |
171 | .channel_id = 0, |
172 | .endpoint_id = 5, |
173 | .toward_ipa = true, |
174 | .endpoint = { |
175 | .filter_support = true, |
176 | }, |
177 | }, |
178 | [IPA_ENDPOINT_MODEM_AP_RX] = { |
179 | .ee_id = GSI_EE_MODEM, |
180 | .channel_id = 5, |
181 | .endpoint_id = 18, |
182 | .toward_ipa = false, |
183 | }, |
184 | }; |
185 | |
186 | /* Source resource configuration data for an SoC having IPA v3.1 */ |
187 | static const struct ipa_resource ipa_resource_src[] = { |
188 | [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { |
189 | .limits[IPA_RSRC_GROUP_SRC_UL] = { |
190 | .min = 3, .max = 255, |
191 | }, |
192 | .limits[IPA_RSRC_GROUP_SRC_DL] = { |
193 | .min = 3, .max = 255, |
194 | }, |
195 | .limits[IPA_RSRC_GROUP_SRC_DIAG] = { |
196 | .min = 1, .max = 255, |
197 | }, |
198 | .limits[IPA_RSRC_GROUP_SRC_DMA] = { |
199 | .min = 1, .max = 255, |
200 | }, |
201 | .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { |
202 | .min = 2, .max = 255, |
203 | }, |
204 | }, |
205 | [IPA_RESOURCE_TYPE_SRC_HDR_SECTORS] = { |
206 | .limits[IPA_RSRC_GROUP_SRC_UL] = { |
207 | .min = 0, .max = 255, |
208 | }, |
209 | .limits[IPA_RSRC_GROUP_SRC_DL] = { |
210 | .min = 0, .max = 255, |
211 | }, |
212 | .limits[IPA_RSRC_GROUP_SRC_DIAG] = { |
213 | .min = 0, .max = 255, |
214 | }, |
215 | .limits[IPA_RSRC_GROUP_SRC_DMA] = { |
216 | .min = 0, .max = 255, |
217 | }, |
218 | .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { |
219 | .min = 0, .max = 255, |
220 | }, |
221 | }, |
222 | [IPA_RESOURCE_TYPE_SRC_HDRI1_BUFFER] = { |
223 | .limits[IPA_RSRC_GROUP_SRC_UL] = { |
224 | .min = 0, .max = 255, |
225 | }, |
226 | .limits[IPA_RSRC_GROUP_SRC_DL] = { |
227 | .min = 0, .max = 255, |
228 | }, |
229 | .limits[IPA_RSRC_GROUP_SRC_DIAG] = { |
230 | .min = 0, .max = 255, |
231 | }, |
232 | .limits[IPA_RSRC_GROUP_SRC_DMA] = { |
233 | .min = 0, .max = 255, |
234 | }, |
235 | .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { |
236 | .min = 0, .max = 255, |
237 | }, |
238 | }, |
239 | [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { |
240 | .limits[IPA_RSRC_GROUP_SRC_UL] = { |
241 | .min = 14, .max = 14, |
242 | }, |
243 | .limits[IPA_RSRC_GROUP_SRC_DL] = { |
244 | .min = 16, .max = 16, |
245 | }, |
246 | .limits[IPA_RSRC_GROUP_SRC_DIAG] = { |
247 | .min = 5, .max = 5, |
248 | }, |
249 | .limits[IPA_RSRC_GROUP_SRC_DMA] = { |
250 | .min = 5, .max = 5, |
251 | }, |
252 | .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { |
253 | .min = 8, .max = 8, |
254 | }, |
255 | }, |
256 | [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { |
257 | .limits[IPA_RSRC_GROUP_SRC_UL] = { |
258 | .min = 19, .max = 19, |
259 | }, |
260 | .limits[IPA_RSRC_GROUP_SRC_DL] = { |
261 | .min = 26, .max = 26, |
262 | }, |
263 | .limits[IPA_RSRC_GROUP_SRC_DIAG] = { |
264 | .min = 5, .max = 5, /* 3 downstream */ |
265 | }, |
266 | .limits[IPA_RSRC_GROUP_SRC_DMA] = { |
267 | .min = 5, .max = 5, /* 7 downstream */ |
268 | }, |
269 | .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { |
270 | .min = 8, .max = 8, |
271 | }, |
272 | }, |
273 | [IPA_RESOURCE_TYPE_SRC_HDRI2_BUFFERS] = { |
274 | .limits[IPA_RSRC_GROUP_SRC_UL] = { |
275 | .min = 0, .max = 255, |
276 | }, |
277 | .limits[IPA_RSRC_GROUP_SRC_DL] = { |
278 | .min = 0, .max = 255, |
279 | }, |
280 | .limits[IPA_RSRC_GROUP_SRC_DIAG] = { |
281 | .min = 0, .max = 255, |
282 | }, |
283 | .limits[IPA_RSRC_GROUP_SRC_DMA] = { |
284 | .min = 0, .max = 255, |
285 | }, |
286 | .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { |
287 | .min = 0, .max = 255, |
288 | }, |
289 | }, |
290 | [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { |
291 | .limits[IPA_RSRC_GROUP_SRC_UL] = { |
292 | .min = 0, .max = 255, |
293 | }, |
294 | .limits[IPA_RSRC_GROUP_SRC_DL] = { |
295 | .min = 0, .max = 255, |
296 | }, |
297 | .limits[IPA_RSRC_GROUP_SRC_DIAG] = { |
298 | .min = 0, .max = 255, |
299 | }, |
300 | .limits[IPA_RSRC_GROUP_SRC_DMA] = { |
301 | .min = 0, .max = 255, |
302 | }, |
303 | .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { |
304 | .min = 0, .max = 255, |
305 | }, |
306 | }, |
307 | [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { |
308 | .limits[IPA_RSRC_GROUP_SRC_UL] = { |
309 | .min = 19, .max = 19, |
310 | }, |
311 | .limits[IPA_RSRC_GROUP_SRC_DL] = { |
312 | .min = 26, .max = 26, |
313 | }, |
314 | .limits[IPA_RSRC_GROUP_SRC_DIAG] = { |
315 | .min = 5, .max = 5, |
316 | }, |
317 | .limits[IPA_RSRC_GROUP_SRC_DMA] = { |
318 | .min = 5, .max = 5, |
319 | }, |
320 | .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { |
321 | .min = 8, .max = 8, |
322 | }, |
323 | }, |
324 | }; |
325 | |
326 | /* Destination resource configuration data for an SoC having IPA v3.1 */ |
327 | static const struct ipa_resource ipa_resource_dst[] = { |
328 | [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { |
329 | .limits[IPA_RSRC_GROUP_DST_UL] = { |
330 | .min = 3, .max = 3, /* 2 downstream */ |
331 | }, |
332 | .limits[IPA_RSRC_GROUP_DST_DL] = { |
333 | .min = 3, .max = 3, |
334 | }, |
335 | .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = { |
336 | .min = 1, .max = 1, /* 0 downstream */ |
337 | }, |
338 | /* IPA_RSRC_GROUP_DST_DMA uses 2 downstream */ |
339 | .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = { |
340 | .min = 3, .max = 3, |
341 | }, |
342 | .limits[IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE] = { |
343 | .min = 3, .max = 3, |
344 | }, |
345 | }, |
346 | [IPA_RESOURCE_TYPE_DST_DATA_SECTOR_LISTS] = { |
347 | .limits[IPA_RSRC_GROUP_DST_UL] = { |
348 | .min = 0, .max = 255, |
349 | }, |
350 | .limits[IPA_RSRC_GROUP_DST_DL] = { |
351 | .min = 0, .max = 255, |
352 | }, |
353 | .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = { |
354 | .min = 0, .max = 255, |
355 | }, |
356 | .limits[IPA_RSRC_GROUP_DST_DMA] = { |
357 | .min = 0, .max = 255, |
358 | }, |
359 | .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = { |
360 | .min = 0, .max = 255, |
361 | }, |
362 | .limits[IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE] = { |
363 | .min = 0, .max = 255, |
364 | }, |
365 | }, |
366 | [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { |
367 | .limits[IPA_RSRC_GROUP_DST_UL] = { |
368 | .min = 1, .max = 1, |
369 | }, |
370 | .limits[IPA_RSRC_GROUP_DST_DL] = { |
371 | .min = 1, .max = 1, |
372 | }, |
373 | .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = { |
374 | .min = 1, .max = 1, |
375 | }, |
376 | .limits[IPA_RSRC_GROUP_DST_DMA] = { |
377 | .min = 1, .max = 1, |
378 | }, |
379 | .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = { |
380 | .min = 1, .max = 1, |
381 | }, |
382 | }, |
383 | }; |
384 | |
385 | /* Resource configuration data for an SoC having IPA v3.1 */ |
386 | static const struct ipa_resource_data ipa_resource_data = { |
387 | .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, |
388 | .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, |
389 | .resource_src_count = ARRAY_SIZE(ipa_resource_src), |
390 | .resource_src = ipa_resource_src, |
391 | .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), |
392 | .resource_dst = ipa_resource_dst, |
393 | }; |
394 | |
395 | /* IPA-resident memory region data for an SoC having IPA v3.1 */ |
396 | static const struct ipa_mem ipa_mem_local_data[] = { |
397 | { |
398 | .id = IPA_MEM_UC_SHARED, |
399 | .offset = 0x0000, |
400 | .size = 0x0080, |
401 | .canary_count = 0, |
402 | }, |
403 | { |
404 | .id = IPA_MEM_UC_INFO, |
405 | .offset = 0x0080, |
406 | .size = 0x0200, |
407 | .canary_count = 0, |
408 | }, |
409 | { |
410 | .id = IPA_MEM_V4_FILTER_HASHED, |
411 | .offset = 0x0288, |
412 | .size = 0x0078, |
413 | .canary_count = 2, |
414 | }, |
415 | { |
416 | .id = IPA_MEM_V4_FILTER, |
417 | .offset = 0x0308, |
418 | .size = 0x0078, |
419 | .canary_count = 2, |
420 | }, |
421 | { |
422 | .id = IPA_MEM_V6_FILTER_HASHED, |
423 | .offset = 0x0388, |
424 | .size = 0x0078, |
425 | .canary_count = 2, |
426 | }, |
427 | { |
428 | .id = IPA_MEM_V6_FILTER, |
429 | .offset = 0x0408, |
430 | .size = 0x0078, |
431 | .canary_count = 2, |
432 | }, |
433 | { |
434 | .id = IPA_MEM_V4_ROUTE_HASHED, |
435 | .offset = 0x0488, |
436 | .size = 0x0078, |
437 | .canary_count = 2, |
438 | }, |
439 | { |
440 | .id = IPA_MEM_V4_ROUTE, |
441 | .offset = 0x0508, |
442 | .size = 0x0078, |
443 | .canary_count = 2, |
444 | }, |
445 | { |
446 | .id = IPA_MEM_V6_ROUTE_HASHED, |
447 | .offset = 0x0588, |
448 | .size = 0x0078, |
449 | .canary_count = 2, |
450 | }, |
451 | { |
452 | .id = IPA_MEM_V6_ROUTE, |
453 | .offset = 0x0608, |
454 | .size = 0x0078, |
455 | .canary_count = 2, |
456 | }, |
457 | { |
458 | .id = IPA_MEM_MODEM_HEADER, |
459 | .offset = 0x0688, |
460 | .size = 0x0140, |
461 | .canary_count = 2, |
462 | }, |
463 | { |
464 | .id = IPA_MEM_MODEM_PROC_CTX, |
465 | .offset = 0x07d0, |
466 | .size = 0x0200, |
467 | .canary_count = 2, |
468 | }, |
469 | { |
470 | .id = IPA_MEM_AP_PROC_CTX, |
471 | .offset = 0x09d0, |
472 | .size = 0x0200, |
473 | .canary_count = 0, |
474 | }, |
475 | { |
476 | .id = IPA_MEM_MODEM, |
477 | .offset = 0x0bd8, |
478 | .size = 0x1424, |
479 | .canary_count = 0, |
480 | }, |
481 | { |
482 | .id = IPA_MEM_END_MARKER, |
483 | .offset = 0x2000, |
484 | .size = 0, |
485 | .canary_count = 1, |
486 | }, |
487 | }; |
488 | |
489 | /* Memory configuration data for an SoC having IPA v3.1 */ |
490 | static const struct ipa_mem_data ipa_mem_data = { |
491 | .local_count = ARRAY_SIZE(ipa_mem_local_data), |
492 | .local = ipa_mem_local_data, |
493 | .imem_addr = 0x146bd000, |
494 | .imem_size = 0x00002000, |
495 | .smem_id = 497, |
496 | .smem_size = 0x00002000, |
497 | }; |
498 | |
499 | /* Interconnect bandwidths are in 1000 byte/second units */ |
500 | static const struct ipa_interconnect_data ipa_interconnect_data[] = { |
501 | { |
502 | .name = "memory" , |
503 | .peak_bandwidth = 640000, /* 640 MBps */ |
504 | .average_bandwidth = 80000, /* 80 MBps */ |
505 | }, |
506 | { |
507 | .name = "imem" , |
508 | .peak_bandwidth = 640000, /* 640 MBps */ |
509 | .average_bandwidth = 80000, /* 80 MBps */ |
510 | }, |
511 | /* Average bandwidth is unused for the next interconnect */ |
512 | { |
513 | .name = "config" , |
514 | .peak_bandwidth = 80000, /* 80 MBps */ |
515 | .average_bandwidth = 0, /* unused */ |
516 | }, |
517 | }; |
518 | |
519 | /* Clock and interconnect configuration data for an SoC having IPA v3.1 */ |
520 | static const struct ipa_power_data ipa_power_data = { |
521 | .core_clock_rate = 16 * 1000 * 1000, /* Hz */ |
522 | .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), |
523 | .interconnect_data = ipa_interconnect_data, |
524 | }; |
525 | |
526 | /* Configuration data for an SoC having IPA v3.1 */ |
527 | const struct ipa_data ipa_data_v3_1 = { |
528 | .version = IPA_VERSION_3_1, |
529 | .backward_compat = BIT(BCR_CMDQ_L_LACK_ONE_ENTRY), |
530 | .qsb_count = ARRAY_SIZE(ipa_qsb_data), |
531 | .qsb_data = ipa_qsb_data, |
532 | .modem_route_count = 8, |
533 | .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), |
534 | .endpoint_data = ipa_gsi_endpoint_data, |
535 | .resource_data = &ipa_resource_data, |
536 | .mem_data = &ipa_mem_data, |
537 | .power_data = &ipa_power_data, |
538 | }; |
539 | |