1/* SPDX-License-Identifier: GPL-2.0 */
2
3/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2023 Linaro Ltd.
5 */
6#ifndef _IPA_REG_H_
7#define _IPA_REG_H_
8
9#include <linux/bitfield.h>
10#include <linux/bug.h>
11
12#include "ipa_version.h"
13#include "reg.h"
14
15struct platform_device;
16
17struct ipa;
18
19/**
20 * DOC: IPA Registers
21 *
22 * IPA registers are located within the "ipa-reg" address space defined by
23 * Device Tree. Each register has a specified offset within that space,
24 * which is mapped into virtual memory space in ipa_mem_init(). Each
25 * has a unique identifer, taken from the ipa_reg_id enumerated type.
26 * All IPA registers are 32 bits wide.
27 *
28 * Certain "parameterized" register types are duplicated for a number of
29 * instances of something. For example, each IPA endpoint has an set of
30 * registers defining its configuration. The offset to an endpoint's set
31 * of registers is computed based on an "base" offset, plus an endpoint's
32 * ID multiplied and a "stride" value for the register. Similarly, some
33 * registers have an offset that depends on execution environment. In
34 * this case, the stride is multiplied by a member of the gsi_ee_id
35 * enumerated type.
36 *
37 * Each version of IPA implements an array of ipa_reg structures indexed
38 * by register ID. Each entry in the array specifies the base offset and
39 * (for parameterized registers) a non-zero stride value. Not all versions
40 * of IPA define all registers. The offset for a register is returned by
41 * reg_offset() when the register's ipa_reg structure is supplied;
42 * zero is returned for an undefined register (this should never happen).
43 *
44 * Some registers encode multiple fields within them. Each field in
45 * such a register has a unique identifier (from an enumerated type).
46 * The position and width of the fields in a register are defined by
47 * an array of field masks, indexed by field ID. Two functions are
48 * used to access register fields; both take an ipa_reg structure as
49 * argument. To encode a value to be represented in a register field,
50 * the value and field ID are passed to reg_encode(). To extract
51 * a value encoded in a register field, the field ID is passed to
52 * reg_decode(). In addition, for single-bit fields, reg_bit()
53 * can be used to either encode the bit value, or to generate a mask
54 * used to extract the bit value.
55 */
56
57/* enum ipa_reg_id - IPA register IDs */
58enum ipa_reg_id {
59 COMP_CFG,
60 CLKON_CFG,
61 ROUTE,
62 SHARED_MEM_SIZE,
63 QSB_MAX_WRITES,
64 QSB_MAX_READS,
65 FILT_ROUT_HASH_EN, /* IPA v4.2 */
66 FILT_ROUT_HASH_FLUSH, /* Not IPA v4.2 nor IPA v5.0+ */
67 FILT_ROUT_CACHE_FLUSH, /* IPA v5.0+ */
68 STATE_AGGR_ACTIVE,
69 IPA_BCR, /* Not IPA v4.5+ */
70 LOCAL_PKT_PROC_CNTXT,
71 AGGR_FORCE_CLOSE,
72 COUNTER_CFG, /* Not IPA v4.5+ */
73 IPA_TX_CFG, /* IPA v3.5+ */
74 FLAVOR_0, /* IPA v3.5+ */
75 IDLE_INDICATION_CFG, /* IPA v3.5+ */
76 QTIME_TIMESTAMP_CFG, /* IPA v4.5+ */
77 TIMERS_XO_CLK_DIV_CFG, /* IPA v4.5+ */
78 TIMERS_PULSE_GRAN_CFG, /* IPA v4.5+ */
79 SRC_RSRC_GRP_01_RSRC_TYPE,
80 SRC_RSRC_GRP_23_RSRC_TYPE,
81 SRC_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+; IPA v4.5, IPA v5.0 */
82 SRC_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+; IPA v5.0 */
83 DST_RSRC_GRP_01_RSRC_TYPE,
84 DST_RSRC_GRP_23_RSRC_TYPE,
85 DST_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+; IPA v4.5, IPA v5.0 */
86 DST_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+; IPA v5.0 */
87 ENDP_INIT_CTRL, /* Not IPA v4.2+ for TX, not IPA v4.0+ for RX */
88 ENDP_INIT_CFG,
89 ENDP_INIT_NAT, /* TX only */
90 ENDP_INIT_HDR,
91 ENDP_INIT_HDR_EXT,
92 ENDP_INIT_HDR_METADATA_MASK, /* RX only */
93 ENDP_INIT_MODE, /* TX only */
94 ENDP_INIT_AGGR,
95 ENDP_INIT_HOL_BLOCK_EN, /* RX only */
96 ENDP_INIT_HOL_BLOCK_TIMER, /* RX only */
97 ENDP_INIT_DEAGGR, /* TX only */
98 ENDP_INIT_RSRC_GRP,
99 ENDP_INIT_SEQ, /* TX only */
100 ENDP_STATUS,
101 ENDP_FILTER_ROUTER_HSH_CFG, /* Not IPA v4.2 */
102 ENDP_FILTER_CACHE_CFG, /* IPA v5.0+ */
103 ENDP_ROUTER_CACHE_CFG, /* IPA v5.0+ */
104 /* The IRQ registers that follow are only used for GSI_EE_AP */
105 IPA_IRQ_STTS,
106 IPA_IRQ_EN,
107 IPA_IRQ_CLR,
108 IPA_IRQ_UC,
109 IRQ_SUSPEND_INFO,
110 IRQ_SUSPEND_EN, /* IPA v3.1+ */
111 IRQ_SUSPEND_CLR, /* IPA v3.1+ */
112 IPA_REG_ID_COUNT, /* Last; not an ID */
113};
114
115/* COMP_CFG register */
116enum ipa_reg_comp_cfg_field_id {
117 COMP_CFG_ENABLE, /* Not IPA v4.0+ */
118 RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS, /* IPA v4.7+ */
119 GSI_SNOC_BYPASS_DIS,
120 GEN_QMB_0_SNOC_BYPASS_DIS,
121 GEN_QMB_1_SNOC_BYPASS_DIS,
122 IPA_DCMP_FAST_CLK_EN, /* Not IPA v4.5+ */
123 IPA_QMB_SELECT_CONS_EN, /* IPA v4.0+ */
124 IPA_QMB_SELECT_PROD_EN, /* IPA v4.0+ */
125 GSI_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */
126 GSI_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */
127 GEN_QMB_0_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */
128 GEN_QMB_1_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */
129 GEN_QMB_0_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */
130 GEN_QMB_1_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */
131 GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS, /* IPA v4.0+ */
132 GSI_SNOC_CNOC_LOOP_PROT_DISABLE, /* IPA v4.0+ */
133 GSI_MULTI_AXI_MASTERS_DIS, /* IPA v4.0+ */
134 IPA_QMB_SELECT_GLOBAL_EN, /* IPA v4.0+ */
135 QMB_RAM_RD_CACHE_DISABLE, /* IPA v4.9+ */
136 GENQMB_AOOOWR, /* IPA v4.9+ */
137 IF_OUT_OF_BUF_STOP_RESET_MASK_EN, /* IPA v4.9+ */
138 GEN_QMB_1_DYNAMIC_ASIZE, /* IPA v4.9+ */
139 GEN_QMB_0_DYNAMIC_ASIZE, /* IPA v4.9+ */
140 ATOMIC_FETCHER_ARB_LOCK_DIS, /* IPA v4.0+ */
141 FULL_FLUSH_WAIT_RS_CLOSURE_EN, /* IPA v4.5+ */
142};
143
144/* CLKON_CFG register */
145enum ipa_reg_clkon_cfg_field_id {
146 CLKON_RX,
147 CLKON_PROC,
148 TX_WRAPPER,
149 CLKON_MISC,
150 RAM_ARB,
151 FTCH_HPS,
152 FTCH_DPS,
153 CLKON_HPS,
154 CLKON_DPS,
155 RX_HPS_CMDQS,
156 HPS_DPS_CMDQS,
157 DPS_TX_CMDQS,
158 RSRC_MNGR,
159 CTX_HANDLER,
160 ACK_MNGR,
161 D_DCPH,
162 H_DCPH,
163 CLKON_DCMP, /* IPA v4.5+ */
164 NTF_TX_CMDQS, /* IPA v3.5+ */
165 CLKON_TX_0, /* IPA v3.5+ */
166 CLKON_TX_1, /* IPA v3.5+ */
167 CLKON_FNR, /* IPA v3.5.1+ */
168 QSB2AXI_CMDQ_L, /* IPA v4.0+ */
169 AGGR_WRAPPER, /* IPA v4.0+ */
170 RAM_SLAVEWAY, /* IPA v4.0+ */
171 CLKON_QMB, /* IPA v4.0+ */
172 WEIGHT_ARB, /* IPA v4.0+ */
173 GSI_IF, /* IPA v4.0+ */
174 CLKON_GLOBAL, /* IPA v4.0+ */
175 GLOBAL_2X_CLK, /* IPA v4.0+ */
176 DPL_FIFO, /* IPA v4.5+ */
177 DRBIP, /* IPA v4.7+ */
178};
179
180/* ROUTE register */
181enum ipa_reg_route_field_id {
182 ROUTE_DIS,
183 ROUTE_DEF_PIPE,
184 ROUTE_DEF_HDR_TABLE,
185 ROUTE_DEF_HDR_OFST,
186 ROUTE_FRAG_DEF_PIPE,
187 ROUTE_DEF_RETAIN_HDR,
188};
189
190/* SHARED_MEM_SIZE register */
191enum ipa_reg_shared_mem_size_field_id {
192 MEM_SIZE,
193 MEM_BADDR,
194};
195
196/* QSB_MAX_WRITES register */
197enum ipa_reg_qsb_max_writes_field_id {
198 GEN_QMB_0_MAX_WRITES,
199 GEN_QMB_1_MAX_WRITES,
200};
201
202/* QSB_MAX_READS register */
203enum ipa_reg_qsb_max_reads_field_id {
204 GEN_QMB_0_MAX_READS,
205 GEN_QMB_1_MAX_READS,
206 GEN_QMB_0_MAX_READS_BEATS, /* IPA v4.0+ */
207 GEN_QMB_1_MAX_READS_BEATS, /* IPA v4.0+ */
208};
209
210/* FILT_ROUT_HASH_EN and FILT_ROUT_HASH_FLUSH registers */
211enum ipa_reg_filt_rout_hash_field_id {
212 IPV6_ROUTER_HASH,
213 IPV6_FILTER_HASH,
214 IPV4_ROUTER_HASH,
215 IPV4_FILTER_HASH,
216};
217
218/* FILT_ROUT_CACHE_FLUSH register */
219enum ipa_reg_filt_rout_cache_field_id {
220 ROUTER_CACHE,
221 FILTER_CACHE,
222};
223
224/* BCR register */
225enum ipa_bcr_compat {
226 BCR_CMDQ_L_LACK_ONE_ENTRY = 0x0, /* Not IPA v4.2+ */
227 BCR_TX_NOT_USING_BRESP = 0x1, /* Not IPA v4.2+ */
228 BCR_TX_SUSPEND_IRQ_ASSERT_ONCE = 0x2, /* Not IPA v4.0+ */
229 BCR_SUSPEND_L2_IRQ = 0x3, /* Not IPA v4.2+ */
230 BCR_HOLB_DROP_L2_IRQ = 0x4, /* Not IPA v4.2+ */
231 BCR_DUAL_TX = 0x5, /* IPA v3.5+ */
232 BCR_ENABLE_FILTER_DATA_CACHE = 0x6, /* IPA v3.5+ */
233 BCR_NOTIF_PRIORITY_OVER_ZLT = 0x7, /* IPA v3.5+ */
234 BCR_FILTER_PREFETCH_EN = 0x8, /* IPA v3.5+ */
235 BCR_ROUTER_PREFETCH_EN = 0x9, /* IPA v3.5+ */
236};
237
238/* LOCAL_PKT_PROC_CNTXT register */
239enum ipa_reg_local_pkt_proc_cntxt_field_id {
240 IPA_BASE_ADDR,
241};
242
243/* COUNTER_CFG register */
244enum ipa_reg_counter_cfg_field_id {
245 EOT_COAL_GRANULARITY, /* Not IPA v3.5+ */
246 AGGR_GRANULARITY,
247};
248
249/* IPA_TX_CFG register */
250enum ipa_reg_ipa_tx_cfg_field_id {
251 TX0_PREFETCH_DISABLE, /* Not IPA v4.0+ */
252 TX1_PREFETCH_DISABLE, /* Not IPA v4.0+ */
253 PREFETCH_ALMOST_EMPTY_SIZE, /* Not IPA v4.0+ */
254 PREFETCH_ALMOST_EMPTY_SIZE_TX0, /* IPA v4.0+ */
255 DMAW_SCND_OUTSD_PRED_THRESHOLD, /* IPA v4.0+ */
256 DMAW_SCND_OUTSD_PRED_EN, /* IPA v4.0+ */
257 DMAW_MAX_BEATS_256_DIS, /* IPA v4.0+ */
258 PA_MASK_EN, /* IPA v4.0+ */
259 PREFETCH_ALMOST_EMPTY_SIZE_TX1, /* IPA v4.0+ */
260 DUAL_TX_ENABLE, /* IPA v4.5+ */
261 SSPND_PA_NO_START_STATE, /* IPA v4,2+, not IPA v4.5 */
262 SSPND_PA_NO_BQ_STATE, /* IPA v4.2 only */
263 HOLB_STICKY_DROP_EN, /* IPA v5.0+ */
264};
265
266/* FLAVOR_0 register */
267enum ipa_reg_flavor_0_field_id {
268 MAX_PIPES,
269 MAX_CONS_PIPES,
270 MAX_PROD_PIPES,
271 PROD_LOWEST,
272};
273
274/* IDLE_INDICATION_CFG register */
275enum ipa_reg_idle_indication_cfg_field_id {
276 ENTER_IDLE_DEBOUNCE_THRESH,
277 CONST_NON_IDLE_ENABLE,
278};
279
280/* QTIME_TIMESTAMP_CFG register */
281enum ipa_reg_qtime_timestamp_cfg_field_id {
282 DPL_TIMESTAMP_LSB, /* Not IPA v5.5+ */
283 DPL_TIMESTAMP_SEL, /* Not IPA v5.5+ */
284 TAG_TIMESTAMP_LSB,
285 NAT_TIMESTAMP_LSB,
286};
287
288/* TIMERS_XO_CLK_DIV_CFG register */
289enum ipa_reg_timers_xo_clk_div_cfg_field_id {
290 DIV_VALUE,
291 DIV_ENABLE,
292};
293
294/* TIMERS_PULSE_GRAN_CFG register */
295enum ipa_reg_timers_pulse_gran_cfg_field_id {
296 PULSE_GRAN_0,
297 PULSE_GRAN_1,
298 PULSE_GRAN_2,
299 PULSE_GRAN_3,
300};
301
302/* Values for IPA_GRAN_x fields of TIMERS_PULSE_GRAN_CFG */
303enum ipa_pulse_gran {
304 IPA_GRAN_10_US = 0x0,
305 IPA_GRAN_20_US = 0x1,
306 IPA_GRAN_50_US = 0x2,
307 IPA_GRAN_100_US = 0x3,
308 IPA_GRAN_1_MS = 0x4,
309 IPA_GRAN_10_MS = 0x5,
310 IPA_GRAN_100_MS = 0x6,
311 IPA_GRAN_655350_US = 0x7,
312};
313
314/* {SRC,DST}_RSRC_GRP_{01,23,45,67}_RSRC_TYPE registers */
315enum ipa_reg_rsrc_grp_rsrc_type_field_id {
316 X_MIN_LIM,
317 X_MAX_LIM,
318 Y_MIN_LIM,
319 Y_MAX_LIM,
320};
321
322/* ENDP_INIT_CTRL register */
323enum ipa_reg_endp_init_ctrl_field_id {
324 ENDP_SUSPEND, /* Not IPA v4.0+ */
325 ENDP_DELAY, /* Not IPA v4.2+ */
326};
327
328/* ENDP_INIT_CFG register */
329enum ipa_reg_endp_init_cfg_field_id {
330 FRAG_OFFLOAD_EN,
331 CS_OFFLOAD_EN,
332 CS_METADATA_HDR_OFFSET,
333 CS_GEN_QMB_MASTER_SEL,
334 PIPE_REPLICATE_EN, /* IPA v5.5+ */
335};
336
337/** enum ipa_cs_offload_en - ENDP_INIT_CFG register CS_OFFLOAD_EN field value */
338enum ipa_cs_offload_en {
339 IPA_CS_OFFLOAD_NONE = 0x0,
340 IPA_CS_OFFLOAD_UL /* TX */ = 0x1, /* Not IPA v4.5+ */
341 IPA_CS_OFFLOAD_DL /* RX */ = 0x2, /* Not IPA v4.5+ */
342 IPA_CS_OFFLOAD_INLINE /* TX and RX */ = 0x1, /* IPA v4.5+ */
343};
344
345/* ENDP_INIT_NAT register */
346enum ipa_reg_endp_init_nat_field_id {
347 NAT_EN,
348};
349
350/** enum ipa_nat_type - ENDP_INIT_NAT register NAT_EN field value */
351enum ipa_nat_type {
352 IPA_NAT_TYPE_BYPASS = 0,
353 IPA_NAT_TYPE_SRC = 1,
354 IPA_NAT_TYPE_DST = 2,
355};
356
357/* ENDP_INIT_HDR register */
358enum ipa_reg_endp_init_hdr_field_id {
359 HDR_LEN,
360 HDR_OFST_METADATA_VALID,
361 HDR_OFST_METADATA,
362 HDR_ADDITIONAL_CONST_LEN,
363 HDR_OFST_PKT_SIZE_VALID,
364 HDR_OFST_PKT_SIZE,
365 HDR_A5_MUX, /* Not IPA v4.9+ */
366 HDR_LEN_INC_DEAGG_HDR,
367 HDR_METADATA_REG_VALID, /* Not IPA v4.5+ */
368 HDR_LEN_MSB, /* IPA v4.5+ */
369 HDR_OFST_METADATA_MSB, /* IPA v4.5+ */
370};
371
372/* ENDP_INIT_HDR_EXT register */
373enum ipa_reg_endp_init_hdr_ext_field_id {
374 HDR_ENDIANNESS,
375 HDR_TOTAL_LEN_OR_PAD_VALID,
376 HDR_TOTAL_LEN_OR_PAD,
377 HDR_PAYLOAD_LEN_INC_PADDING,
378 HDR_TOTAL_LEN_OR_PAD_OFFSET,
379 HDR_PAD_TO_ALIGNMENT,
380 HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB, /* IPA v4.5+ */
381 HDR_OFST_PKT_SIZE_MSB, /* IPA v4.5+ */
382 HDR_ADDITIONAL_CONST_LEN_MSB, /* IPA v4.5+ */
383 HDR_BYTES_TO_REMOVE_VALID, /* IPA v5.0+ */
384 HDR_BYTES_TO_REMOVE, /* IPA v5.0+ */
385};
386
387/* ENDP_INIT_MODE register */
388enum ipa_reg_endp_init_mode_field_id {
389 ENDP_MODE,
390 DCPH_ENABLE, /* IPA v4.5+ */
391 DEST_PIPE_INDEX,
392 BYTE_THRESHOLD,
393 PIPE_REPLICATION_EN, /* Not IPA v5.5+ */
394 PAD_EN,
395 HDR_FTCH_DISABLE, /* IPA v4.5+ */
396 DRBIP_ACL_ENABLE, /* IPA v4.9+ */
397};
398
399/** enum ipa_mode - ENDP_INIT_MODE register MODE field value */
400enum ipa_mode {
401 IPA_BASIC = 0x0,
402 IPA_ENABLE_FRAMING_HDLC = 0x1,
403 IPA_ENABLE_DEFRAMING_HDLC = 0x2,
404 IPA_DMA = 0x3,
405};
406
407/* ENDP_INIT_AGGR register */
408enum ipa_reg_endp_init_aggr_field_id {
409 AGGR_EN,
410 AGGR_TYPE,
411 BYTE_LIMIT,
412 TIME_LIMIT,
413 PKT_LIMIT,
414 SW_EOF_ACTIVE,
415 FORCE_CLOSE,
416 HARD_BYTE_LIMIT_EN,
417 AGGR_GRAN_SEL,
418 AGGR_COAL_L2, /* IPA v5.5+ */
419};
420
421/** enum ipa_aggr_en - ENDP_INIT_AGGR register AGGR_EN field value */
422enum ipa_aggr_en {
423 IPA_BYPASS_AGGR /* TX and RX */ = 0x0,
424 IPA_ENABLE_AGGR /* RX */ = 0x1,
425 IPA_ENABLE_DEAGGR /* TX */ = 0x2,
426};
427
428/** enum ipa_aggr_type - ENDP_INIT_AGGR register AGGR_TYPE field value */
429enum ipa_aggr_type {
430 IPA_MBIM_16 = 0x0,
431 IPA_HDLC = 0x1,
432 IPA_TLP = 0x2,
433 IPA_RNDIS = 0x3,
434 IPA_GENERIC = 0x4,
435 IPA_COALESCE = 0x5,
436 IPA_QCMAP = 0x6,
437};
438
439/* ENDP_INIT_HOL_BLOCK_EN register */
440enum ipa_reg_endp_init_hol_block_en_field_id {
441 HOL_BLOCK_EN,
442};
443
444/* ENDP_INIT_HOL_BLOCK_TIMER register */
445enum ipa_reg_endp_init_hol_block_timer_field_id {
446 TIMER_BASE_VALUE, /* Not IPA v4.5+ */
447 TIMER_SCALE, /* IPA v4.2 only */
448 TIMER_LIMIT, /* IPA v4.5+ */
449 TIMER_GRAN_SEL, /* IPA v4.5+ */
450};
451
452/* ENDP_INIT_DEAGGR register */
453enum ipa_reg_endp_deaggr_field_id {
454 DEAGGR_HDR_LEN,
455 SYSPIPE_ERR_DETECTION,
456 PACKET_OFFSET_VALID,
457 PACKET_OFFSET_LOCATION,
458 IGNORE_MIN_PKT_ERR,
459 MAX_PACKET_LEN,
460};
461
462/* ENDP_INIT_RSRC_GRP register */
463enum ipa_reg_endp_init_rsrc_grp_field_id {
464 ENDP_RSRC_GRP,
465};
466
467/* ENDP_INIT_SEQ register */
468enum ipa_reg_endp_init_seq_field_id {
469 SEQ_TYPE,
470 SEQ_REP_TYPE, /* Not IPA v4.5+ */
471};
472
473/**
474 * enum ipa_seq_type - HPS and DPS sequencer type
475 * @IPA_SEQ_DMA: Perform DMA only
476 * @IPA_SEQ_1_PASS: One pass through the pipeline
477 * @IPA_SEQ_2_PASS_SKIP_LAST_UC: Two passes, skip the microcprocessor
478 * @IPA_SEQ_1_PASS_SKIP_LAST_UC: One pass, skip the microcprocessor
479 * @IPA_SEQ_2_PASS: Two passes through the pipeline
480 * @IPA_SEQ_3_PASS_SKIP_LAST_UC: Three passes, skip the microcprocessor
481 * @IPA_SEQ_DECIPHER: Optional deciphering step (combined)
482 *
483 * The low-order byte of the sequencer type register defines the number of
484 * passes a packet takes through the IPA pipeline. The last pass through can
485 * optionally skip the microprocessor. Deciphering is optional for all types;
486 * if enabled, an additional mask (two bits) is added to the type value.
487 *
488 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are
489 * supported (or meaningful).
490 */
491enum ipa_seq_type {
492 IPA_SEQ_DMA = 0x00,
493 IPA_SEQ_1_PASS = 0x02,
494 IPA_SEQ_2_PASS_SKIP_LAST_UC = 0x04,
495 IPA_SEQ_1_PASS_SKIP_LAST_UC = 0x06,
496 IPA_SEQ_2_PASS = 0x0a,
497 IPA_SEQ_3_PASS_SKIP_LAST_UC = 0x0c,
498 /* The next value can be ORed with the above */
499 IPA_SEQ_DECIPHER = 0x11,
500};
501
502/**
503 * enum ipa_seq_rep_type - replicated packet sequencer type
504 * @IPA_SEQ_REP_DMA_PARSER: DMA parser for replicated packets
505 *
506 * This goes in the second byte of the endpoint sequencer type register.
507 *
508 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are
509 * supported (or meaningful).
510 */
511enum ipa_seq_rep_type {
512 IPA_SEQ_REP_DMA_PARSER = 0x08,
513};
514
515/* ENDP_STATUS register */
516enum ipa_reg_endp_status_field_id {
517 STATUS_EN,
518 STATUS_ENDP,
519 STATUS_LOCATION, /* Not IPA v4.5+ */
520 STATUS_PKT_SUPPRESS, /* IPA v4.0+ */
521};
522
523/* ENDP_FILTER_ROUTER_HSH_CFG register */
524enum ipa_reg_endp_filter_router_hsh_cfg_field_id {
525 FILTER_HASH_MSK_SRC_ID,
526 FILTER_HASH_MSK_SRC_IP,
527 FILTER_HASH_MSK_DST_IP,
528 FILTER_HASH_MSK_SRC_PORT,
529 FILTER_HASH_MSK_DST_PORT,
530 FILTER_HASH_MSK_PROTOCOL,
531 FILTER_HASH_MSK_METADATA,
532 FILTER_HASH_MSK_ALL, /* Bitwise OR of the above 6 fields */
533
534 ROUTER_HASH_MSK_SRC_ID,
535 ROUTER_HASH_MSK_SRC_IP,
536 ROUTER_HASH_MSK_DST_IP,
537 ROUTER_HASH_MSK_SRC_PORT,
538 ROUTER_HASH_MSK_DST_PORT,
539 ROUTER_HASH_MSK_PROTOCOL,
540 ROUTER_HASH_MSK_METADATA,
541 ROUTER_HASH_MSK_ALL, /* Bitwise OR of the above 6 fields */
542};
543
544/* ENDP_FILTER_CACHE_CFG and ENDP_ROUTER_CACHE_CFG registers */
545enum ipa_reg_endp_cache_cfg_field_id {
546 CACHE_MSK_SRC_ID,
547 CACHE_MSK_SRC_IP,
548 CACHE_MSK_DST_IP,
549 CACHE_MSK_SRC_PORT,
550 CACHE_MSK_DST_PORT,
551 CACHE_MSK_PROTOCOL,
552 CACHE_MSK_METADATA,
553};
554
555/* IPA_IRQ_STTS, IPA_IRQ_EN, and IPA_IRQ_CLR registers */
556/**
557 * enum ipa_irq_id - Bit positions representing type of IPA IRQ
558 * @IPA_IRQ_UC_0: Microcontroller event interrupt
559 * @IPA_IRQ_UC_1: Microcontroller response interrupt
560 * @IPA_IRQ_TX_SUSPEND: Data ready interrupt
561 * @IPA_IRQ_COUNT: Number of IRQ ids (must be last)
562 *
563 * IRQ types not described above are not currently used.
564 *
565 * @IPA_IRQ_BAD_SNOC_ACCESS: (Not currently used)
566 * @IPA_IRQ_EOT_COAL: (Not currently used)
567 * @IPA_IRQ_UC_2: (Not currently used)
568 * @IPA_IRQ_UC_3: (Not currently used)
569 * @IPA_IRQ_UC_IN_Q_NOT_EMPTY: (Not currently used)
570 * @IPA_IRQ_UC_RX_CMD_Q_NOT_FULL: (Not currently used)
571 * @IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY: (Not currently used)
572 * @IPA_IRQ_RX_ERR: (Not currently used)
573 * @IPA_IRQ_DEAGGR_ERR: (Not currently used)
574 * @IPA_IRQ_TX_ERR: (Not currently used)
575 * @IPA_IRQ_STEP_MODE: (Not currently used)
576 * @IPA_IRQ_PROC_ERR: (Not currently used)
577 * @IPA_IRQ_TX_HOLB_DROP: (Not currently used)
578 * @IPA_IRQ_BAM_GSI_IDLE: (Not currently used)
579 * @IPA_IRQ_PIPE_YELLOW_BELOW: (Not currently used)
580 * @IPA_IRQ_PIPE_RED_BELOW: (Not currently used)
581 * @IPA_IRQ_PIPE_YELLOW_ABOVE: (Not currently used)
582 * @IPA_IRQ_PIPE_RED_ABOVE: (Not currently used)
583 * @IPA_IRQ_UCP: (Not currently used)
584 * @IPA_IRQ_DCMP: (Not currently used)
585 * @IPA_IRQ_GSI_EE: (Not currently used)
586 * @IPA_IRQ_GSI_IPA_IF_TLV_RCVD: (Not currently used)
587 * @IPA_IRQ_GSI_UC: (Not currently used)
588 * @IPA_IRQ_TLV_LEN_MIN_DSM: (Not currently used)
589 * @IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN: (Not currently used)
590 * @IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN: (Not currently used)
591 * @IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN: (Not currently used)
592 * @IPA_IRQ_ERROR_NON_FATAL: (Not currently used)
593 * @IPA_IRQ_ERROR_FATAL: (Not currently used)
594 */
595enum ipa_irq_id {
596 IPA_IRQ_BAD_SNOC_ACCESS = 0x0, /* Not IPA v5.5+ */
597 IPA_IRQ_EOT_COAL = 0x1, /* Not IPA v3.5+ */
598 IPA_IRQ_UC_0 = 0x2,
599 IPA_IRQ_UC_1 = 0x3,
600 IPA_IRQ_UC_2 = 0x4,
601 IPA_IRQ_UC_3 = 0x5,
602 IPA_IRQ_UC_IN_Q_NOT_EMPTY = 0x6,
603 IPA_IRQ_UC_RX_CMD_Q_NOT_FULL = 0x7,
604 IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY = 0x8,
605 IPA_IRQ_RX_ERR = 0x9, /* Not IPA v5.5+ */
606 IPA_IRQ_DEAGGR_ERR = 0xa, /* Not IPA v5.5+ */
607 IPA_IRQ_TX_ERR = 0xb, /* Not IPA v5.5+ */
608 IPA_IRQ_STEP_MODE = 0xc, /* Not IPA v5.5+ */
609 IPA_IRQ_PROC_ERR = 0xd, /* Not IPA v5.5+ */
610 IPA_IRQ_TX_SUSPEND = 0xe,
611 IPA_IRQ_TX_HOLB_DROP = 0xf,
612 IPA_IRQ_BAM_GSI_IDLE = 0x10,
613 IPA_IRQ_PIPE_YELLOW_BELOW = 0x11,
614 IPA_IRQ_PIPE_RED_BELOW = 0x12,
615 IPA_IRQ_PIPE_YELLOW_ABOVE = 0x13,
616 IPA_IRQ_PIPE_RED_ABOVE = 0x14,
617 IPA_IRQ_UCP = 0x15,
618 IPA_IRQ_DCMP = 0x16, /* Not IPA v4.5+ */
619 IPA_IRQ_GSI_EE = 0x17,
620 IPA_IRQ_GSI_IPA_IF_TLV_RCVD = 0x18,
621 IPA_IRQ_GSI_UC = 0x19,
622 IPA_IRQ_TLV_LEN_MIN_DSM = 0x1a, /* IPA v4.5-v5.2 */
623 IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN = 0x1b, /* IPA v4.9-v5.2 */
624 IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN = 0x1c, /* IPA v4.9-v5.2 */
625 IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN = 0x1d, /* IPA v4.9-v5.2 */
626 IPA_IRQ_ERROR_NON_FATAL = 0x1e, /* IPA v5.5+ */
627 IPA_IRQ_ERROR_FATAL = 0x1f, /* IPA v5.5+ */
628 IPA_IRQ_COUNT, /* Last; not an id */
629};
630
631/* IPA_IRQ_UC register */
632enum ipa_reg_ipa_irq_uc_field_id {
633 UC_INTR,
634};
635
636extern const struct regs ipa_regs_v3_1;
637extern const struct regs ipa_regs_v3_5_1;
638extern const struct regs ipa_regs_v4_2;
639extern const struct regs ipa_regs_v4_5;
640extern const struct regs ipa_regs_v4_7;
641extern const struct regs ipa_regs_v4_9;
642extern const struct regs ipa_regs_v4_11;
643extern const struct regs ipa_regs_v5_0;
644extern const struct regs ipa_regs_v5_5;
645
646const struct reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id);
647
648int ipa_reg_init(struct ipa *ipa, struct platform_device *pdev);
649void ipa_reg_exit(struct ipa *ipa);
650
651#endif /* _IPA_REG_H_ */
652

source code of linux/drivers/net/ipa/ipa_reg.h