1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (C) 2022 Linaro Ltd. */
4
5#include <linux/types.h>
6
7#include "../ipa.h"
8#include "../ipa_reg.h"
9
10static const u32 reg_comp_cfg_fmask[] = {
11 [COMP_CFG_ENABLE] = BIT(0),
12 [GSI_SNOC_BYPASS_DIS] = BIT(1),
13 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
14 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
15 [IPA_DCMP_FAST_CLK_EN] = BIT(4),
16 /* Bits 5-31 reserved */
17};
18
19REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
20
21static const u32 reg_clkon_cfg_fmask[] = {
22 [CLKON_RX] = BIT(0),
23 [CLKON_PROC] = BIT(1),
24 [TX_WRAPPER] = BIT(2),
25 [CLKON_MISC] = BIT(3),
26 [RAM_ARB] = BIT(4),
27 [FTCH_HPS] = BIT(5),
28 [FTCH_DPS] = BIT(6),
29 [CLKON_HPS] = BIT(7),
30 [CLKON_DPS] = BIT(8),
31 [RX_HPS_CMDQS] = BIT(9),
32 [HPS_DPS_CMDQS] = BIT(10),
33 [DPS_TX_CMDQS] = BIT(11),
34 [RSRC_MNGR] = BIT(12),
35 [CTX_HANDLER] = BIT(13),
36 [ACK_MNGR] = BIT(14),
37 [D_DCPH] = BIT(15),
38 [H_DCPH] = BIT(16),
39 /* Bits 17-31 reserved */
40};
41
42REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
43
44static const u32 reg_route_fmask[] = {
45 [ROUTE_DIS] = BIT(0),
46 [ROUTE_DEF_PIPE] = GENMASK(5, 1),
47 [ROUTE_DEF_HDR_TABLE] = BIT(6),
48 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
49 [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),
50 /* Bits 22-23 reserved */
51 [ROUTE_DEF_RETAIN_HDR] = BIT(24),
52 /* Bits 25-31 reserved */
53};
54
55REG_FIELDS(ROUTE, route, 0x00000048);
56
57static const u32 reg_shared_mem_size_fmask[] = {
58 [MEM_SIZE] = GENMASK(15, 0),
59 [MEM_BADDR] = GENMASK(31, 16),
60};
61
62REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
63
64static const u32 reg_qsb_max_writes_fmask[] = {
65 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
66 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
67 /* Bits 8-31 reserved */
68};
69
70REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
71
72static const u32 reg_qsb_max_reads_fmask[] = {
73 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
74 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
75};
76
77REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
78
79static const u32 reg_filt_rout_hash_en_fmask[] = {
80 [IPV6_ROUTER_HASH] = BIT(0),
81 /* Bits 1-3 reserved */
82 [IPV6_FILTER_HASH] = BIT(4),
83 /* Bits 5-7 reserved */
84 [IPV4_ROUTER_HASH] = BIT(8),
85 /* Bits 9-11 reserved */
86 [IPV4_FILTER_HASH] = BIT(12),
87 /* Bits 13-31 reserved */
88};
89
90REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x000008c);
91
92static const u32 reg_filt_rout_hash_flush_fmask[] = {
93 [IPV6_ROUTER_HASH] = BIT(0),
94 /* Bits 1-3 reserved */
95 [IPV6_FILTER_HASH] = BIT(4),
96 /* Bits 5-7 reserved */
97 [IPV4_ROUTER_HASH] = BIT(8),
98 /* Bits 9-11 reserved */
99 [IPV4_FILTER_HASH] = BIT(12),
100 /* Bits 13-31 reserved */
101};
102
103REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090);
104
105/* Valid bits defined by ipa->available */
106REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c, 0x0004);
107
108REG(IPA_BCR, ipa_bcr, 0x000001d0);
109
110static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
111 [IPA_BASE_ADDR] = GENMASK(16, 0),
112 /* Bits 17-31 reserved */
113};
114
115/* Offset must be a multiple of 8 */
116REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
117
118/* Valid bits defined by ipa->available */
119REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
120
121static const u32 reg_counter_cfg_fmask[] = {
122 [EOT_COAL_GRANULARITY] = GENMASK(3, 0),
123 [AGGR_GRANULARITY] = GENMASK(8, 4),
124 /* Bits 5-31 reserved */
125};
126
127REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);
128
129static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
130 [X_MIN_LIM] = GENMASK(7, 0),
131 [X_MAX_LIM] = GENMASK(15, 8),
132 [Y_MIN_LIM] = GENMASK(23, 16),
133 [Y_MAX_LIM] = GENMASK(31, 24),
134};
135
136REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
137 0x00000400, 0x0020);
138
139static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
140 [X_MIN_LIM] = GENMASK(7, 0),
141 [X_MAX_LIM] = GENMASK(15, 8),
142 [Y_MIN_LIM] = GENMASK(23, 16),
143 [Y_MAX_LIM] = GENMASK(31, 24),
144};
145
146REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
147 0x00000404, 0x0020);
148
149static const u32 reg_src_rsrc_grp_45_rsrc_type_fmask[] = {
150 [X_MIN_LIM] = GENMASK(7, 0),
151 [X_MAX_LIM] = GENMASK(15, 8),
152 [Y_MIN_LIM] = GENMASK(23, 16),
153 [Y_MAX_LIM] = GENMASK(31, 24),
154};
155
156REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type,
157 0x00000408, 0x0020);
158
159static const u32 reg_src_rsrc_grp_67_rsrc_type_fmask[] = {
160 [X_MIN_LIM] = GENMASK(7, 0),
161 [X_MAX_LIM] = GENMASK(15, 8),
162 [Y_MIN_LIM] = GENMASK(23, 16),
163 [Y_MAX_LIM] = GENMASK(31, 24),
164};
165
166REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type,
167 0x0000040c, 0x0020);
168
169static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
170 [X_MIN_LIM] = GENMASK(7, 0),
171 [X_MAX_LIM] = GENMASK(15, 8),
172 [Y_MIN_LIM] = GENMASK(23, 16),
173 [Y_MAX_LIM] = GENMASK(31, 24),
174};
175
176REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
177 0x00000500, 0x0020);
178
179static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
180 [X_MIN_LIM] = GENMASK(7, 0),
181 [X_MAX_LIM] = GENMASK(15, 8),
182 [Y_MIN_LIM] = GENMASK(23, 16),
183 [Y_MAX_LIM] = GENMASK(31, 24),
184};
185
186REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
187 0x00000504, 0x0020);
188
189static const u32 reg_dst_rsrc_grp_45_rsrc_type_fmask[] = {
190 [X_MIN_LIM] = GENMASK(7, 0),
191 [X_MAX_LIM] = GENMASK(15, 8),
192 [Y_MIN_LIM] = GENMASK(23, 16),
193 [Y_MAX_LIM] = GENMASK(31, 24),
194};
195
196REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type,
197 0x00000508, 0x0020);
198
199static const u32 reg_dst_rsrc_grp_67_rsrc_type_fmask[] = {
200 [X_MIN_LIM] = GENMASK(7, 0),
201 [X_MAX_LIM] = GENMASK(15, 8),
202 [Y_MIN_LIM] = GENMASK(23, 16),
203 [Y_MAX_LIM] = GENMASK(31, 24),
204};
205
206REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type,
207 0x0000050c, 0x0020);
208
209static const u32 reg_endp_init_ctrl_fmask[] = {
210 [ENDP_SUSPEND] = BIT(0),
211 [ENDP_DELAY] = BIT(1),
212 /* Bits 2-31 reserved */
213};
214
215REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070);
216
217static const u32 reg_endp_init_cfg_fmask[] = {
218 [FRAG_OFFLOAD_EN] = BIT(0),
219 [CS_OFFLOAD_EN] = GENMASK(2, 1),
220 [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
221 /* Bit 7 reserved */
222 [CS_GEN_QMB_MASTER_SEL] = BIT(8),
223 /* Bits 9-31 reserved */
224};
225
226REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
227
228static const u32 reg_endp_init_nat_fmask[] = {
229 [NAT_EN] = GENMASK(1, 0),
230 /* Bits 2-31 reserved */
231};
232
233REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
234
235static const u32 reg_endp_init_hdr_fmask[] = {
236 [HDR_LEN] = GENMASK(5, 0),
237 [HDR_OFST_METADATA_VALID] = BIT(6),
238 [HDR_OFST_METADATA] = GENMASK(12, 7),
239 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
240 [HDR_OFST_PKT_SIZE_VALID] = BIT(19),
241 [HDR_OFST_PKT_SIZE] = GENMASK(25, 20),
242 [HDR_A5_MUX] = BIT(26),
243 [HDR_LEN_INC_DEAGG_HDR] = BIT(27),
244 [HDR_METADATA_REG_VALID] = BIT(28),
245 /* Bits 29-31 reserved */
246};
247
248REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
249
250static const u32 reg_endp_init_hdr_ext_fmask[] = {
251 [HDR_ENDIANNESS] = BIT(0),
252 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
253 [HDR_TOTAL_LEN_OR_PAD] = BIT(2),
254 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
255 [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),
256 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
257 /* Bits 14-31 reserved */
258};
259
260REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
261
262REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
263 0x00000818, 0x0070);
264
265static const u32 reg_endp_init_mode_fmask[] = {
266 [ENDP_MODE] = GENMASK(2, 0),
267 /* Bit 3 reserved */
268 [DEST_PIPE_INDEX] = GENMASK(8, 4),
269 /* Bits 9-11 reserved */
270 [BYTE_THRESHOLD] = GENMASK(27, 12),
271 [PIPE_REPLICATION_EN] = BIT(28),
272 [PAD_EN] = BIT(29),
273 [HDR_FTCH_DISABLE] = BIT(30),
274 /* Bit 31 reserved */
275};
276
277REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
278
279static const u32 reg_endp_init_aggr_fmask[] = {
280 [AGGR_EN] = GENMASK(1, 0),
281 [AGGR_TYPE] = GENMASK(4, 2),
282 [BYTE_LIMIT] = GENMASK(9, 5),
283 [TIME_LIMIT] = GENMASK(14, 10),
284 [PKT_LIMIT] = GENMASK(20, 15),
285 [SW_EOF_ACTIVE] = BIT(21),
286 [FORCE_CLOSE] = BIT(22),
287 /* Bit 23 reserved */
288 [HARD_BYTE_LIMIT_EN] = BIT(24),
289 /* Bits 25-31 reserved */
290};
291
292REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
293
294static const u32 reg_endp_init_hol_block_en_fmask[] = {
295 [HOL_BLOCK_EN] = BIT(0),
296 /* Bits 1-31 reserved */
297};
298
299REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
300 0x0000082c, 0x0070);
301
302/* Entire register is a tick count */
303static const u32 reg_endp_init_hol_block_timer_fmask[] = {
304 [TIMER_BASE_VALUE] = GENMASK(31, 0),
305};
306
307REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
308 0x00000830, 0x0070);
309
310static const u32 reg_endp_init_deaggr_fmask[] = {
311 [DEAGGR_HDR_LEN] = GENMASK(5, 0),
312 [SYSPIPE_ERR_DETECTION] = BIT(6),
313 [PACKET_OFFSET_VALID] = BIT(7),
314 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8),
315 [IGNORE_MIN_PKT_ERR] = BIT(14),
316 /* Bit 15 reserved */
317 [MAX_PACKET_LEN] = GENMASK(31, 16),
318};
319
320REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
321
322static const u32 reg_endp_init_rsrc_grp_fmask[] = {
323 [ENDP_RSRC_GRP] = GENMASK(2, 0),
324 /* Bits 3-31 reserved */
325};
326
327REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
328
329static const u32 reg_endp_init_seq_fmask[] = {
330 [SEQ_TYPE] = GENMASK(7, 0),
331 [SEQ_REP_TYPE] = GENMASK(15, 8),
332 /* Bits 16-31 reserved */
333};
334
335REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
336
337static const u32 reg_endp_status_fmask[] = {
338 [STATUS_EN] = BIT(0),
339 [STATUS_ENDP] = GENMASK(5, 1),
340 /* Bits 6-7 reserved */
341 [STATUS_LOCATION] = BIT(8),
342 /* Bits 9-31 reserved */
343};
344
345REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
346
347static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = {
348 [FILTER_HASH_MSK_SRC_ID] = BIT(0),
349 [FILTER_HASH_MSK_SRC_IP] = BIT(1),
350 [FILTER_HASH_MSK_DST_IP] = BIT(2),
351 [FILTER_HASH_MSK_SRC_PORT] = BIT(3),
352 [FILTER_HASH_MSK_DST_PORT] = BIT(4),
353 [FILTER_HASH_MSK_PROTOCOL] = BIT(5),
354 [FILTER_HASH_MSK_METADATA] = BIT(6),
355 [FILTER_HASH_MSK_ALL] = GENMASK(6, 0),
356 /* Bits 7-15 reserved */
357 [ROUTER_HASH_MSK_SRC_ID] = BIT(16),
358 [ROUTER_HASH_MSK_SRC_IP] = BIT(17),
359 [ROUTER_HASH_MSK_DST_IP] = BIT(18),
360 [ROUTER_HASH_MSK_SRC_PORT] = BIT(19),
361 [ROUTER_HASH_MSK_DST_PORT] = BIT(20),
362 [ROUTER_HASH_MSK_PROTOCOL] = BIT(21),
363 [ROUTER_HASH_MSK_METADATA] = BIT(22),
364 [ROUTER_HASH_MSK_ALL] = GENMASK(22, 16),
365 /* Bits 23-31 reserved */
366};
367
368REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,
369 0x0000085c, 0x0070);
370
371/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
372REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
373
374/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
375REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
376
377/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
378REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
379
380static const u32 reg_ipa_irq_uc_fmask[] = {
381 [UC_INTR] = BIT(0),
382 /* Bits 1-31 reserved */
383};
384
385REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
386
387/* Valid bits defined by ipa->available */
388REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
389 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
390
391/* Valid bits defined by ipa->available */
392REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
393 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
394
395/* Valid bits defined by ipa->available */
396REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
397 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);
398
399static const struct reg *reg_array[] = {
400 [COMP_CFG] = &reg_comp_cfg,
401 [CLKON_CFG] = &reg_clkon_cfg,
402 [ROUTE] = &reg_route,
403 [SHARED_MEM_SIZE] = &reg_shared_mem_size,
404 [QSB_MAX_WRITES] = &reg_qsb_max_writes,
405 [QSB_MAX_READS] = &reg_qsb_max_reads,
406 [FILT_ROUT_HASH_EN] = &reg_filt_rout_hash_en,
407 [FILT_ROUT_HASH_FLUSH] = &reg_filt_rout_hash_flush,
408 [STATE_AGGR_ACTIVE] = &reg_state_aggr_active,
409 [IPA_BCR] = &reg_ipa_bcr,
410 [LOCAL_PKT_PROC_CNTXT] = &reg_local_pkt_proc_cntxt,
411 [AGGR_FORCE_CLOSE] = &reg_aggr_force_close,
412 [COUNTER_CFG] = &reg_counter_cfg,
413 [SRC_RSRC_GRP_01_RSRC_TYPE] = &reg_src_rsrc_grp_01_rsrc_type,
414 [SRC_RSRC_GRP_23_RSRC_TYPE] = &reg_src_rsrc_grp_23_rsrc_type,
415 [SRC_RSRC_GRP_45_RSRC_TYPE] = &reg_src_rsrc_grp_45_rsrc_type,
416 [SRC_RSRC_GRP_67_RSRC_TYPE] = &reg_src_rsrc_grp_67_rsrc_type,
417 [DST_RSRC_GRP_01_RSRC_TYPE] = &reg_dst_rsrc_grp_01_rsrc_type,
418 [DST_RSRC_GRP_23_RSRC_TYPE] = &reg_dst_rsrc_grp_23_rsrc_type,
419 [DST_RSRC_GRP_45_RSRC_TYPE] = &reg_dst_rsrc_grp_45_rsrc_type,
420 [DST_RSRC_GRP_67_RSRC_TYPE] = &reg_dst_rsrc_grp_67_rsrc_type,
421 [ENDP_INIT_CTRL] = &reg_endp_init_ctrl,
422 [ENDP_INIT_CFG] = &reg_endp_init_cfg,
423 [ENDP_INIT_NAT] = &reg_endp_init_nat,
424 [ENDP_INIT_HDR] = &reg_endp_init_hdr,
425 [ENDP_INIT_HDR_EXT] = &reg_endp_init_hdr_ext,
426 [ENDP_INIT_HDR_METADATA_MASK] = &reg_endp_init_hdr_metadata_mask,
427 [ENDP_INIT_MODE] = &reg_endp_init_mode,
428 [ENDP_INIT_AGGR] = &reg_endp_init_aggr,
429 [ENDP_INIT_HOL_BLOCK_EN] = &reg_endp_init_hol_block_en,
430 [ENDP_INIT_HOL_BLOCK_TIMER] = &reg_endp_init_hol_block_timer,
431 [ENDP_INIT_DEAGGR] = &reg_endp_init_deaggr,
432 [ENDP_INIT_RSRC_GRP] = &reg_endp_init_rsrc_grp,
433 [ENDP_INIT_SEQ] = &reg_endp_init_seq,
434 [ENDP_STATUS] = &reg_endp_status,
435 [ENDP_FILTER_ROUTER_HSH_CFG] = &reg_endp_filter_router_hsh_cfg,
436 [IPA_IRQ_STTS] = &reg_ipa_irq_stts,
437 [IPA_IRQ_EN] = &reg_ipa_irq_en,
438 [IPA_IRQ_CLR] = &reg_ipa_irq_clr,
439 [IPA_IRQ_UC] = &reg_ipa_irq_uc,
440 [IRQ_SUSPEND_INFO] = &reg_irq_suspend_info,
441 [IRQ_SUSPEND_EN] = &reg_irq_suspend_en,
442 [IRQ_SUSPEND_CLR] = &reg_irq_suspend_clr,
443};
444
445const struct regs ipa_regs_v3_1 = {
446 .reg_count = ARRAY_SIZE(reg_array),
447 .reg = reg_array,
448};
449

source code of linux/drivers/net/ipa/reg/ipa_reg-v3.1.c