1 | // SPDX-License-Identifier: GPL-2.0 |
2 | |
3 | /* Copyright (C) 2022 Linaro Ltd. */ |
4 | |
5 | #include <linux/types.h> |
6 | |
7 | #include "../ipa.h" |
8 | #include "../ipa_reg.h" |
9 | |
10 | static const u32 reg_comp_cfg_fmask[] = { |
11 | /* Bit 0 reserved */ |
12 | [GSI_SNOC_BYPASS_DIS] = BIT(1), |
13 | [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), |
14 | [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), |
15 | [IPA_DCMP_FAST_CLK_EN] = BIT(4), |
16 | [IPA_QMB_SELECT_CONS_EN] = BIT(5), |
17 | [IPA_QMB_SELECT_PROD_EN] = BIT(6), |
18 | [GSI_MULTI_INORDER_RD_DIS] = BIT(7), |
19 | [GSI_MULTI_INORDER_WR_DIS] = BIT(8), |
20 | [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9), |
21 | [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10), |
22 | [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11), |
23 | [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12), |
24 | [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13), |
25 | [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14), |
26 | [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15), |
27 | [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16), |
28 | [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(20, 17), |
29 | /* Bits 21-31 reserved */ |
30 | }; |
31 | |
32 | REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); |
33 | |
34 | static const u32 reg_clkon_cfg_fmask[] = { |
35 | [CLKON_RX] = BIT(0), |
36 | [CLKON_PROC] = BIT(1), |
37 | [TX_WRAPPER] = BIT(2), |
38 | [CLKON_MISC] = BIT(3), |
39 | [RAM_ARB] = BIT(4), |
40 | [FTCH_HPS] = BIT(5), |
41 | [FTCH_DPS] = BIT(6), |
42 | [CLKON_HPS] = BIT(7), |
43 | [CLKON_DPS] = BIT(8), |
44 | [RX_HPS_CMDQS] = BIT(9), |
45 | [HPS_DPS_CMDQS] = BIT(10), |
46 | [DPS_TX_CMDQS] = BIT(11), |
47 | [RSRC_MNGR] = BIT(12), |
48 | [CTX_HANDLER] = BIT(13), |
49 | [ACK_MNGR] = BIT(14), |
50 | [D_DCPH] = BIT(15), |
51 | [H_DCPH] = BIT(16), |
52 | /* Bit 17 reserved */ |
53 | [NTF_TX_CMDQS] = BIT(18), |
54 | [CLKON_TX_0] = BIT(19), |
55 | [CLKON_TX_1] = BIT(20), |
56 | [CLKON_FNR] = BIT(21), |
57 | [QSB2AXI_CMDQ_L] = BIT(22), |
58 | [AGGR_WRAPPER] = BIT(23), |
59 | [RAM_SLAVEWAY] = BIT(24), |
60 | [CLKON_QMB] = BIT(25), |
61 | [WEIGHT_ARB] = BIT(26), |
62 | [GSI_IF] = BIT(27), |
63 | [CLKON_GLOBAL] = BIT(28), |
64 | [GLOBAL_2X_CLK] = BIT(29), |
65 | /* Bits 30-31 reserved */ |
66 | }; |
67 | |
68 | REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); |
69 | |
70 | static const u32 reg_route_fmask[] = { |
71 | [ROUTE_DIS] = BIT(0), |
72 | [ROUTE_DEF_PIPE] = GENMASK(5, 1), |
73 | [ROUTE_DEF_HDR_TABLE] = BIT(6), |
74 | [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7), |
75 | [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17), |
76 | /* Bits 22-23 reserved */ |
77 | [ROUTE_DEF_RETAIN_HDR] = BIT(24), |
78 | /* Bits 25-31 reserved */ |
79 | }; |
80 | |
81 | REG_FIELDS(ROUTE, route, 0x00000048); |
82 | |
83 | static const u32 reg_shared_mem_size_fmask[] = { |
84 | [MEM_SIZE] = GENMASK(15, 0), |
85 | [MEM_BADDR] = GENMASK(31, 16), |
86 | }; |
87 | |
88 | REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); |
89 | |
90 | static const u32 reg_qsb_max_writes_fmask[] = { |
91 | [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), |
92 | [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), |
93 | /* Bits 8-31 reserved */ |
94 | }; |
95 | |
96 | REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); |
97 | |
98 | static const u32 reg_qsb_max_reads_fmask[] = { |
99 | [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), |
100 | [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), |
101 | /* Bits 8-15 reserved */ |
102 | [GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16), |
103 | [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24), |
104 | }; |
105 | |
106 | REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); |
107 | |
108 | static const u32 reg_filt_rout_hash_en_fmask[] = { |
109 | [IPV6_ROUTER_HASH] = BIT(0), |
110 | /* Bits 1-3 reserved */ |
111 | [IPV6_FILTER_HASH] = BIT(4), |
112 | /* Bits 5-7 reserved */ |
113 | [IPV4_ROUTER_HASH] = BIT(8), |
114 | /* Bits 9-11 reserved */ |
115 | [IPV4_FILTER_HASH] = BIT(12), |
116 | /* Bits 13-31 reserved */ |
117 | }; |
118 | |
119 | REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148); |
120 | |
121 | static const u32 reg_filt_rout_hash_flush_fmask[] = { |
122 | [IPV6_ROUTER_HASH] = BIT(0), |
123 | /* Bits 1-3 reserved */ |
124 | [IPV6_FILTER_HASH] = BIT(4), |
125 | /* Bits 5-7 reserved */ |
126 | [IPV4_ROUTER_HASH] = BIT(8), |
127 | /* Bits 9-11 reserved */ |
128 | [IPV4_FILTER_HASH] = BIT(12), |
129 | /* Bits 13-31 reserved */ |
130 | }; |
131 | |
132 | REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c); |
133 | |
134 | /* Valid bits defined by ipa->available */ |
135 | REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004); |
136 | |
137 | REG(IPA_BCR, ipa_bcr, 0x000001d0); |
138 | |
139 | static const u32 reg_local_pkt_proc_cntxt_fmask[] = { |
140 | [IPA_BASE_ADDR] = GENMASK(16, 0), |
141 | /* Bits 17-31 reserved */ |
142 | }; |
143 | |
144 | /* Offset must be a multiple of 8 */ |
145 | REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); |
146 | |
147 | /* Valid bits defined by ipa->available */ |
148 | REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004); |
149 | |
150 | static const u32 reg_counter_cfg_fmask[] = { |
151 | /* Bits 0-3 reserved */ |
152 | [AGGR_GRANULARITY] = GENMASK(8, 4), |
153 | /* Bits 9-31 reserved */ |
154 | }; |
155 | |
156 | REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0); |
157 | |
158 | static const u32 reg_ipa_tx_cfg_fmask[] = { |
159 | /* Bits 0-1 reserved */ |
160 | [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2), |
161 | [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6), |
162 | [DMAW_SCND_OUTSD_PRED_EN] = BIT(10), |
163 | [DMAW_MAX_BEATS_256_DIS] = BIT(11), |
164 | [PA_MASK_EN] = BIT(12), |
165 | [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13), |
166 | /* Bit 17 reserved */ |
167 | [SSPND_PA_NO_START_STATE] = BIT(18), |
168 | [SSPND_PA_NO_BQ_STATE] = BIT(19), |
169 | /* Bits 20-31 reserved */ |
170 | }; |
171 | |
172 | REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); |
173 | |
174 | static const u32 reg_flavor_0_fmask[] = { |
175 | [MAX_PIPES] = GENMASK(3, 0), |
176 | /* Bits 4-7 reserved */ |
177 | [MAX_CONS_PIPES] = GENMASK(12, 8), |
178 | /* Bits 13-15 reserved */ |
179 | [MAX_PROD_PIPES] = GENMASK(20, 16), |
180 | /* Bits 21-23 reserved */ |
181 | [PROD_LOWEST] = GENMASK(27, 24), |
182 | /* Bits 28-31 reserved */ |
183 | }; |
184 | |
185 | REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); |
186 | |
187 | static const u32 reg_idle_indication_cfg_fmask[] = { |
188 | [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), |
189 | [CONST_NON_IDLE_ENABLE] = BIT(16), |
190 | /* Bits 17-31 reserved */ |
191 | }; |
192 | |
193 | REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240); |
194 | |
195 | static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = { |
196 | [X_MIN_LIM] = GENMASK(5, 0), |
197 | /* Bits 6-7 reserved */ |
198 | [X_MAX_LIM] = GENMASK(13, 8), |
199 | /* Bits 14-15 reserved */ |
200 | [Y_MIN_LIM] = GENMASK(21, 16), |
201 | /* Bits 22-23 reserved */ |
202 | [Y_MAX_LIM] = GENMASK(29, 24), |
203 | /* Bits 30-31 reserved */ |
204 | }; |
205 | |
206 | REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, |
207 | 0x00000400, 0x0020); |
208 | |
209 | static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = { |
210 | [X_MIN_LIM] = GENMASK(5, 0), |
211 | /* Bits 6-7 reserved */ |
212 | [X_MAX_LIM] = GENMASK(13, 8), |
213 | /* Bits 14-15 reserved */ |
214 | [Y_MIN_LIM] = GENMASK(21, 16), |
215 | /* Bits 22-23 reserved */ |
216 | [Y_MAX_LIM] = GENMASK(29, 24), |
217 | /* Bits 30-31 reserved */ |
218 | }; |
219 | |
220 | REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, |
221 | 0x00000404, 0x0020); |
222 | |
223 | static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { |
224 | [X_MIN_LIM] = GENMASK(5, 0), |
225 | /* Bits 6-7 reserved */ |
226 | [X_MAX_LIM] = GENMASK(13, 8), |
227 | /* Bits 14-15 reserved */ |
228 | [Y_MIN_LIM] = GENMASK(21, 16), |
229 | /* Bits 22-23 reserved */ |
230 | [Y_MAX_LIM] = GENMASK(29, 24), |
231 | /* Bits 30-31 reserved */ |
232 | }; |
233 | |
234 | REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, |
235 | 0x00000500, 0x0020); |
236 | |
237 | static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { |
238 | [X_MIN_LIM] = GENMASK(5, 0), |
239 | /* Bits 6-7 reserved */ |
240 | [X_MAX_LIM] = GENMASK(13, 8), |
241 | /* Bits 14-15 reserved */ |
242 | [Y_MIN_LIM] = GENMASK(21, 16), |
243 | /* Bits 22-23 reserved */ |
244 | [Y_MAX_LIM] = GENMASK(29, 24), |
245 | /* Bits 30-31 reserved */ |
246 | }; |
247 | |
248 | REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, |
249 | 0x00000504, 0x0020); |
250 | |
251 | static const u32 reg_endp_init_cfg_fmask[] = { |
252 | [FRAG_OFFLOAD_EN] = BIT(0), |
253 | [CS_OFFLOAD_EN] = GENMASK(2, 1), |
254 | [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), |
255 | /* Bit 7 reserved */ |
256 | [CS_GEN_QMB_MASTER_SEL] = BIT(8), |
257 | /* Bits 9-31 reserved */ |
258 | }; |
259 | |
260 | REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); |
261 | |
262 | static const u32 reg_endp_init_nat_fmask[] = { |
263 | [NAT_EN] = GENMASK(1, 0), |
264 | /* Bits 2-31 reserved */ |
265 | }; |
266 | |
267 | REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); |
268 | |
269 | static const u32 reg_endp_init_hdr_fmask[] = { |
270 | [HDR_LEN] = GENMASK(5, 0), |
271 | [HDR_OFST_METADATA_VALID] = BIT(6), |
272 | [HDR_OFST_METADATA] = GENMASK(12, 7), |
273 | [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13), |
274 | [HDR_OFST_PKT_SIZE_VALID] = BIT(19), |
275 | [HDR_OFST_PKT_SIZE] = GENMASK(25, 20), |
276 | [HDR_A5_MUX] = BIT(26), |
277 | [HDR_LEN_INC_DEAGG_HDR] = BIT(27), |
278 | [HDR_METADATA_REG_VALID] = BIT(28), |
279 | /* Bits 29-31 reserved */ |
280 | }; |
281 | |
282 | REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); |
283 | |
284 | static const u32 reg_endp_init_hdr_ext_fmask[] = { |
285 | [HDR_ENDIANNESS] = BIT(0), |
286 | [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), |
287 | [HDR_TOTAL_LEN_OR_PAD] = BIT(2), |
288 | [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3), |
289 | [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4), |
290 | [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10), |
291 | /* Bits 14-31 reserved */ |
292 | }; |
293 | |
294 | REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); |
295 | |
296 | REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, |
297 | 0x00000818, 0x0070); |
298 | |
299 | static const u32 reg_endp_init_mode_fmask[] = { |
300 | [ENDP_MODE] = GENMASK(2, 0), |
301 | /* Bit 3 reserved */ |
302 | [DEST_PIPE_INDEX] = GENMASK(8, 4), |
303 | /* Bits 9-11 reserved */ |
304 | [BYTE_THRESHOLD] = GENMASK(27, 12), |
305 | [PIPE_REPLICATION_EN] = BIT(28), |
306 | [PAD_EN] = BIT(29), |
307 | [HDR_FTCH_DISABLE] = BIT(30), |
308 | /* Bit 31 reserved */ |
309 | }; |
310 | |
311 | REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); |
312 | |
313 | static const u32 reg_endp_init_aggr_fmask[] = { |
314 | [AGGR_EN] = GENMASK(1, 0), |
315 | [AGGR_TYPE] = GENMASK(4, 2), |
316 | [BYTE_LIMIT] = GENMASK(9, 5), |
317 | [TIME_LIMIT] = GENMASK(14, 10), |
318 | [PKT_LIMIT] = GENMASK(20, 15), |
319 | [SW_EOF_ACTIVE] = BIT(21), |
320 | [FORCE_CLOSE] = BIT(22), |
321 | /* Bit 23 reserved */ |
322 | [HARD_BYTE_LIMIT_EN] = BIT(24), |
323 | /* Bits 25-31 reserved */ |
324 | }; |
325 | |
326 | REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); |
327 | |
328 | static const u32 reg_endp_init_hol_block_en_fmask[] = { |
329 | [HOL_BLOCK_EN] = BIT(0), |
330 | /* Bits 1-31 reserved */ |
331 | }; |
332 | |
333 | REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, |
334 | 0x0000082c, 0x0070); |
335 | |
336 | static const u32 reg_endp_init_hol_block_timer_fmask[] = { |
337 | [TIMER_BASE_VALUE] = GENMASK(4, 0), |
338 | /* Bits 5-7 reserved */ |
339 | [TIMER_SCALE] = GENMASK(12, 8), |
340 | /* Bits 9-31 reserved */ |
341 | }; |
342 | |
343 | REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, |
344 | 0x00000830, 0x0070); |
345 | |
346 | static const u32 reg_endp_init_deaggr_fmask[] = { |
347 | [DEAGGR_HDR_LEN] = GENMASK(5, 0), |
348 | [SYSPIPE_ERR_DETECTION] = BIT(6), |
349 | [PACKET_OFFSET_VALID] = BIT(7), |
350 | [PACKET_OFFSET_LOCATION] = GENMASK(13, 8), |
351 | [IGNORE_MIN_PKT_ERR] = BIT(14), |
352 | /* Bit 15 reserved */ |
353 | [MAX_PACKET_LEN] = GENMASK(31, 16), |
354 | }; |
355 | |
356 | REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); |
357 | |
358 | static const u32 reg_endp_init_rsrc_grp_fmask[] = { |
359 | [ENDP_RSRC_GRP] = BIT(0), |
360 | /* Bits 1-31 reserved */ |
361 | }; |
362 | |
363 | REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070); |
364 | |
365 | static const u32 reg_endp_init_seq_fmask[] = { |
366 | [SEQ_TYPE] = GENMASK(7, 0), |
367 | [SEQ_REP_TYPE] = GENMASK(15, 8), |
368 | /* Bits 16-31 reserved */ |
369 | }; |
370 | |
371 | REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); |
372 | |
373 | static const u32 reg_endp_status_fmask[] = { |
374 | [STATUS_EN] = BIT(0), |
375 | [STATUS_ENDP] = GENMASK(5, 1), |
376 | /* Bits 6-7 reserved */ |
377 | [STATUS_LOCATION] = BIT(8), |
378 | [STATUS_PKT_SUPPRESS] = BIT(9), |
379 | /* Bits 10-31 reserved */ |
380 | }; |
381 | |
382 | REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); |
383 | |
384 | /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ |
385 | REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); |
386 | |
387 | /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ |
388 | REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); |
389 | |
390 | /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ |
391 | REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); |
392 | |
393 | static const u32 reg_ipa_irq_uc_fmask[] = { |
394 | [UC_INTR] = BIT(0), |
395 | /* Bits 1-31 reserved */ |
396 | }; |
397 | |
398 | REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); |
399 | |
400 | /* Valid bits defined by ipa->available */ |
401 | REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, |
402 | 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004); |
403 | |
404 | /* Valid bits defined by ipa->available */ |
405 | REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, |
406 | 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004); |
407 | |
408 | /* Valid bits defined by ipa->available */ |
409 | REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, |
410 | 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004); |
411 | |
412 | static const struct reg *reg_array[] = { |
413 | [COMP_CFG] = ®_comp_cfg, |
414 | [CLKON_CFG] = ®_clkon_cfg, |
415 | [ROUTE] = ®_route, |
416 | [SHARED_MEM_SIZE] = ®_shared_mem_size, |
417 | [QSB_MAX_WRITES] = ®_qsb_max_writes, |
418 | [QSB_MAX_READS] = ®_qsb_max_reads, |
419 | [FILT_ROUT_HASH_EN] = ®_filt_rout_hash_en, |
420 | [FILT_ROUT_HASH_FLUSH] = ®_filt_rout_hash_flush, |
421 | [STATE_AGGR_ACTIVE] = ®_state_aggr_active, |
422 | [IPA_BCR] = ®_ipa_bcr, |
423 | [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt, |
424 | [AGGR_FORCE_CLOSE] = ®_aggr_force_close, |
425 | [COUNTER_CFG] = ®_counter_cfg, |
426 | [IPA_TX_CFG] = ®_ipa_tx_cfg, |
427 | [FLAVOR_0] = ®_flavor_0, |
428 | [IDLE_INDICATION_CFG] = ®_idle_indication_cfg, |
429 | [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type, |
430 | [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type, |
431 | [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type, |
432 | [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type, |
433 | [ENDP_INIT_CFG] = ®_endp_init_cfg, |
434 | [ENDP_INIT_NAT] = ®_endp_init_nat, |
435 | [ENDP_INIT_HDR] = ®_endp_init_hdr, |
436 | [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext, |
437 | [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask, |
438 | [ENDP_INIT_MODE] = ®_endp_init_mode, |
439 | [ENDP_INIT_AGGR] = ®_endp_init_aggr, |
440 | [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en, |
441 | [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer, |
442 | [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr, |
443 | [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp, |
444 | [ENDP_INIT_SEQ] = ®_endp_init_seq, |
445 | [ENDP_STATUS] = ®_endp_status, |
446 | [IPA_IRQ_STTS] = ®_ipa_irq_stts, |
447 | [IPA_IRQ_EN] = ®_ipa_irq_en, |
448 | [IPA_IRQ_CLR] = ®_ipa_irq_clr, |
449 | [IPA_IRQ_UC] = ®_ipa_irq_uc, |
450 | [IRQ_SUSPEND_INFO] = ®_irq_suspend_info, |
451 | [IRQ_SUSPEND_EN] = ®_irq_suspend_en, |
452 | [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr, |
453 | }; |
454 | |
455 | const struct regs ipa_regs_v4_2 = { |
456 | .reg_count = ARRAY_SIZE(reg_array), |
457 | .reg = reg_array, |
458 | }; |
459 | |