1 | // SPDX-License-Identifier: GPL-2.0 |
2 | |
3 | /* Copyright (C) 2022 Linaro Ltd. */ |
4 | |
5 | #include <linux/types.h> |
6 | |
7 | #include "../ipa.h" |
8 | #include "../ipa_reg.h" |
9 | |
10 | static const u32 reg_comp_cfg_fmask[] = { |
11 | /* Bit 0 reserved */ |
12 | [GSI_SNOC_BYPASS_DIS] = BIT(1), |
13 | [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), |
14 | [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), |
15 | /* Bit 4 reserved */ |
16 | [IPA_QMB_SELECT_CONS_EN] = BIT(5), |
17 | [IPA_QMB_SELECT_PROD_EN] = BIT(6), |
18 | [GSI_MULTI_INORDER_RD_DIS] = BIT(7), |
19 | [GSI_MULTI_INORDER_WR_DIS] = BIT(8), |
20 | [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9), |
21 | [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10), |
22 | [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11), |
23 | [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12), |
24 | [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13), |
25 | [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14), |
26 | [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15), |
27 | [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16), |
28 | [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(20, 17), |
29 | [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(21), |
30 | /* Bits 22-31 reserved */ |
31 | }; |
32 | |
33 | REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); |
34 | |
35 | static const u32 reg_clkon_cfg_fmask[] = { |
36 | [CLKON_RX] = BIT(0), |
37 | [CLKON_PROC] = BIT(1), |
38 | [TX_WRAPPER] = BIT(2), |
39 | [CLKON_MISC] = BIT(3), |
40 | [RAM_ARB] = BIT(4), |
41 | [FTCH_HPS] = BIT(5), |
42 | [FTCH_DPS] = BIT(6), |
43 | [CLKON_HPS] = BIT(7), |
44 | [CLKON_DPS] = BIT(8), |
45 | [RX_HPS_CMDQS] = BIT(9), |
46 | [HPS_DPS_CMDQS] = BIT(10), |
47 | [DPS_TX_CMDQS] = BIT(11), |
48 | [RSRC_MNGR] = BIT(12), |
49 | [CTX_HANDLER] = BIT(13), |
50 | [ACK_MNGR] = BIT(14), |
51 | [D_DCPH] = BIT(15), |
52 | [H_DCPH] = BIT(16), |
53 | [CLKON_DCMP] = BIT(17), |
54 | [NTF_TX_CMDQS] = BIT(18), |
55 | [CLKON_TX_0] = BIT(19), |
56 | [CLKON_TX_1] = BIT(20), |
57 | [CLKON_FNR] = BIT(21), |
58 | [QSB2AXI_CMDQ_L] = BIT(22), |
59 | [AGGR_WRAPPER] = BIT(23), |
60 | [RAM_SLAVEWAY] = BIT(24), |
61 | [CLKON_QMB] = BIT(25), |
62 | [WEIGHT_ARB] = BIT(26), |
63 | [GSI_IF] = BIT(27), |
64 | [CLKON_GLOBAL] = BIT(28), |
65 | [GLOBAL_2X_CLK] = BIT(29), |
66 | [DPL_FIFO] = BIT(30), |
67 | /* Bit 31 reserved */ |
68 | }; |
69 | |
70 | REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); |
71 | |
72 | static const u32 reg_route_fmask[] = { |
73 | [ROUTE_DIS] = BIT(0), |
74 | [ROUTE_DEF_PIPE] = GENMASK(5, 1), |
75 | [ROUTE_DEF_HDR_TABLE] = BIT(6), |
76 | [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7), |
77 | [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17), |
78 | /* Bits 22-23 reserved */ |
79 | [ROUTE_DEF_RETAIN_HDR] = BIT(24), |
80 | /* Bits 25-31 reserved */ |
81 | }; |
82 | |
83 | REG_FIELDS(ROUTE, route, 0x00000048); |
84 | |
85 | static const u32 reg_shared_mem_size_fmask[] = { |
86 | [MEM_SIZE] = GENMASK(15, 0), |
87 | [MEM_BADDR] = GENMASK(31, 16), |
88 | }; |
89 | |
90 | REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); |
91 | |
92 | static const u32 reg_qsb_max_writes_fmask[] = { |
93 | [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), |
94 | [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), |
95 | /* Bits 8-31 reserved */ |
96 | }; |
97 | |
98 | REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); |
99 | |
100 | static const u32 reg_qsb_max_reads_fmask[] = { |
101 | [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), |
102 | [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), |
103 | /* Bits 8-15 reserved */ |
104 | [GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16), |
105 | [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24), |
106 | }; |
107 | |
108 | REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); |
109 | |
110 | static const u32 reg_filt_rout_hash_en_fmask[] = { |
111 | [IPV6_ROUTER_HASH] = BIT(0), |
112 | /* Bits 1-3 reserved */ |
113 | [IPV6_FILTER_HASH] = BIT(4), |
114 | /* Bits 5-7 reserved */ |
115 | [IPV4_ROUTER_HASH] = BIT(8), |
116 | /* Bits 9-11 reserved */ |
117 | [IPV4_FILTER_HASH] = BIT(12), |
118 | /* Bits 13-31 reserved */ |
119 | }; |
120 | |
121 | REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148); |
122 | |
123 | static const u32 reg_filt_rout_hash_flush_fmask[] = { |
124 | [IPV6_ROUTER_HASH] = BIT(0), |
125 | /* Bits 1-3 reserved */ |
126 | [IPV6_FILTER_HASH] = BIT(4), |
127 | /* Bits 5-7 reserved */ |
128 | [IPV4_ROUTER_HASH] = BIT(8), |
129 | /* Bits 9-11 reserved */ |
130 | [IPV4_FILTER_HASH] = BIT(12), |
131 | /* Bits 13-31 reserved */ |
132 | }; |
133 | |
134 | REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c); |
135 | |
136 | /* Valid bits defined by ipa->available */ |
137 | REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004); |
138 | |
139 | static const u32 reg_local_pkt_proc_cntxt_fmask[] = { |
140 | [IPA_BASE_ADDR] = GENMASK(17, 0), |
141 | /* Bits 18-31 reserved */ |
142 | }; |
143 | |
144 | /* Offset must be a multiple of 8 */ |
145 | REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); |
146 | |
147 | /* Valid bits defined by ipa->available */ |
148 | REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004); |
149 | |
150 | static const u32 reg_ipa_tx_cfg_fmask[] = { |
151 | /* Bits 0-1 reserved */ |
152 | [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2), |
153 | [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6), |
154 | [DMAW_SCND_OUTSD_PRED_EN] = BIT(10), |
155 | [DMAW_MAX_BEATS_256_DIS] = BIT(11), |
156 | [PA_MASK_EN] = BIT(12), |
157 | [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13), |
158 | [DUAL_TX_ENABLE] = BIT(17), |
159 | /* Bits 18-31 reserved */ |
160 | }; |
161 | |
162 | REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); |
163 | |
164 | static const u32 reg_flavor_0_fmask[] = { |
165 | [MAX_PIPES] = GENMASK(3, 0), |
166 | /* Bits 4-7 reserved */ |
167 | [MAX_CONS_PIPES] = GENMASK(12, 8), |
168 | /* Bits 13-15 reserved */ |
169 | [MAX_PROD_PIPES] = GENMASK(20, 16), |
170 | /* Bits 21-23 reserved */ |
171 | [PROD_LOWEST] = GENMASK(27, 24), |
172 | /* Bits 28-31 reserved */ |
173 | }; |
174 | |
175 | REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); |
176 | |
177 | static const u32 reg_idle_indication_cfg_fmask[] = { |
178 | [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), |
179 | [CONST_NON_IDLE_ENABLE] = BIT(16), |
180 | /* Bits 17-31 reserved */ |
181 | }; |
182 | |
183 | REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240); |
184 | |
185 | static const u32 reg_qtime_timestamp_cfg_fmask[] = { |
186 | [DPL_TIMESTAMP_LSB] = GENMASK(4, 0), |
187 | /* Bits 5-6 reserved */ |
188 | [DPL_TIMESTAMP_SEL] = BIT(7), |
189 | [TAG_TIMESTAMP_LSB] = GENMASK(12, 8), |
190 | /* Bits 13-15 reserved */ |
191 | [NAT_TIMESTAMP_LSB] = GENMASK(20, 16), |
192 | /* Bits 21-31 reserved */ |
193 | }; |
194 | |
195 | REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c); |
196 | |
197 | static const u32 reg_timers_xo_clk_div_cfg_fmask[] = { |
198 | [DIV_VALUE] = GENMASK(8, 0), |
199 | /* Bits 9-30 reserved */ |
200 | [DIV_ENABLE] = BIT(31), |
201 | }; |
202 | |
203 | REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250); |
204 | |
205 | static const u32 reg_timers_pulse_gran_cfg_fmask[] = { |
206 | [PULSE_GRAN_0] = GENMASK(2, 0), |
207 | [PULSE_GRAN_1] = GENMASK(5, 3), |
208 | [PULSE_GRAN_2] = GENMASK(8, 6), |
209 | }; |
210 | |
211 | REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254); |
212 | |
213 | static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = { |
214 | [X_MIN_LIM] = GENMASK(5, 0), |
215 | /* Bits 6-7 reserved */ |
216 | [X_MAX_LIM] = GENMASK(13, 8), |
217 | /* Bits 14-15 reserved */ |
218 | [Y_MIN_LIM] = GENMASK(21, 16), |
219 | /* Bits 22-23 reserved */ |
220 | [Y_MAX_LIM] = GENMASK(29, 24), |
221 | /* Bits 30-31 reserved */ |
222 | }; |
223 | |
224 | REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, |
225 | 0x00000400, 0x0020); |
226 | |
227 | static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = { |
228 | [X_MIN_LIM] = GENMASK(5, 0), |
229 | /* Bits 6-7 reserved */ |
230 | [X_MAX_LIM] = GENMASK(13, 8), |
231 | /* Bits 14-15 reserved */ |
232 | [Y_MIN_LIM] = GENMASK(21, 16), |
233 | /* Bits 22-23 reserved */ |
234 | [Y_MAX_LIM] = GENMASK(29, 24), |
235 | /* Bits 30-31 reserved */ |
236 | }; |
237 | |
238 | REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, |
239 | 0x00000404, 0x0020); |
240 | |
241 | static const u32 reg_src_rsrc_grp_45_rsrc_type_fmask[] = { |
242 | [X_MIN_LIM] = GENMASK(5, 0), |
243 | /* Bits 6-7 reserved */ |
244 | [X_MAX_LIM] = GENMASK(13, 8), |
245 | /* Bits 14-15 reserved */ |
246 | [Y_MIN_LIM] = GENMASK(21, 16), |
247 | /* Bits 22-23 reserved */ |
248 | [Y_MAX_LIM] = GENMASK(29, 24), |
249 | /* Bits 30-31 reserved */ |
250 | }; |
251 | |
252 | REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type, |
253 | 0x00000408, 0x0020); |
254 | |
255 | static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { |
256 | [X_MIN_LIM] = GENMASK(5, 0), |
257 | /* Bits 6-7 reserved */ |
258 | [X_MAX_LIM] = GENMASK(13, 8), |
259 | /* Bits 14-15 reserved */ |
260 | [Y_MIN_LIM] = GENMASK(21, 16), |
261 | /* Bits 22-23 reserved */ |
262 | [Y_MAX_LIM] = GENMASK(29, 24), |
263 | /* Bits 30-31 reserved */ |
264 | }; |
265 | |
266 | REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, |
267 | 0x00000500, 0x0020); |
268 | |
269 | static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { |
270 | [X_MIN_LIM] = GENMASK(5, 0), |
271 | /* Bits 6-7 reserved */ |
272 | [X_MAX_LIM] = GENMASK(13, 8), |
273 | /* Bits 14-15 reserved */ |
274 | [Y_MIN_LIM] = GENMASK(21, 16), |
275 | /* Bits 22-23 reserved */ |
276 | [Y_MAX_LIM] = GENMASK(29, 24), |
277 | /* Bits 30-31 reserved */ |
278 | }; |
279 | |
280 | REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, |
281 | 0x00000504, 0x0020); |
282 | |
283 | static const u32 reg_dst_rsrc_grp_45_rsrc_type_fmask[] = { |
284 | [X_MIN_LIM] = GENMASK(5, 0), |
285 | /* Bits 6-7 reserved */ |
286 | [X_MAX_LIM] = GENMASK(13, 8), |
287 | /* Bits 14-15 reserved */ |
288 | [Y_MIN_LIM] = GENMASK(21, 16), |
289 | /* Bits 22-23 reserved */ |
290 | [Y_MAX_LIM] = GENMASK(29, 24), |
291 | /* Bits 30-31 reserved */ |
292 | }; |
293 | |
294 | REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type, |
295 | 0x00000508, 0x0020); |
296 | |
297 | static const u32 reg_endp_init_cfg_fmask[] = { |
298 | [FRAG_OFFLOAD_EN] = BIT(0), |
299 | [CS_OFFLOAD_EN] = GENMASK(2, 1), |
300 | [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), |
301 | /* Bit 7 reserved */ |
302 | [CS_GEN_QMB_MASTER_SEL] = BIT(8), |
303 | /* Bits 9-31 reserved */ |
304 | }; |
305 | |
306 | REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); |
307 | |
308 | static const u32 reg_endp_init_nat_fmask[] = { |
309 | [NAT_EN] = GENMASK(1, 0), |
310 | /* Bits 2-31 reserved */ |
311 | }; |
312 | |
313 | REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); |
314 | |
315 | static const u32 reg_endp_init_hdr_fmask[] = { |
316 | [HDR_LEN] = GENMASK(5, 0), |
317 | [HDR_OFST_METADATA_VALID] = BIT(6), |
318 | [HDR_OFST_METADATA] = GENMASK(12, 7), |
319 | [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13), |
320 | [HDR_OFST_PKT_SIZE_VALID] = BIT(19), |
321 | [HDR_OFST_PKT_SIZE] = GENMASK(25, 20), |
322 | [HDR_A5_MUX] = BIT(26), |
323 | [HDR_LEN_INC_DEAGG_HDR] = BIT(27), |
324 | [HDR_LEN_MSB] = GENMASK(29, 28), |
325 | [HDR_OFST_METADATA_MSB] = GENMASK(31, 30), |
326 | }; |
327 | |
328 | REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); |
329 | |
330 | static const u32 reg_endp_init_hdr_ext_fmask[] = { |
331 | [HDR_ENDIANNESS] = BIT(0), |
332 | [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), |
333 | [HDR_TOTAL_LEN_OR_PAD] = BIT(2), |
334 | [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3), |
335 | [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4), |
336 | [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10), |
337 | /* Bits 14-15 reserved */ |
338 | [HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16), |
339 | [HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18), |
340 | [HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20), |
341 | /* Bits 22-31 reserved */ |
342 | }; |
343 | |
344 | REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); |
345 | |
346 | REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, |
347 | 0x00000818, 0x0070); |
348 | |
349 | static const u32 reg_endp_init_mode_fmask[] = { |
350 | [ENDP_MODE] = GENMASK(2, 0), |
351 | [DCPH_ENABLE] = BIT(3), |
352 | [DEST_PIPE_INDEX] = GENMASK(8, 4), |
353 | /* Bits 9-11 reserved */ |
354 | [BYTE_THRESHOLD] = GENMASK(27, 12), |
355 | [PIPE_REPLICATION_EN] = BIT(28), |
356 | [PAD_EN] = BIT(29), |
357 | /* Bits 30-31 reserved */ |
358 | }; |
359 | |
360 | REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); |
361 | |
362 | static const u32 reg_endp_init_aggr_fmask[] = { |
363 | [AGGR_EN] = GENMASK(1, 0), |
364 | [AGGR_TYPE] = GENMASK(4, 2), |
365 | [BYTE_LIMIT] = GENMASK(10, 5), |
366 | /* Bit 11 reserved */ |
367 | [TIME_LIMIT] = GENMASK(16, 12), |
368 | [PKT_LIMIT] = GENMASK(22, 17), |
369 | [SW_EOF_ACTIVE] = BIT(23), |
370 | [FORCE_CLOSE] = BIT(24), |
371 | /* Bit 25 reserved */ |
372 | [HARD_BYTE_LIMIT_EN] = BIT(26), |
373 | [AGGR_GRAN_SEL] = BIT(27), |
374 | /* Bits 28-31 reserved */ |
375 | }; |
376 | |
377 | REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); |
378 | |
379 | static const u32 reg_endp_init_hol_block_en_fmask[] = { |
380 | [HOL_BLOCK_EN] = BIT(0), |
381 | /* Bits 1-31 reserved */ |
382 | }; |
383 | |
384 | REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, |
385 | 0x0000082c, 0x0070); |
386 | |
387 | static const u32 reg_endp_init_hol_block_timer_fmask[] = { |
388 | [TIMER_LIMIT] = GENMASK(4, 0), |
389 | /* Bits 5-7 reserved */ |
390 | [TIMER_GRAN_SEL] = BIT(8), |
391 | /* Bits 9-31 reserved */ |
392 | }; |
393 | |
394 | REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, |
395 | 0x00000830, 0x0070); |
396 | |
397 | static const u32 reg_endp_init_deaggr_fmask[] = { |
398 | [DEAGGR_HDR_LEN] = GENMASK(5, 0), |
399 | [SYSPIPE_ERR_DETECTION] = BIT(6), |
400 | [PACKET_OFFSET_VALID] = BIT(7), |
401 | [PACKET_OFFSET_LOCATION] = GENMASK(13, 8), |
402 | [IGNORE_MIN_PKT_ERR] = BIT(14), |
403 | /* Bit 15 reserved */ |
404 | [MAX_PACKET_LEN] = GENMASK(31, 16), |
405 | }; |
406 | |
407 | REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); |
408 | |
409 | static const u32 reg_endp_init_rsrc_grp_fmask[] = { |
410 | [ENDP_RSRC_GRP] = GENMASK(2, 0), |
411 | /* Bits 3-31 reserved */ |
412 | }; |
413 | |
414 | REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070); |
415 | |
416 | static const u32 reg_endp_init_seq_fmask[] = { |
417 | [SEQ_TYPE] = GENMASK(7, 0), |
418 | /* Bits 8-31 reserved */ |
419 | }; |
420 | |
421 | REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); |
422 | |
423 | static const u32 reg_endp_status_fmask[] = { |
424 | [STATUS_EN] = BIT(0), |
425 | [STATUS_ENDP] = GENMASK(5, 1), |
426 | /* Bits 6-8 reserved */ |
427 | [STATUS_PKT_SUPPRESS] = BIT(9), |
428 | /* Bits 10-31 reserved */ |
429 | }; |
430 | |
431 | REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); |
432 | |
433 | static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = { |
434 | [FILTER_HASH_MSK_SRC_ID] = BIT(0), |
435 | [FILTER_HASH_MSK_SRC_IP] = BIT(1), |
436 | [FILTER_HASH_MSK_DST_IP] = BIT(2), |
437 | [FILTER_HASH_MSK_SRC_PORT] = BIT(3), |
438 | [FILTER_HASH_MSK_DST_PORT] = BIT(4), |
439 | [FILTER_HASH_MSK_PROTOCOL] = BIT(5), |
440 | [FILTER_HASH_MSK_METADATA] = BIT(6), |
441 | [FILTER_HASH_MSK_ALL] = GENMASK(6, 0), |
442 | /* Bits 7-15 reserved */ |
443 | [ROUTER_HASH_MSK_SRC_ID] = BIT(16), |
444 | [ROUTER_HASH_MSK_SRC_IP] = BIT(17), |
445 | [ROUTER_HASH_MSK_DST_IP] = BIT(18), |
446 | [ROUTER_HASH_MSK_SRC_PORT] = BIT(19), |
447 | [ROUTER_HASH_MSK_DST_PORT] = BIT(20), |
448 | [ROUTER_HASH_MSK_PROTOCOL] = BIT(21), |
449 | [ROUTER_HASH_MSK_METADATA] = BIT(22), |
450 | [ROUTER_HASH_MSK_ALL] = GENMASK(22, 16), |
451 | /* Bits 23-31 reserved */ |
452 | }; |
453 | |
454 | REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, |
455 | 0x0000085c, 0x0070); |
456 | |
457 | /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ |
458 | REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); |
459 | |
460 | /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ |
461 | REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); |
462 | |
463 | /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ |
464 | REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); |
465 | |
466 | static const u32 reg_ipa_irq_uc_fmask[] = { |
467 | [UC_INTR] = BIT(0), |
468 | /* Bits 1-31 reserved */ |
469 | }; |
470 | |
471 | REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); |
472 | |
473 | /* Valid bits defined by ipa->available */ |
474 | REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, |
475 | 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004); |
476 | |
477 | /* Valid bits defined by ipa->available */ |
478 | REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, |
479 | 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004); |
480 | |
481 | /* Valid bits defined by ipa->available */ |
482 | REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, |
483 | 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004); |
484 | |
485 | static const struct reg *reg_array[] = { |
486 | [COMP_CFG] = ®_comp_cfg, |
487 | [CLKON_CFG] = ®_clkon_cfg, |
488 | [ROUTE] = ®_route, |
489 | [SHARED_MEM_SIZE] = ®_shared_mem_size, |
490 | [QSB_MAX_WRITES] = ®_qsb_max_writes, |
491 | [QSB_MAX_READS] = ®_qsb_max_reads, |
492 | [FILT_ROUT_HASH_EN] = ®_filt_rout_hash_en, |
493 | [FILT_ROUT_HASH_FLUSH] = ®_filt_rout_hash_flush, |
494 | [STATE_AGGR_ACTIVE] = ®_state_aggr_active, |
495 | [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt, |
496 | [AGGR_FORCE_CLOSE] = ®_aggr_force_close, |
497 | [IPA_TX_CFG] = ®_ipa_tx_cfg, |
498 | [FLAVOR_0] = ®_flavor_0, |
499 | [IDLE_INDICATION_CFG] = ®_idle_indication_cfg, |
500 | [QTIME_TIMESTAMP_CFG] = ®_qtime_timestamp_cfg, |
501 | [TIMERS_XO_CLK_DIV_CFG] = ®_timers_xo_clk_div_cfg, |
502 | [TIMERS_PULSE_GRAN_CFG] = ®_timers_pulse_gran_cfg, |
503 | [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type, |
504 | [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type, |
505 | [SRC_RSRC_GRP_45_RSRC_TYPE] = ®_src_rsrc_grp_45_rsrc_type, |
506 | [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type, |
507 | [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type, |
508 | [DST_RSRC_GRP_45_RSRC_TYPE] = ®_dst_rsrc_grp_45_rsrc_type, |
509 | [ENDP_INIT_CFG] = ®_endp_init_cfg, |
510 | [ENDP_INIT_NAT] = ®_endp_init_nat, |
511 | [ENDP_INIT_HDR] = ®_endp_init_hdr, |
512 | [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext, |
513 | [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask, |
514 | [ENDP_INIT_MODE] = ®_endp_init_mode, |
515 | [ENDP_INIT_AGGR] = ®_endp_init_aggr, |
516 | [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en, |
517 | [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer, |
518 | [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr, |
519 | [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp, |
520 | [ENDP_INIT_SEQ] = ®_endp_init_seq, |
521 | [ENDP_STATUS] = ®_endp_status, |
522 | [ENDP_FILTER_ROUTER_HSH_CFG] = ®_endp_filter_router_hsh_cfg, |
523 | [IPA_IRQ_STTS] = ®_ipa_irq_stts, |
524 | [IPA_IRQ_EN] = ®_ipa_irq_en, |
525 | [IPA_IRQ_CLR] = ®_ipa_irq_clr, |
526 | [IPA_IRQ_UC] = ®_ipa_irq_uc, |
527 | [IRQ_SUSPEND_INFO] = ®_irq_suspend_info, |
528 | [IRQ_SUSPEND_EN] = ®_irq_suspend_en, |
529 | [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr, |
530 | }; |
531 | |
532 | const struct regs ipa_regs_v4_5 = { |
533 | .reg_count = ARRAY_SIZE(reg_array), |
534 | .reg = reg_array, |
535 | }; |
536 | |