1	// SPDX-License-Identifier: BSD-3-Clause-Clear
2	/*
3	* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4	* Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5	*/
6
7	#include <linux/module.h>
8	#include <linux/slab.h>
9	#include <linux/remoteproc.h>
10	#include <linux/firmware.h>
11	#include <linux/of.h>
12
13	#include "core.h"
14	#include "dp_tx.h"
15	#include "dp_rx.h"
16	#include "debug.h"
17	#include "hif.h"
18	#include "wow.h"
19	#include "fw.h"
20
21	unsigned int ath11k_debug_mask;
22	EXPORT_SYMBOL(ath11k_debug_mask);
23	module_param_named(debug_mask, ath11k_debug_mask, uint, 0644);
24	MODULE_PARM_DESC(debug_mask, "Debugging mask");
25
26	static unsigned int ath11k_crypto_mode;
27	module_param_named(crypto_mode, ath11k_crypto_mode, uint, 0644);
28	MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software");
29
30	/* frame mode values are mapped as per enum ath11k_hw_txrx_mode */
31	unsigned int ath11k_frame_mode = ATH11K_HW_TXRX_NATIVE_WIFI;
32	module_param_named(frame_mode, ath11k_frame_mode, uint, 0644);
33	MODULE_PARM_DESC(frame_mode,
34	"Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)");
35
36	bool ath11k_ftm_mode;
37	module_param_named(ftm_mode, ath11k_ftm_mode, bool, 0444);
38	MODULE_PARM_DESC(ftm_mode, "Boots up in factory test mode");
39
40	static const struct ath11k_hw_params ath11k_hw_params[] = {
41	{
42	.hw_rev = ATH11K_HW_IPQ8074,
43	.name = "ipq8074 hw2.0",
44	.fw = {
45	.dir = "IPQ8074/hw2.0",
46	.board_size = 256 * 1024,
47	.cal_offset = 128 * 1024,
48	},
49	.max_radios = 3,
50	.bdf_addr = 0x4B0C0000,
51	.hw_ops = &ipq8074_ops,
52	.ring_mask = &ath11k_hw_ring_mask_ipq8074,
53	.internal_sleep_clock = false,
54	.regs = &ipq8074_regs,
55	.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
56	.host_ce_config = ath11k_host_ce_config_ipq8074,
57	.ce_count = 12,
58	.target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
59	.target_ce_count = 11,
60	.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074,
61	.svc_to_ce_map_len = 21,
62	.ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
63	.single_pdev_only = false,
64	.rxdma1_enable = true,
65	.num_rxdma_per_pdev = 1,
66	.rx_mac_buf_ring = false,
67	.vdev_start_delay = false,
68	.htt_peer_map_v2 = true,
69
70	.spectral = {
71	.fft_sz = 2,
72	/* HW bug, expected BIN size is 2 bytes but HW report as 4 bytes.
73	* so added pad size as 2 bytes to compensate the BIN size
74	*/
75	.fft_pad_sz = 2,
76	.summary_pad_sz = 0,
77	.fft_hdr_len = 16,
78	.max_fft_bins = 512,
79	.fragment_160mhz = true,
80	},
81
82	.interface_modes = BIT(NL80211_IFTYPE_STATION) |
83	BIT(NL80211_IFTYPE_AP) |
84	BIT(NL80211_IFTYPE_MESH_POINT),
85	.supports_monitor = true,
86	.full_monitor_mode = false,
87	.supports_shadow_regs = false,
88	.idle_ps = false,
89	.supports_sta_ps = false,
90	.coldboot_cal_mm = true,
91	.coldboot_cal_ftm = true,
92	.cbcal_restart_fw = true,
93	.fw_mem_mode = 0,
94	.num_vdevs = 16 + 1,
95	.num_peers = 512,
96	.supports_suspend = false,
97	.hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
98	.supports_regdb = false,
99	.fix_l1ss = true,
100	.credit_flow = false,
101	.max_tx_ring = DP_TCL_NUM_RING_MAX,
102	.hal_params = &ath11k_hw_hal_params_ipq8074,
103	.supports_dynamic_smps_6ghz = false,
104	.alloc_cacheable_memory = true,
105	.supports_rssi_stats = false,
106	.fw_wmi_diag_event = false,
107	.current_cc_support = false,
108	.dbr_debug_support = true,
109	.global_reset = false,
110	.bios_sar_capa = NULL,
111	.m3_fw_support = false,
112	.fixed_bdf_addr = true,
113	.fixed_mem_region = true,
114	.static_window_map = false,
115	.hybrid_bus_type = false,
116	.fixed_fw_mem = false,
117	.support_off_channel_tx = false,
118	.supports_multi_bssid = false,
119
120	.sram_dump = {},
121
122	.tcl_ring_retry = true,
123	.tx_ring_size = DP_TCL_DATA_RING_SIZE,
124	.smp2p_wow_exit = false,
125	.support_dual_stations = false,
126	.pdev_suspend = false,
127	},
128	{
129	.hw_rev = ATH11K_HW_IPQ6018_HW10,
130	.name = "ipq6018 hw1.0",
131	.fw = {
132	.dir = "IPQ6018/hw1.0",
133	.board_size = 256 * 1024,
134	.cal_offset = 128 * 1024,
135	},
136	.max_radios = 2,
137	.bdf_addr = 0x4ABC0000,
138	.hw_ops = &ipq6018_ops,
139	.ring_mask = &ath11k_hw_ring_mask_ipq8074,
140	.internal_sleep_clock = false,
141	.regs = &ipq8074_regs,
142	.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
143	.host_ce_config = ath11k_host_ce_config_ipq8074,
144	.ce_count = 12,
145	.target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
146	.target_ce_count = 11,
147	.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018,
148	.svc_to_ce_map_len = 19,
149	.ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
150	.single_pdev_only = false,
151	.rxdma1_enable = true,
152	.num_rxdma_per_pdev = 1,
153	.rx_mac_buf_ring = false,
154	.vdev_start_delay = false,
155	.htt_peer_map_v2 = true,
156
157	.spectral = {
158	.fft_sz = 4,
159	.fft_pad_sz = 0,
160	.summary_pad_sz = 0,
161	.fft_hdr_len = 16,
162	.max_fft_bins = 512,
163	.fragment_160mhz = true,
164	},
165
166	.interface_modes = BIT(NL80211_IFTYPE_STATION) |
167	BIT(NL80211_IFTYPE_AP) |
168	BIT(NL80211_IFTYPE_MESH_POINT),
169	.supports_monitor = true,
170	.full_monitor_mode = false,
171	.supports_shadow_regs = false,
172	.idle_ps = false,
173	.supports_sta_ps = false,
174	.coldboot_cal_mm = true,
175	.coldboot_cal_ftm = true,
176	.cbcal_restart_fw = true,
177	.fw_mem_mode = 0,
178	.num_vdevs = 16 + 1,
179	.num_peers = 512,
180	.supports_suspend = false,
181	.hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
182	.supports_regdb = false,
183	.fix_l1ss = true,
184	.credit_flow = false,
185	.max_tx_ring = DP_TCL_NUM_RING_MAX,
186	.hal_params = &ath11k_hw_hal_params_ipq8074,
187	.supports_dynamic_smps_6ghz = false,
188	.alloc_cacheable_memory = true,
189	.supports_rssi_stats = false,
190	.fw_wmi_diag_event = false,
191	.current_cc_support = false,
192	.dbr_debug_support = true,
193	.global_reset = false,
194	.bios_sar_capa = NULL,
195	.m3_fw_support = false,
196	.fixed_bdf_addr = true,
197	.fixed_mem_region = true,
198	.static_window_map = false,
199	.hybrid_bus_type = false,
200	.fixed_fw_mem = false,
201	.support_off_channel_tx = false,
202	.supports_multi_bssid = false,
203
204	.sram_dump = {},
205
206	.tcl_ring_retry = true,
207	.tx_ring_size = DP_TCL_DATA_RING_SIZE,
208	.smp2p_wow_exit = false,
209	.support_fw_mac_sequence = false,
210	.support_dual_stations = false,
211	.pdev_suspend = false,
212	},
213	{
214	.name = "qca6390 hw2.0",
215	.hw_rev = ATH11K_HW_QCA6390_HW20,
216	.fw = {
217	.dir = "QCA6390/hw2.0",
218	.board_size = 256 * 1024,
219	.cal_offset = 128 * 1024,
220	},
221	.max_radios = 3,
222	.bdf_addr = 0x4B0C0000,
223	.hw_ops = &qca6390_ops,
224	.ring_mask = &ath11k_hw_ring_mask_qca6390,
225	.internal_sleep_clock = true,
226	.regs = &qca6390_regs,
227	.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
228	.host_ce_config = ath11k_host_ce_config_qca6390,
229	.ce_count = 9,
230	.target_ce_config = ath11k_target_ce_config_wlan_qca6390,
231	.target_ce_count = 9,
232	.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
233	.svc_to_ce_map_len = 14,
234	.ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
235	.single_pdev_only = true,
236	.rxdma1_enable = false,
237	.num_rxdma_per_pdev = 2,
238	.rx_mac_buf_ring = true,
239	.vdev_start_delay = true,
240	.htt_peer_map_v2 = false,
241
242	.spectral = {
243	.fft_sz = 0,
244	.fft_pad_sz = 0,
245	.summary_pad_sz = 0,
246	.fft_hdr_len = 0,
247	.max_fft_bins = 0,
248	.fragment_160mhz = false,
249	},
250
251	.interface_modes = BIT(NL80211_IFTYPE_STATION) |
252	BIT(NL80211_IFTYPE_AP) |
253	BIT(NL80211_IFTYPE_P2P_DEVICE) |
254	BIT(NL80211_IFTYPE_P2P_CLIENT) |
255	BIT(NL80211_IFTYPE_P2P_GO),
256	.supports_monitor = false,
257	.full_monitor_mode = false,
258	.supports_shadow_regs = true,
259	.idle_ps = true,
260	.supports_sta_ps = true,
261	.coldboot_cal_mm = false,
262	.coldboot_cal_ftm = false,
263	.cbcal_restart_fw = false,
264	.fw_mem_mode = 0,
265	.num_vdevs = 2 + 1,
266	.num_peers = 512,
267	.supports_suspend = true,
268	.hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
269	.supports_regdb = false,
270	.fix_l1ss = true,
271	.credit_flow = true,
272	.max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
273	.hal_params = &ath11k_hw_hal_params_qca6390,
274	.supports_dynamic_smps_6ghz = false,
275	.alloc_cacheable_memory = false,
276	.supports_rssi_stats = true,
277	.fw_wmi_diag_event = true,
278	.current_cc_support = true,
279	.dbr_debug_support = false,
280	.global_reset = true,
281	.bios_sar_capa = NULL,
282	.m3_fw_support = true,
283	.fixed_bdf_addr = false,
284	.fixed_mem_region = false,
285	.static_window_map = false,
286	.hybrid_bus_type = false,
287	.fixed_fw_mem = false,
288	.support_off_channel_tx = true,
289	.supports_multi_bssid = true,
290
291	.sram_dump = {
292	.start = 0x01400000,
293	.end = 0x0171ffff,
294	},
295
296	.tcl_ring_retry = true,
297	.tx_ring_size = DP_TCL_DATA_RING_SIZE,
298	.smp2p_wow_exit = false,
299	.support_fw_mac_sequence = true,
300	.support_dual_stations = true,
301	.pdev_suspend = false,
302	},
303	{
304	.name = "qcn9074 hw1.0",
305	.hw_rev = ATH11K_HW_QCN9074_HW10,
306	.fw = {
307	.dir = "QCN9074/hw1.0",
308	.board_size = 256 * 1024,
309	.cal_offset = 128 * 1024,
310	},
311	.max_radios = 1,
312	.single_pdev_only = false,
313	.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074,
314	.hw_ops = &qcn9074_ops,
315	.ring_mask = &ath11k_hw_ring_mask_qcn9074,
316	.internal_sleep_clock = false,
317	.regs = &qcn9074_regs,
318	.host_ce_config = ath11k_host_ce_config_qcn9074,
319	.ce_count = 6,
320	.target_ce_config = ath11k_target_ce_config_wlan_qcn9074,
321	.target_ce_count = 9,
322	.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074,
323	.svc_to_ce_map_len = 18,
324	.ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
325	.rxdma1_enable = true,
326	.num_rxdma_per_pdev = 1,
327	.rx_mac_buf_ring = false,
328	.vdev_start_delay = false,
329	.htt_peer_map_v2 = true,
330
331	.spectral = {
332	.fft_sz = 2,
333	.fft_pad_sz = 0,
334	.summary_pad_sz = 16,
335	.fft_hdr_len = 24,
336	.max_fft_bins = 1024,
337	.fragment_160mhz = false,
338	},
339
340	.interface_modes = BIT(NL80211_IFTYPE_STATION) |
341	BIT(NL80211_IFTYPE_AP) |
342	BIT(NL80211_IFTYPE_MESH_POINT),
343	.supports_monitor = true,
344	.full_monitor_mode = true,
345	.supports_shadow_regs = false,
346	.idle_ps = false,
347	.supports_sta_ps = false,
348	.coldboot_cal_mm = false,
349	.coldboot_cal_ftm = true,
350	.cbcal_restart_fw = true,
351	.fw_mem_mode = 2,
352	.num_vdevs = 8,
353	.num_peers = 128,
354	.supports_suspend = false,
355	.hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
356	.supports_regdb = false,
357	.fix_l1ss = true,
358	.credit_flow = false,
359	.max_tx_ring = DP_TCL_NUM_RING_MAX,
360	.hal_params = &ath11k_hw_hal_params_ipq8074,
361	.supports_dynamic_smps_6ghz = true,
362	.alloc_cacheable_memory = true,
363	.supports_rssi_stats = false,
364	.fw_wmi_diag_event = false,
365	.current_cc_support = false,
366	.dbr_debug_support = true,
367	.global_reset = false,
368	.bios_sar_capa = NULL,
369	.m3_fw_support = true,
370	.fixed_bdf_addr = false,
371	.fixed_mem_region = false,
372	.static_window_map = true,
373	.hybrid_bus_type = false,
374	.fixed_fw_mem = false,
375	.support_off_channel_tx = false,
376	.supports_multi_bssid = false,
377
378	.sram_dump = {},
379
380	.tcl_ring_retry = true,
381	.tx_ring_size = DP_TCL_DATA_RING_SIZE,
382	.smp2p_wow_exit = false,
383	.support_fw_mac_sequence = false,
384	.support_dual_stations = false,
385	.pdev_suspend = false,
386	},
387	{
388	.name = "wcn6855 hw2.0",
389	.hw_rev = ATH11K_HW_WCN6855_HW20,
390	.fw = {
391	.dir = "WCN6855/hw2.0",
392	.board_size = 256 * 1024,
393	.cal_offset = 128 * 1024,
394	},
395	.max_radios = 3,
396	.bdf_addr = 0x4B0C0000,
397	.hw_ops = &wcn6855_ops,
398	.ring_mask = &ath11k_hw_ring_mask_qca6390,
399	.internal_sleep_clock = true,
400	.regs = &wcn6855_regs,
401	.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
402	.host_ce_config = ath11k_host_ce_config_qca6390,
403	.ce_count = 9,
404	.target_ce_config = ath11k_target_ce_config_wlan_qca6390,
405	.target_ce_count = 9,
406	.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
407	.svc_to_ce_map_len = 14,
408	.ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
409	.single_pdev_only = true,
410	.rxdma1_enable = false,
411	.num_rxdma_per_pdev = 2,
412	.rx_mac_buf_ring = true,
413	.vdev_start_delay = true,
414	.htt_peer_map_v2 = false,
415
416	.spectral = {
417	.fft_sz = 0,
418	.fft_pad_sz = 0,
419	.summary_pad_sz = 0,
420	.fft_hdr_len = 0,
421	.max_fft_bins = 0,
422	.fragment_160mhz = false,
423	},
424
425	.interface_modes = BIT(NL80211_IFTYPE_STATION) |
426	BIT(NL80211_IFTYPE_AP) |
427	BIT(NL80211_IFTYPE_P2P_DEVICE) |
428	BIT(NL80211_IFTYPE_P2P_CLIENT) |
429	BIT(NL80211_IFTYPE_P2P_GO),
430	.supports_monitor = false,
431	.full_monitor_mode = false,
432	.supports_shadow_regs = true,
433	.idle_ps = true,
434	.supports_sta_ps = true,
435	.coldboot_cal_mm = false,
436	.coldboot_cal_ftm = false,
437	.cbcal_restart_fw = false,
438	.fw_mem_mode = 0,
439	.num_vdevs = 2 + 1,
440	.num_peers = 512,
441	.supports_suspend = true,
442	.hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
443	.supports_regdb = true,
444	.fix_l1ss = false,
445	.credit_flow = true,
446	.max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
447	.hal_params = &ath11k_hw_hal_params_qca6390,
448	.supports_dynamic_smps_6ghz = false,
449	.alloc_cacheable_memory = false,
450	.supports_rssi_stats = true,
451	.fw_wmi_diag_event = true,
452	.current_cc_support = true,
453	.dbr_debug_support = false,
454	.global_reset = true,
455	.bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
456	.m3_fw_support = true,
457	.fixed_bdf_addr = false,
458	.fixed_mem_region = false,
459	.static_window_map = false,
460	.hybrid_bus_type = false,
461	.fixed_fw_mem = false,
462	.support_off_channel_tx = true,
463	.supports_multi_bssid = true,
464
465	.sram_dump = {
466	.start = 0x01400000,
467	.end = 0x0177ffff,
468	},
469
470	.tcl_ring_retry = true,
471	.tx_ring_size = DP_TCL_DATA_RING_SIZE,
472	.smp2p_wow_exit = false,
473	.support_fw_mac_sequence = true,
474	.support_dual_stations = true,
475	.pdev_suspend = false,
476	},
477	{
478	.name = "wcn6855 hw2.1",
479	.hw_rev = ATH11K_HW_WCN6855_HW21,
480	.fw = {
481	.dir = "WCN6855/hw2.1",
482	.board_size = 256 * 1024,
483	.cal_offset = 128 * 1024,
484	},
485	.max_radios = 3,
486	.bdf_addr = 0x4B0C0000,
487	.hw_ops = &wcn6855_ops,
488	.ring_mask = &ath11k_hw_ring_mask_qca6390,
489	.internal_sleep_clock = true,
490	.regs = &wcn6855_regs,
491	.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
492	.host_ce_config = ath11k_host_ce_config_qca6390,
493	.ce_count = 9,
494	.target_ce_config = ath11k_target_ce_config_wlan_qca6390,
495	.target_ce_count = 9,
496	.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
497	.svc_to_ce_map_len = 14,
498	.single_pdev_only = true,
499	.rxdma1_enable = false,
500	.num_rxdma_per_pdev = 2,
501	.rx_mac_buf_ring = true,
502	.vdev_start_delay = true,
503	.htt_peer_map_v2 = false,
504
505	.spectral = {
506	.fft_sz = 0,
507	.fft_pad_sz = 0,
508	.summary_pad_sz = 0,
509	.fft_hdr_len = 0,
510	.max_fft_bins = 0,
511	.fragment_160mhz = false,
512	},
513
514	.interface_modes = BIT(NL80211_IFTYPE_STATION) |
515	BIT(NL80211_IFTYPE_AP) |
516	BIT(NL80211_IFTYPE_P2P_DEVICE) |
517	BIT(NL80211_IFTYPE_P2P_CLIENT) |
518	BIT(NL80211_IFTYPE_P2P_GO),
519	.supports_monitor = false,
520	.supports_shadow_regs = true,
521	.idle_ps = true,
522	.supports_sta_ps = true,
523	.coldboot_cal_mm = false,
524	.coldboot_cal_ftm = false,
525	.cbcal_restart_fw = false,
526	.fw_mem_mode = 0,
527	.num_vdevs = 2 + 1,
528	.num_peers = 512,
529	.supports_suspend = true,
530	.hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
531	.supports_regdb = true,
532	.fix_l1ss = false,
533	.credit_flow = true,
534	.max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
535	.hal_params = &ath11k_hw_hal_params_qca6390,
536	.supports_dynamic_smps_6ghz = false,
537	.alloc_cacheable_memory = false,
538	.supports_rssi_stats = true,
539	.fw_wmi_diag_event = true,
540	.current_cc_support = true,
541	.dbr_debug_support = false,
542	.global_reset = true,
543	.bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
544	.m3_fw_support = true,
545	.fixed_bdf_addr = false,
546	.fixed_mem_region = false,
547	.static_window_map = false,
548	.hybrid_bus_type = false,
549	.fixed_fw_mem = false,
550	.support_off_channel_tx = true,
551	.supports_multi_bssid = true,
552
553	.sram_dump = {
554	.start = 0x01400000,
555	.end = 0x0177ffff,
556	},
557
558	.tcl_ring_retry = true,
559	.tx_ring_size = DP_TCL_DATA_RING_SIZE,
560	.smp2p_wow_exit = false,
561	.support_fw_mac_sequence = true,
562	.support_dual_stations = true,
563	.pdev_suspend = false,
564	},
565	{
566	.name = "wcn6750 hw1.0",
567	.hw_rev = ATH11K_HW_WCN6750_HW10,
568	.fw = {
569	.dir = "WCN6750/hw1.0",
570	.board_size = 256 * 1024,
571	.cal_offset = 128 * 1024,
572	},
573	.max_radios = 1,
574	.bdf_addr = 0x4B0C0000,
575	.hw_ops = &wcn6750_ops,
576	.ring_mask = &ath11k_hw_ring_mask_wcn6750,
577	.internal_sleep_clock = false,
578	.regs = &wcn6750_regs,
579	.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750,
580	.host_ce_config = ath11k_host_ce_config_qca6390,
581	.ce_count = 9,
582	.target_ce_config = ath11k_target_ce_config_wlan_qca6390,
583	.target_ce_count = 9,
584	.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
585	.svc_to_ce_map_len = 14,
586	.ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
587	.single_pdev_only = true,
588	.rxdma1_enable = false,
589	.num_rxdma_per_pdev = 1,
590	.rx_mac_buf_ring = true,
591	.vdev_start_delay = true,
592	.htt_peer_map_v2 = false,
593
594	.spectral = {
595	.fft_sz = 0,
596	.fft_pad_sz = 0,
597	.summary_pad_sz = 0,
598	.fft_hdr_len = 0,
599	.max_fft_bins = 0,
600	.fragment_160mhz = false,
601	},
602
603	.interface_modes = BIT(NL80211_IFTYPE_STATION) |
604	BIT(NL80211_IFTYPE_AP),
605	.supports_monitor = false,
606	.supports_shadow_regs = true,
607	.idle_ps = true,
608	.supports_sta_ps = true,
609	.coldboot_cal_mm = true,
610	.coldboot_cal_ftm = true,
611	.cbcal_restart_fw = false,
612	.fw_mem_mode = 0,
613	.num_vdevs = 3,
614	.num_peers = 512,
615	.supports_suspend = false,
616	.hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
617	.supports_regdb = true,
618	.fix_l1ss = false,
619	.credit_flow = true,
620	.max_tx_ring = DP_TCL_NUM_RING_MAX,
621	.hal_params = &ath11k_hw_hal_params_wcn6750,
622	.supports_dynamic_smps_6ghz = false,
623	.alloc_cacheable_memory = false,
624	.supports_rssi_stats = true,
625	.fw_wmi_diag_event = true,
626	.current_cc_support = true,
627	.dbr_debug_support = false,
628	.global_reset = false,
629	.bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
630	.m3_fw_support = false,
631	.fixed_bdf_addr = false,
632	.fixed_mem_region = false,
633	.static_window_map = true,
634	.hybrid_bus_type = true,
635	.fixed_fw_mem = true,
636	.support_off_channel_tx = true,
637	.supports_multi_bssid = true,
638
639	.sram_dump = {},
640
641	.tcl_ring_retry = false,
642	.tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750,
643	.smp2p_wow_exit = true,
644	.support_fw_mac_sequence = true,
645	.support_dual_stations = false,
646	.pdev_suspend = true,
647	},
648	{
649	.hw_rev = ATH11K_HW_IPQ5018_HW10,
650	.name = "ipq5018 hw1.0",
651	.fw = {
652	.dir = "IPQ5018/hw1.0",
653	.board_size = 256 * 1024,
654	.cal_offset = 128 * 1024,
655	},
656	.max_radios = MAX_RADIOS_5018,
657	.bdf_addr = 0x4BA00000,
658	/* hal_desc_sz and hw ops are similar to qcn9074 */
659	.hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
660	.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
661	.ring_mask = &ath11k_hw_ring_mask_ipq8074,
662	.credit_flow = false,
663	.max_tx_ring = 1,
664	.spectral = {
665	.fft_sz = 2,
666	.fft_pad_sz = 0,
667	.summary_pad_sz = 16,
668	.fft_hdr_len = 24,
669	.max_fft_bins = 1024,
670	},
671	.internal_sleep_clock = false,
672	.regs = &ipq5018_regs,
673	.hw_ops = &ipq5018_ops,
674	.host_ce_config = ath11k_host_ce_config_qcn9074,
675	.ce_count = CE_CNT_5018,
676	.target_ce_config = ath11k_target_ce_config_wlan_ipq5018,
677	.target_ce_count = TARGET_CE_CNT_5018,
678	.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq5018,
679	.svc_to_ce_map_len = SVC_CE_MAP_LEN_5018,
680	.ce_ie_addr = &ath11k_ce_ie_addr_ipq5018,
681	.ce_remap = &ath11k_ce_remap_ipq5018,
682	.rxdma1_enable = true,
683	.num_rxdma_per_pdev = RXDMA_PER_PDEV_5018,
684	.rx_mac_buf_ring = false,
685	.vdev_start_delay = false,
686	.htt_peer_map_v2 = true,
687	.interface_modes = BIT(NL80211_IFTYPE_STATION) |
688	BIT(NL80211_IFTYPE_AP) |
689	BIT(NL80211_IFTYPE_MESH_POINT),
690	.supports_monitor = false,
691	.supports_sta_ps = false,
692	.supports_shadow_regs = false,
693	.fw_mem_mode = 0,
694	.num_vdevs = 16 + 1,
695	.num_peers = 512,
696	.supports_regdb = false,
697	.idle_ps = false,
698	.supports_suspend = false,
699	.hal_params = &ath11k_hw_hal_params_ipq8074,
700	.single_pdev_only = false,
701	.coldboot_cal_mm = true,
702	.coldboot_cal_ftm = true,
703	.cbcal_restart_fw = true,
704	.fix_l1ss = true,
705	.supports_dynamic_smps_6ghz = false,
706	.alloc_cacheable_memory = true,
707	.supports_rssi_stats = false,
708	.fw_wmi_diag_event = false,
709	.current_cc_support = false,
710	.dbr_debug_support = true,
711	.global_reset = false,
712	.bios_sar_capa = NULL,
713	.m3_fw_support = false,
714	.fixed_bdf_addr = true,
715	.fixed_mem_region = true,
716	.static_window_map = false,
717	.hybrid_bus_type = false,
718	.fixed_fw_mem = false,
719	.support_off_channel_tx = false,
720	.supports_multi_bssid = false,
721
722	.sram_dump = {},
723
724	.tcl_ring_retry = true,
725	.tx_ring_size = DP_TCL_DATA_RING_SIZE,
726	.smp2p_wow_exit = false,
727	.support_fw_mac_sequence = false,
728	.support_dual_stations = false,
729	.pdev_suspend = false,
730	},
731	{
732	.name = "qca2066 hw2.1",
733	.hw_rev = ATH11K_HW_QCA2066_HW21,
734	.fw = {
735	.dir = "QCA2066/hw2.1",
736	.board_size = 256 * 1024,
737	.cal_offset = 128 * 1024,
738	},
739	.max_radios = 3,
740	.bdf_addr = 0x4B0C0000,
741	.hw_ops = &wcn6855_ops,
742	.ring_mask = &ath11k_hw_ring_mask_qca6390,
743	.internal_sleep_clock = true,
744	.regs = &wcn6855_regs,
745	.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
746	.host_ce_config = ath11k_host_ce_config_qca6390,
747	.ce_count = 9,
748	.target_ce_config = ath11k_target_ce_config_wlan_qca6390,
749	.target_ce_count = 9,
750	.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
751	.svc_to_ce_map_len = 14,
752	.ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
753	.single_pdev_only = true,
754	.rxdma1_enable = false,
755	.num_rxdma_per_pdev = 2,
756	.rx_mac_buf_ring = true,
757	.vdev_start_delay = true,
758	.htt_peer_map_v2 = false,
759
760	.spectral = {
761	.fft_sz = 0,
762	.fft_pad_sz = 0,
763	.summary_pad_sz = 0,
764	.fft_hdr_len = 0,
765	.max_fft_bins = 0,
766	.fragment_160mhz = false,
767	},
768
769	.interface_modes = BIT(NL80211_IFTYPE_STATION) |
770	BIT(NL80211_IFTYPE_AP) |
771	BIT(NL80211_IFTYPE_P2P_DEVICE) |
772	BIT(NL80211_IFTYPE_P2P_CLIENT) |
773	BIT(NL80211_IFTYPE_P2P_GO),
774	.supports_monitor = false,
775	.full_monitor_mode = false,
776	.supports_shadow_regs = true,
777	.idle_ps = true,
778	.supports_sta_ps = true,
779	.coldboot_cal_mm = false,
780	.coldboot_cal_ftm = false,
781	.cbcal_restart_fw = false,
782	.fw_mem_mode = 0,
783	.num_vdevs = 2 + 1,
784	.num_peers = 512,
785	.supports_suspend = true,
786	.hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
787	.supports_regdb = true,
788	.fix_l1ss = false,
789	.credit_flow = true,
790	.max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
791	.hal_params = &ath11k_hw_hal_params_qca6390,
792	.supports_dynamic_smps_6ghz = false,
793	.alloc_cacheable_memory = false,
794	.supports_rssi_stats = true,
795	.fw_wmi_diag_event = true,
796	.current_cc_support = true,
797	.dbr_debug_support = false,
798	.global_reset = true,
799	.bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
800	.m3_fw_support = true,
801	.fixed_bdf_addr = false,
802	.fixed_mem_region = false,
803	.static_window_map = false,
804	.hybrid_bus_type = false,
805	.fixed_fw_mem = false,
806	.support_off_channel_tx = true,
807	.supports_multi_bssid = true,
808
809	.sram_dump = {
810	.start = 0x01400000,
811	.end = 0x0177ffff,
812	},
813
814	.tcl_ring_retry = true,
815	.tx_ring_size = DP_TCL_DATA_RING_SIZE,
816	.smp2p_wow_exit = false,
817	.support_fw_mac_sequence = true,
818	.support_dual_stations = true,
819	},
820	{
821	.name = "qca6698aq hw2.1",
822	.hw_rev = ATH11K_HW_QCA6698AQ_HW21,
823	.fw = {
824	.dir = "QCA6698AQ/hw2.1",
825	.board_size = 256 * 1024,
826	.cal_offset = 128 * 1024,
827	},
828	.max_radios = 3,
829	.bdf_addr = 0x4B0C0000,
830	.hw_ops = &wcn6855_ops,
831	.ring_mask = &ath11k_hw_ring_mask_qca6390,
832	.internal_sleep_clock = true,
833	.regs = &wcn6855_regs,
834	.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
835	.host_ce_config = ath11k_host_ce_config_qca6390,
836	.ce_count = 9,
837	.target_ce_config = ath11k_target_ce_config_wlan_qca6390,
838	.target_ce_count = 9,
839	.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
840	.svc_to_ce_map_len = 14,
841	.single_pdev_only = true,
842	.rxdma1_enable = false,
843	.num_rxdma_per_pdev = 2,
844	.rx_mac_buf_ring = true,
845	.vdev_start_delay = true,
846	.htt_peer_map_v2 = false,
847
848	.spectral = {
849	.fft_sz = 0,
850	.fft_pad_sz = 0,
851	.summary_pad_sz = 0,
852	.fft_hdr_len = 0,
853	.max_fft_bins = 0,
854	.fragment_160mhz = false,
855	},
856
857	.interface_modes = BIT(NL80211_IFTYPE_STATION) |
858	BIT(NL80211_IFTYPE_AP) |
859	BIT(NL80211_IFTYPE_P2P_DEVICE) |
860	BIT(NL80211_IFTYPE_P2P_CLIENT) |
861	BIT(NL80211_IFTYPE_P2P_GO),
862	.supports_monitor = false,
863	.supports_shadow_regs = true,
864	.idle_ps = true,
865	.supports_sta_ps = true,
866	.coldboot_cal_mm = false,
867	.coldboot_cal_ftm = false,
868	.cbcal_restart_fw = false,
869	.fw_mem_mode = 0,
870	.num_vdevs = 2 + 1,
871	.num_peers = 512,
872	.supports_suspend = true,
873	.hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
874	.supports_regdb = true,
875	.fix_l1ss = false,
876	.credit_flow = true,
877	.max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
878	.hal_params = &ath11k_hw_hal_params_qca6390,
879	.supports_dynamic_smps_6ghz = false,
880	.alloc_cacheable_memory = false,
881	.supports_rssi_stats = true,
882	.fw_wmi_diag_event = true,
883	.current_cc_support = true,
884	.dbr_debug_support = false,
885	.global_reset = true,
886	.bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
887	.m3_fw_support = true,
888	.fixed_bdf_addr = false,
889	.fixed_mem_region = false,
890	.static_window_map = false,
891	.hybrid_bus_type = false,
892	.fixed_fw_mem = false,
893	.support_off_channel_tx = true,
894	.supports_multi_bssid = true,
895
896	.sram_dump = {
897	.start = 0x01400000,
898	.end = 0x0177ffff,
899	},
900
901	.tcl_ring_retry = true,
902	.tx_ring_size = DP_TCL_DATA_RING_SIZE,
903	.smp2p_wow_exit = false,
904	.support_fw_mac_sequence = true,
905	.support_dual_stations = true,
906	.pdev_suspend = false,
907	},
908	};
909
910	static const struct dmi_system_id ath11k_pm_quirk_table[] = {
911	{
912	.driver_data = (void *)ATH11K_PM_WOW,
913	.matches = {
914	DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
915	DMI_MATCH(DMI_PRODUCT_NAME, "21J4"),
916	},
917	},
918	{
919	.driver_data = (void *)ATH11K_PM_WOW,
920	.matches = {
921	DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
922	DMI_MATCH(DMI_PRODUCT_NAME, "21K4"),
923	},
924	},
925	{
926	.driver_data = (void *)ATH11K_PM_WOW,
927	.matches = {
928	DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
929	DMI_MATCH(DMI_PRODUCT_NAME, "21K6"),
930	},
931	},
932	{
933	.driver_data = (void *)ATH11K_PM_WOW,
934	.matches = {
935	DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
936	DMI_MATCH(DMI_PRODUCT_NAME, "21K8"),
937	},
938	},
939	{
940	.driver_data = (void *)ATH11K_PM_WOW,
941	.matches = {
942	DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
943	DMI_MATCH(DMI_PRODUCT_NAME, "21KA"),
944	},
945	},
946	{
947	.driver_data = (void *)ATH11K_PM_WOW,
948	.matches = {
949	DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
950	DMI_MATCH(DMI_PRODUCT_NAME, "21F9"),
951	},
952	},
953	{}
954	};
955
956	void ath11k_fw_stats_pdevs_free(struct list_head *head)
957	{
958	struct ath11k_fw_stats_pdev *i, *tmp;
959
960	list_for_each_entry_safe(i, tmp, head, list) {
961	list_del(entry: &i->list);
962	kfree(objp: i);
963	}
964	}
965
966	void ath11k_fw_stats_vdevs_free(struct list_head *head)
967	{
968	struct ath11k_fw_stats_vdev *i, *tmp;
969
970	list_for_each_entry_safe(i, tmp, head, list) {
971	list_del(entry: &i->list);
972	kfree(objp: i);
973	}
974	}
975
976	void ath11k_fw_stats_bcn_free(struct list_head *head)
977	{
978	struct ath11k_fw_stats_bcn *i, *tmp;
979
980	list_for_each_entry_safe(i, tmp, head, list) {
981	list_del(entry: &i->list);
982	kfree(objp: i);
983	}
984	}
985
986	void ath11k_fw_stats_init(struct ath11k *ar)
987	{
988	INIT_LIST_HEAD(list: &ar->fw_stats.pdevs);
989	INIT_LIST_HEAD(list: &ar->fw_stats.vdevs);
990	INIT_LIST_HEAD(list: &ar->fw_stats.bcn);
991
992	init_completion(x: &ar->fw_stats_complete);
993	}
994
995	void ath11k_fw_stats_free(struct ath11k_fw_stats *stats)
996	{
997	ath11k_fw_stats_pdevs_free(head: &stats->pdevs);
998	ath11k_fw_stats_vdevs_free(head: &stats->vdevs);
999	ath11k_fw_stats_bcn_free(head: &stats->bcn);
1000	}
1001
1002	bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab)
1003	{
1004	if (!ath11k_cold_boot_cal)
1005	return false;
1006
1007	if (ath11k_ftm_mode)
1008	return ab->hw_params.coldboot_cal_ftm;
1009
1010	else
1011	return ab->hw_params.coldboot_cal_mm;
1012	}
1013
1014	/* Check if we need to continue with suspend/resume operation.
1015	* Return:
1016	* a negative value: error happens and don't continue.
1017	* 0: no error but don't continue.
1018	* positive value: no error and do continue.
1019	*/
1020	static int ath11k_core_continue_suspend_resume(struct ath11k_base *ab)
1021	{
1022	struct ath11k *ar;
1023
1024	if (!ab->hw_params.supports_suspend)
1025	return -EOPNOTSUPP;
1026
1027	/* so far single_pdev_only chips have supports_suspend as true
1028	* so pass 0 as a dummy pdev_id here.
1029	*/
1030	ar = ab->pdevs[0].ar;
1031	if (!ar || ar->state != ATH11K_STATE_OFF)
1032	return 0;
1033
1034	return 1;
1035	}
1036
1037	static int ath11k_core_suspend_wow(struct ath11k_base *ab)
1038	{
1039	int ret;
1040
1041	ret = ath11k_dp_rx_pktlog_stop(ab, stop_timer: true);
1042	if (ret) {
1043	ath11k_warn(ab, fmt: "failed to stop dp rx (and timer) pktlog during suspend: %d\n",
1044	ret);
1045	return ret;
1046	}
1047
1048	/* So far only single_pdev_only devices can reach here,
1049	* so it is valid to handle the first, and the only, pdev.
1050	*/
1051	ret = ath11k_mac_wait_tx_complete(ar: ab->pdevs[0].ar);
1052	if (ret) {
1053	ath11k_warn(ab, fmt: "failed to wait tx complete: %d\n", ret);
1054	return ret;
1055	}
1056
1057	ret = ath11k_wow_enable(ab);
1058	if (ret) {
1059	ath11k_warn(ab, fmt: "failed to enable wow during suspend: %d\n", ret);
1060	return ret;
1061	}
1062
1063	ret = ath11k_dp_rx_pktlog_stop(ab, stop_timer: false);
1064	if (ret) {
1065	ath11k_warn(ab, fmt: "failed to stop dp rx pktlog during suspend: %d\n",
1066	ret);
1067	return ret;
1068	}
1069
1070	ath11k_ce_stop_shadow_timers(ab);
1071	ath11k_dp_stop_shadow_timers(ab);
1072
1073	ath11k_hif_irq_disable(ab);
1074	ath11k_hif_ce_irq_disable(ab);
1075
1076	ret = ath11k_hif_suspend(ab);
1077	if (ret) {
1078	ath11k_warn(ab, fmt: "failed to suspend hif: %d\n", ret);
1079	return ret;
1080	}
1081
1082	return 0;
1083	}
1084
1085	static int ath11k_core_suspend_default(struct ath11k_base *ab)
1086	{
1087	int ret;
1088
1089	ret = ath11k_dp_rx_pktlog_stop(ab, stop_timer: true);
1090	if (ret) {
1091	ath11k_warn(ab, fmt: "failed to stop dp rx (and timer) pktlog during suspend: %d\n",
1092	ret);
1093	return ret;
1094	}
1095
1096	/* So far only single_pdev_only devices can reach here,
1097	* so it is valid to handle the first, and the only, pdev.
1098	*/
1099	ret = ath11k_mac_wait_tx_complete(ar: ab->pdevs[0].ar);
1100	if (ret) {
1101	ath11k_warn(ab, fmt: "failed to wait tx complete: %d\n", ret);
1102	return ret;
1103	}
1104
1105	ret = ath11k_dp_rx_pktlog_stop(ab, stop_timer: false);
1106	if (ret) {
1107	ath11k_warn(ab, fmt: "failed to stop dp rx pktlog during suspend: %d\n",
1108	ret);
1109	return ret;
1110	}
1111
1112	ath11k_ce_stop_shadow_timers(ab);
1113	ath11k_dp_stop_shadow_timers(ab);
1114
1115	/* PM framework skips suspend_late/resume_early callbacks
1116	* if other devices report errors in their suspend callbacks.
1117	* However ath11k_core_resume() would still be called because
1118	* here we return success thus kernel put us on dpm_suspended_list.
1119	* Since we won't go through a power down/up cycle, there is
1120	* no chance to call complete(&ab->restart_completed) in
1121	* ath11k_core_restart(), making ath11k_core_resume() timeout.
1122	* So call it here to avoid this issue. This also works in case
1123	* no error happens thus suspend_late/resume_early get called,
1124	* because it will be reinitialized in ath11k_core_resume_early().
1125	*/
1126	complete(&ab->restart_completed);
1127
1128	return 0;
1129	}
1130
1131	int ath11k_core_suspend(struct ath11k_base *ab)
1132	{
1133	int ret;
1134
1135	ret = ath11k_core_continue_suspend_resume(ab);
1136	if (ret <= 0)
1137	return ret;
1138
1139	if (ab->actual_pm_policy == ATH11K_PM_WOW)
1140	return ath11k_core_suspend_wow(ab);
1141
1142	return ath11k_core_suspend_default(ab);
1143	}
1144	EXPORT_SYMBOL(ath11k_core_suspend);
1145
1146	int ath11k_core_suspend_late(struct ath11k_base *ab)
1147	{
1148	int ret;
1149
1150	ret = ath11k_core_continue_suspend_resume(ab);
1151	if (ret <= 0)
1152	return ret;
1153
1154	if (ab->actual_pm_policy == ATH11K_PM_WOW)
1155	return 0;
1156
1157	ath11k_hif_irq_disable(ab);
1158	ath11k_hif_ce_irq_disable(ab);
1159
1160	ath11k_hif_power_down(ab, is_suspend: true);
1161
1162	return 0;
1163	}
1164	EXPORT_SYMBOL(ath11k_core_suspend_late);
1165
1166	int ath11k_core_resume_early(struct ath11k_base *ab)
1167	{
1168	int ret;
1169
1170	ret = ath11k_core_continue_suspend_resume(ab);
1171	if (ret <= 0)
1172	return ret;
1173
1174	if (ab->actual_pm_policy == ATH11K_PM_WOW)
1175	return 0;
1176
1177	reinit_completion(x: &ab->restart_completed);
1178	ret = ath11k_hif_power_up(ab);
1179	if (ret)
1180	ath11k_warn(ab, fmt: "failed to power up hif during resume: %d\n", ret);
1181
1182	return ret;
1183	}
1184	EXPORT_SYMBOL(ath11k_core_resume_early);
1185
1186	static int ath11k_core_resume_default(struct ath11k_base *ab)
1187	{
1188	struct ath11k *ar;
1189	long time_left;
1190	int ret;
1191
1192	time_left = wait_for_completion_timeout(x: &ab->restart_completed,
1193	ATH11K_RESET_TIMEOUT_HZ);
1194	if (time_left == 0) {
1195	ath11k_warn(ab, fmt: "timeout while waiting for restart complete");
1196	return -ETIMEDOUT;
1197	}
1198
1199	/* So far only single_pdev_only devices can reach here,
1200	* so it is valid to handle the first, and the only, pdev.
1201	*/
1202	ar = ab->pdevs[0].ar;
1203	if (ab->hw_params.current_cc_support &&
1204	ar->alpha2[0] != 0 && ar->alpha2[1] != 0) {
1205	ret = ath11k_reg_set_cc(ar);
1206	if (ret) {
1207	ath11k_warn(ab, fmt: "failed to set country code during resume: %d\n",
1208	ret);
1209	return ret;
1210	}
1211	}
1212
1213	ret = ath11k_dp_rx_pktlog_start(ab);
1214	if (ret)
1215	ath11k_warn(ab, fmt: "failed to start rx pktlog during resume: %d\n",
1216	ret);
1217
1218	return ret;
1219	}
1220
1221	static int ath11k_core_resume_wow(struct ath11k_base *ab)
1222	{
1223	int ret;
1224
1225	ret = ath11k_hif_resume(ab);
1226	if (ret) {
1227	ath11k_warn(ab, fmt: "failed to resume hif during resume: %d\n", ret);
1228	return ret;
1229	}
1230
1231	ath11k_hif_ce_irq_enable(ab);
1232	ath11k_hif_irq_enable(ab);
1233
1234	ret = ath11k_dp_rx_pktlog_start(ab);
1235	if (ret) {
1236	ath11k_warn(ab, fmt: "failed to start rx pktlog during resume: %d\n",
1237	ret);
1238	return ret;
1239	}
1240
1241	ret = ath11k_wow_wakeup(ab);
1242	if (ret) {
1243	ath11k_warn(ab, fmt: "failed to wakeup wow during resume: %d\n", ret);
1244	return ret;
1245	}
1246
1247	return 0;
1248	}
1249
1250	int ath11k_core_resume(struct ath11k_base *ab)
1251	{
1252	int ret;
1253
1254	ret = ath11k_core_continue_suspend_resume(ab);
1255	if (ret <= 0)
1256	return ret;
1257
1258	if (ab->actual_pm_policy == ATH11K_PM_WOW)
1259	return ath11k_core_resume_wow(ab);
1260
1261	return ath11k_core_resume_default(ab);
1262	}
1263	EXPORT_SYMBOL(ath11k_core_resume);
1264
1265	static void ath11k_core_check_cc_code_bdfext(const struct dmi_header *hdr, void *data)
1266	{
1267	struct ath11k_base *ab = data;
1268	const char *magic = ATH11K_SMBIOS_BDF_EXT_MAGIC;
1269	struct ath11k_smbios_bdf *smbios = (struct ath11k_smbios_bdf *)hdr;
1270	ssize_t copied;
1271	size_t len;
1272	int i;
1273
1274	if (ab->qmi.target.bdf_ext[0] != '\0')
1275	return;
1276
1277	if (hdr->type != ATH11K_SMBIOS_BDF_EXT_TYPE)
1278	return;
1279
1280	if (hdr->length != ATH11K_SMBIOS_BDF_EXT_LENGTH) {
1281	ath11k_dbg(ab, ATH11K_DBG_BOOT,
1282	"wrong smbios bdf ext type length (%d).\n",
1283	hdr->length);
1284	return;
1285	}
1286
1287	spin_lock_bh(lock: &ab->base_lock);
1288
1289	switch (smbios->country_code_flag) {
1290	case ATH11K_SMBIOS_CC_ISO:
1291	ab->new_alpha2[0] = (smbios->cc_code >> 8) & 0xff;
1292	ab->new_alpha2[1] = smbios->cc_code & 0xff;
1293	ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios cc_code %c%c\n",
1294	ab->new_alpha2[0], ab->new_alpha2[1]);
1295	break;
1296	case ATH11K_SMBIOS_CC_WW:
1297	ab->new_alpha2[0] = '0';
1298	ab->new_alpha2[1] = '0';
1299	ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios worldwide regdomain\n");
1300	break;
1301	default:
1302	ath11k_dbg(ab, ATH11K_DBG_BOOT, "ignore smbios country code setting %d\n",
1303	smbios->country_code_flag);
1304	break;
1305	}
1306
1307	spin_unlock_bh(lock: &ab->base_lock);
1308
1309	if (!smbios->bdf_enabled) {
1310	ath11k_dbg(ab, ATH11K_DBG_BOOT, "bdf variant name not found.\n");
1311	return;
1312	}
1313
1314	/* Only one string exists (per spec) */
1315	if (memcmp(p: smbios->bdf_ext, q: magic, strlen(magic)) != 0) {
1316	ath11k_dbg(ab, ATH11K_DBG_BOOT,
1317	"bdf variant magic does not match.\n");
1318	return;
1319	}
1320
1321	len = min_t(size_t,
1322	strlen(smbios->bdf_ext), sizeof(ab->qmi.target.bdf_ext));
1323	for (i = 0; i < len; i++) {
1324	if (!isascii(smbios->bdf_ext[i]) || !isprint(smbios->bdf_ext[i])) {
1325	ath11k_dbg(ab, ATH11K_DBG_BOOT,
1326	"bdf variant name contains non ascii chars.\n");
1327	return;
1328	}
1329	}
1330
1331	/* Copy extension name without magic prefix */
1332	copied = strscpy(ab->qmi.target.bdf_ext, smbios->bdf_ext + strlen(magic),
1333	sizeof(ab->qmi.target.bdf_ext));
1334	if (copied < 0) {
1335	ath11k_dbg(ab, ATH11K_DBG_BOOT,
1336	"bdf variant string is longer than the buffer can accommodate\n");
1337	return;
1338	}
1339
1340	ath11k_dbg(ab, ATH11K_DBG_BOOT,
1341	"found and validated bdf variant smbios_type 0x%x bdf %s\n",
1342	ATH11K_SMBIOS_BDF_EXT_TYPE, ab->qmi.target.bdf_ext);
1343	}
1344
1345	int ath11k_core_check_smbios(struct ath11k_base *ab)
1346	{
1347	ab->qmi.target.bdf_ext[0] = '\0';
1348	dmi_walk(decode: ath11k_core_check_cc_code_bdfext, private_data: ab);
1349
1350	if (ab->qmi.target.bdf_ext[0] == '\0')
1351	return -ENODATA;
1352
1353	return 0;
1354	}
1355
1356	int ath11k_core_check_dt(struct ath11k_base *ab)
1357	{
1358	size_t max_len = sizeof(ab->qmi.target.bdf_ext);
1359	const char *variant = NULL;
1360	struct device_node *node;
1361
1362	node = ab->dev->of_node;
1363	if (!node)
1364	return -ENOENT;
1365
1366	of_property_read_string(np: node, propname: "qcom,calibration-variant",
1367	out_string: &variant);
1368	if (!variant)
1369	of_property_read_string(np: node, propname: "qcom,ath11k-calibration-variant",
1370	out_string: &variant);
1371	if (!variant)
1372	return -ENODATA;
1373
1374	if (strscpy(ab->qmi.target.bdf_ext, variant, max_len) < 0)
1375	ath11k_dbg(ab, ATH11K_DBG_BOOT,
1376	"bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
1377	variant);
1378
1379	return 0;
1380	}
1381
1382	enum ath11k_bdf_name_type {
1383	ATH11K_BDF_NAME_FULL,
1384	ATH11K_BDF_NAME_BUS_NAME,
1385	ATH11K_BDF_NAME_CHIP_ID,
1386	};
1387
1388	static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
1389	size_t name_len, bool with_variant,
1390	enum ath11k_bdf_name_type name_type)
1391	{
1392	/* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */
1393	char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = { 0 };
1394
1395	if (with_variant && ab->qmi.target.bdf_ext[0] != '\0')
1396	scnprintf(buf: variant, size: sizeof(variant), fmt: ",variant=%s",
1397	ab->qmi.target.bdf_ext);
1398
1399	switch (ab->id.bdf_search) {
1400	case ATH11K_BDF_SEARCH_BUS_AND_BOARD:
1401	switch (name_type) {
1402	case ATH11K_BDF_NAME_FULL:
1403	scnprintf(buf: name, size: name_len,
1404	fmt: "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s",
1405	ath11k_bus_str(bus: ab->hif.bus),
1406	ab->id.vendor, ab->id.device,
1407	ab->id.subsystem_vendor,
1408	ab->id.subsystem_device,
1409	ab->qmi.target.chip_id,
1410	ab->qmi.target.board_id,
1411	variant);
1412	break;
1413	case ATH11K_BDF_NAME_BUS_NAME:
1414	scnprintf(buf: name, size: name_len,
1415	fmt: "bus=%s",
1416	ath11k_bus_str(bus: ab->hif.bus));
1417	break;
1418	case ATH11K_BDF_NAME_CHIP_ID:
1419	scnprintf(buf: name, size: name_len,
1420	fmt: "bus=%s,qmi-chip-id=%d",
1421	ath11k_bus_str(bus: ab->hif.bus),
1422	ab->qmi.target.chip_id);
1423	break;
1424	}
1425	break;
1426	default:
1427	scnprintf(buf: name, size: name_len,
1428	fmt: "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s",
1429	ath11k_bus_str(bus: ab->hif.bus),
1430	ab->qmi.target.chip_id,
1431	ab->qmi.target.board_id, variant);
1432	break;
1433	}
1434
1435	ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board name '%s'\n", name);
1436
1437	return 0;
1438	}
1439
1440	static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
1441	size_t name_len)
1442	{
1443	return __ath11k_core_create_board_name(ab, name, name_len, with_variant: true,
1444	name_type: ATH11K_BDF_NAME_FULL);
1445	}
1446
1447	static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name,
1448	size_t name_len)
1449	{
1450	return __ath11k_core_create_board_name(ab, name, name_len, with_variant: false,
1451	name_type: ATH11K_BDF_NAME_FULL);
1452	}
1453
1454	static int ath11k_core_create_bus_type_board_name(struct ath11k_base *ab, char *name,
1455	size_t name_len)
1456	{
1457	return __ath11k_core_create_board_name(ab, name, name_len, with_variant: false,
1458	name_type: ATH11K_BDF_NAME_BUS_NAME);
1459	}
1460
1461	static int ath11k_core_create_chip_id_board_name(struct ath11k_base *ab, char *name,
1462	size_t name_len)
1463	{
1464	return __ath11k_core_create_board_name(ab, name, name_len, with_variant: false,
1465	name_type: ATH11K_BDF_NAME_CHIP_ID);
1466	}
1467
1468	const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab,
1469	const char *file)
1470	{
1471	const struct firmware *fw;
1472	char path[100];
1473	int ret;
1474
1475	if (file == NULL)
1476	return ERR_PTR(error: -ENOENT);
1477
1478	ath11k_core_create_firmware_path(ab, filename: file, buf: path, buf_len: sizeof(path));
1479
1480	ret = firmware_request_nowarn(fw: &fw, name: path, device: ab->dev);
1481	if (ret)
1482	return ERR_PTR(error: ret);
1483
1484	ath11k_dbg(ab, ATH11K_DBG_BOOT, "firmware request %s size %zu\n",
1485	path, fw->size);
1486
1487	return fw;
1488	}
1489
1490	void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
1491	{
1492	if (!IS_ERR(ptr: bd->fw))
1493	release_firmware(fw: bd->fw);
1494
1495	memset(bd, 0, sizeof(*bd));
1496	}
1497
1498	static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab,
1499	struct ath11k_board_data *bd,
1500	const void *buf, size_t buf_len,
1501	const char *boardname,
1502	int ie_id,
1503	int name_id,
1504	int data_id)
1505	{
1506	const struct ath11k_fw_ie *hdr;
1507	bool name_match_found;
1508	int ret, board_ie_id;
1509	size_t board_ie_len;
1510	const void *board_ie_data;
1511
1512	name_match_found = false;
1513
1514	/* go through ATH11K_BD_IE_BOARD_/ATH11K_BD_IE_REGDB_ elements */
1515	while (buf_len > sizeof(struct ath11k_fw_ie)) {
1516	hdr = buf;
1517	board_ie_id = le32_to_cpu(hdr->id);
1518	board_ie_len = le32_to_cpu(hdr->len);
1519	board_ie_data = hdr->data;
1520
1521	buf_len -= sizeof(*hdr);
1522	buf += sizeof(*hdr);
1523
1524	if (buf_len < ALIGN(board_ie_len, 4)) {
1525	ath11k_err(ab, fmt: "invalid %s length: %zu < %zu\n",
1526	ath11k_bd_ie_type_str(type: ie_id),
1527	buf_len, ALIGN(board_ie_len, 4));
1528	ret = -EINVAL;
1529	goto out;
1530	}
1531
1532	if (board_ie_id == name_id) {
1533	ath11k_dbg_dump(ab, mask: ATH11K_DBG_BOOT, msg: "board name", prefix: "",
1534	buf: board_ie_data, len: board_ie_len);
1535
1536	if (board_ie_len != strlen(boardname))
1537	goto next;
1538
1539	ret = memcmp(p: board_ie_data, q: boardname, strlen(boardname));
1540	if (ret)
1541	goto next;
1542
1543	name_match_found = true;
1544	ath11k_dbg(ab, ATH11K_DBG_BOOT,
1545	"found match %s for name '%s'",
1546	ath11k_bd_ie_type_str(ie_id),
1547	boardname);
1548	} else if (board_ie_id == data_id) {
1549	if (!name_match_found)
1550	/* no match found */
1551	goto next;
1552
1553	ath11k_dbg(ab, ATH11K_DBG_BOOT,
1554	"found %s for '%s'",
1555	ath11k_bd_ie_type_str(ie_id),
1556	boardname);
1557
1558	bd->data = board_ie_data;
1559	bd->len = board_ie_len;
1560
1561	ret = 0;
1562	goto out;
1563	} else {
1564	ath11k_warn(ab, fmt: "unknown %s id found: %d\n",
1565	ath11k_bd_ie_type_str(type: ie_id),
1566	board_ie_id);
1567	}
1568	next:
1569	/* jump over the padding */
1570	board_ie_len = ALIGN(board_ie_len, 4);
1571
1572	buf_len -= board_ie_len;
1573	buf += board_ie_len;
1574	}
1575
1576	/* no match found */
1577	ret = -ENOENT;
1578
1579	out:
1580	return ret;
1581	}
1582
1583	static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab,
1584	struct ath11k_board_data *bd,
1585	const char *boardname,
1586	int ie_id_match,
1587	int name_id,
1588	int data_id)
1589	{
1590	size_t len, magic_len;
1591	const u8 *data;
1592	char *filename, filepath[100];
1593	size_t ie_len;
1594	struct ath11k_fw_ie *hdr;
1595	int ret, ie_id;
1596
1597	filename = ATH11K_BOARD_API2_FILE;
1598
1599	if (!bd->fw)
1600	bd->fw = ath11k_core_firmware_request(ab, file: filename);
1601
1602	if (IS_ERR(ptr: bd->fw))
1603	return PTR_ERR(ptr: bd->fw);
1604
1605	data = bd->fw->data;
1606	len = bd->fw->size;
1607
1608	ath11k_core_create_firmware_path(ab, filename,
1609	buf: filepath, buf_len: sizeof(filepath));
1610
1611	/* magic has extra null byte padded */
1612	magic_len = strlen(ATH11K_BOARD_MAGIC) + 1;
1613	if (len < magic_len) {
1614	ath11k_err(ab, fmt: "failed to find magic value in %s, file too short: %zu\n",
1615	filepath, len);
1616	ret = -EINVAL;
1617	goto err;
1618	}
1619
1620	if (memcmp(p: data, ATH11K_BOARD_MAGIC, size: magic_len)) {
1621	ath11k_err(ab, fmt: "found invalid board magic\n");
1622	ret = -EINVAL;
1623	goto err;
1624	}
1625
1626	/* magic is padded to 4 bytes */
1627	magic_len = ALIGN(magic_len, 4);
1628	if (len < magic_len) {
1629	ath11k_err(ab, fmt: "failed: %s too small to contain board data, len: %zu\n",
1630	filepath, len);
1631	ret = -EINVAL;
1632	goto err;
1633	}
1634
1635	data += magic_len;
1636	len -= magic_len;
1637
1638	while (len > sizeof(struct ath11k_fw_ie)) {
1639	hdr = (struct ath11k_fw_ie *)data;
1640	ie_id = le32_to_cpu(hdr->id);
1641	ie_len = le32_to_cpu(hdr->len);
1642
1643	len -= sizeof(*hdr);
1644	data = hdr->data;
1645
1646	if (len < ALIGN(ie_len, 4)) {
1647	ath11k_err(ab, fmt: "invalid length for board ie_id %d ie_len %zu len %zu\n",
1648	ie_id, ie_len, len);
1649	ret = -EINVAL;
1650	goto err;
1651	}
1652
1653	if (ie_id == ie_id_match) {
1654	ret = ath11k_core_parse_bd_ie_board(ab, bd, buf: data,
1655	buf_len: ie_len,
1656	boardname,
1657	ie_id: ie_id_match,
1658	name_id,
1659	data_id);
1660	if (ret == -ENOENT)
1661	/* no match found, continue */
1662	goto next;
1663	else if (ret)
1664	/* there was an error, bail out */
1665	goto err;
1666	/* either found or error, so stop searching */
1667	goto out;
1668	}
1669	next:
1670	/* jump over the padding */
1671	ie_len = ALIGN(ie_len, 4);
1672
1673	len -= ie_len;
1674	data += ie_len;
1675	}
1676
1677	out:
1678	if (!bd->data || !bd->len) {
1679	ath11k_dbg(ab, ATH11K_DBG_BOOT,
1680	"failed to fetch %s for %s from %s\n",
1681	ath11k_bd_ie_type_str(ie_id_match),
1682	boardname, filepath);
1683	ret = -ENODATA;
1684	goto err;
1685	}
1686
1687	return 0;
1688
1689	err:
1690	ath11k_core_free_bdf(ab, bd);
1691	return ret;
1692	}
1693
1694	int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab,
1695	struct ath11k_board_data *bd,
1696	const char *name)
1697	{
1698	bd->fw = ath11k_core_firmware_request(ab, file: name);
1699
1700	if (IS_ERR(ptr: bd->fw))
1701	return PTR_ERR(ptr: bd->fw);
1702
1703	bd->data = bd->fw->data;
1704	bd->len = bd->fw->size;
1705
1706	return 0;
1707	}
1708
1709	#define BOARD_NAME_SIZE 200
1710	int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
1711	{
1712	char *boardname = NULL, *fallback_boardname = NULL, *chip_id_boardname = NULL;
1713	char *filename, filepath[100];
1714	int bd_api;
1715	int ret = 0;
1716
1717	filename = ATH11K_BOARD_API2_FILE;
1718	boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL);
1719	if (!boardname) {
1720	ret = -ENOMEM;
1721	goto exit;
1722	}
1723
1724	ret = ath11k_core_create_board_name(ab, name: boardname, BOARD_NAME_SIZE);
1725	if (ret) {
1726	ath11k_err(ab, fmt: "failed to create board name: %d", ret);
1727	goto exit;
1728	}
1729
1730	bd_api = 2;
1731	ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
1732	ie_id_match: ATH11K_BD_IE_BOARD,
1733	name_id: ATH11K_BD_IE_BOARD_NAME,
1734	data_id: ATH11K_BD_IE_BOARD_DATA);
1735	if (!ret)
1736	goto exit;
1737
1738	fallback_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL);
1739	if (!fallback_boardname) {
1740	ret = -ENOMEM;
1741	goto exit;
1742	}
1743
1744	ret = ath11k_core_create_fallback_board_name(ab, name: fallback_boardname,
1745	BOARD_NAME_SIZE);
1746	if (ret) {
1747	ath11k_err(ab, fmt: "failed to create fallback board name: %d", ret);
1748	goto exit;
1749	}
1750
1751	ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname: fallback_boardname,
1752	ie_id_match: ATH11K_BD_IE_BOARD,
1753	name_id: ATH11K_BD_IE_BOARD_NAME,
1754	data_id: ATH11K_BD_IE_BOARD_DATA);
1755	if (!ret)
1756	goto exit;
1757
1758	chip_id_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL);
1759	if (!chip_id_boardname) {
1760	ret = -ENOMEM;
1761	goto exit;
1762	}
1763
1764	ret = ath11k_core_create_chip_id_board_name(ab, name: chip_id_boardname,
1765	BOARD_NAME_SIZE);
1766	if (ret) {
1767	ath11k_err(ab, fmt: "failed to create chip id board name: %d", ret);
1768	goto exit;
1769	}
1770
1771	ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname: chip_id_boardname,
1772	ie_id_match: ATH11K_BD_IE_BOARD,
1773	name_id: ATH11K_BD_IE_BOARD_NAME,
1774	data_id: ATH11K_BD_IE_BOARD_DATA);
1775
1776	if (!ret)
1777	goto exit;
1778
1779	bd_api = 1;
1780	ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE);
1781	if (ret) {
1782	ath11k_core_create_firmware_path(ab, filename,
1783	buf: filepath, buf_len: sizeof(filepath));
1784	ath11k_err(ab, fmt: "failed to fetch board data for %s from %s\n",
1785	boardname, filepath);
1786	if (memcmp(p: boardname, q: fallback_boardname, strlen(boardname)))
1787	ath11k_err(ab, fmt: "failed to fetch board data for %s from %s\n",
1788	fallback_boardname, filepath);
1789
1790	ath11k_err(ab, fmt: "failed to fetch board data for %s from %s\n",
1791	chip_id_boardname, filepath);
1792
1793	ath11k_err(ab, fmt: "failed to fetch board.bin from %s\n",
1794	ab->hw_params.fw.dir);
1795	}
1796
1797	exit:
1798	kfree(objp: boardname);
1799	kfree(objp: fallback_boardname);
1800	kfree(objp: chip_id_boardname);
1801
1802	if (!ret)
1803	ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", bd_api);
1804
1805	return ret;
1806	}
1807
1808	int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd)
1809	{
1810	char boardname[BOARD_NAME_SIZE], default_boardname[BOARD_NAME_SIZE];
1811	int ret;
1812
1813	ret = ath11k_core_create_board_name(ab, name: boardname, BOARD_NAME_SIZE);
1814	if (ret) {
1815	ath11k_dbg(ab, ATH11K_DBG_BOOT,
1816	"failed to create board name for regdb: %d", ret);
1817	goto exit;
1818	}
1819
1820	ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
1821	ie_id_match: ATH11K_BD_IE_REGDB,
1822	name_id: ATH11K_BD_IE_REGDB_NAME,
1823	data_id: ATH11K_BD_IE_REGDB_DATA);
1824	if (!ret)
1825	goto exit;
1826
1827	ret = ath11k_core_create_bus_type_board_name(ab, name: default_boardname,
1828	BOARD_NAME_SIZE);
1829	if (ret) {
1830	ath11k_dbg(ab, ATH11K_DBG_BOOT,
1831	"failed to create default board name for regdb: %d", ret);
1832	goto exit;
1833	}
1834
1835	ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname: default_boardname,
1836	ie_id_match: ATH11K_BD_IE_REGDB,
1837	name_id: ATH11K_BD_IE_REGDB_NAME,
1838	data_id: ATH11K_BD_IE_REGDB_DATA);
1839	if (!ret)
1840	goto exit;
1841
1842	ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_REGDB_FILE_NAME);
1843	if (ret)
1844	ath11k_dbg(ab, ATH11K_DBG_BOOT, "failed to fetch %s from %s\n",
1845	ATH11K_REGDB_FILE_NAME, ab->hw_params.fw.dir);
1846
1847	exit:
1848	if (!ret)
1849	ath11k_dbg(ab, ATH11K_DBG_BOOT, "fetched regdb\n");
1850
1851	return ret;
1852	}
1853
1854	static void ath11k_core_stop(struct ath11k_base *ab)
1855	{
1856	if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
1857	ath11k_qmi_firmware_stop(ab);
1858
1859	ath11k_hif_stop(ab);
1860	ath11k_wmi_detach(ab);
1861	ath11k_dp_pdev_reo_cleanup(ab);
1862
1863	/* De-Init of components as needed */
1864	}
1865
1866	static int ath11k_core_soc_create(struct ath11k_base *ab)
1867	{
1868	int ret;
1869
1870	if (ath11k_ftm_mode) {
1871	ab->fw_mode = ATH11K_FIRMWARE_MODE_FTM;
1872	ath11k_info(ab, fmt: "Booting in factory test mode\n");
1873	}
1874
1875	ret = ath11k_qmi_init_service(ab);
1876	if (ret) {
1877	ath11k_err(ab, fmt: "failed to initialize qmi :%d\n", ret);
1878	return ret;
1879	}
1880
1881	ret = ath11k_debugfs_soc_create(ab);
1882	if (ret) {
1883	ath11k_err(ab, fmt: "failed to create ath11k debugfs\n");
1884	goto err_qmi_deinit;
1885	}
1886
1887	ret = ath11k_hif_power_up(ab);
1888	if (ret) {
1889	ath11k_err(ab, fmt: "failed to power up :%d\n", ret);
1890	goto err_debugfs_reg;
1891	}
1892
1893	return 0;
1894
1895	err_debugfs_reg:
1896	ath11k_debugfs_soc_destroy(ab);
1897	err_qmi_deinit:
1898	ath11k_qmi_deinit_service(ab);
1899	return ret;
1900	}
1901
1902	static void ath11k_core_soc_destroy(struct ath11k_base *ab)
1903	{
1904	ath11k_debugfs_soc_destroy(ab);
1905	ath11k_dp_free(ab);
1906	ath11k_reg_free(ab);
1907	ath11k_qmi_deinit_service(ab);
1908	}
1909
1910	static int ath11k_core_pdev_create(struct ath11k_base *ab)
1911	{
1912	int ret;
1913
1914	ret = ath11k_debugfs_pdev_create(ab);
1915	if (ret) {
1916	ath11k_err(ab, fmt: "failed to create core pdev debugfs: %d\n", ret);
1917	return ret;
1918	}
1919
1920	ret = ath11k_dp_pdev_alloc(ab);
1921	if (ret) {
1922	ath11k_err(ab, fmt: "failed to attach DP pdev: %d\n", ret);
1923	goto err_pdev_debug;
1924	}
1925
1926	ret = ath11k_mac_register(ab);
1927	if (ret) {
1928	ath11k_err(ab, fmt: "failed register the radio with mac80211: %d\n", ret);
1929	goto err_dp_pdev_free;
1930	}
1931
1932	ret = ath11k_thermal_register(ab);
1933	if (ret) {
1934	ath11k_err(ab, fmt: "could not register thermal device: %d\n",
1935	ret);
1936	goto err_mac_unregister;
1937	}
1938
1939	ret = ath11k_spectral_init(ab);
1940	if (ret) {
1941	ath11k_err(ab, fmt: "failed to init spectral %d\n", ret);
1942	goto err_thermal_unregister;
1943	}
1944
1945	return 0;
1946
1947	err_thermal_unregister:
1948	ath11k_thermal_unregister(ab);
1949	err_mac_unregister:
1950	ath11k_mac_unregister(ab);
1951	err_dp_pdev_free:
1952	ath11k_dp_pdev_free(ab);
1953	err_pdev_debug:
1954	ath11k_debugfs_pdev_destroy(ab);
1955
1956	return ret;
1957	}
1958
1959	static void ath11k_core_pdev_suspend_target(struct ath11k_base *ab)
1960	{
1961	struct ath11k *ar;
1962	struct ath11k_pdev *pdev;
1963	unsigned long time_left;
1964	int ret;
1965	int i;
1966
1967	if (!ab->hw_params.pdev_suspend)
1968	return;
1969
1970	for (i = 0; i < ab->num_radios; i++) {
1971	pdev = &ab->pdevs[i];
1972	ar = pdev->ar;
1973
1974	reinit_completion(x: &ab->htc_suspend);
1975
1976	ret = ath11k_wmi_pdev_suspend(ar, suspend_opt: WMI_PDEV_SUSPEND_AND_DISABLE_INTR,
1977	pdev_id: pdev->pdev_id);
1978	if (ret) {
1979	ath11k_warn(ab, fmt: "could not suspend target :%d\n", ret);
1980	/* pointless to try other pdevs */
1981	return;
1982	}
1983
1984	time_left = wait_for_completion_timeout(x: &ab->htc_suspend, timeout: 3 * HZ);
1985
1986	if (!time_left) {
1987	ath11k_warn(ab, fmt: "suspend timed out - target pause event never came\n");
1988	/* pointless to try other pdevs */
1989	return;
1990	}
1991	}
1992	}
1993
1994	static void ath11k_core_pdev_destroy(struct ath11k_base *ab)
1995	{
1996	ath11k_spectral_deinit(ab);
1997	ath11k_thermal_unregister(ab);
1998	ath11k_mac_unregister(ab);
1999	ath11k_core_pdev_suspend_target(ab);
2000	ath11k_hif_irq_disable(ab);
2001	ath11k_dp_pdev_free(ab);
2002	ath11k_debugfs_pdev_destroy(ab);
2003	}
2004
2005	static int ath11k_core_start(struct ath11k_base *ab)
2006	{
2007	int ret;
2008
2009	ret = ath11k_wmi_attach(ab);
2010	if (ret) {
2011	ath11k_err(ab, fmt: "failed to attach wmi: %d\n", ret);
2012	return ret;
2013	}
2014
2015	ret = ath11k_htc_init(ar: ab);
2016	if (ret) {
2017	ath11k_err(ab, fmt: "failed to init htc: %d\n", ret);
2018	goto err_wmi_detach;
2019	}
2020
2021	ret = ath11k_hif_start(ab);
2022	if (ret) {
2023	ath11k_err(ab, fmt: "failed to start HIF: %d\n", ret);
2024	goto err_wmi_detach;
2025	}
2026
2027	ret = ath11k_htc_wait_target(htc: &ab->htc);
2028	if (ret) {
2029	ath11k_err(ab, fmt: "failed to connect to HTC: %d\n", ret);
2030	goto err_hif_stop;
2031	}
2032
2033	ret = ath11k_dp_htt_connect(dp: &ab->dp);
2034	if (ret) {
2035	ath11k_err(ab, fmt: "failed to connect to HTT: %d\n", ret);
2036	goto err_hif_stop;
2037	}
2038
2039	ret = ath11k_wmi_connect(ab);
2040	if (ret) {
2041	ath11k_err(ab, fmt: "failed to connect wmi: %d\n", ret);
2042	goto err_hif_stop;
2043	}
2044
2045	ret = ath11k_htc_start(htc: &ab->htc);
2046	if (ret) {
2047	ath11k_err(ab, fmt: "failed to start HTC: %d\n", ret);
2048	goto err_hif_stop;
2049	}
2050
2051	ret = ath11k_wmi_wait_for_service_ready(ab);
2052	if (ret) {
2053	ath11k_err(ab, fmt: "failed to receive wmi service ready event: %d\n",
2054	ret);
2055	goto err_hif_stop;
2056	}
2057
2058	ret = ath11k_mac_allocate(ab);
2059	if (ret) {
2060	ath11k_err(ab, fmt: "failed to create new hw device with mac80211 :%d\n",
2061	ret);
2062	goto err_hif_stop;
2063	}
2064
2065	ath11k_dp_pdev_pre_alloc(ab);
2066
2067	ret = ath11k_dp_pdev_reo_setup(ab);
2068	if (ret) {
2069	ath11k_err(ab, fmt: "failed to initialize reo destination rings: %d\n", ret);
2070	goto err_mac_destroy;
2071	}
2072
2073	ret = ath11k_wmi_cmd_init(ab);
2074	if (ret) {
2075	ath11k_err(ab, fmt: "failed to send wmi init cmd: %d\n", ret);
2076	goto err_reo_cleanup;
2077	}
2078
2079	ret = ath11k_wmi_wait_for_unified_ready(ab);
2080	if (ret) {
2081	ath11k_err(ab, fmt: "failed to receive wmi unified ready event: %d\n",
2082	ret);
2083	goto err_reo_cleanup;
2084	}
2085
2086	/* put hardware to DBS mode */
2087	if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxdma_per_pdev > 1) {
2088	ret = ath11k_wmi_set_hw_mode(ab, mode: WMI_HOST_HW_MODE_DBS);
2089	if (ret) {
2090	ath11k_err(ab, fmt: "failed to send dbs mode: %d\n", ret);
2091	goto err_hif_stop;
2092	}
2093	}
2094
2095	ret = ath11k_dp_tx_htt_h2t_ver_req_msg(ab);
2096	if (ret) {
2097	ath11k_err(ab, fmt: "failed to send htt version request message: %d\n",
2098	ret);
2099	goto err_reo_cleanup;
2100	}
2101
2102	return 0;
2103
2104	err_reo_cleanup:
2105	ath11k_dp_pdev_reo_cleanup(ab);
2106	err_mac_destroy:
2107	ath11k_mac_destroy(ab);
2108	err_hif_stop:
2109	ath11k_hif_stop(ab);
2110	err_wmi_detach:
2111	ath11k_wmi_detach(ab);
2112
2113	return ret;
2114	}
2115
2116	static int ath11k_core_start_firmware(struct ath11k_base *ab,
2117	enum ath11k_firmware_mode mode)
2118	{
2119	int ret;
2120
2121	ath11k_ce_get_shadow_config(ab, shadow_cfg: &ab->qmi.ce_cfg.shadow_reg_v2,
2122	shadow_cfg_len: &ab->qmi.ce_cfg.shadow_reg_v2_len);
2123
2124	ret = ath11k_qmi_firmware_start(ab, mode);
2125	if (ret) {
2126	ath11k_err(ab, fmt: "failed to send firmware start: %d\n", ret);
2127	return ret;
2128	}
2129
2130	return ret;
2131	}
2132
2133	int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab)
2134	{
2135	int ret;
2136
2137	ret = ath11k_core_start_firmware(ab, mode: ab->fw_mode);
2138	if (ret) {
2139	ath11k_err(ab, fmt: "failed to start firmware: %d\n", ret);
2140	return ret;
2141	}
2142
2143	ret = ath11k_ce_init_pipes(ab);
2144	if (ret) {
2145	ath11k_err(ab, fmt: "failed to initialize CE: %d\n", ret);
2146	goto err_firmware_stop;
2147	}
2148
2149	ret = ath11k_dp_alloc(ab);
2150	if (ret) {
2151	ath11k_err(ab, fmt: "failed to init DP: %d\n", ret);
2152	goto err_firmware_stop;
2153	}
2154
2155	switch (ath11k_crypto_mode) {
2156	case ATH11K_CRYPT_MODE_SW:
2157	set_bit(nr: ATH11K_FLAG_HW_CRYPTO_DISABLED, addr: &ab->dev_flags);
2158	set_bit(nr: ATH11K_FLAG_RAW_MODE, addr: &ab->dev_flags);
2159	break;
2160	case ATH11K_CRYPT_MODE_HW:
2161	clear_bit(nr: ATH11K_FLAG_HW_CRYPTO_DISABLED, addr: &ab->dev_flags);
2162	clear_bit(nr: ATH11K_FLAG_RAW_MODE, addr: &ab->dev_flags);
2163	break;
2164	default:
2165	ath11k_info(ab, fmt: "invalid crypto_mode: %d\n", ath11k_crypto_mode);
2166	return -EINVAL;
2167	}
2168
2169	if (ath11k_frame_mode == ATH11K_HW_TXRX_RAW)
2170	set_bit(nr: ATH11K_FLAG_RAW_MODE, addr: &ab->dev_flags);
2171
2172	mutex_lock(&ab->core_lock);
2173	ret = ath11k_core_start(ab);
2174	if (ret) {
2175	ath11k_err(ab, fmt: "failed to start core: %d\n", ret);
2176	goto err_dp_free;
2177	}
2178
2179	ret = ath11k_core_pdev_create(ab);
2180	if (ret) {
2181	ath11k_err(ab, fmt: "failed to create pdev core: %d\n", ret);
2182	goto err_core_stop;
2183	}
2184	ath11k_hif_irq_enable(ab);
2185	mutex_unlock(lock: &ab->core_lock);
2186
2187	return 0;
2188
2189	err_core_stop:
2190	ath11k_core_stop(ab);
2191	ath11k_mac_destroy(ab);
2192	err_dp_free:
2193	ath11k_dp_free(ab);
2194	mutex_unlock(lock: &ab->core_lock);
2195	err_firmware_stop:
2196	ath11k_qmi_firmware_stop(ab);
2197
2198	return ret;
2199	}
2200
2201	static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab)
2202	{
2203	int ret;
2204
2205	mutex_lock(&ab->core_lock);
2206	ath11k_thermal_unregister(ab);
2207	ath11k_dp_pdev_free(ab);
2208	ath11k_spectral_deinit(ab);
2209	ath11k_ce_cleanup_pipes(ab);
2210	ath11k_wmi_detach(ab);
2211	ath11k_dp_pdev_reo_cleanup(ab);
2212	mutex_unlock(lock: &ab->core_lock);
2213
2214	ath11k_dp_free(ab);
2215	ath11k_hal_srng_deinit(ath11k: ab);
2216
2217	ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1;
2218
2219	ret = ath11k_hal_srng_init(ath11k: ab);
2220	if (ret)
2221	return ret;
2222
2223	clear_bit(nr: ATH11K_FLAG_CRASH_FLUSH, addr: &ab->dev_flags);
2224
2225	ret = ath11k_core_qmi_firmware_ready(ab);
2226	if (ret)
2227	goto err_hal_srng_deinit;
2228
2229	clear_bit(nr: ATH11K_FLAG_RECOVERY, addr: &ab->dev_flags);
2230
2231	return 0;
2232
2233	err_hal_srng_deinit:
2234	ath11k_hal_srng_deinit(ath11k: ab);
2235	return ret;
2236	}
2237
2238	void ath11k_core_halt(struct ath11k *ar)
2239	{
2240	struct ath11k_base *ab = ar->ab;
2241	struct list_head *pos, *n;
2242
2243	lockdep_assert_held(&ar->conf_mutex);
2244
2245	ar->num_created_vdevs = 0;
2246	ar->allocated_vdev_map = 0;
2247
2248	ath11k_mac_scan_finish(ar);
2249	ath11k_mac_peer_cleanup_all(ar);
2250	cancel_delayed_work_sync(dwork: &ar->scan.timeout);
2251	cancel_work_sync(work: &ar->channel_update_work);
2252	cancel_work_sync(work: &ar->regd_update_work);
2253	cancel_work_sync(work: &ab->update_11d_work);
2254
2255	rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL);
2256	synchronize_rcu();
2257
2258	spin_lock_bh(lock: &ar->data_lock);
2259	list_for_each_safe(pos, n, &ar->arvifs)
2260	list_del_init(entry: pos);
2261	spin_unlock_bh(lock: &ar->data_lock);
2262
2263	idr_init(idr: &ar->txmgmt_idr);
2264	}
2265
2266	static void ath11k_update_11d(struct work_struct *work)
2267	{
2268	struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work);
2269	struct ath11k *ar;
2270	struct ath11k_pdev *pdev;
2271	int ret, i;
2272
2273	for (i = 0; i < ab->num_radios; i++) {
2274	pdev = &ab->pdevs[i];
2275	ar = pdev->ar;
2276
2277	spin_lock_bh(lock: &ab->base_lock);
2278	memcpy(&ar->alpha2, &ab->new_alpha2, 2);
2279	spin_unlock_bh(lock: &ab->base_lock);
2280
2281	ath11k_dbg(ab, ATH11K_DBG_WMI, "update 11d new cc %c%c for pdev %d\n",
2282	ar->alpha2[0], ar->alpha2[1], i);
2283
2284	ret = ath11k_reg_set_cc(ar);
2285	if (ret)
2286	ath11k_warn(ab: ar->ab,
2287	fmt: "pdev id %d failed set current country code: %d\n",
2288	i, ret);
2289	}
2290	}
2291
2292	void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab)
2293	{
2294	struct ath11k *ar;
2295	struct ath11k_pdev *pdev;
2296	int i;
2297
2298	spin_lock_bh(lock: &ab->base_lock);
2299	ab->stats.fw_crash_counter++;
2300	spin_unlock_bh(lock: &ab->base_lock);
2301
2302	for (i = 0; i < ab->num_radios; i++) {
2303	pdev = &ab->pdevs[i];
2304	ar = pdev->ar;
2305	if (!ar || ar->state == ATH11K_STATE_OFF ||
2306	ar->state == ATH11K_STATE_FTM)
2307	continue;
2308
2309	ieee80211_stop_queues(hw: ar->hw);
2310	ath11k_mac_drain_tx(ar);
2311	ar->state_11d = ATH11K_11D_IDLE;
2312	complete(&ar->completed_11d_scan);
2313	complete(&ar->scan.started);
2314	complete_all(&ar->scan.completed);
2315	complete(&ar->scan.on_channel);
2316	complete(&ar->peer_assoc_done);
2317	complete(&ar->peer_delete_done);
2318	complete(&ar->install_key_done);
2319	complete(&ar->vdev_setup_done);
2320	complete(&ar->vdev_delete_done);
2321	complete(&ar->bss_survey_done);
2322	complete(&ar->thermal.wmi_sync);
2323
2324	wake_up(&ar->dp.tx_empty_waitq);
2325	idr_for_each(&ar->txmgmt_idr,
2326	fn: ath11k_mac_tx_mgmt_pending_free, data: ar);
2327	idr_destroy(&ar->txmgmt_idr);
2328	wake_up(&ar->txmgmt_empty_waitq);
2329
2330	ar->monitor_vdev_id = -1;
2331	clear_bit(nr: ATH11K_FLAG_MONITOR_STARTED, addr: &ar->monitor_flags);
2332	clear_bit(nr: ATH11K_FLAG_MONITOR_VDEV_CREATED, addr: &ar->monitor_flags);
2333	}
2334
2335	wake_up(&ab->wmi_ab.tx_credits_wq);
2336	wake_up(&ab->peer_mapping_wq);
2337
2338	reinit_completion(x: &ab->driver_recovery);
2339	}
2340
2341	static void ath11k_core_post_reconfigure_recovery(struct ath11k_base *ab)
2342	{
2343	struct ath11k *ar;
2344	struct ath11k_pdev *pdev;
2345	int i;
2346
2347	for (i = 0; i < ab->num_radios; i++) {
2348	pdev = &ab->pdevs[i];
2349	ar = pdev->ar;
2350	if (!ar || ar->state == ATH11K_STATE_OFF)
2351	continue;
2352
2353	mutex_lock(&ar->conf_mutex);
2354
2355	switch (ar->state) {
2356	case ATH11K_STATE_ON:
2357	ar->state = ATH11K_STATE_RESTARTING;
2358	ath11k_core_halt(ar);
2359	ieee80211_restart_hw(hw: ar->hw);
2360	break;
2361	case ATH11K_STATE_OFF:
2362	ath11k_warn(ab,
2363	fmt: "cannot restart radio %d that hasn't been started\n",
2364	i);
2365	break;
2366	case ATH11K_STATE_RESTARTING:
2367	break;
2368	case ATH11K_STATE_RESTARTED:
2369	ar->state = ATH11K_STATE_WEDGED;
2370	fallthrough;
2371	case ATH11K_STATE_WEDGED:
2372	ath11k_warn(ab,
2373	fmt: "device is wedged, will not restart radio %d\n", i);
2374	break;
2375	case ATH11K_STATE_FTM:
2376	ath11k_dbg(ab, ATH11K_DBG_TESTMODE,
2377	"fw mode reset done radio %d\n", i);
2378	break;
2379	}
2380
2381	mutex_unlock(lock: &ar->conf_mutex);
2382	}
2383	complete(&ab->driver_recovery);
2384	}
2385
2386	static void ath11k_core_restart(struct work_struct *work)
2387	{
2388	struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work);
2389	int ret;
2390
2391	ret = ath11k_core_reconfigure_on_crash(ab);
2392	if (ret) {
2393	ath11k_err(ab, fmt: "failed to reconfigure driver on crash recovery\n");
2394	return;
2395	}
2396
2397	if (ab->is_reset)
2398	complete_all(&ab->reconfigure_complete);
2399
2400	if (!ab->is_reset)
2401	ath11k_core_post_reconfigure_recovery(ab);
2402
2403	complete(&ab->restart_completed);
2404	}
2405
2406	static void ath11k_core_reset(struct work_struct *work)
2407	{
2408	struct ath11k_base *ab = container_of(work, struct ath11k_base, reset_work);
2409	int reset_count, fail_cont_count;
2410	long time_left;
2411
2412	if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags))) {
2413	ath11k_warn(ab, fmt: "ignore reset dev flags 0x%lx\n", ab->dev_flags);
2414	return;
2415	}
2416
2417	/* Sometimes the recovery will fail and then the next all recovery fail,
2418	* this is to avoid infinite recovery since it can not recovery success.
2419	*/
2420	fail_cont_count = atomic_read(v: &ab->fail_cont_count);
2421
2422	if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FINAL)
2423	return;
2424
2425	if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FIRST &&
2426	time_before(jiffies, ab->reset_fail_timeout))
2427	return;
2428
2429	reset_count = atomic_inc_return(v: &ab->reset_count);
2430
2431	if (reset_count > 1) {
2432	/* Sometimes it happened another reset worker before the previous one
2433	* completed, then the second reset worker will destroy the previous one,
2434	* thus below is to avoid that.
2435	*/
2436	ath11k_warn(ab, fmt: "already resetting count %d\n", reset_count);
2437
2438	reinit_completion(x: &ab->reset_complete);
2439	time_left = wait_for_completion_timeout(x: &ab->reset_complete,
2440	ATH11K_RESET_TIMEOUT_HZ);
2441
2442	if (time_left) {
2443	ath11k_dbg(ab, ATH11K_DBG_BOOT, "to skip reset\n");
2444	atomic_dec(v: &ab->reset_count);
2445	return;
2446	}
2447
2448	ab->reset_fail_timeout = jiffies + ATH11K_RESET_FAIL_TIMEOUT_HZ;
2449	/* Record the continuous recovery fail count when recovery failed*/
2450	atomic_inc(v: &ab->fail_cont_count);
2451	}
2452
2453	ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset starting\n");
2454
2455	ab->is_reset = true;
2456	atomic_set(v: &ab->recovery_count, i: 0);
2457	reinit_completion(x: &ab->recovery_start);
2458	atomic_set(v: &ab->recovery_start_count, i: 0);
2459
2460	ath11k_coredump_collect(ab);
2461	ath11k_core_pre_reconfigure_recovery(ab);
2462
2463	reinit_completion(x: &ab->reconfigure_complete);
2464	ath11k_core_post_reconfigure_recovery(ab);
2465
2466	ath11k_dbg(ab, ATH11K_DBG_BOOT, "waiting recovery start...\n");
2467
2468	time_left = wait_for_completion_timeout(x: &ab->recovery_start,
2469	ATH11K_RECOVER_START_TIMEOUT_HZ);
2470
2471	ath11k_hif_irq_disable(ab);
2472	ath11k_hif_ce_irq_disable(ab);
2473
2474	ath11k_hif_power_down(ab, is_suspend: false);
2475	ath11k_hif_power_up(ab);
2476
2477	ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset started\n");
2478	}
2479
2480	static int ath11k_init_hw_params(struct ath11k_base *ab)
2481	{
2482	const struct ath11k_hw_params *hw_params = NULL;
2483	int i;
2484
2485	for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) {
2486	hw_params = &ath11k_hw_params[i];
2487
2488	if (hw_params->hw_rev == ab->hw_rev)
2489	break;
2490	}
2491
2492	if (i == ARRAY_SIZE(ath11k_hw_params)) {
2493	ath11k_err(ab, fmt: "Unsupported hardware version: 0x%x\n", ab->hw_rev);
2494	return -EINVAL;
2495	}
2496
2497	ab->hw_params = *hw_params;
2498
2499	ath11k_info(ab, fmt: "%s\n", ab->hw_params.name);
2500
2501	return 0;
2502	}
2503
2504	int ath11k_core_pre_init(struct ath11k_base *ab)
2505	{
2506	int ret;
2507
2508	ret = ath11k_init_hw_params(ab);
2509	if (ret) {
2510	ath11k_err(ab, fmt: "failed to get hw params: %d\n", ret);
2511	return ret;
2512	}
2513
2514	ret = ath11k_fw_pre_init(ab);
2515	if (ret) {
2516	ath11k_err(ab, fmt: "failed to pre init firmware: %d", ret);
2517	return ret;
2518	}
2519
2520	return 0;
2521	}
2522	EXPORT_SYMBOL(ath11k_core_pre_init);
2523
2524	static int ath11k_core_pm_notify(struct notifier_block *nb,
2525	unsigned long action, void *nouse)
2526	{
2527	struct ath11k_base *ab = container_of(nb, struct ath11k_base,
2528	pm_nb);
2529
2530	switch (action) {
2531	case PM_SUSPEND_PREPARE:
2532	ab->actual_pm_policy = ab->pm_policy;
2533	break;
2534	case PM_HIBERNATION_PREPARE:
2535	ab->actual_pm_policy = ATH11K_PM_DEFAULT;
2536	break;
2537	default:
2538	break;
2539	}
2540
2541	return NOTIFY_OK;
2542	}
2543
2544	static int ath11k_core_pm_notifier_register(struct ath11k_base *ab)
2545	{
2546	ab->pm_nb.notifier_call = ath11k_core_pm_notify;
2547	return register_pm_notifier(nb: &ab->pm_nb);
2548	}
2549
2550	void ath11k_core_pm_notifier_unregister(struct ath11k_base *ab)
2551	{
2552	int ret;
2553
2554	ret = unregister_pm_notifier(nb: &ab->pm_nb);
2555	if (ret)
2556	/* just warn here, there is nothing can be done in fail case */
2557	ath11k_warn(ab, fmt: "failed to unregister PM notifier %d\n", ret);
2558	}
2559	EXPORT_SYMBOL(ath11k_core_pm_notifier_unregister);
2560
2561	int ath11k_core_init(struct ath11k_base *ab)
2562	{
2563	const struct dmi_system_id *dmi_id;
2564	int ret;
2565
2566	dmi_id = dmi_first_match(list: ath11k_pm_quirk_table);
2567	if (dmi_id)
2568	ab->pm_policy = (kernel_ulong_t)dmi_id->driver_data;
2569	else
2570	ab->pm_policy = ATH11K_PM_DEFAULT;
2571
2572	ath11k_dbg(ab, ATH11K_DBG_BOOT, "pm policy %u\n", ab->pm_policy);
2573
2574	ret = ath11k_core_pm_notifier_register(ab);
2575	if (ret) {
2576	ath11k_err(ab, fmt: "failed to register PM notifier: %d\n", ret);
2577	return ret;
2578	}
2579
2580	ret = ath11k_core_soc_create(ab);
2581	if (ret) {
2582	ath11k_err(ab, fmt: "failed to create soc core: %d\n", ret);
2583	return ret;
2584	}
2585
2586	return 0;
2587	}
2588	EXPORT_SYMBOL(ath11k_core_init);
2589
2590	void ath11k_core_deinit(struct ath11k_base *ab)
2591	{
2592	mutex_lock(&ab->core_lock);
2593
2594	ath11k_core_pdev_destroy(ab);
2595	ath11k_core_stop(ab);
2596
2597	mutex_unlock(lock: &ab->core_lock);
2598
2599	ath11k_hif_power_down(ab, is_suspend: false);
2600	ath11k_mac_destroy(ab);
2601	ath11k_core_soc_destroy(ab);
2602	ath11k_core_pm_notifier_unregister(ab);
2603	}
2604	EXPORT_SYMBOL(ath11k_core_deinit);
2605
2606	void ath11k_core_free(struct ath11k_base *ab)
2607	{
2608	destroy_workqueue(wq: ab->workqueue_aux);
2609	destroy_workqueue(wq: ab->workqueue);
2610
2611	kfree(objp: ab);
2612	}
2613	EXPORT_SYMBOL(ath11k_core_free);
2614
2615	struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size,
2616	enum ath11k_bus bus)
2617	{
2618	struct ath11k_base *ab;
2619
2620	ab = kzalloc(sizeof(*ab) + priv_size, GFP_KERNEL);
2621	if (!ab)
2622	return NULL;
2623
2624	init_completion(x: &ab->driver_recovery);
2625
2626	ab->workqueue = create_singlethread_workqueue("ath11k_wq");
2627	if (!ab->workqueue)
2628	goto err_sc_free;
2629
2630	ab->workqueue_aux = create_singlethread_workqueue("ath11k_aux_wq");
2631	if (!ab->workqueue_aux)
2632	goto err_free_wq;
2633
2634	mutex_init(&ab->core_lock);
2635	mutex_init(&ab->tbl_mtx_lock);
2636	spin_lock_init(&ab->base_lock);
2637	mutex_init(&ab->vdev_id_11d_lock);
2638	init_completion(x: &ab->reset_complete);
2639	init_completion(x: &ab->reconfigure_complete);
2640	init_completion(x: &ab->recovery_start);
2641
2642	INIT_LIST_HEAD(list: &ab->peers);
2643	init_waitqueue_head(&ab->peer_mapping_wq);
2644	init_waitqueue_head(&ab->wmi_ab.tx_credits_wq);
2645	init_waitqueue_head(&ab->qmi.cold_boot_waitq);
2646	INIT_WORK(&ab->restart_work, ath11k_core_restart);
2647	INIT_WORK(&ab->update_11d_work, ath11k_update_11d);
2648	INIT_WORK(&ab->reset_work, ath11k_core_reset);
2649	INIT_WORK(&ab->dump_work, ath11k_coredump_upload);
2650	timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0);
2651	init_completion(x: &ab->htc_suspend);
2652	init_completion(x: &ab->wow.wakeup_completed);
2653	init_completion(x: &ab->restart_completed);
2654
2655	ab->dev = dev;
2656	ab->hif.bus = bus;
2657
2658	return ab;
2659
2660	err_free_wq:
2661	destroy_workqueue(wq: ab->workqueue);
2662	err_sc_free:
2663	kfree(objp: ab);
2664	return NULL;
2665	}
2666	EXPORT_SYMBOL(ath11k_core_alloc);
2667
2668	MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ax wireless LAN cards.");
2669	MODULE_LICENSE("Dual BSD/GPL");
2670