1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * (c) Copyright 2002-2010, Ralink Technology, Inc. |
4 | * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl> |
5 | * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> |
6 | * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com> |
7 | */ |
8 | |
9 | #ifndef __MT76X0U_INITVALS_INIT_H |
10 | #define __MT76X0U_INITVALS_INIT_H |
11 | |
12 | #include "phy.h" |
13 | |
14 | static const struct mt76_reg_pair common_mac_reg_table[] = { |
15 | { MT_BCN_OFFSET(0), 0xf8f0e8e0 }, |
16 | { MT_BCN_OFFSET(1), 0x6f77d0c8 }, |
17 | { MT_LEGACY_BASIC_RATE, 0x0000013f }, |
18 | { MT_HT_BASIC_RATE, 0x00008003 }, |
19 | { MT_MAC_SYS_CTRL, 0x00000000 }, |
20 | { MT_RX_FILTR_CFG, 0x00017f97 }, |
21 | { MT_BKOFF_SLOT_CFG, 0x00000209 }, |
22 | { MT_TX_SW_CFG0, 0x00000000 }, |
23 | { MT_TX_SW_CFG1, 0x00080606 }, |
24 | { MT_TX_LINK_CFG, 0x00001020 }, |
25 | { MT_TX_TIMEOUT_CFG, 0x000a2090 }, |
26 | { MT_MAX_LEN_CFG, 0xa0fff | 0x00001000 }, |
27 | { MT_LED_CFG, 0x7f031e46 }, |
28 | { MT_PBF_TX_MAX_PCNT, 0x1fbf1f1f }, |
29 | { MT_PBF_RX_MAX_PCNT, 0x0000fe9f }, |
30 | { MT_TX_RETRY_CFG, 0x47d01f0f }, |
31 | { MT_AUTO_RSP_CFG, 0x00000013 }, |
32 | { MT_CCK_PROT_CFG, 0x07f40003 }, |
33 | { MT_OFDM_PROT_CFG, 0x07f42004 }, |
34 | { MT_PBF_CFG, 0x00f40006 }, |
35 | { MT_WPDMA_GLO_CFG, 0x00000030 }, |
36 | { MT_GF20_PROT_CFG, 0x01742004 }, |
37 | { MT_GF40_PROT_CFG, 0x03f42084 }, |
38 | { MT_MM20_PROT_CFG, 0x01742004 }, |
39 | { MT_MM40_PROT_CFG, 0x03f42084 }, |
40 | { MT_TXOP_CTRL_CFG, 0x0000583f }, |
41 | { MT_TX_RTS_CFG, 0x00ffff20 }, |
42 | { MT_EXP_ACK_TIME, 0x002400ca }, |
43 | { MT_TXOP_HLDR_ET, 0x00000002 }, |
44 | { MT_XIFS_TIME_CFG, 0x33a41010 }, |
45 | { MT_PWR_PIN_CFG, 0x00000000 }, |
46 | }; |
47 | |
48 | static const struct mt76_reg_pair mt76x0_mac_reg_table[] = { |
49 | { MT_IOCFG_6, 0xa0040080 }, |
50 | { MT_PBF_SYS_CTRL, 0x00080c00 }, |
51 | { MT_PBF_CFG, 0x77723c1f }, |
52 | { MT_FCE_PSE_CTRL, 0x00000001 }, |
53 | { MT_AMPDU_MAX_LEN_20M1S, 0xAAA99887 }, |
54 | { MT_TX_SW_CFG0, 0x00000601 }, |
55 | { MT_TX_SW_CFG1, 0x00040000 }, |
56 | { MT_TX_SW_CFG2, 0x00000000 }, |
57 | { 0xa44, 0x00000000 }, |
58 | { MT_HEADER_TRANS_CTRL_REG, 0x00000000 }, |
59 | { MT_TSO_CTRL, 0x00000000 }, |
60 | { MT_BB_PA_MODE_CFG1, 0x00500055 }, |
61 | { MT_RF_PA_MODE_CFG1, 0x00500055 }, |
62 | { MT_TX_ALC_CFG_0, 0x2F2F000C }, |
63 | { MT_TX0_BB_GAIN_ATTEN, 0x00000000 }, |
64 | { MT_TX_PWR_CFG_0, 0x3A3A3A3A }, |
65 | { MT_TX_PWR_CFG_1, 0x3A3A3A3A }, |
66 | { MT_TX_PWR_CFG_2, 0x3A3A3A3A }, |
67 | { MT_TX_PWR_CFG_3, 0x3A3A3A3A }, |
68 | { MT_TX_PWR_CFG_4, 0x3A3A3A3A }, |
69 | { MT_TX_PWR_CFG_7, 0x3A3A3A3A }, |
70 | { MT_TX_PWR_CFG_8, 0x0000003A }, |
71 | { MT_TX_PWR_CFG_9, 0x0000003A }, |
72 | { 0x150C, 0x00000002 }, |
73 | { 0x1238, 0x001700C8 }, |
74 | { MT_LDO_CTRL_0, 0x00A647B6 }, |
75 | { MT_LDO_CTRL_1, 0x6B006464 }, |
76 | { MT_HT_BASIC_RATE, 0x00004003 }, |
77 | { MT_HT_CTRL_CFG, 0x000001FF }, |
78 | { MT_TXOP_HLDR_ET, 0x00000000 }, |
79 | { MT_PN_PAD_MODE, 0x00000003 }, |
80 | { MT_TX_PROT_CFG6, 0xe3f42004 }, |
81 | { MT_TX_PROT_CFG7, 0xe3f42084 }, |
82 | { MT_TX_PROT_CFG8, 0xe3f42104 }, |
83 | { MT_VHT_HT_FBK_CFG1, 0xedcba980 }, |
84 | }; |
85 | |
86 | static const struct mt76_reg_pair mt76x0_bbp_init_tab[] = { |
87 | { MT_BBP(CORE, 1), 0x00000002 }, |
88 | { MT_BBP(CORE, 4), 0x00000000 }, |
89 | { MT_BBP(CORE, 24), 0x00000000 }, |
90 | { MT_BBP(CORE, 32), 0x4003000a }, |
91 | { MT_BBP(CORE, 42), 0x00000000 }, |
92 | { MT_BBP(CORE, 44), 0x00000000 }, |
93 | { MT_BBP(IBI, 11), 0x0FDE8081 }, |
94 | { MT_BBP(AGC, 0), 0x00021400 }, |
95 | { MT_BBP(AGC, 1), 0x00000003 }, |
96 | { MT_BBP(AGC, 2), 0x003A6464 }, |
97 | { MT_BBP(AGC, 15), 0x88A28CB8 }, |
98 | { MT_BBP(AGC, 22), 0x00001E21 }, |
99 | { MT_BBP(AGC, 23), 0x0000272C }, |
100 | { MT_BBP(AGC, 24), 0x00002F3A }, |
101 | { MT_BBP(AGC, 25), 0x8000005A }, |
102 | { MT_BBP(AGC, 26), 0x007C2005 }, |
103 | { MT_BBP(AGC, 33), 0x00003238 }, |
104 | { MT_BBP(AGC, 34), 0x000A0C0C }, |
105 | { MT_BBP(AGC, 37), 0x2121262C }, |
106 | { MT_BBP(AGC, 41), 0x38383E45 }, |
107 | { MT_BBP(AGC, 57), 0x00001010 }, |
108 | { MT_BBP(AGC, 59), 0xBAA20E96 }, |
109 | { MT_BBP(AGC, 63), 0x00000001 }, |
110 | { MT_BBP(TXC, 0), 0x00280403 }, |
111 | { MT_BBP(TXC, 1), 0x00000000 }, |
112 | { MT_BBP(RXC, 1), 0x00000012 }, |
113 | { MT_BBP(RXC, 2), 0x00000011 }, |
114 | { MT_BBP(RXC, 3), 0x00000005 }, |
115 | { MT_BBP(RXC, 4), 0x00000000 }, |
116 | { MT_BBP(RXC, 5), 0xF977C4EC }, |
117 | { MT_BBP(RXC, 7), 0x00000090 }, |
118 | { MT_BBP(TXO, 8), 0x00000000 }, |
119 | { MT_BBP(TXBE, 0), 0x00000000 }, |
120 | { MT_BBP(TXBE, 4), 0x00000004 }, |
121 | { MT_BBP(TXBE, 6), 0x00000000 }, |
122 | { MT_BBP(TXBE, 8), 0x00000014 }, |
123 | { MT_BBP(TXBE, 9), 0x20000000 }, |
124 | { MT_BBP(TXBE, 10), 0x00000000 }, |
125 | { MT_BBP(TXBE, 12), 0x00000000 }, |
126 | { MT_BBP(TXBE, 13), 0x00000000 }, |
127 | { MT_BBP(TXBE, 14), 0x00000000 }, |
128 | { MT_BBP(TXBE, 15), 0x00000000 }, |
129 | { MT_BBP(TXBE, 16), 0x00000000 }, |
130 | { MT_BBP(TXBE, 17), 0x00000000 }, |
131 | { MT_BBP(RXFE, 1), 0x00008800 }, |
132 | { MT_BBP(RXFE, 3), 0x00000000 }, |
133 | { MT_BBP(RXFE, 4), 0x00000000 }, |
134 | { MT_BBP(RXO, 13), 0x00000192 }, |
135 | { MT_BBP(RXO, 14), 0x00060612 }, |
136 | { MT_BBP(RXO, 15), 0xC8321B18 }, |
137 | { MT_BBP(RXO, 16), 0x0000001E }, |
138 | { MT_BBP(RXO, 17), 0x00000000 }, |
139 | { MT_BBP(RXO, 18), 0xCC00A993 }, |
140 | { MT_BBP(RXO, 19), 0xB9CB9CB9 }, |
141 | { MT_BBP(RXO, 20), 0x26c00057 }, |
142 | { MT_BBP(RXO, 21), 0x00000001 }, |
143 | { MT_BBP(RXO, 24), 0x00000006 }, |
144 | { MT_BBP(RXO, 28), 0x0000003F }, |
145 | }; |
146 | |
147 | static const struct mt76_reg_pair mt76x0_dcoc_tab[] = { |
148 | { MT_BBP(CAL, 47), 0x000010F0 }, |
149 | { MT_BBP(CAL, 48), 0x00008080 }, |
150 | { MT_BBP(CAL, 49), 0x00000F07 }, |
151 | { MT_BBP(CAL, 50), 0x00000040 }, |
152 | { MT_BBP(CAL, 51), 0x00000404 }, |
153 | { MT_BBP(CAL, 52), 0x00080803 }, |
154 | { MT_BBP(CAL, 53), 0x00000704 }, |
155 | { MT_BBP(CAL, 54), 0x00002828 }, |
156 | { MT_BBP(CAL, 55), 0x00005050 }, |
157 | }; |
158 | |
159 | #endif |
160 | |