1/* SPDX-License-Identifier: ISC */
2/*
3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4 */
5
6#ifndef __MT76_H
7#define __MT76_H
8
9#include <linux/kernel.h>
10#include <linux/io.h>
11#include <linux/spinlock.h>
12#include <linux/skbuff.h>
13#include <linux/leds.h>
14#include <linux/usb.h>
15#include <linux/average.h>
16#include <linux/soc/mediatek/mtk_wed.h>
17#include <net/mac80211.h>
18#include <net/page_pool/helpers.h>
19#include "util.h"
20#include "testmode.h"
21
22#define MT_MCU_RING_SIZE 32
23#define MT_RX_BUF_SIZE 2048
24#define MT_SKB_HEAD_LEN 256
25
26#define MT_MAX_NON_AQL_PKT 16
27#define MT_TXQ_FREE_THR 32
28
29#define MT76_TOKEN_FREE_THR 64
30
31#define MT_QFLAG_WED_RING GENMASK(1, 0)
32#define MT_QFLAG_WED_TYPE GENMASK(4, 2)
33#define MT_QFLAG_WED BIT(5)
34#define MT_QFLAG_WED_RRO BIT(6)
35#define MT_QFLAG_WED_RRO_EN BIT(7)
36
37#define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \
38 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \
39 FIELD_PREP(MT_QFLAG_WED_RING, _n))
40#define __MT_WED_RRO_Q(_type, _n) (MT_QFLAG_WED_RRO | __MT_WED_Q(_type, _n))
41
42#define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n)
43#define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n)
44#define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0)
45#define MT_WED_RRO_Q_DATA(_n) __MT_WED_RRO_Q(MT76_WED_RRO_Q_DATA, _n)
46#define MT_WED_RRO_Q_MSDU_PG(_n) __MT_WED_RRO_Q(MT76_WED_RRO_Q_MSDU_PG, _n)
47#define MT_WED_RRO_Q_IND __MT_WED_RRO_Q(MT76_WED_RRO_Q_IND, 0)
48
49struct mt76_dev;
50struct mt76_phy;
51struct mt76_wcid;
52struct mt76s_intr;
53struct mt76_chanctx;
54struct mt76_vif_link;
55
56struct mt76_reg_pair {
57 u32 reg;
58 u32 value;
59};
60
61enum mt76_bus_type {
62 MT76_BUS_MMIO,
63 MT76_BUS_USB,
64 MT76_BUS_SDIO,
65};
66
67enum mt76_wed_type {
68 MT76_WED_Q_TX,
69 MT76_WED_Q_TXFREE,
70 MT76_WED_Q_RX,
71 MT76_WED_RRO_Q_DATA,
72 MT76_WED_RRO_Q_MSDU_PG,
73 MT76_WED_RRO_Q_IND,
74};
75
76struct mt76_bus_ops {
77 u32 (*rr)(struct mt76_dev *dev, u32 offset);
78 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val);
79 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val);
80 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data,
81 int len);
82 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data,
83 int len);
84 int (*wr_rp)(struct mt76_dev *dev, u32 base,
85 const struct mt76_reg_pair *rp, int len);
86 int (*rd_rp)(struct mt76_dev *dev, u32 base,
87 struct mt76_reg_pair *rp, int len);
88 enum mt76_bus_type type;
89};
90
91#define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB)
92#define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO)
93#define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO)
94
95enum mt76_txq_id {
96 MT_TXQ_VO = IEEE80211_AC_VO,
97 MT_TXQ_VI = IEEE80211_AC_VI,
98 MT_TXQ_BE = IEEE80211_AC_BE,
99 MT_TXQ_BK = IEEE80211_AC_BK,
100 MT_TXQ_PSD,
101 MT_TXQ_BEACON,
102 MT_TXQ_CAB,
103 __MT_TXQ_MAX
104};
105
106enum mt76_mcuq_id {
107 MT_MCUQ_WM,
108 MT_MCUQ_WA,
109 MT_MCUQ_FWDL,
110 __MT_MCUQ_MAX
111};
112
113enum mt76_rxq_id {
114 MT_RXQ_MAIN,
115 MT_RXQ_MCU,
116 MT_RXQ_MCU_WA,
117 MT_RXQ_BAND1,
118 MT_RXQ_BAND1_WA,
119 MT_RXQ_MAIN_WA,
120 MT_RXQ_BAND2,
121 MT_RXQ_BAND2_WA,
122 MT_RXQ_RRO_BAND0,
123 MT_RXQ_RRO_BAND1,
124 MT_RXQ_RRO_BAND2,
125 MT_RXQ_MSDU_PAGE_BAND0,
126 MT_RXQ_MSDU_PAGE_BAND1,
127 MT_RXQ_MSDU_PAGE_BAND2,
128 MT_RXQ_TXFREE_BAND0,
129 MT_RXQ_TXFREE_BAND1,
130 MT_RXQ_TXFREE_BAND2,
131 MT_RXQ_RRO_IND,
132 __MT_RXQ_MAX
133};
134
135enum mt76_band_id {
136 MT_BAND0,
137 MT_BAND1,
138 MT_BAND2,
139 __MT_MAX_BAND
140};
141
142enum mt76_cipher_type {
143 MT_CIPHER_NONE,
144 MT_CIPHER_WEP40,
145 MT_CIPHER_TKIP,
146 MT_CIPHER_TKIP_NO_MIC,
147 MT_CIPHER_AES_CCMP,
148 MT_CIPHER_WEP104,
149 MT_CIPHER_BIP_CMAC_128,
150 MT_CIPHER_WEP128,
151 MT_CIPHER_WAPI,
152 MT_CIPHER_CCMP_CCX,
153 MT_CIPHER_CCMP_256,
154 MT_CIPHER_GCMP,
155 MT_CIPHER_GCMP_256,
156};
157
158enum mt76_dfs_state {
159 MT_DFS_STATE_UNKNOWN,
160 MT_DFS_STATE_DISABLED,
161 MT_DFS_STATE_CAC,
162 MT_DFS_STATE_ACTIVE,
163};
164
165#define MT76_RNR_SCAN_MAX_BSSIDS 16
166struct mt76_scan_rnr_param {
167 u8 bssid[MT76_RNR_SCAN_MAX_BSSIDS][ETH_ALEN];
168 u8 channel[MT76_RNR_SCAN_MAX_BSSIDS];
169 u8 random_mac[ETH_ALEN];
170 u8 seq_num;
171 u8 bssid_num;
172 u32 sreq_flag;
173};
174
175struct mt76_queue_buf {
176 dma_addr_t addr;
177 u16 len:15,
178 skip_unmap:1;
179};
180
181struct mt76_tx_info {
182 struct mt76_queue_buf buf[32];
183 struct sk_buff *skb;
184 int nbuf;
185 u32 info;
186};
187
188struct mt76_queue_entry {
189 union {
190 void *buf;
191 struct sk_buff *skb;
192 };
193 union {
194 struct mt76_txwi_cache *txwi;
195 struct urb *urb;
196 int buf_sz;
197 };
198 dma_addr_t dma_addr[2];
199 u16 dma_len[2];
200 u16 wcid;
201 bool skip_buf0:1;
202 bool skip_buf1:1;
203 bool done:1;
204};
205
206struct mt76_queue_regs {
207 u32 desc_base;
208 u32 ring_size;
209 u32 cpu_idx;
210 u32 dma_idx;
211} __packed __aligned(4);
212
213struct mt76_queue {
214 struct mt76_queue_regs __iomem *regs;
215
216 spinlock_t lock;
217 spinlock_t cleanup_lock;
218 struct mt76_queue_entry *entry;
219 struct mt76_rro_desc *rro_desc;
220 struct mt76_desc *desc;
221
222 u16 first;
223 u16 head;
224 u16 tail;
225 u8 hw_idx;
226 u8 ep;
227 int ndesc;
228 int queued;
229 int buf_size;
230 bool stopped;
231 bool blocked;
232
233 u8 buf_offset;
234 u16 flags;
235
236 struct mtk_wed_device *wed;
237 u32 wed_regs;
238
239 dma_addr_t desc_dma;
240 struct sk_buff *rx_head;
241 struct page_pool *page_pool;
242};
243
244struct mt76_mcu_ops {
245 unsigned int max_retry;
246 u32 headroom;
247 u32 tailroom;
248
249 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data,
250 int len, bool wait_resp);
251 int (*mcu_skb_prepare_msg)(struct mt76_dev *dev, struct sk_buff *skb,
252 int cmd, int *seq);
253 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb,
254 int cmd, int *seq);
255 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd,
256 struct sk_buff *skb, int seq);
257 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset);
258 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val);
259 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base,
260 const struct mt76_reg_pair *rp, int len);
261 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base,
262 struct mt76_reg_pair *rp, int len);
263 int (*mcu_restart)(struct mt76_dev *dev);
264};
265
266struct mt76_queue_ops {
267 int (*init)(struct mt76_dev *dev,
268 int (*poll)(struct napi_struct *napi, int budget));
269
270 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q,
271 int idx, int n_desc, int bufsize,
272 u32 ring_base);
273
274 int (*tx_queue_skb)(struct mt76_phy *phy, struct mt76_queue *q,
275 enum mt76_txq_id qid, struct sk_buff *skb,
276 struct mt76_wcid *wcid, struct ieee80211_sta *sta);
277
278 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q,
279 struct sk_buff *skb, u32 tx_info);
280
281 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
282 int *len, u32 *info, bool *more);
283
284 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid);
285
286 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q,
287 bool flush);
288
289 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q);
290
291 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q);
292
293 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q);
294};
295
296enum mt76_phy_type {
297 MT_PHY_TYPE_CCK,
298 MT_PHY_TYPE_OFDM,
299 MT_PHY_TYPE_HT,
300 MT_PHY_TYPE_HT_GF,
301 MT_PHY_TYPE_VHT,
302 MT_PHY_TYPE_HE_SU = 8,
303 MT_PHY_TYPE_HE_EXT_SU,
304 MT_PHY_TYPE_HE_TB,
305 MT_PHY_TYPE_HE_MU,
306 MT_PHY_TYPE_EHT_SU = 13,
307 MT_PHY_TYPE_EHT_TRIG,
308 MT_PHY_TYPE_EHT_MU,
309 __MT_PHY_TYPE_MAX,
310};
311
312struct mt76_sta_stats {
313 u64 tx_mode[__MT_PHY_TYPE_MAX];
314 u64 tx_bw[5]; /* 20, 40, 80, 160, 320 */
315 u64 tx_nss[4]; /* 1, 2, 3, 4 */
316 u64 tx_mcs[16]; /* mcs idx */
317 u64 tx_bytes;
318 /* WED TX */
319 u32 tx_packets; /* unit: MSDU */
320 u32 tx_retries;
321 u32 tx_failed;
322 /* WED RX */
323 u64 rx_bytes;
324 u32 rx_packets;
325 u32 rx_errors;
326 u32 rx_drops;
327};
328
329enum mt76_wcid_flags {
330 MT_WCID_FLAG_CHECK_PS,
331 MT_WCID_FLAG_PS,
332 MT_WCID_FLAG_4ADDR,
333 MT_WCID_FLAG_HDR_TRANS,
334};
335
336#define MT76_N_WCIDS 1088
337
338/* stored in ieee80211_tx_info::hw_queue */
339#define MT_TX_HW_QUEUE_PHY GENMASK(3, 2)
340
341DECLARE_EWMA(signal, 10, 8);
342
343#define MT_WCID_TX_INFO_RATE GENMASK(15, 0)
344#define MT_WCID_TX_INFO_NSS GENMASK(17, 16)
345#define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18)
346#define MT_WCID_TX_INFO_SET BIT(31)
347
348struct mt76_wcid {
349 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS];
350
351 atomic_t non_aql_packets;
352 unsigned long flags;
353
354 struct ewma_signal rssi;
355 int inactive_count;
356
357 struct rate_info rate;
358 unsigned long ampdu_state;
359
360 u16 idx;
361 u8 hw_key_idx;
362 u8 hw_key_idx2;
363
364 u8 offchannel:1;
365 u8 sta:1;
366 u8 sta_disabled:1;
367 u8 amsdu:1;
368 u8 phy_idx:2;
369 u8 link_id:4;
370 bool link_valid;
371
372 u8 rx_check_pn;
373 u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6];
374 u16 cipher;
375
376 u32 tx_info;
377 bool sw_iv;
378
379 struct list_head tx_list;
380 struct sk_buff_head tx_pending;
381 struct sk_buff_head tx_offchannel;
382
383 struct list_head list;
384 struct idr pktid;
385
386 struct mt76_sta_stats stats;
387
388 struct list_head poll_list;
389
390 struct mt76_wcid *def_wcid;
391};
392
393struct mt76_txq {
394 u16 wcid;
395
396 u16 agg_ssn;
397 bool send_bar;
398 bool aggr;
399};
400
401struct mt76_wed_rro_ind {
402 u32 se_id : 12;
403 u32 rsv : 4;
404 u32 start_sn : 12;
405 u32 ind_reason : 4;
406 u32 ind_cnt : 13;
407 u32 win_sz : 3;
408 u32 rsv2 : 13;
409 u32 magic_cnt : 3;
410};
411
412struct mt76_txwi_cache {
413 struct list_head list;
414 dma_addr_t dma_addr;
415
416 union {
417 struct sk_buff *skb;
418 void *ptr;
419 };
420};
421
422struct mt76_rx_tid {
423 struct rcu_head rcu_head;
424
425 struct mt76_dev *dev;
426
427 spinlock_t lock;
428 struct delayed_work reorder_work;
429
430 u16 id;
431 u16 head;
432 u16 size;
433 u16 nframes;
434
435 u8 num;
436
437 u8 started:1, stopped:1, timer_pending:1;
438
439 struct sk_buff *reorder_buf[] __counted_by(size);
440};
441
442#define MT_TX_CB_DMA_DONE BIT(0)
443#define MT_TX_CB_TXS_DONE BIT(1)
444#define MT_TX_CB_TXS_FAILED BIT(2)
445
446#define MT_PACKET_ID_MASK GENMASK(6, 0)
447#define MT_PACKET_ID_NO_ACK 0
448#define MT_PACKET_ID_NO_SKB 1
449#define MT_PACKET_ID_WED 2
450#define MT_PACKET_ID_FIRST 3
451#define MT_PACKET_ID_HAS_RATE BIT(7)
452/* This is timer for when to give up when waiting for TXS callback,
453 * with starting time being the time at which the DMA_DONE callback
454 * was seen (so, we know packet was processed then, it should not take
455 * long after that for firmware to send the TXS callback if it is going
456 * to do so.)
457 */
458#define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4)
459
460struct mt76_tx_cb {
461 unsigned long jiffies;
462 u16 wcid;
463 u8 pktid;
464 u8 flags;
465};
466
467enum {
468 MT76_STATE_INITIALIZED,
469 MT76_STATE_REGISTERED,
470 MT76_STATE_RUNNING,
471 MT76_STATE_MCU_RUNNING,
472 MT76_SCANNING,
473 MT76_HW_SCANNING,
474 MT76_HW_SCHED_SCANNING,
475 MT76_RESTART,
476 MT76_RESET,
477 MT76_MCU_RESET,
478 MT76_REMOVED,
479 MT76_READING_STATS,
480 MT76_STATE_POWER_OFF,
481 MT76_STATE_SUSPEND,
482 MT76_STATE_ROC,
483 MT76_STATE_PM,
484 MT76_STATE_WED_RESET,
485};
486
487enum mt76_sta_event {
488 MT76_STA_EVENT_ASSOC,
489 MT76_STA_EVENT_AUTHORIZE,
490 MT76_STA_EVENT_DISASSOC,
491};
492
493struct mt76_hw_cap {
494 bool has_2ghz;
495 bool has_5ghz;
496 bool has_6ghz;
497};
498
499#define MT_DRV_TXWI_NO_FREE BIT(0)
500#define MT_DRV_TX_ALIGNED4_SKBS BIT(1)
501#define MT_DRV_SW_RX_AIRTIME BIT(2)
502#define MT_DRV_RX_DMA_HDR BIT(3)
503#define MT_DRV_HW_MGMT_TXQ BIT(4)
504#define MT_DRV_AMSDU_OFFLOAD BIT(5)
505#define MT_DRV_IGNORE_TXS_FAILED BIT(6)
506
507struct mt76_driver_ops {
508 u32 drv_flags;
509 u32 survey_flags;
510 u16 txwi_size;
511 u16 token_size;
512 u8 mcs_rates;
513
514 unsigned int link_data_size;
515
516 void (*update_survey)(struct mt76_phy *phy);
517 int (*set_channel)(struct mt76_phy *phy);
518
519 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr,
520 enum mt76_txq_id qid, struct mt76_wcid *wcid,
521 struct ieee80211_sta *sta,
522 struct mt76_tx_info *tx_info);
523
524 void (*tx_complete_skb)(struct mt76_dev *dev,
525 struct mt76_queue_entry *e);
526
527 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update);
528
529 bool (*rx_check)(struct mt76_dev *dev, void *data, int len);
530
531 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q,
532 struct sk_buff *skb, u32 *info);
533
534 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q);
535
536 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta,
537 bool ps);
538
539 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif,
540 struct ieee80211_sta *sta);
541
542 int (*sta_event)(struct mt76_dev *dev, struct ieee80211_vif *vif,
543 struct ieee80211_sta *sta, enum mt76_sta_event ev);
544
545 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif,
546 struct ieee80211_sta *sta);
547
548 int (*vif_link_add)(struct mt76_phy *phy, struct ieee80211_vif *vif,
549 struct ieee80211_bss_conf *link_conf,
550 struct mt76_vif_link *mlink);
551
552 void (*vif_link_remove)(struct mt76_phy *phy,
553 struct ieee80211_vif *vif,
554 struct ieee80211_bss_conf *link_conf,
555 struct mt76_vif_link *mlink);
556};
557
558struct mt76_channel_state {
559 u64 cc_active;
560 u64 cc_busy;
561 u64 cc_rx;
562 u64 cc_bss_rx;
563 u64 cc_tx;
564
565 s8 noise;
566};
567
568struct mt76_sband {
569 struct ieee80211_supported_band sband;
570 struct mt76_channel_state *chan;
571};
572
573/* addr req mask */
574#define MT_VEND_TYPE_EEPROM BIT(31)
575#define MT_VEND_TYPE_CFG BIT(30)
576#define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG)
577
578#define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n))
579enum mt_vendor_req {
580 MT_VEND_DEV_MODE = 0x1,
581 MT_VEND_WRITE = 0x2,
582 MT_VEND_POWER_ON = 0x4,
583 MT_VEND_MULTI_WRITE = 0x6,
584 MT_VEND_MULTI_READ = 0x7,
585 MT_VEND_READ_EEPROM = 0x9,
586 MT_VEND_WRITE_FCE = 0x42,
587 MT_VEND_WRITE_CFG = 0x46,
588 MT_VEND_READ_CFG = 0x47,
589 MT_VEND_READ_EXT = 0x63,
590 MT_VEND_WRITE_EXT = 0x66,
591 MT_VEND_FEATURE_SET = 0x91,
592};
593
594enum mt76u_in_ep {
595 MT_EP_IN_PKT_RX,
596 MT_EP_IN_CMD_RESP,
597 __MT_EP_IN_MAX,
598};
599
600enum mt76u_out_ep {
601 MT_EP_OUT_INBAND_CMD,
602 MT_EP_OUT_AC_BE,
603 MT_EP_OUT_AC_BK,
604 MT_EP_OUT_AC_VI,
605 MT_EP_OUT_AC_VO,
606 MT_EP_OUT_HCCA,
607 __MT_EP_OUT_MAX,
608};
609
610struct mt76_mcu {
611 struct mutex mutex;
612 u32 msg_seq;
613 int timeout;
614
615 struct sk_buff_head res_q;
616 wait_queue_head_t wait;
617};
618
619#define MT_TX_SG_MAX_SIZE 8
620#define MT_RX_SG_MAX_SIZE 4
621#define MT_NUM_TX_ENTRIES 256
622#define MT_NUM_RX_ENTRIES 128
623#define MCU_RESP_URB_SIZE 1024
624struct mt76_usb {
625 struct mutex usb_ctrl_mtx;
626 u8 *data;
627 u16 data_len;
628
629 struct mt76_worker status_worker;
630 struct mt76_worker rx_worker;
631
632 struct work_struct stat_work;
633
634 u8 out_ep[__MT_EP_OUT_MAX];
635 u8 in_ep[__MT_EP_IN_MAX];
636 bool sg_en;
637
638 struct mt76u_mcu {
639 u8 *data;
640 /* multiple reads */
641 struct mt76_reg_pair *rp;
642 int rp_len;
643 u32 base;
644 } mcu;
645};
646
647#define MT76S_XMIT_BUF_SZ 0x3fe00
648#define MT76S_NUM_TX_ENTRIES 256
649#define MT76S_NUM_RX_ENTRIES 512
650struct mt76_sdio {
651 struct mt76_worker txrx_worker;
652 struct mt76_worker status_worker;
653 struct mt76_worker net_worker;
654 struct mt76_worker stat_worker;
655
656 u8 *xmit_buf;
657 u32 xmit_buf_sz;
658
659 struct sdio_func *func;
660 void *intr_data;
661 u8 hw_ver;
662 wait_queue_head_t wait;
663
664 int pse_mcu_quota_max;
665 struct {
666 int pse_data_quota;
667 int ple_data_quota;
668 int pse_mcu_quota;
669 int pse_page_size;
670 int deficit;
671 } sched;
672
673 int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr);
674};
675
676struct mt76_mmio {
677 void __iomem *regs;
678 spinlock_t irq_lock;
679 u32 irqmask;
680
681 struct mtk_wed_device wed;
682 struct mtk_wed_device wed_hif2;
683 struct completion wed_reset;
684 struct completion wed_reset_complete;
685};
686
687struct mt76_rx_status {
688 union {
689 struct mt76_wcid *wcid;
690 u16 wcid_idx;
691 };
692
693 u32 reorder_time;
694
695 u32 ampdu_ref;
696 u32 timestamp;
697
698 u8 iv[6];
699
700 u8 phy_idx:2;
701 u8 aggr:1;
702 u8 qos_ctl;
703 u16 seqno;
704
705 u16 freq;
706 u32 flag;
707 u8 enc_flags;
708 u8 encoding:3, bw:4;
709 union {
710 struct {
711 u8 he_ru:3;
712 u8 he_gi:2;
713 u8 he_dcm:1;
714 };
715 struct {
716 u8 ru:4;
717 u8 gi:2;
718 } eht;
719 };
720
721 u8 amsdu:1, first_amsdu:1, last_amsdu:1;
722 u8 rate_idx;
723 u8 nss:5, band:3;
724 s8 signal;
725 u8 chains;
726 s8 chain_signal[IEEE80211_MAX_CHAINS];
727};
728
729struct mt76_freq_range_power {
730 const struct cfg80211_sar_freq_ranges *range;
731 s8 power;
732};
733
734struct mt76_testmode_ops {
735 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state);
736 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb,
737 enum mt76_testmode_state new_state);
738 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg);
739};
740
741struct mt76_testmode_data {
742 enum mt76_testmode_state state;
743
744 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)];
745 struct sk_buff *tx_skb;
746
747 u32 tx_count;
748 u16 tx_mpdu_len;
749
750 u8 tx_rate_mode;
751 u8 tx_rate_idx;
752 u8 tx_rate_nss;
753 u8 tx_rate_sgi;
754 u8 tx_rate_ldpc;
755 u8 tx_rate_stbc;
756 u8 tx_ltf;
757
758 u8 tx_antenna_mask;
759 u8 tx_spe_idx;
760
761 u8 tx_duty_cycle;
762 u32 tx_time;
763 u32 tx_ipg;
764
765 u32 freq_offset;
766
767 u8 tx_power[4];
768 u8 tx_power_control;
769
770 u8 addr[3][ETH_ALEN];
771
772 u32 tx_pending;
773 u32 tx_queued;
774 u16 tx_queued_limit;
775 u32 tx_done;
776 struct {
777 u64 packets[__MT_RXQ_MAX];
778 u64 fcs_error[__MT_RXQ_MAX];
779 } rx_stats;
780};
781
782struct mt76_vif_link {
783 u8 idx;
784 u8 link_idx;
785 u8 omac_idx;
786 u8 band_idx;
787 u8 wmm_idx;
788 u8 scan_seq_num;
789 u8 cipher;
790 u8 basic_rates_idx;
791 u8 mcast_rates_idx;
792 u8 beacon_rates_idx;
793 bool offchannel;
794 struct ieee80211_chanctx_conf *ctx;
795 struct mt76_wcid *wcid;
796 struct mt76_vif_data *mvif;
797 struct rcu_head rcu_head;
798};
799
800struct mt76_vif_data {
801 struct mt76_vif_link __rcu *link[IEEE80211_MLD_MAX_NUM_LINKS];
802 struct mt76_vif_link __rcu *offchannel_link;
803
804 struct mt76_phy *roc_phy;
805 u16 valid_links;
806 u8 deflink_id;
807};
808
809struct mt76_phy {
810 struct ieee80211_hw *hw;
811 struct mt76_dev *dev;
812 void *priv;
813
814 unsigned long state;
815 unsigned int num_sta;
816 u8 band_idx;
817
818 spinlock_t tx_lock;
819 struct list_head tx_list;
820 struct mt76_queue *q_tx[__MT_TXQ_MAX];
821
822 struct cfg80211_chan_def chandef;
823 struct cfg80211_chan_def main_chandef;
824 bool offchannel;
825 bool radar_enabled;
826
827 struct delayed_work roc_work;
828 struct ieee80211_vif *roc_vif;
829 struct mt76_vif_link *roc_link;
830
831 struct mt76_chanctx *chanctx;
832
833 struct mt76_channel_state *chan_state;
834 enum mt76_dfs_state dfs_state;
835 ktime_t survey_time;
836
837 u32 aggr_stats[32];
838
839 struct mt76_hw_cap cap;
840 struct mt76_sband sband_2g;
841 struct mt76_sband sband_5g;
842 struct mt76_sband sband_6g;
843
844 u8 macaddr[ETH_ALEN];
845
846 int txpower_cur;
847 u8 antenna_mask;
848 u16 chainmask;
849
850#ifdef CONFIG_NL80211_TESTMODE
851 struct mt76_testmode_data test;
852#endif
853
854 struct delayed_work mac_work;
855 u8 mac_work_count;
856
857 struct {
858 struct sk_buff *head;
859 struct sk_buff **tail;
860 u16 seqno;
861 } rx_amsdu[__MT_RXQ_MAX];
862
863 struct mt76_freq_range_power *frp;
864
865 struct {
866 struct led_classdev cdev;
867 char name[32];
868 bool al;
869 u8 pin;
870 } leds;
871};
872
873struct mt76_dev {
874 struct mt76_phy phy; /* must be first */
875 struct mt76_phy *phys[__MT_MAX_BAND];
876 struct mt76_phy *band_phys[NUM_NL80211_BANDS];
877
878 struct ieee80211_hw *hw;
879
880 spinlock_t wed_lock;
881 spinlock_t lock;
882 spinlock_t cc_lock;
883
884 u32 cur_cc_bss_rx;
885
886 struct mt76_rx_status rx_ampdu_status;
887 u32 rx_ampdu_len;
888 u32 rx_ampdu_ref;
889
890 struct mutex mutex;
891
892 const struct mt76_bus_ops *bus;
893 const struct mt76_driver_ops *drv;
894 const struct mt76_mcu_ops *mcu_ops;
895 struct device *dev;
896 struct device *dma_dev;
897
898 struct mt76_mcu mcu;
899
900 struct net_device *napi_dev;
901 struct net_device *tx_napi_dev;
902 spinlock_t rx_lock;
903 struct napi_struct napi[__MT_RXQ_MAX];
904 struct sk_buff_head rx_skb[__MT_RXQ_MAX];
905 struct tasklet_struct irq_tasklet;
906
907 struct list_head txwi_cache;
908 struct list_head rxwi_cache;
909 struct mt76_queue *q_mcu[__MT_MCUQ_MAX];
910 struct mt76_queue q_rx[__MT_RXQ_MAX];
911 const struct mt76_queue_ops *queue_ops;
912 int tx_dma_idx[4];
913
914 struct mt76_worker tx_worker;
915 struct napi_struct tx_napi;
916
917 spinlock_t token_lock;
918 struct idr token;
919 u16 wed_token_count;
920 u16 token_count;
921 u16 token_size;
922
923 spinlock_t rx_token_lock;
924 struct idr rx_token;
925 u16 rx_token_size;
926
927 wait_queue_head_t tx_wait;
928 /* spinclock used to protect wcid pktid linked list */
929 spinlock_t status_lock;
930
931 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)];
932
933 u64 vif_mask;
934
935 struct mt76_wcid global_wcid;
936 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS];
937 struct list_head wcid_list;
938
939 struct list_head sta_poll_list;
940 spinlock_t sta_poll_lock;
941
942 u32 rev;
943
944 struct tasklet_struct pre_tbtt_tasklet;
945 int beacon_int;
946 u8 beacon_mask;
947
948 struct debugfs_blob_wrapper eeprom;
949 struct debugfs_blob_wrapper otp;
950
951 char alpha2[3];
952 enum nl80211_dfs_regions region;
953
954 struct mt76_scan_rnr_param rnr;
955
956 u32 debugfs_reg;
957
958 u8 csa_complete;
959
960 u32 rxfilter;
961
962 struct delayed_work scan_work;
963 struct {
964 struct cfg80211_scan_request *req;
965 struct ieee80211_channel *chan;
966 struct ieee80211_vif *vif;
967 struct mt76_vif_link *mlink;
968 struct mt76_phy *phy;
969 int chan_idx;
970 } scan;
971
972#ifdef CONFIG_NL80211_TESTMODE
973 const struct mt76_testmode_ops *test_ops;
974 struct {
975 const char *name;
976 u32 offset;
977 } test_mtd;
978#endif
979 struct workqueue_struct *wq;
980
981 union {
982 struct mt76_mmio mmio;
983 struct mt76_usb usb;
984 struct mt76_sdio sdio;
985 };
986};
987
988/* per-phy stats. */
989struct mt76_mib_stats {
990 u32 ack_fail_cnt;
991 u32 fcs_err_cnt;
992 u32 rts_cnt;
993 u32 rts_retries_cnt;
994 u32 ba_miss_cnt;
995 u32 tx_bf_cnt;
996 u32 tx_mu_bf_cnt;
997 u32 tx_mu_mpdu_cnt;
998 u32 tx_mu_acked_mpdu_cnt;
999 u32 tx_su_acked_mpdu_cnt;
1000 u32 tx_bf_ibf_ppdu_cnt;
1001 u32 tx_bf_ebf_ppdu_cnt;
1002
1003 u32 tx_bf_rx_fb_all_cnt;
1004 u32 tx_bf_rx_fb_eht_cnt;
1005 u32 tx_bf_rx_fb_he_cnt;
1006 u32 tx_bf_rx_fb_vht_cnt;
1007 u32 tx_bf_rx_fb_ht_cnt;
1008
1009 u32 tx_bf_rx_fb_bw; /* value of last sample, not cumulative */
1010 u32 tx_bf_rx_fb_nc_cnt;
1011 u32 tx_bf_rx_fb_nr_cnt;
1012 u32 tx_bf_fb_cpl_cnt;
1013 u32 tx_bf_fb_trig_cnt;
1014
1015 u32 tx_ampdu_cnt;
1016 u32 tx_stop_q_empty_cnt;
1017 u32 tx_mpdu_attempts_cnt;
1018 u32 tx_mpdu_success_cnt;
1019 u32 tx_pkt_ebf_cnt;
1020 u32 tx_pkt_ibf_cnt;
1021
1022 u32 tx_rwp_fail_cnt;
1023 u32 tx_rwp_need_cnt;
1024
1025 /* rx stats */
1026 u32 rx_fifo_full_cnt;
1027 u32 channel_idle_cnt;
1028 u32 primary_cca_busy_time;
1029 u32 secondary_cca_busy_time;
1030 u32 primary_energy_detect_time;
1031 u32 cck_mdrdy_time;
1032 u32 ofdm_mdrdy_time;
1033 u32 green_mdrdy_time;
1034 u32 rx_vector_mismatch_cnt;
1035 u32 rx_delimiter_fail_cnt;
1036 u32 rx_mrdy_cnt;
1037 u32 rx_len_mismatch_cnt;
1038 u32 rx_mpdu_cnt;
1039 u32 rx_ampdu_cnt;
1040 u32 rx_ampdu_bytes_cnt;
1041 u32 rx_ampdu_valid_subframe_cnt;
1042 u32 rx_ampdu_valid_subframe_bytes_cnt;
1043 u32 rx_pfdrop_cnt;
1044 u32 rx_vec_queue_overflow_drop_cnt;
1045 u32 rx_ba_cnt;
1046
1047 u32 tx_amsdu[8];
1048 u32 tx_amsdu_cnt;
1049
1050 /* mcu_muru_stats */
1051 u32 dl_cck_cnt;
1052 u32 dl_ofdm_cnt;
1053 u32 dl_htmix_cnt;
1054 u32 dl_htgf_cnt;
1055 u32 dl_vht_su_cnt;
1056 u32 dl_vht_2mu_cnt;
1057 u32 dl_vht_3mu_cnt;
1058 u32 dl_vht_4mu_cnt;
1059 u32 dl_he_su_cnt;
1060 u32 dl_he_ext_su_cnt;
1061 u32 dl_he_2ru_cnt;
1062 u32 dl_he_2mu_cnt;
1063 u32 dl_he_3ru_cnt;
1064 u32 dl_he_3mu_cnt;
1065 u32 dl_he_4ru_cnt;
1066 u32 dl_he_4mu_cnt;
1067 u32 dl_he_5to8ru_cnt;
1068 u32 dl_he_9to16ru_cnt;
1069 u32 dl_he_gtr16ru_cnt;
1070
1071 u32 ul_hetrig_su_cnt;
1072 u32 ul_hetrig_2ru_cnt;
1073 u32 ul_hetrig_3ru_cnt;
1074 u32 ul_hetrig_4ru_cnt;
1075 u32 ul_hetrig_5to8ru_cnt;
1076 u32 ul_hetrig_9to16ru_cnt;
1077 u32 ul_hetrig_gtr16ru_cnt;
1078 u32 ul_hetrig_2mu_cnt;
1079 u32 ul_hetrig_3mu_cnt;
1080 u32 ul_hetrig_4mu_cnt;
1081};
1082
1083struct mt76_power_limits {
1084 s8 cck[4];
1085 s8 ofdm[8];
1086 s8 mcs[4][10];
1087 s8 ru[7][12];
1088 s8 eht[16][16];
1089};
1090
1091struct mt76_ethtool_worker_info {
1092 u64 *data;
1093 int idx;
1094 int initial_stat_idx;
1095 int worker_stat_count;
1096 int sta_count;
1097};
1098
1099struct mt76_chanctx {
1100 struct mt76_phy *phy;
1101};
1102
1103#define CCK_RATE(_idx, _rate) { \
1104 .bitrate = _rate, \
1105 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \
1106 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \
1107 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \
1108}
1109
1110#define OFDM_RATE(_idx, _rate) { \
1111 .bitrate = _rate, \
1112 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \
1113 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \
1114}
1115
1116extern struct ieee80211_rate mt76_rates[12];
1117
1118#define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__)
1119#define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__)
1120#define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__)
1121#define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__)
1122#define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__)
1123
1124#define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val)
1125#define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0)
1126
1127#define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__)
1128#define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__)
1129#define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__)
1130#define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__)
1131#define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__)
1132#define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__)
1133#define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__)
1134
1135
1136#define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76))
1137
1138#define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val)
1139#define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0)
1140
1141#define mt76_get_field(_dev, _reg, _field) \
1142 FIELD_GET(_field, mt76_rr(dev, _reg))
1143
1144#define mt76_rmw_field(_dev, _reg, _field, _val) \
1145 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
1146
1147#define __mt76_rmw_field(_dev, _reg, _field, _val) \
1148 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
1149
1150#define mt76_hw(dev) (dev)->mphy.hw
1151
1152bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
1153 int timeout);
1154
1155#define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__)
1156
1157bool ____mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
1158 int timeout, int kick);
1159#define __mt76_poll_msec(...) ____mt76_poll_msec(__VA_ARGS__, 10)
1160#define mt76_poll_msec(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__, 10)
1161#define mt76_poll_msec_tick(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__)
1162
1163void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs);
1164void mt76_pci_disable_aspm(struct pci_dev *pdev);
1165bool mt76_pci_aspm_supported(struct pci_dev *pdev);
1166
1167static inline u16 mt76_chip(struct mt76_dev *dev)
1168{
1169 return dev->rev >> 16;
1170}
1171
1172static inline u16 mt76_rev(struct mt76_dev *dev)
1173{
1174 return dev->rev & 0xffff;
1175}
1176
1177void mt76_wed_release_rx_buf(struct mtk_wed_device *wed);
1178void mt76_wed_offload_disable(struct mtk_wed_device *wed);
1179void mt76_wed_reset_complete(struct mtk_wed_device *wed);
1180void mt76_wed_dma_reset(struct mt76_dev *dev);
1181int mt76_wed_net_setup_tc(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1182 struct net_device *netdev, enum tc_setup_type type,
1183 void *type_data);
1184#ifdef CONFIG_NET_MEDIATEK_SOC_WED
1185u32 mt76_wed_init_rx_buf(struct mtk_wed_device *wed, int size);
1186int mt76_wed_offload_enable(struct mtk_wed_device *wed);
1187int mt76_wed_dma_setup(struct mt76_dev *dev, struct mt76_queue *q, bool reset);
1188#else
1189static inline u32 mt76_wed_init_rx_buf(struct mtk_wed_device *wed, int size)
1190{
1191 return 0;
1192}
1193
1194static inline int mt76_wed_offload_enable(struct mtk_wed_device *wed)
1195{
1196 return 0;
1197}
1198
1199static inline int mt76_wed_dma_setup(struct mt76_dev *dev, struct mt76_queue *q,
1200 bool reset)
1201{
1202 return 0;
1203}
1204#endif /* CONFIG_NET_MEDIATEK_SOC_WED */
1205
1206#define mt76xx_chip(dev) mt76_chip(&((dev)->mt76))
1207#define mt76xx_rev(dev) mt76_rev(&((dev)->mt76))
1208
1209#define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__)
1210#define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__)
1211#define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__)
1212#define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mphy), __VA_ARGS__)
1213#define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__)
1214#define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__)
1215#define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__)
1216#define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__)
1217#define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__)
1218
1219#define mt76_for_each_q_rx(dev, i) \
1220 for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \
1221 if ((dev)->q_rx[i].ndesc)
1222
1223
1224#define mt76_dereference(p, dev) \
1225 rcu_dereference_protected(p, lockdep_is_held(&(dev)->mutex))
1226
1227struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size,
1228 const struct ieee80211_ops *ops,
1229 const struct mt76_driver_ops *drv_ops);
1230int mt76_register_device(struct mt76_dev *dev, bool vht,
1231 struct ieee80211_rate *rates, int n_rates);
1232void mt76_unregister_device(struct mt76_dev *dev);
1233void mt76_free_device(struct mt76_dev *dev);
1234void mt76_unregister_phy(struct mt76_phy *phy);
1235
1236struct mt76_phy *mt76_alloc_radio_phy(struct mt76_dev *dev, unsigned int size,
1237 u8 band_idx);
1238struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size,
1239 const struct ieee80211_ops *ops,
1240 u8 band_idx);
1241int mt76_register_phy(struct mt76_phy *phy, bool vht,
1242 struct ieee80211_rate *rates, int n_rates);
1243struct mt76_phy *mt76_vif_phy(struct ieee80211_hw *hw,
1244 struct ieee80211_vif *vif);
1245
1246struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy,
1247 const struct file_operations *ops);
1248static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev)
1249{
1250 return mt76_register_debugfs_fops(phy: &dev->phy, NULL);
1251}
1252
1253int mt76_queues_read(struct seq_file *s, void *data);
1254void mt76_seq_puts_array(struct seq_file *file, const char *str,
1255 s8 *val, int len);
1256
1257int mt76_eeprom_init(struct mt76_dev *dev, int len);
1258void mt76_eeprom_override(struct mt76_phy *phy);
1259int mt76_get_of_data_from_mtd(struct mt76_dev *dev, void *eep, int offset, int len);
1260int mt76_get_of_data_from_nvmem(struct mt76_dev *dev, void *eep,
1261 const char *cell_name, int len);
1262
1263struct mt76_queue *
1264mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc,
1265 int ring_base, void *wed, u32 flags);
1266static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx,
1267 int n_desc, int ring_base, void *wed,
1268 u32 flags)
1269{
1270 struct mt76_queue *q;
1271
1272 q = mt76_init_queue(dev: phy->dev, qid, idx, n_desc, ring_base, wed, flags);
1273 if (IS_ERR(ptr: q))
1274 return PTR_ERR(ptr: q);
1275
1276 phy->q_tx[qid] = q;
1277
1278 return 0;
1279}
1280
1281static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx,
1282 int n_desc, int ring_base)
1283{
1284 struct mt76_queue *q;
1285
1286 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, NULL, flags: 0);
1287 if (IS_ERR(ptr: q))
1288 return PTR_ERR(ptr: q);
1289
1290 dev->q_mcu[qid] = q;
1291
1292 return 0;
1293}
1294
1295static inline struct mt76_phy *
1296mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx)
1297{
1298 if ((phy_idx == MT_BAND1 && dev->phys[phy_idx]) ||
1299 (phy_idx == MT_BAND2 && dev->phys[phy_idx]))
1300 return dev->phys[phy_idx];
1301
1302 return &dev->phy;
1303}
1304
1305static inline struct ieee80211_hw *
1306mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx)
1307{
1308 return mt76_dev_phy(dev, phy_idx)->hw;
1309}
1310
1311static inline u8 *
1312mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t)
1313{
1314 return (u8 *)t - dev->drv->txwi_size;
1315}
1316
1317/* increment with wrap-around */
1318static inline int mt76_incr(int val, int size)
1319{
1320 return (val + 1) & (size - 1);
1321}
1322
1323/* decrement with wrap-around */
1324static inline int mt76_decr(int val, int size)
1325{
1326 return (val - 1) & (size - 1);
1327}
1328
1329u8 mt76_ac_to_hwq(u8 ac);
1330
1331static inline struct ieee80211_txq *
1332mtxq_to_txq(struct mt76_txq *mtxq)
1333{
1334 void *ptr = mtxq;
1335
1336 return container_of(ptr, struct ieee80211_txq, drv_priv);
1337}
1338
1339static inline struct ieee80211_sta *
1340wcid_to_sta(struct mt76_wcid *wcid)
1341{
1342 void *ptr = wcid;
1343
1344 if (!wcid || !wcid->sta)
1345 return NULL;
1346
1347 if (wcid->def_wcid)
1348 ptr = wcid->def_wcid;
1349
1350 return container_of(ptr, struct ieee80211_sta, drv_priv);
1351}
1352
1353static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb)
1354{
1355 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) >
1356 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data));
1357 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data);
1358}
1359
1360static inline void *mt76_skb_get_hdr(struct sk_buff *skb)
1361{
1362 struct mt76_rx_status mstat;
1363 u8 *data = skb->data;
1364
1365 /* Alignment concerns */
1366 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4);
1367 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4);
1368
1369 mstat = *((struct mt76_rx_status *)skb->cb);
1370
1371 if (mstat.flag & RX_FLAG_RADIOTAP_HE)
1372 data += sizeof(struct ieee80211_radiotap_he);
1373 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU)
1374 data += sizeof(struct ieee80211_radiotap_he_mu);
1375
1376 return data;
1377}
1378
1379static inline void mt76_insert_hdr_pad(struct sk_buff *skb)
1380{
1381 int len = ieee80211_get_hdrlen_from_skb(skb);
1382
1383 if (len % 4 == 0)
1384 return;
1385
1386 skb_push(skb, len: 2);
1387 memmove(skb->data, skb->data + 2, len);
1388
1389 skb->data[len] = 0;
1390 skb->data[len + 1] = 0;
1391}
1392
1393static inline bool mt76_is_skb_pktid(u8 pktid)
1394{
1395 if (pktid & MT_PACKET_ID_HAS_RATE)
1396 return false;
1397
1398 return pktid >= MT_PACKET_ID_FIRST;
1399}
1400
1401static inline u8 mt76_tx_power_path_delta(u8 path)
1402{
1403 static const u8 path_delta[5] = { 0, 6, 9, 12, 14 };
1404 u8 idx = path - 1;
1405
1406 return (idx < ARRAY_SIZE(path_delta)) ? path_delta[idx] : 0;
1407}
1408
1409static inline bool mt76_testmode_enabled(struct mt76_phy *phy)
1410{
1411#ifdef CONFIG_NL80211_TESTMODE
1412 return phy->test.state != MT76_TM_STATE_OFF;
1413#else
1414 return false;
1415#endif
1416}
1417
1418static inline bool mt76_is_testmode_skb(struct mt76_dev *dev,
1419 struct sk_buff *skb,
1420 struct ieee80211_hw **hw)
1421{
1422#ifdef CONFIG_NL80211_TESTMODE
1423 int i;
1424
1425 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) {
1426 struct mt76_phy *phy = dev->phys[i];
1427
1428 if (phy && skb == phy->test.tx_skb) {
1429 *hw = dev->phys[i]->hw;
1430 return true;
1431 }
1432 }
1433 return false;
1434#else
1435 return false;
1436#endif
1437}
1438
1439void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb);
1440void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta,
1441 struct mt76_wcid *wcid, struct sk_buff *skb);
1442void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq);
1443void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta,
1444 bool send_bar);
1445void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb);
1446void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid);
1447void mt76_txq_schedule_all(struct mt76_phy *phy);
1448void mt76_tx_worker_run(struct mt76_dev *dev);
1449void mt76_tx_worker(struct mt76_worker *w);
1450void mt76_release_buffered_frames(struct ieee80211_hw *hw,
1451 struct ieee80211_sta *sta,
1452 u16 tids, int nframes,
1453 enum ieee80211_frame_release_type reason,
1454 bool more_data);
1455bool mt76_has_tx_pending(struct mt76_phy *phy);
1456int mt76_update_channel(struct mt76_phy *phy);
1457void mt76_update_survey(struct mt76_phy *phy);
1458void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time);
1459int mt76_get_survey(struct ieee80211_hw *hw, int idx,
1460 struct survey_info *survey);
1461int mt76_rx_signal(u8 chain_mask, s8 *chain_signal);
1462void mt76_set_stream_caps(struct mt76_phy *phy, bool vht);
1463
1464int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid,
1465 u16 ssn, u16 size);
1466void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid);
1467
1468void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid,
1469 struct ieee80211_key_conf *key);
1470
1471void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list)
1472 __acquires(&dev->status_lock);
1473void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list)
1474 __releases(&dev->status_lock);
1475
1476int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid,
1477 struct sk_buff *skb);
1478struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev,
1479 struct mt76_wcid *wcid, int pktid,
1480 struct sk_buff_head *list);
1481void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb,
1482 struct sk_buff_head *list);
1483void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb,
1484 struct list_head *free_list);
1485static inline void
1486mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb)
1487{
1488 __mt76_tx_complete_skb(dev, wcid, skb, NULL);
1489}
1490
1491void mt76_tx_status_check(struct mt76_dev *dev, bool flush);
1492int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1493 struct ieee80211_sta *sta,
1494 enum ieee80211_sta_state old_state,
1495 enum ieee80211_sta_state new_state);
1496void __mt76_sta_remove(struct mt76_phy *phy, struct ieee80211_vif *vif,
1497 struct ieee80211_sta *sta);
1498void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1499 struct ieee80211_sta *sta);
1500
1501int mt76_get_min_avg_rssi(struct mt76_dev *dev, u8 phy_idx);
1502
1503s8 mt76_get_power_bound(struct mt76_phy *phy, s8 txpower);
1504
1505int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1506 unsigned int link_id, int *dbm);
1507int mt76_init_sar_power(struct ieee80211_hw *hw,
1508 const struct cfg80211_sar_specs *sar);
1509int mt76_get_sar_power(struct mt76_phy *phy,
1510 struct ieee80211_channel *chan,
1511 int power);
1512
1513void mt76_csa_check(struct mt76_dev *dev);
1514void mt76_csa_finish(struct mt76_dev *dev);
1515
1516int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant);
1517int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set);
1518void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id);
1519int mt76_get_rate(struct mt76_dev *dev,
1520 struct ieee80211_supported_band *sband,
1521 int idx, bool cck);
1522int mt76_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1523 struct ieee80211_scan_request *hw_req);
1524void mt76_cancel_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1525void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1526 const u8 *mac);
1527void mt76_sw_scan_complete(struct ieee80211_hw *hw,
1528 struct ieee80211_vif *vif);
1529enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy);
1530int mt76_add_chanctx(struct ieee80211_hw *hw,
1531 struct ieee80211_chanctx_conf *conf);
1532void mt76_remove_chanctx(struct ieee80211_hw *hw,
1533 struct ieee80211_chanctx_conf *conf);
1534void mt76_change_chanctx(struct ieee80211_hw *hw,
1535 struct ieee80211_chanctx_conf *conf,
1536 u32 changed);
1537int mt76_assign_vif_chanctx(struct ieee80211_hw *hw,
1538 struct ieee80211_vif *vif,
1539 struct ieee80211_bss_conf *link_conf,
1540 struct ieee80211_chanctx_conf *conf);
1541void mt76_unassign_vif_chanctx(struct ieee80211_hw *hw,
1542 struct ieee80211_vif *vif,
1543 struct ieee80211_bss_conf *link_conf,
1544 struct ieee80211_chanctx_conf *conf);
1545int mt76_switch_vif_chanctx(struct ieee80211_hw *hw,
1546 struct ieee80211_vif_chanctx_switch *vifs,
1547 int n_vifs,
1548 enum ieee80211_chanctx_switch_mode mode);
1549int mt76_remain_on_channel(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1550 struct ieee80211_channel *chan, int duration,
1551 enum ieee80211_roc_type type);
1552int mt76_cancel_remain_on_channel(struct ieee80211_hw *hw,
1553 struct ieee80211_vif *vif);
1554int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1555 void *data, int len);
1556int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb,
1557 struct netlink_callback *cb, void *data, int len);
1558int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state);
1559int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len);
1560
1561static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable)
1562{
1563#ifdef CONFIG_NL80211_TESTMODE
1564 enum mt76_testmode_state state = MT76_TM_STATE_IDLE;
1565
1566 if (disable || phy->test.state == MT76_TM_STATE_OFF)
1567 state = MT76_TM_STATE_OFF;
1568
1569 mt76_testmode_set_state(phy, state);
1570#endif
1571}
1572
1573
1574/* internal */
1575static inline struct ieee80211_hw *
1576mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb)
1577{
1578 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1579 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2;
1580 struct ieee80211_hw *hw = mt76_phy_hw(dev, phy_idx);
1581
1582 info->hw_queue &= ~MT_TX_HW_QUEUE_PHY;
1583
1584 return hw;
1585}
1586
1587void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
1588void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
1589struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev);
1590void mt76_free_pending_rxwi(struct mt76_dev *dev);
1591void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames,
1592 struct napi_struct *napi);
1593void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
1594 struct napi_struct *napi);
1595void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames);
1596void mt76_testmode_tx_pending(struct mt76_phy *phy);
1597void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q,
1598 struct mt76_queue_entry *e);
1599int __mt76_set_channel(struct mt76_phy *phy, struct cfg80211_chan_def *chandef,
1600 bool offchannel);
1601int mt76_set_channel(struct mt76_phy *phy, struct cfg80211_chan_def *chandef,
1602 bool offchannel);
1603void mt76_scan_work(struct work_struct *work);
1604void mt76_abort_scan(struct mt76_dev *dev);
1605void mt76_roc_complete_work(struct work_struct *work);
1606void mt76_abort_roc(struct mt76_phy *phy);
1607struct mt76_vif_link *mt76_get_vif_phy_link(struct mt76_phy *phy,
1608 struct ieee80211_vif *vif);
1609void mt76_put_vif_phy_link(struct mt76_phy *phy, struct ieee80211_vif *vif,
1610 struct mt76_vif_link *mlink);
1611
1612/* usb */
1613static inline bool mt76u_urb_error(struct urb *urb)
1614{
1615 return urb->status &&
1616 urb->status != -ECONNRESET &&
1617 urb->status != -ESHUTDOWN &&
1618 urb->status != -ENOENT;
1619}
1620
1621static inline int
1622mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len,
1623 int timeout, int ep)
1624{
1625 struct usb_interface *uintf = to_usb_interface(dev->dev);
1626 struct usb_device *udev = interface_to_usbdev(uintf);
1627 struct mt76_usb *usb = &dev->usb;
1628 unsigned int pipe;
1629
1630 if (actual_len)
1631 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]);
1632 else
1633 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]);
1634
1635 return usb_bulk_msg(usb_dev: udev, pipe, data, len, actual_length: actual_len, timeout);
1636}
1637
1638void mt76_ethtool_page_pool_stats(struct mt76_dev *dev, u64 *data, int *index);
1639void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi,
1640 struct mt76_sta_stats *stats, bool eht);
1641int mt76_skb_adjust_pad(struct sk_buff *skb, int pad);
1642int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type,
1643 u16 val, u16 offset, void *buf, size_t len);
1644int mt76u_vendor_request(struct mt76_dev *dev, u8 req,
1645 u8 req_type, u16 val, u16 offset,
1646 void *buf, size_t len);
1647void mt76u_single_wr(struct mt76_dev *dev, const u8 req,
1648 const u16 offset, const u32 val);
1649void mt76u_read_copy(struct mt76_dev *dev, u32 offset,
1650 void *data, int len);
1651u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr);
1652void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type,
1653 u32 addr, u32 val);
1654int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf,
1655 struct mt76_bus_ops *ops);
1656int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf);
1657int mt76u_alloc_mcu_queue(struct mt76_dev *dev);
1658int mt76u_alloc_queues(struct mt76_dev *dev);
1659void mt76u_stop_tx(struct mt76_dev *dev);
1660void mt76u_stop_rx(struct mt76_dev *dev);
1661int mt76u_resume_rx(struct mt76_dev *dev);
1662void mt76u_queues_deinit(struct mt76_dev *dev);
1663
1664int mt76s_init(struct mt76_dev *dev, struct sdio_func *func,
1665 const struct mt76_bus_ops *bus_ops);
1666int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid);
1667int mt76s_alloc_tx(struct mt76_dev *dev);
1668void mt76s_deinit(struct mt76_dev *dev);
1669void mt76s_sdio_irq(struct sdio_func *func);
1670void mt76s_txrx_worker(struct mt76_sdio *sdio);
1671bool mt76s_txqs_empty(struct mt76_dev *dev);
1672int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func,
1673 int hw_ver);
1674u32 mt76s_rr(struct mt76_dev *dev, u32 offset);
1675void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val);
1676u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val);
1677u32 mt76s_read_pcr(struct mt76_dev *dev);
1678void mt76s_write_copy(struct mt76_dev *dev, u32 offset,
1679 const void *data, int len);
1680void mt76s_read_copy(struct mt76_dev *dev, u32 offset,
1681 void *data, int len);
1682int mt76s_wr_rp(struct mt76_dev *dev, u32 base,
1683 const struct mt76_reg_pair *data,
1684 int len);
1685int mt76s_rd_rp(struct mt76_dev *dev, u32 base,
1686 struct mt76_reg_pair *data, int len);
1687
1688struct sk_buff *
1689__mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data,
1690 int len, int data_len, gfp_t gfp);
1691static inline struct sk_buff *
1692mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data,
1693 int data_len)
1694{
1695 return __mt76_mcu_msg_alloc(dev, data, len: data_len, data_len, GFP_KERNEL);
1696}
1697
1698void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb);
1699struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev,
1700 unsigned long expires);
1701int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data,
1702 int len, bool wait_resp, struct sk_buff **ret);
1703int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb,
1704 int cmd, bool wait_resp, struct sk_buff **ret);
1705int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data,
1706 int len, int max_len);
1707static inline int
1708mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data,
1709 int len)
1710{
1711 int max_len = 4096 - dev->mcu_ops->headroom;
1712
1713 return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len);
1714}
1715
1716static inline int
1717mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len,
1718 bool wait_resp)
1719{
1720 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL);
1721}
1722
1723static inline int
1724mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd,
1725 bool wait_resp)
1726{
1727 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL);
1728}
1729
1730void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set);
1731
1732struct device_node *
1733mt76_find_power_limits_node(struct mt76_dev *dev);
1734struct device_node *
1735mt76_find_channel_node(struct device_node *np, struct ieee80211_channel *chan);
1736
1737s8 mt76_get_rate_power_limits(struct mt76_phy *phy,
1738 struct ieee80211_channel *chan,
1739 struct mt76_power_limits *dest,
1740 s8 target_power);
1741
1742static inline bool mt76_queue_is_rx(struct mt76_dev *dev, struct mt76_queue *q)
1743{
1744 int i;
1745
1746 for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++) {
1747 if (q == &dev->q_rx[i])
1748 return true;
1749 }
1750
1751 return false;
1752}
1753
1754static inline bool mt76_queue_is_wed_tx_free(struct mt76_queue *q)
1755{
1756 return (q->flags & MT_QFLAG_WED) &&
1757 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_TXFREE;
1758}
1759
1760static inline bool mt76_queue_is_wed_rro(struct mt76_queue *q)
1761{
1762 return q->flags & MT_QFLAG_WED_RRO;
1763}
1764
1765static inline bool mt76_queue_is_wed_rro_ind(struct mt76_queue *q)
1766{
1767 return mt76_queue_is_wed_rro(q) &&
1768 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_IND;
1769}
1770
1771static inline bool mt76_queue_is_wed_rro_data(struct mt76_queue *q)
1772{
1773 return mt76_queue_is_wed_rro(q) &&
1774 (FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_DATA ||
1775 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_MSDU_PG);
1776}
1777
1778static inline bool mt76_queue_is_wed_rx(struct mt76_queue *q)
1779{
1780 if (!(q->flags & MT_QFLAG_WED))
1781 return false;
1782
1783 return FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX ||
1784 mt76_queue_is_wed_rro_ind(q) || mt76_queue_is_wed_rro_data(q);
1785
1786}
1787
1788struct mt76_txwi_cache *
1789mt76_token_release(struct mt76_dev *dev, int token, bool *wake);
1790int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi);
1791void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked);
1792struct mt76_txwi_cache *mt76_rx_token_release(struct mt76_dev *dev, int token);
1793int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr,
1794 struct mt76_txwi_cache *r, dma_addr_t phys);
1795int mt76_create_page_pool(struct mt76_dev *dev, struct mt76_queue *q);
1796static inline void mt76_put_page_pool_buf(void *buf, bool allow_direct)
1797{
1798 struct page *page = virt_to_head_page(x: buf);
1799
1800 page_pool_put_full_page(pool: page->pp, page, allow_direct);
1801}
1802
1803static inline void *
1804mt76_get_page_pool_buf(struct mt76_queue *q, u32 *offset, u32 size)
1805{
1806 struct page *page;
1807
1808 page = page_pool_dev_alloc_frag(pool: q->page_pool, offset, size);
1809 if (!page)
1810 return NULL;
1811
1812 return page_address(page) + *offset;
1813}
1814
1815static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked)
1816{
1817 spin_lock_bh(lock: &dev->token_lock);
1818 __mt76_set_tx_blocked(dev, blocked);
1819 spin_unlock_bh(lock: &dev->token_lock);
1820}
1821
1822static inline int
1823mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi)
1824{
1825 int token;
1826
1827 spin_lock_bh(lock: &dev->token_lock);
1828 token = idr_alloc(&dev->token, ptr: *ptxwi, start: 0, end: dev->token_size, GFP_ATOMIC);
1829 spin_unlock_bh(lock: &dev->token_lock);
1830
1831 return token;
1832}
1833
1834static inline struct mt76_txwi_cache *
1835mt76_token_put(struct mt76_dev *dev, int token)
1836{
1837 struct mt76_txwi_cache *txwi;
1838
1839 spin_lock_bh(lock: &dev->token_lock);
1840 txwi = idr_remove(&dev->token, id: token);
1841 spin_unlock_bh(lock: &dev->token_lock);
1842
1843 return txwi;
1844}
1845
1846void mt76_wcid_init(struct mt76_wcid *wcid, u8 band_idx);
1847void mt76_wcid_cleanup(struct mt76_dev *dev, struct mt76_wcid *wcid);
1848void mt76_wcid_add_poll(struct mt76_dev *dev, struct mt76_wcid *wcid);
1849
1850static inline void
1851mt76_vif_init(struct ieee80211_vif *vif, struct mt76_vif_data *mvif)
1852{
1853 struct mt76_vif_link *mlink = (struct mt76_vif_link *)vif->drv_priv;
1854
1855 mlink->mvif = mvif;
1856 rcu_assign_pointer(mvif->link[0], mlink);
1857}
1858
1859void mt76_vif_cleanup(struct mt76_dev *dev, struct ieee80211_vif *vif);
1860
1861static inline struct mt76_vif_link *
1862mt76_vif_link(struct mt76_dev *dev, struct ieee80211_vif *vif, int link_id)
1863{
1864 struct mt76_vif_link *mlink = (struct mt76_vif_link *)vif->drv_priv;
1865 struct mt76_vif_data *mvif = mlink->mvif;
1866
1867 return mt76_dereference(mvif->link[link_id], dev);
1868}
1869
1870static inline struct mt76_vif_link *
1871mt76_vif_conf_link(struct mt76_dev *dev, struct ieee80211_vif *vif,
1872 struct ieee80211_bss_conf *link_conf)
1873{
1874 struct mt76_vif_link *mlink = (struct mt76_vif_link *)vif->drv_priv;
1875 struct mt76_vif_data *mvif = mlink->mvif;
1876
1877 if (link_conf == &vif->bss_conf)
1878 return mlink;
1879
1880 return mt76_dereference(mvif->link[link_conf->link_id], dev);
1881}
1882
1883static inline struct mt76_phy *
1884mt76_vif_link_phy(struct mt76_vif_link *mlink)
1885{
1886 struct mt76_chanctx *ctx;
1887
1888 if (!mlink->ctx)
1889 return NULL;
1890
1891 ctx = (struct mt76_chanctx *)mlink->ctx->drv_priv;
1892
1893 return ctx->phy;
1894}
1895
1896#endif
1897

source code of linux/drivers/net/wireless/mediatek/mt76/mt76.h