1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5#include "coex.h"
6#include "fw.h"
7#include "mac.h"
8#include "phy.h"
9#include "reg.h"
10#include "rtw8852a.h"
11#include "rtw8852a_rfk.h"
12#include "rtw8852a_table.h"
13#include "txrx.h"
14
15#define RTW8852A_FW_FORMAT_MAX 0
16#define RTW8852A_FW_BASENAME "rtw89/rtw8852a_fw"
17#define RTW8852A_MODULE_FIRMWARE \
18 RTW8852A_FW_BASENAME ".bin"
19
20static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = {
21 {128, 1896, grp_0}, /* ACH 0 */
22 {128, 1896, grp_0}, /* ACH 1 */
23 {128, 1896, grp_0}, /* ACH 2 */
24 {128, 1896, grp_0}, /* ACH 3 */
25 {128, 1896, grp_1}, /* ACH 4 */
26 {128, 1896, grp_1}, /* ACH 5 */
27 {128, 1896, grp_1}, /* ACH 6 */
28 {128, 1896, grp_1}, /* ACH 7 */
29 {32, 1896, grp_0}, /* B0MGQ */
30 {128, 1896, grp_0}, /* B0HIQ */
31 {32, 1896, grp_1}, /* B1MGQ */
32 {128, 1896, grp_1}, /* B1HIQ */
33 {40, 0, 0} /* FWCMDQ */
34};
35
36static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_pcie = {
37 1896, /* Group 0 */
38 1896, /* Group 1 */
39 3792, /* Public Max */
40 0 /* WP threshold */
41};
42
43static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_pcie[] = {
44 [RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_pcie, &rtw8852a_hfc_pubcfg_pcie,
45 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH},
46 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie,
47 RTW89_HCIFC_POH},
48 [RTW89_QTA_INVALID] = {NULL},
49};
50
51static const struct rtw89_dle_mem rtw8852a_dle_mem_pcie[] = {
52 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size0,
53 &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0,
54 &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4,
55 &rtw89_mac_size.ple_qt5},
56 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size0,
57 &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0,
58 &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4,
59 &rtw89_mac_size.ple_qt_52a_wow},
60 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4,
61 &rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4,
62 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
63 &rtw89_mac_size.ple_qt13},
64 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
65 NULL},
66};
67
68static const struct rtw89_reg2_def rtw8852a_pmac_ht20_mcs7_tbl[] = {
69 {0x44AC, 0x00000000},
70 {0x44B0, 0x00000000},
71 {0x44B4, 0x00000000},
72 {0x44B8, 0x00000000},
73 {0x44BC, 0x00000000},
74 {0x44C0, 0x00000000},
75 {0x44C4, 0x00000000},
76 {0x44C8, 0x00000000},
77 {0x44CC, 0x00000000},
78 {0x44D0, 0x00000000},
79 {0x44D4, 0x00000000},
80 {0x44D8, 0x00000000},
81 {0x44DC, 0x00000000},
82 {0x44E0, 0x00000000},
83 {0x44E4, 0x00000000},
84 {0x44E8, 0x00000000},
85 {0x44EC, 0x00000000},
86 {0x44F0, 0x00000000},
87 {0x44F4, 0x00000000},
88 {0x44F8, 0x00000000},
89 {0x44FC, 0x00000000},
90 {0x4500, 0x00000000},
91 {0x4504, 0x00000000},
92 {0x4508, 0x00000000},
93 {0x450C, 0x00000000},
94 {0x4510, 0x00000000},
95 {0x4514, 0x00000000},
96 {0x4518, 0x00000000},
97 {0x451C, 0x00000000},
98 {0x4520, 0x00000000},
99 {0x4524, 0x00000000},
100 {0x4528, 0x00000000},
101 {0x452C, 0x00000000},
102 {0x4530, 0x4E1F3E81},
103 {0x4534, 0x00000000},
104 {0x4538, 0x0000005A},
105 {0x453C, 0x00000000},
106 {0x4540, 0x00000000},
107 {0x4544, 0x00000000},
108 {0x4548, 0x00000000},
109 {0x454C, 0x00000000},
110 {0x4550, 0x00000000},
111 {0x4554, 0x00000000},
112 {0x4558, 0x00000000},
113 {0x455C, 0x00000000},
114 {0x4560, 0x4060001A},
115 {0x4564, 0x40000000},
116 {0x4568, 0x00000000},
117 {0x456C, 0x00000000},
118 {0x4570, 0x04000007},
119 {0x4574, 0x0000DC87},
120 {0x4578, 0x00000BAB},
121 {0x457C, 0x03E00000},
122 {0x4580, 0x00000048},
123 {0x4584, 0x00000000},
124 {0x4588, 0x000003E8},
125 {0x458C, 0x30000000},
126 {0x4590, 0x00000000},
127 {0x4594, 0x10000000},
128 {0x4598, 0x00000001},
129 {0x459C, 0x00030000},
130 {0x45A0, 0x01000000},
131 {0x45A4, 0x03000200},
132 {0x45A8, 0xC00001C0},
133 {0x45AC, 0x78018000},
134 {0x45B0, 0x80000000},
135 {0x45B4, 0x01C80600},
136 {0x45B8, 0x00000002},
137 {0x4594, 0x10000000}
138};
139
140static const struct rtw89_reg3_def rtw8852a_btc_preagc_en_defs[] = {
141 {0x4624, GENMASK(20, 14), 0x40},
142 {0x46f8, GENMASK(20, 14), 0x40},
143 {0x4674, GENMASK(20, 19), 0x2},
144 {0x4748, GENMASK(20, 19), 0x2},
145 {0x4650, GENMASK(14, 10), 0x18},
146 {0x4724, GENMASK(14, 10), 0x18},
147 {0x4688, GENMASK(1, 0), 0x3},
148 {0x475c, GENMASK(1, 0), 0x3},
149};
150
151static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_en_defs);
152
153static const struct rtw89_reg3_def rtw8852a_btc_preagc_dis_defs[] = {
154 {0x4624, GENMASK(20, 14), 0x1a},
155 {0x46f8, GENMASK(20, 14), 0x1a},
156 {0x4674, GENMASK(20, 19), 0x1},
157 {0x4748, GENMASK(20, 19), 0x1},
158 {0x4650, GENMASK(14, 10), 0x12},
159 {0x4724, GENMASK(14, 10), 0x12},
160 {0x4688, GENMASK(1, 0), 0x0},
161 {0x475c, GENMASK(1, 0), 0x0},
162};
163
164static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_dis_defs);
165
166static const struct rtw89_pwr_cfg rtw8852a_pwron[] = {
167 {0x00C6,
168 PWR_CV_MSK_B,
169 PWR_INTF_MSK_PCIE,
170 PWR_BASE_MAC,
171 PWR_CMD_WRITE, BIT(6), BIT(6)},
172 {0x1086,
173 PWR_CV_MSK_ALL,
174 PWR_INTF_MSK_SDIO,
175 PWR_BASE_MAC,
176 PWR_CMD_WRITE, BIT(0), .addr: 0},
177 {0x1086,
178 PWR_CV_MSK_ALL,
179 PWR_INTF_MSK_SDIO,
180 PWR_BASE_MAC,
181 PWR_CMD_POLL, BIT(1), BIT(1)},
182 {0x0005,
183 PWR_CV_MSK_ALL,
184 PWR_INTF_MSK_ALL,
185 PWR_BASE_MAC,
186 PWR_CMD_WRITE, BIT(4) | BIT(3), .addr: 0},
187 {0x0005,
188 PWR_CV_MSK_ALL,
189 PWR_INTF_MSK_ALL,
190 PWR_BASE_MAC,
191 PWR_CMD_WRITE, BIT(7), 0},
192 {0x0005,
193 PWR_CV_MSK_ALL,
194 PWR_INTF_MSK_ALL,
195 PWR_BASE_MAC,
196 PWR_CMD_WRITE, BIT(2), .addr: 0},
197 {0x0006,
198 PWR_CV_MSK_ALL,
199 PWR_INTF_MSK_ALL,
200 PWR_BASE_MAC,
201 PWR_CMD_POLL, BIT(1), BIT(1)},
202 {0x0006,
203 PWR_CV_MSK_ALL,
204 PWR_INTF_MSK_ALL,
205 PWR_BASE_MAC,
206 PWR_CMD_WRITE, BIT(0), BIT(0)},
207 {0x0005,
208 PWR_CV_MSK_ALL,
209 PWR_INTF_MSK_ALL,
210 PWR_BASE_MAC,
211 PWR_CMD_WRITE, BIT(0), BIT(0)},
212 {0x0005,
213 PWR_CV_MSK_ALL,
214 PWR_INTF_MSK_ALL,
215 PWR_BASE_MAC,
216 PWR_CMD_POLL, BIT(0), .addr: 0},
217 {0x106D,
218 PWR_CV_MSK_B | PWR_CV_MSK_C,
219 PWR_INTF_MSK_USB,
220 PWR_BASE_MAC,
221 PWR_CMD_WRITE, BIT(6), 0},
222 {0x0088,
223 PWR_CV_MSK_ALL,
224 PWR_INTF_MSK_ALL,
225 PWR_BASE_MAC,
226 PWR_CMD_WRITE, BIT(0), BIT(0)},
227 {0x0088,
228 PWR_CV_MSK_ALL,
229 PWR_INTF_MSK_ALL,
230 PWR_BASE_MAC,
231 PWR_CMD_WRITE, BIT(0), 0},
232 {0x0088,
233 PWR_CV_MSK_ALL,
234 PWR_INTF_MSK_ALL,
235 PWR_BASE_MAC,
236 PWR_CMD_WRITE, BIT(0), BIT(0)},
237 {0x0088,
238 PWR_CV_MSK_ALL,
239 PWR_INTF_MSK_ALL,
240 PWR_BASE_MAC,
241 PWR_CMD_WRITE, BIT(0), 0},
242 {0x0088,
243 PWR_CV_MSK_ALL,
244 PWR_INTF_MSK_ALL,
245 PWR_BASE_MAC,
246 PWR_CMD_WRITE, BIT(0), BIT(0)},
247 {0x0083,
248 PWR_CV_MSK_ALL,
249 PWR_INTF_MSK_ALL,
250 PWR_BASE_MAC,
251 PWR_CMD_WRITE, BIT(6), 0},
252 {0x0080,
253 PWR_CV_MSK_ALL,
254 PWR_INTF_MSK_ALL,
255 PWR_BASE_MAC,
256 PWR_CMD_WRITE, BIT(5), BIT(5)},
257 {0x0024,
258 PWR_CV_MSK_ALL,
259 PWR_INTF_MSK_ALL,
260 PWR_BASE_MAC,
261 PWR_CMD_WRITE, BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0},
262 {0x02A0,
263 PWR_CV_MSK_ALL,
264 PWR_INTF_MSK_ALL,
265 PWR_BASE_MAC,
266 PWR_CMD_WRITE, BIT(1), BIT(1)},
267 {0x02A2,
268 PWR_CV_MSK_ALL,
269 PWR_INTF_MSK_ALL,
270 PWR_BASE_MAC,
271 PWR_CMD_WRITE, BIT(7) | BIT(6) | BIT(5), 0},
272 {0x0071,
273 PWR_CV_MSK_ALL,
274 PWR_INTF_MSK_PCIE,
275 PWR_BASE_MAC,
276 PWR_CMD_WRITE, BIT(4), .addr: 0},
277 {0x0010,
278 PWR_CV_MSK_A,
279 PWR_INTF_MSK_PCIE,
280 PWR_BASE_MAC,
281 PWR_CMD_WRITE, BIT(2), BIT(2)},
282 {0x02A0,
283 PWR_CV_MSK_A,
284 PWR_INTF_MSK_ALL,
285 PWR_BASE_MAC,
286 PWR_CMD_WRITE, BIT(7) | BIT(6), .addr: 0},
287 {0xFFFF,
288 PWR_CV_MSK_ALL,
289 PWR_INTF_MSK_ALL,
290 0,
291 PWR_CMD_END, 0, 0},
292};
293
294static const struct rtw89_pwr_cfg rtw8852a_pwroff[] = {
295 {0x02F0,
296 PWR_CV_MSK_ALL,
297 PWR_INTF_MSK_ALL,
298 PWR_BASE_MAC,
299 PWR_CMD_WRITE, 0xFF, .addr: 0},
300 {0x02F1,
301 PWR_CV_MSK_ALL,
302 PWR_INTF_MSK_ALL,
303 PWR_BASE_MAC,
304 PWR_CMD_WRITE, 0xFF, 0},
305 {0x0006,
306 PWR_CV_MSK_ALL,
307 PWR_INTF_MSK_ALL,
308 PWR_BASE_MAC,
309 PWR_CMD_WRITE, BIT(0), BIT(0)},
310 {0x0002,
311 PWR_CV_MSK_ALL,
312 PWR_INTF_MSK_ALL,
313 PWR_BASE_MAC,
314 PWR_CMD_WRITE, BIT(1) | BIT(0), 0},
315 {0x0082,
316 PWR_CV_MSK_ALL,
317 PWR_INTF_MSK_ALL,
318 PWR_BASE_MAC,
319 PWR_CMD_WRITE, BIT(1) | BIT(0), .addr: 0},
320 {0x106D,
321 PWR_CV_MSK_B | PWR_CV_MSK_C,
322 PWR_INTF_MSK_USB,
323 PWR_BASE_MAC,
324 PWR_CMD_WRITE, BIT(6), BIT(6)},
325 {0x0005,
326 PWR_CV_MSK_ALL,
327 PWR_INTF_MSK_ALL,
328 PWR_BASE_MAC,
329 PWR_CMD_WRITE, BIT(1), BIT(1)},
330 {0x0005,
331 PWR_CV_MSK_ALL,
332 PWR_INTF_MSK_ALL,
333 PWR_BASE_MAC,
334 PWR_CMD_POLL, BIT(1), 0},
335 {0x0091,
336 PWR_CV_MSK_ALL,
337 PWR_INTF_MSK_PCIE,
338 PWR_BASE_MAC,
339 PWR_CMD_WRITE, BIT(0), .addr: 0},
340 {0x0092,
341 PWR_CV_MSK_ALL,
342 PWR_INTF_MSK_PCIE,
343 PWR_BASE_MAC,
344 PWR_CMD_WRITE, BIT(4), BIT(4)},
345 {0x0005,
346 PWR_CV_MSK_ALL,
347 PWR_INTF_MSK_PCIE,
348 PWR_BASE_MAC,
349 PWR_CMD_WRITE, BIT(2), BIT(2)},
350 {0x0007,
351 PWR_CV_MSK_ALL,
352 PWR_INTF_MSK_USB,
353 PWR_BASE_MAC,
354 PWR_CMD_WRITE, BIT(4), 0},
355 {0x0007,
356 PWR_CV_MSK_ALL,
357 PWR_INTF_MSK_SDIO,
358 PWR_BASE_MAC,
359 PWR_CMD_WRITE, BIT(6) | BIT(4), .addr: 0},
360 {0x0005,
361 PWR_CV_MSK_ALL,
362 PWR_INTF_MSK_SDIO,
363 PWR_BASE_MAC,
364 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)},
365 {0x0005,
366 PWR_CV_MSK_C | PWR_CV_MSK_D | PWR_CV_MSK_E | PWR_CV_MSK_F |
367 PWR_CV_MSK_G,
368 PWR_INTF_MSK_USB,
369 PWR_BASE_MAC,
370 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)},
371 {0x1086,
372 PWR_CV_MSK_ALL,
373 PWR_INTF_MSK_SDIO,
374 PWR_BASE_MAC,
375 PWR_CMD_WRITE, BIT(0), BIT(0)},
376 {0x1086,
377 PWR_CV_MSK_ALL,
378 PWR_INTF_MSK_SDIO,
379 PWR_BASE_MAC,
380 PWR_CMD_POLL, BIT(1), .addr: 0},
381 {0xFFFF,
382 PWR_CV_MSK_ALL,
383 PWR_INTF_MSK_ALL,
384 0,
385 PWR_CMD_END, 0, 0},
386};
387
388static const struct rtw89_pwr_cfg * const pwr_on_seq_8852a[] = {
389 rtw8852a_pwron, NULL
390};
391
392static const struct rtw89_pwr_cfg * const pwr_off_seq_8852a[] = {
393 rtw8852a_pwroff, NULL
394};
395
396static const u32 rtw8852a_h2c_regs[RTW89_H2CREG_MAX] = {
397 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2,
398 R_AX_H2CREG_DATA3
399};
400
401static const u32 rtw8852a_c2h_regs[RTW89_C2HREG_MAX] = {
402 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2,
403 R_AX_C2HREG_DATA3
404};
405
406static const u32 rtw8852a_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = {
407 R_AX_C2HREG_DATA3 + 3, R_AX_C2HREG_DATA3 + 3,
408};
409
410static const struct rtw89_page_regs rtw8852a_page_regs = {
411 .hci_fc_ctrl = R_AX_HCI_FC_CTRL,
412 .ch_page_ctrl = R_AX_CH_PAGE_CTRL,
413 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL,
414 .ach_page_info = R_AX_ACH0_PAGE_INFO,
415 .pub_page_info3 = R_AX_PUB_PAGE_INFO3,
416 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1,
417 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2,
418 .pub_page_info1 = R_AX_PUB_PAGE_INFO1,
419 .pub_page_info2 = R_AX_PUB_PAGE_INFO2,
420 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1,
421 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2,
422 .wp_page_info1 = R_AX_WP_PAGE_INFO1,
423};
424
425static const struct rtw89_reg_def rtw8852a_dcfo_comp = {
426 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK
427};
428
429static const struct rtw89_imr_info rtw8852a_imr_info = {
430 .wdrls_imr_set = B_AX_WDRLS_IMR_SET,
431 .wsec_imr_reg = R_AX_SEC_DEBUG,
432 .wsec_imr_set = B_AX_IMR_ERROR,
433 .mpdu_tx_imr_set = 0,
434 .mpdu_rx_imr_set = 0,
435 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET,
436 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR,
437 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR,
438 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET,
439 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1,
440 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR,
441 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET,
442 .wde_imr_clr = B_AX_WDE_IMR_CLR,
443 .wde_imr_set = B_AX_WDE_IMR_SET,
444 .ple_imr_clr = B_AX_PLE_IMR_CLR,
445 .ple_imr_set = B_AX_PLE_IMR_SET,
446 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR,
447 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET,
448 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR,
449 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET,
450 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR,
451 .other_disp_imr_set = 0,
452 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR,
453 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR,
454 .bbrpt_err_imr_set = 0,
455 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR,
456 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR,
457 .ptcl_imr_set = B_AX_PTCL_IMR_SET,
458 .cdma_imr_0_reg = R_AX_DLE_CTRL,
459 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR,
460 .cdma_imr_0_set = B_AX_DLE_IMR_SET,
461 .cdma_imr_1_reg = 0,
462 .cdma_imr_1_clr = 0,
463 .cdma_imr_1_set = 0,
464 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR,
465 .phy_intf_imr_clr = 0,
466 .phy_intf_imr_set = 0,
467 .rmac_imr_reg = R_AX_RMAC_ERR_ISR,
468 .rmac_imr_clr = B_AX_RMAC_IMR_CLR,
469 .rmac_imr_set = B_AX_RMAC_IMR_SET,
470 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR,
471 .tmac_imr_clr = B_AX_TMAC_IMR_CLR,
472 .tmac_imr_set = B_AX_TMAC_IMR_SET,
473};
474
475static const struct rtw89_xtal_info rtw8852a_xtal_info = {
476 .xcap_reg = R_AX_XTAL_ON_CTRL0,
477 .sc_xo_mask = B_AX_XTAL_SC_XO_MASK,
478 .sc_xi_mask = B_AX_XTAL_SC_XI_MASK,
479};
480
481static const struct rtw89_rrsr_cfgs rtw8852a_rrsr_cfgs = {
482 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
483 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2},
484};
485
486static const struct rtw89_rfkill_regs rtw8852a_rfkill_regs = {
487 .pinmux = {R_AX_GPIO8_15_FUNC_SEL,
488 B_AX_PINMUX_GPIO9_FUNC_SEL_MASK,
489 0xf},
490 .mode = {R_AX_GPIO_EXT_CTRL + 2,
491 (B_AX_GPIO_MOD_9 | B_AX_GPIO_IO_SEL_9) >> 16,
492 0x0},
493};
494
495static const struct rtw89_dig_regs rtw8852a_dig_regs = {
496 .seg0_pd_reg = R_SEG0R_PD,
497 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
498 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK,
499 .bmode_pd_reg = R_BMODE_PDTH_EN_V1,
500 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1,
501 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1,
502 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1,
503 .p0_lna_init = {R_PATH0_LNA_INIT, B_PATH0_LNA_INIT_IDX_MSK},
504 .p1_lna_init = {R_PATH1_LNA_INIT, B_PATH1_LNA_INIT_IDX_MSK},
505 .p0_tia_init = {R_PATH0_TIA_INIT, B_PATH0_TIA_INIT_IDX_MSK},
506 .p1_tia_init = {R_PATH1_TIA_INIT, B_PATH1_TIA_INIT_IDX_MSK},
507 .p0_rxb_init = {R_PATH0_RXB_INIT, B_PATH0_RXB_INIT_IDX_MSK},
508 .p1_rxb_init = {R_PATH1_RXB_INIT, B_PATH1_RXB_INIT_IDX_MSK},
509 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC,
510 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
511 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC,
512 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
513 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC,
514 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
515 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC,
516 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
517};
518
519static const struct rtw89_edcca_regs rtw8852a_edcca_regs = {
520 .edcca_level = R_SEG0R_EDCCA_LVL,
521 .edcca_mask = B_EDCCA_LVL_MSK0,
522 .edcca_p_mask = B_EDCCA_LVL_MSK1,
523 .ppdu_level = R_SEG0R_EDCCA_LVL,
524 .ppdu_mask = B_EDCCA_LVL_MSK3,
525 .p = {{
526 .rpt_a = R_EDCCA_RPT_A,
527 .rpt_b = R_EDCCA_RPT_B,
528 .rpt_sel = R_EDCCA_RPT_SEL,
529 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK,
530 }, {
531 .rpt_a = R_EDCCA_RPT_P1_A,
532 .rpt_b = R_EDCCA_RPT_P1_B,
533 .rpt_sel = R_EDCCA_RPT_SEL,
534 .rpt_sel_mask = B_EDCCA_RPT_SEL_P1_MSK,
535 }},
536 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST,
537 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M,
538};
539
540static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse,
541 struct rtw8852a_efuse *map)
542{
543 ether_addr_copy(dst: efuse->addr, src: map->e.mac_addr);
544 efuse->rfe_type = map->rfe_type;
545 efuse->xtal_cap = map->xtal_k;
546}
547
548static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
549 struct rtw8852a_efuse *map)
550{
551 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
552 struct rtw8852a_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi};
553 u8 i, j;
554
555 tssi->thermal[RF_PATH_A] = map->path_a_therm;
556 tssi->thermal[RF_PATH_B] = map->path_b_therm;
557
558 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
559 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
560 sizeof(ofst[i]->cck_tssi));
561
562 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
563 rtw89_debug(rtwdev, mask: RTW89_DBG_TSSI,
564 fmt: "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
565 i, j, tssi->tssi_cck[i][j]);
566
567 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
568 sizeof(ofst[i]->bw40_tssi));
569 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
570 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
571
572 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
573 rtw89_debug(rtwdev, mask: RTW89_DBG_TSSI,
574 fmt: "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
575 i, j, tssi->tssi_mcs[i][j]);
576 }
577}
578
579static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map,
580 enum rtw89_efuse_block block)
581{
582 struct rtw89_efuse *efuse = &rtwdev->efuse;
583 struct rtw8852a_efuse *map;
584
585 map = (struct rtw8852a_efuse *)log_map;
586
587 efuse->country_code[0] = map->country_code[0];
588 efuse->country_code[1] = map->country_code[1];
589 rtw8852a_efuse_parsing_tssi(rtwdev, map);
590
591 switch (rtwdev->hci.type) {
592 case RTW89_HCI_TYPE_PCIE:
593 rtw8852ae_efuse_parsing(efuse, map);
594 break;
595 default:
596 return -ENOTSUPP;
597 }
598
599 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
600
601 return 0;
602}
603
604static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
605{
606 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
607 static const u32 tssi_trim_addr[RF_PATH_NUM_8852A] = {0x5D6, 0x5AB};
608 u32 addr = rtwdev->chip->phycap_addr;
609 bool pg = false;
610 u32 ofst;
611 u8 i, j;
612
613 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
614 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
615 /* addrs are in decreasing order */
616 ofst = tssi_trim_addr[i] - addr - j;
617 tssi->tssi_trim[i][j] = phycap_map[ofst];
618
619 if (phycap_map[ofst] != 0xff)
620 pg = true;
621 }
622 }
623
624 if (!pg) {
625 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
626 rtw89_debug(rtwdev, mask: RTW89_DBG_TSSI,
627 fmt: "[TSSI][TRIM] no PG, set all trim info to 0\n");
628 }
629
630 for (i = 0; i < RF_PATH_NUM_8852A; i++)
631 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
632 rtw89_debug(rtwdev, mask: RTW89_DBG_TSSI,
633 fmt: "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
634 i, j, tssi->tssi_trim[i][j],
635 tssi_trim_addr[i] - j);
636}
637
638static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
639 u8 *phycap_map)
640{
641 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
642 static const u32 thm_trim_addr[RF_PATH_NUM_8852A] = {0x5DF, 0x5DC};
643 u32 addr = rtwdev->chip->phycap_addr;
644 u8 i;
645
646 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
647 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
648
649 rtw89_debug(rtwdev, mask: RTW89_DBG_RFK,
650 fmt: "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
651 i, info->thermal_trim[i]);
652
653 if (info->thermal_trim[i] != 0xff)
654 info->pg_thermal_trim = true;
655 }
656}
657
658static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev)
659{
660#define __thm_setting(raw) \
661({ \
662 u8 __v = (raw); \
663 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \
664})
665 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
666 u8 i, val;
667
668 if (!info->pg_thermal_trim) {
669 rtw89_debug(rtwdev, mask: RTW89_DBG_RFK,
670 fmt: "[THERMAL][TRIM] no PG, do nothing\n");
671
672 return;
673 }
674
675 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
676 val = __thm_setting(info->thermal_trim[i]);
677 rtw89_write_rf(rtwdev, rf_path: i, RR_TM2, RR_TM2_OFF, data: val);
678
679 rtw89_debug(rtwdev, mask: RTW89_DBG_RFK,
680 fmt: "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
681 i, val);
682 }
683#undef __thm_setting
684}
685
686static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
687 u8 *phycap_map)
688{
689 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
690 static const u32 pabias_trim_addr[RF_PATH_NUM_8852A] = {0x5DE, 0x5DB};
691 u32 addr = rtwdev->chip->phycap_addr;
692 u8 i;
693
694 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
695 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
696
697 rtw89_debug(rtwdev, mask: RTW89_DBG_RFK,
698 fmt: "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
699 i, info->pa_bias_trim[i]);
700
701 if (info->pa_bias_trim[i] != 0xff)
702 info->pg_pa_bias_trim = true;
703 }
704}
705
706static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev)
707{
708 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
709 u8 pabias_2g, pabias_5g;
710 u8 i;
711
712 if (!info->pg_pa_bias_trim) {
713 rtw89_debug(rtwdev, mask: RTW89_DBG_RFK,
714 fmt: "[PA_BIAS][TRIM] no PG, do nothing\n");
715
716 return;
717 }
718
719 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
720 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);
721 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);
722
723 rtw89_debug(rtwdev, mask: RTW89_DBG_RFK,
724 fmt: "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
725 i, pabias_2g, pabias_5g);
726
727 rtw89_write_rf(rtwdev, rf_path: i, RR_BIASA, RR_BIASA_TXG, data: pabias_2g);
728 rtw89_write_rf(rtwdev, rf_path: i, RR_BIASA, RR_BIASA_TXA, data: pabias_5g);
729 }
730}
731
732static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
733{
734 rtw8852a_phycap_parsing_tssi(rtwdev, phycap_map);
735 rtw8852a_phycap_parsing_thermal_trim(rtwdev, phycap_map);
736 rtw8852a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
737
738 return 0;
739}
740
741static void rtw8852a_power_trim(struct rtw89_dev *rtwdev)
742{
743 rtw8852a_thermal_trim(rtwdev);
744 rtw8852a_pa_bias_trim(rtwdev);
745}
746
747static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev,
748 const struct rtw89_chan *chan,
749 u8 mac_idx)
750{
751 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, band: mac_idx);
752 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, band: mac_idx);
753 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, band: mac_idx);
754 u8 txsc20 = 0, txsc40 = 0;
755
756 switch (chan->band_width) {
757 case RTW89_CHANNEL_WIDTH_80:
758 txsc40 = rtw89_phy_get_txsc(rtwdev, chan,
759 dbw: RTW89_CHANNEL_WIDTH_40);
760 fallthrough;
761 case RTW89_CHANNEL_WIDTH_40:
762 txsc20 = rtw89_phy_get_txsc(rtwdev, chan,
763 dbw: RTW89_CHANNEL_WIDTH_20);
764 break;
765 default:
766 break;
767 }
768
769 switch (chan->band_width) {
770 case RTW89_CHANNEL_WIDTH_80:
771 rtw89_write8_mask(rtwdev, addr: rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1));
772 rtw89_write32(rtwdev, addr: sub_carr, data: txsc20 | (txsc40 << 4));
773 break;
774 case RTW89_CHANNEL_WIDTH_40:
775 rtw89_write8_mask(rtwdev, addr: rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));
776 rtw89_write32(rtwdev, addr: sub_carr, data: txsc20);
777 break;
778 case RTW89_CHANNEL_WIDTH_20:
779 rtw89_write8_clr(rtwdev, addr: rf_mod, B_AX_WMAC_RFMOD_MASK);
780 rtw89_write32(rtwdev, addr: sub_carr, data: 0);
781 break;
782 default:
783 break;
784 }
785
786 if (chan->channel > 14)
787 rtw89_write8_set(rtwdev, addr: chk_rate,
788 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
789 else
790 rtw89_write8_clr(rtwdev, addr: chk_rate,
791 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
792}
793
794static const u32 rtw8852a_sco_barker_threshold[14] = {
795 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6,
796 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4
797};
798
799static const u32 rtw8852a_sco_cck_threshold[14] = {
800 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724,
801 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed
802};
803
804static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch,
805 u8 primary_ch, enum rtw89_bandwidth bw)
806{
807 u8 ch_element;
808
809 if (bw == RTW89_CHANNEL_WIDTH_20) {
810 ch_element = central_ch - 1;
811 } else if (bw == RTW89_CHANNEL_WIDTH_40) {
812 if (primary_ch == 1)
813 ch_element = central_ch - 1 + 2;
814 else
815 ch_element = central_ch - 1 - 2;
816 } else {
817 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw);
818 return -EINVAL;
819 }
820 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH,
821 data: rtw8852a_sco_barker_threshold[ch_element]);
822 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH,
823 data: rtw8852a_sco_cck_threshold[ch_element]);
824
825 return 0;
826}
827
828static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch,
829 u8 path)
830{
831 u32 val;
832
833 val = rtw89_read_rf(rtwdev, rf_path: path, RR_CFGCH, RFREG_MASK);
834 if (val == INV_RF_DATA) {
835 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path);
836 return;
837 }
838 val &= ~0x303ff;
839 val |= central_ch;
840 if (central_ch > 14)
841 val |= (BIT(16) | BIT(8));
842 rtw89_write_rf(rtwdev, rf_path: path, RR_CFGCH, RFREG_MASK, data: val);
843}
844
845static u8 rtw8852a_sco_mapping(u8 central_ch)
846{
847 if (central_ch == 1)
848 return 109;
849 else if (central_ch >= 2 && central_ch <= 6)
850 return 108;
851 else if (central_ch >= 7 && central_ch <= 10)
852 return 107;
853 else if (central_ch >= 11 && central_ch <= 14)
854 return 106;
855 else if (central_ch == 36 || central_ch == 38)
856 return 51;
857 else if (central_ch >= 40 && central_ch <= 58)
858 return 50;
859 else if (central_ch >= 60 && central_ch <= 64)
860 return 49;
861 else if (central_ch == 100 || central_ch == 102)
862 return 48;
863 else if (central_ch >= 104 && central_ch <= 126)
864 return 47;
865 else if (central_ch >= 128 && central_ch <= 151)
866 return 46;
867 else if (central_ch >= 153 && central_ch <= 177)
868 return 45;
869 else
870 return 0;
871}
872
873static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch,
874 enum rtw89_phy_idx phy_idx)
875{
876 u8 sco_comp;
877 bool is_2g = central_ch <= 14;
878
879 if (phy_idx == RTW89_PHY_0) {
880 /* Path A */
881 rtw8852a_ch_setting(rtwdev, central_ch, path: RF_PATH_A);
882 if (is_2g)
883 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1,
884 B_PATH0_TIA_ERR_G1_SEL, data: 1,
885 phy_idx);
886 else
887 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1,
888 B_PATH0_TIA_ERR_G1_SEL, data: 0,
889 phy_idx);
890
891 /* Path B */
892 if (!rtwdev->dbcc_en) {
893 rtw8852a_ch_setting(rtwdev, central_ch, path: RF_PATH_B);
894 if (is_2g)
895 rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
896 B_P1_MODE_SEL,
897 data: 1, phy_idx);
898 else
899 rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
900 B_P1_MODE_SEL,
901 data: 0, phy_idx);
902 } else {
903 if (is_2g)
904 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND,
905 B_2P4G_BAND_SEL);
906 else
907 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND,
908 B_2P4G_BAND_SEL);
909 }
910 /* SCO compensate FC setting */
911 sco_comp = rtw8852a_sco_mapping(central_ch);
912 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV,
913 data: sco_comp, phy_idx);
914 } else {
915 /* Path B */
916 rtw8852a_ch_setting(rtwdev, central_ch, path: RF_PATH_B);
917 if (is_2g)
918 rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
919 B_P1_MODE_SEL,
920 data: 1, phy_idx);
921 else
922 rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
923 B_P1_MODE_SEL,
924 data: 0, phy_idx);
925 /* SCO compensate FC setting */
926 sco_comp = rtw8852a_sco_mapping(central_ch);
927 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV,
928 data: sco_comp, phy_idx);
929 }
930
931 /* Band edge */
932 if (is_2g)
933 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, data: 1,
934 phy_idx);
935 else
936 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, data: 0,
937 phy_idx);
938
939 /* CCK parameters */
940 if (central_ch == 14) {
941 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01,
942 data: 0x3b13ff);
943 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23,
944 data: 0x1c42de);
945 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45,
946 data: 0xfdb0ad);
947 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67,
948 data: 0xf60f6e);
949 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89,
950 data: 0xfd8f92);
951 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, data: 0x2d011);
952 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, data: 0x1c02c);
953 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF,
954 data: 0xfff00a);
955 } else {
956 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01,
957 data: 0x3d23ff);
958 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23,
959 data: 0x29b354);
960 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, data: 0xfc1c8);
961 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67,
962 data: 0xfdb053);
963 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89,
964 data: 0xf86f9a);
965 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB,
966 data: 0xfaef92);
967 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD,
968 data: 0xfe5fcc);
969 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF,
970 data: 0xffdff5);
971 }
972}
973
974static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path)
975{
976 u32 val = 0;
977 u32 adc_sel[2] = {0x12d0, 0x32d0};
978 u32 wbadc_sel[2] = {0x12ec, 0x32ec};
979
980 val = rtw89_read_rf(rtwdev, rf_path: path, RR_CFGCH, RFREG_MASK);
981 if (val == INV_RF_DATA) {
982 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path);
983 return;
984 }
985 val &= ~(BIT(11) | BIT(10));
986 switch (bw) {
987 case RTW89_CHANNEL_WIDTH_5:
988 rtw89_phy_write32_mask(rtwdev, addr: adc_sel[path], mask: 0x6000, data: 0x1);
989 rtw89_phy_write32_mask(rtwdev, addr: wbadc_sel[path], mask: 0x30, data: 0x0);
990 val |= (BIT(11) | BIT(10));
991 break;
992 case RTW89_CHANNEL_WIDTH_10:
993 rtw89_phy_write32_mask(rtwdev, addr: adc_sel[path], mask: 0x6000, data: 0x2);
994 rtw89_phy_write32_mask(rtwdev, addr: wbadc_sel[path], mask: 0x30, data: 0x1);
995 val |= (BIT(11) | BIT(10));
996 break;
997 case RTW89_CHANNEL_WIDTH_20:
998 rtw89_phy_write32_mask(rtwdev, addr: adc_sel[path], mask: 0x6000, data: 0x0);
999 rtw89_phy_write32_mask(rtwdev, addr: wbadc_sel[path], mask: 0x30, data: 0x2);
1000 val |= (BIT(11) | BIT(10));
1001 break;
1002 case RTW89_CHANNEL_WIDTH_40:
1003 rtw89_phy_write32_mask(rtwdev, addr: adc_sel[path], mask: 0x6000, data: 0x0);
1004 rtw89_phy_write32_mask(rtwdev, addr: wbadc_sel[path], mask: 0x30, data: 0x2);
1005 val |= BIT(11);
1006 break;
1007 case RTW89_CHANNEL_WIDTH_80:
1008 rtw89_phy_write32_mask(rtwdev, addr: adc_sel[path], mask: 0x6000, data: 0x0);
1009 rtw89_phy_write32_mask(rtwdev, addr: wbadc_sel[path], mask: 0x30, data: 0x2);
1010 val |= BIT(10);
1011 break;
1012 default:
1013 rtw89_warn(rtwdev, "Fail to set ADC\n");
1014 }
1015
1016 rtw89_write_rf(rtwdev, rf_path: path, RR_CFGCH, RFREG_MASK, data: val);
1017}
1018
1019static void
1020rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
1021 enum rtw89_phy_idx phy_idx)
1022{
1023 /* Switch bandwidth */
1024 switch (bw) {
1025 case RTW89_CHANNEL_WIDTH_5:
1026 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, data: 0x0,
1027 phy_idx);
1028 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, data: 0x1,
1029 phy_idx);
1030 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1031 data: 0x0, phy_idx);
1032 break;
1033 case RTW89_CHANNEL_WIDTH_10:
1034 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, data: 0x0,
1035 phy_idx);
1036 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, data: 0x2,
1037 phy_idx);
1038 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1039 data: 0x0, phy_idx);
1040 break;
1041 case RTW89_CHANNEL_WIDTH_20:
1042 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, data: 0x0,
1043 phy_idx);
1044 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, data: 0x0,
1045 phy_idx);
1046 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1047 data: 0x0, phy_idx);
1048 break;
1049 case RTW89_CHANNEL_WIDTH_40:
1050 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, data: 0x1,
1051 phy_idx);
1052 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, data: 0x0,
1053 phy_idx);
1054 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1055 data: pri_ch,
1056 phy_idx);
1057 if (pri_ch == RTW89_SC_20_UPPER)
1058 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, data: 1);
1059 else
1060 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, data: 0);
1061 break;
1062 case RTW89_CHANNEL_WIDTH_80:
1063 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, data: 0x2,
1064 phy_idx);
1065 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, data: 0x0,
1066 phy_idx);
1067 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1068 data: pri_ch,
1069 phy_idx);
1070 break;
1071 default:
1072 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
1073 pri_ch);
1074 }
1075
1076 if (phy_idx == RTW89_PHY_0) {
1077 rtw8852a_bw_setting(rtwdev, bw, path: RF_PATH_A);
1078 if (!rtwdev->dbcc_en)
1079 rtw8852a_bw_setting(rtwdev, bw, path: RF_PATH_B);
1080 } else {
1081 rtw8852a_bw_setting(rtwdev, bw, path: RF_PATH_B);
1082 }
1083}
1084
1085static void rtw8852a_spur_elimination(struct rtw89_dev *rtwdev, u8 central_ch)
1086{
1087 if (central_ch == 153) {
1088 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
1089 data: 0x210);
1090 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
1091 data: 0x210);
1092 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, data: 0x7c0);
1093 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1094 B_P0_NBIIDX_NOTCH_EN, data: 0x1);
1095 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1096 B_P1_NBIIDX_NOTCH_EN, data: 0x1);
1097 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1098 data: 0x1);
1099 } else if (central_ch == 151) {
1100 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
1101 data: 0x210);
1102 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
1103 data: 0x210);
1104 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, data: 0x40);
1105 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1106 B_P0_NBIIDX_NOTCH_EN, data: 0x1);
1107 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1108 B_P1_NBIIDX_NOTCH_EN, data: 0x1);
1109 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1110 data: 0x1);
1111 } else if (central_ch == 155) {
1112 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
1113 data: 0x2d0);
1114 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
1115 data: 0x2d0);
1116 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, data: 0x740);
1117 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1118 B_P0_NBIIDX_NOTCH_EN, data: 0x1);
1119 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1120 B_P1_NBIIDX_NOTCH_EN, data: 0x1);
1121 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1122 data: 0x1);
1123 } else {
1124 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1125 B_P0_NBIIDX_NOTCH_EN, data: 0x0);
1126 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1127 B_P1_NBIIDX_NOTCH_EN, data: 0x0);
1128 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1129 data: 0x0);
1130 }
1131}
1132
1133static void rtw8852a_bb_reset_all(struct rtw89_dev *rtwdev,
1134 enum rtw89_phy_idx phy_idx)
1135{
1136 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, data: 1,
1137 phy_idx);
1138 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, data: 0,
1139 phy_idx);
1140 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, data: 1,
1141 phy_idx);
1142}
1143
1144static void rtw8852a_bb_reset_en(struct rtw89_dev *rtwdev,
1145 enum rtw89_phy_idx phy_idx, bool en)
1146{
1147 if (en)
1148 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL,
1149 data: 1,
1150 phy_idx);
1151 else
1152 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL,
1153 data: 0,
1154 phy_idx);
1155}
1156
1157static void rtw8852a_bb_reset(struct rtw89_dev *rtwdev,
1158 enum rtw89_phy_idx phy_idx)
1159{
1160 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1161 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1162 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1163 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1164 rtw8852a_bb_reset_all(rtwdev, phy_idx);
1165 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1166 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1167 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1168 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1169}
1170
1171static void rtw8852a_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
1172 enum rtw89_phy_idx phy_idx)
1173{
1174 u32 addr;
1175
1176 for (addr = R_AX_PWR_MACID_LMT_TABLE0;
1177 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
1178 rtw89_mac_txpwr_write32(rtwdev, phy_idx, reg_base: addr, val: 0);
1179}
1180
1181static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev)
1182{
1183 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
1184 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP);
1185
1186 if (rtwdev->hal.cv <= CHIP_CCV) {
1187 rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG);
1188 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, data: 0x864FA000);
1189 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, data: 0x43F);
1190 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, data: 0x7FFF);
1191 rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST);
1192 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1193 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1194 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, B_STS_PARSING_TIME);
1195 }
1196 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, data: 0x1f);
1197 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, data: 0x0c);
1198 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, data: 0x0, phy_idx: RTW89_PHY_0);
1199 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, data: 0x0, phy_idx: RTW89_PHY_1);
1200 rtw89_phy_write32_clr(rtwdev, R_NDP_BRK0, B_NDP_RU_BRK);
1201 rtw89_phy_write32_set(rtwdev, R_NDP_BRK1, B_NDP_RU_BRK);
1202
1203 rtw8852a_bb_macid_ctrl_init(rtwdev, phy_idx: RTW89_PHY_0);
1204}
1205
1206static void rtw8852a_bbrst_for_rfk(struct rtw89_dev *rtwdev,
1207 enum rtw89_phy_idx phy_idx)
1208{
1209 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1210 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1211 rtw8852a_bb_reset_all(rtwdev, phy_idx);
1212 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1213 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1214 udelay(usec: 1);
1215}
1216
1217static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev,
1218 const struct rtw89_chan *chan,
1219 enum rtw89_phy_idx phy_idx)
1220{
1221 bool cck_en = chan->channel <= 14;
1222 u8 pri_ch_idx = chan->pri_ch_idx;
1223
1224 if (cck_en)
1225 rtw8852a_ctrl_sco_cck(rtwdev, central_ch: chan->channel,
1226 primary_ch: chan->primary_channel,
1227 bw: chan->band_width);
1228
1229 rtw8852a_ctrl_ch(rtwdev, central_ch: chan->channel, phy_idx);
1230 rtw8852a_ctrl_bw(rtwdev, pri_ch: pri_ch_idx, bw: chan->band_width, phy_idx);
1231 if (cck_en) {
1232 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, data: 0);
1233 } else {
1234 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, data: 1);
1235 rtw8852a_bbrst_for_rfk(rtwdev, phy_idx);
1236 }
1237 rtw8852a_spur_elimination(rtwdev, central_ch: chan->channel);
1238 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0,
1239 data: chan->primary_channel);
1240 rtw8852a_bb_reset_all(rtwdev, phy_idx);
1241}
1242
1243static void rtw8852a_set_channel(struct rtw89_dev *rtwdev,
1244 const struct rtw89_chan *chan,
1245 enum rtw89_mac_idx mac_idx,
1246 enum rtw89_phy_idx phy_idx)
1247{
1248 rtw8852a_set_channel_mac(rtwdev, chan, mac_idx);
1249 rtw8852a_set_channel_bb(rtwdev, chan, phy_idx);
1250}
1251
1252static void rtw8852a_dfs_en(struct rtw89_dev *rtwdev, bool en)
1253{
1254 if (en)
1255 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, data: 1);
1256 else
1257 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, data: 0);
1258}
1259
1260static void rtw8852a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
1261 enum rtw89_rf_path path)
1262{
1263 static const u32 tssi_trk[2] = {0x5818, 0x7818};
1264 static const u32 ctrl_bbrst[2] = {0x58dc, 0x78dc};
1265
1266 if (en) {
1267 rtw89_phy_write32_mask(rtwdev, addr: ctrl_bbrst[path], BIT(30), data: 0x0);
1268 rtw89_phy_write32_mask(rtwdev, addr: tssi_trk[path], BIT(30), data: 0x0);
1269 } else {
1270 rtw89_phy_write32_mask(rtwdev, addr: ctrl_bbrst[path], BIT(30), data: 0x1);
1271 rtw89_phy_write32_mask(rtwdev, addr: tssi_trk[path], BIT(30), data: 0x1);
1272 }
1273}
1274
1275static void rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
1276 u8 phy_idx)
1277{
1278 if (!rtwdev->dbcc_en) {
1279 rtw8852a_tssi_cont_en(rtwdev, en, path: RF_PATH_A);
1280 rtw8852a_tssi_cont_en(rtwdev, en, path: RF_PATH_B);
1281 } else {
1282 if (phy_idx == RTW89_PHY_0)
1283 rtw8852a_tssi_cont_en(rtwdev, en, path: RF_PATH_A);
1284 else
1285 rtw8852a_tssi_cont_en(rtwdev, en, path: RF_PATH_B);
1286 }
1287}
1288
1289static void rtw8852a_adc_en(struct rtw89_dev *rtwdev, bool en)
1290{
1291 if (en)
1292 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1293 data: 0x0);
1294 else
1295 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1296 data: 0xf);
1297}
1298
1299static void rtw8852a_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
1300 struct rtw89_channel_help_params *p,
1301 const struct rtw89_chan *chan,
1302 enum rtw89_mac_idx mac_idx,
1303 enum rtw89_phy_idx phy_idx)
1304{
1305 if (enter) {
1306 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, tx_en: &p->tx_en,
1307 sel: RTW89_SCH_TX_SEL_ALL);
1308 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, enable: false);
1309 rtw8852a_dfs_en(rtwdev, en: false);
1310 rtw8852a_tssi_cont_en_phyidx(rtwdev, en: false, phy_idx);
1311 rtw8852a_adc_en(rtwdev, en: false);
1312 fsleep(usecs: 40);
1313 rtw8852a_bb_reset_en(rtwdev, phy_idx, en: false);
1314 } else {
1315 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, enable: true);
1316 rtw8852a_adc_en(rtwdev, en: true);
1317 rtw8852a_dfs_en(rtwdev, en: true);
1318 rtw8852a_tssi_cont_en_phyidx(rtwdev, en: true, phy_idx);
1319 rtw8852a_bb_reset_en(rtwdev, phy_idx, en: true);
1320 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, tx_en: p->tx_en);
1321 }
1322}
1323
1324static void rtw8852a_fem_setup(struct rtw89_dev *rtwdev)
1325{
1326 struct rtw89_efuse *efuse = &rtwdev->efuse;
1327
1328 switch (efuse->rfe_type) {
1329 case 11:
1330 case 12:
1331 case 17:
1332 case 18:
1333 case 51:
1334 case 53:
1335 rtwdev->fem.epa_2g = true;
1336 rtwdev->fem.elna_2g = true;
1337 fallthrough;
1338 case 9:
1339 case 10:
1340 case 15:
1341 case 16:
1342 rtwdev->fem.epa_5g = true;
1343 rtwdev->fem.elna_5g = true;
1344 break;
1345 default:
1346 break;
1347 }
1348}
1349
1350static void rtw8852a_rfk_init(struct rtw89_dev *rtwdev)
1351{
1352 rtwdev->is_tssi_mode[RF_PATH_A] = false;
1353 rtwdev->is_tssi_mode[RF_PATH_B] = false;
1354
1355 rtw8852a_rck(rtwdev);
1356 rtw8852a_dack(rtwdev, chanctx_idx: RTW89_CHANCTX_0);
1357 rtw8852a_rx_dck(rtwdev, phy_idx: RTW89_PHY_0, is_afe: true, chanctx_idx: RTW89_CHANCTX_0);
1358}
1359
1360static void rtw8852a_rfk_channel(struct rtw89_dev *rtwdev,
1361 struct rtw89_vif_link *rtwvif_link)
1362{
1363 enum rtw89_chanctx_idx chanctx_idx = rtwvif_link->chanctx_idx;
1364 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx;
1365
1366 rtw89_btc_ntfy_conn_rfk(rtwdev, state: true);
1367
1368 rtw8852a_rx_dck(rtwdev, phy_idx, is_afe: true, chanctx_idx);
1369 rtw8852a_iqk(rtwdev, phy_idx, chanctx_idx);
1370 rtw89_btc_ntfy_preserve_bt_time(rtwdev, ms: 30);
1371 rtw8852a_tssi(rtwdev, phy: phy_idx, chanctx_idx);
1372 rtw89_btc_ntfy_preserve_bt_time(rtwdev, ms: 30);
1373 rtw8852a_dpk(rtwdev, phy_idx, chanctx_idx);
1374
1375 rtw89_btc_ntfy_conn_rfk(rtwdev, state: false);
1376}
1377
1378static void rtw8852a_rfk_band_changed(struct rtw89_dev *rtwdev,
1379 enum rtw89_phy_idx phy_idx,
1380 const struct rtw89_chan *chan)
1381{
1382 rtw8852a_tssi_scan(rtwdev, phy: phy_idx, chan);
1383}
1384
1385static void rtw8852a_rfk_scan(struct rtw89_dev *rtwdev,
1386 struct rtw89_vif_link *rtwvif_link,
1387 bool start)
1388{
1389 rtw8852a_wifi_scan_notify(rtwdev, scan_start: start, phy_idx: rtwvif_link->phy_idx);
1390}
1391
1392static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev)
1393{
1394 rtw8852a_dpk_track(rtwdev);
1395 rtw8852a_tssi_track(rtwdev);
1396}
1397
1398static u32 rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
1399 enum rtw89_phy_idx phy_idx, s16 ref)
1400{
1401 s8 ofst_int = 0;
1402 u8 base_cw_0db = 0x27;
1403 u16 tssi_16dbm_cw = 0x12c;
1404 s16 pwr_s10_3 = 0;
1405 s16 rf_pwr_cw = 0;
1406 u16 bb_pwr_cw = 0;
1407 u32 pwr_cw = 0;
1408 u32 tssi_ofst_cw = 0;
1409
1410 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3);
1411 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3);
1412 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3);
1413 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63);
1414 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw;
1415
1416 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3));
1417 rtw89_debug(rtwdev, mask: RTW89_DBG_TXPWR,
1418 fmt: "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n",
1419 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw);
1420
1421 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0));
1422}
1423
1424static
1425void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
1426 s8 pw_ofst, enum rtw89_mac_idx mac_idx)
1427{
1428 s8 val_1t = 0;
1429 s8 val_2t = 0;
1430 u32 reg;
1431
1432 if (pw_ofst < -16 || pw_ofst > 15) {
1433 rtw89_debug(rtwdev, mask: RTW89_DBG_TXPWR, fmt: "[ULTB] Err pwr_offset=%d\n",
1434 pw_ofst);
1435 return;
1436 }
1437 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, band: mac_idx);
1438 rtw89_write32_set(rtwdev, addr: reg, B_AX_PWR_UL_TB_CTRL_EN);
1439 val_1t = pw_ofst;
1440 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, band: mac_idx);
1441 rtw89_write32_mask(rtwdev, addr: reg, B_AX_PWR_UL_TB_1T_MASK, data: val_1t);
1442 val_2t = max(val_1t - 3, -16);
1443 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, band: mac_idx);
1444 rtw89_write32_mask(rtwdev, addr: reg, B_AX_PWR_UL_TB_2T_MASK, data: val_2t);
1445 rtw89_debug(rtwdev, mask: RTW89_DBG_TXPWR, fmt: "[ULTB] Set TB pwr_offset=(%d, %d)\n",
1446 val_1t, val_2t);
1447}
1448
1449static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev,
1450 enum rtw89_phy_idx phy_idx)
1451{
1452 static const u32 addr[RF_PATH_NUM_8852A] = {0x5800, 0x7800};
1453 const u32 mask = 0x7FFFFFF;
1454 const u8 ofst_ofdm = 0x4;
1455 const u8 ofst_cck = 0x8;
1456 s16 ref_ofdm = 0;
1457 s16 ref_cck = 0;
1458 u32 val;
1459 u8 i;
1460
1461 rtw89_debug(rtwdev, mask: RTW89_DBG_TXPWR, fmt: "[TXPWR] set txpwr reference\n");
1462
1463 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
1464 GENMASK(27, 10), val: 0x0);
1465
1466 rtw89_debug(rtwdev, mask: RTW89_DBG_TXPWR, fmt: "[TXPWR] set bb ofdm txpwr ref\n");
1467 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref: ref_ofdm);
1468
1469 for (i = 0; i < RF_PATH_NUM_8852A; i++)
1470 rtw89_phy_write32_idx(rtwdev, addr: addr[i] + ofst_ofdm, mask, data: val,
1471 phy_idx);
1472
1473 rtw89_debug(rtwdev, mask: RTW89_DBG_TXPWR, fmt: "[TXPWR] set bb cck txpwr ref\n");
1474 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref: ref_cck);
1475
1476 for (i = 0; i < RF_PATH_NUM_8852A; i++)
1477 rtw89_phy_write32_idx(rtwdev, addr: addr[i] + ofst_cck, mask, data: val,
1478 phy_idx);
1479}
1480
1481static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev,
1482 const struct rtw89_chan *chan,
1483 enum rtw89_phy_idx phy_idx)
1484{
1485 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
1486 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
1487 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
1488 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
1489}
1490
1491static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
1492 enum rtw89_phy_idx phy_idx)
1493{
1494 rtw8852a_set_txpwr_ref(rtwdev, phy_idx);
1495}
1496
1497static int
1498rtw8852a_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1499{
1500 int ret;
1501
1502 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, val: 0x07763333);
1503 if (ret)
1504 return ret;
1505
1506 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, val: 0x01ebf004);
1507 if (ret)
1508 return ret;
1509
1510 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, val: 0x0002f8ff);
1511 if (ret)
1512 return ret;
1513
1514 return 0;
1515}
1516
1517void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev)
1518{
1519 u8 i = 0;
1520 u32 addr, val;
1521
1522 for (i = 0; i < ARRAY_SIZE(rtw8852a_pmac_ht20_mcs7_tbl); i++) {
1523 addr = rtw8852a_pmac_ht20_mcs7_tbl[i].addr;
1524 val = rtw8852a_pmac_ht20_mcs7_tbl[i].data;
1525 rtw89_phy_write32(rtwdev, addr, data: val);
1526 }
1527}
1528
1529static void rtw8852a_stop_pmac_tx(struct rtw89_dev *rtwdev,
1530 struct rtw8852a_bb_pmac_info *tx_info,
1531 enum rtw89_phy_idx idx)
1532{
1533 rtw89_debug(rtwdev, mask: RTW89_DBG_TSSI, fmt: "PMAC Stop Tx");
1534 if (tx_info->mode == CONT_TX)
1535 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, data: 0,
1536 phy_idx: idx);
1537 else if (tx_info->mode == PKTS_TX)
1538 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, data: 0,
1539 phy_idx: idx);
1540}
1541
1542static void rtw8852a_start_pmac_tx(struct rtw89_dev *rtwdev,
1543 struct rtw8852a_bb_pmac_info *tx_info,
1544 enum rtw89_phy_idx idx)
1545{
1546 enum rtw8852a_pmac_mode mode = tx_info->mode;
1547 u32 pkt_cnt = tx_info->tx_cnt;
1548 u16 period = tx_info->period;
1549
1550 if (mode == CONT_TX && !tx_info->is_cck) {
1551 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, data: 1,
1552 phy_idx: idx);
1553 rtw89_debug(rtwdev, mask: RTW89_DBG_TSSI, fmt: "PMAC CTx Start");
1554 } else if (mode == PKTS_TX) {
1555 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, data: 1,
1556 phy_idx: idx);
1557 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD,
1558 B_PMAC_TX_PRD_MSK, data: period, phy_idx: idx);
1559 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK,
1560 data: pkt_cnt, phy_idx: idx);
1561 rtw89_debug(rtwdev, mask: RTW89_DBG_TSSI, fmt: "PMAC PTx Start");
1562 }
1563 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, data: 1, phy_idx: idx);
1564 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, data: 0, phy_idx: idx);
1565}
1566
1567void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev,
1568 struct rtw8852a_bb_pmac_info *tx_info,
1569 enum rtw89_phy_idx idx, const struct rtw89_chan *chan)
1570{
1571 if (!tx_info->en_pmac_tx) {
1572 rtw8852a_stop_pmac_tx(rtwdev, tx_info, idx);
1573 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, data: 0, phy_idx: idx);
1574 if (chan->band_type == RTW89_BAND_2G)
1575 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS);
1576 return;
1577 }
1578 rtw89_debug(rtwdev, mask: RTW89_DBG_TSSI, fmt: "PMAC Tx Enable");
1579 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, data: 1, phy_idx: idx);
1580 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, data: 1, phy_idx: idx);
1581 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, data: 0x3f,
1582 phy_idx: idx);
1583 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, data: 0, phy_idx: idx);
1584 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, data: 1, phy_idx: idx);
1585 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS);
1586 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, data: 1, phy_idx: idx);
1587 rtw8852a_start_pmac_tx(rtwdev, tx_info, idx);
1588}
1589
1590void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable,
1591 u16 tx_cnt, u16 period, u16 tx_time,
1592 enum rtw89_phy_idx idx, const struct rtw89_chan *chan)
1593{
1594 struct rtw8852a_bb_pmac_info tx_info = {0};
1595
1596 tx_info.en_pmac_tx = enable;
1597 tx_info.is_cck = 0;
1598 tx_info.mode = PKTS_TX;
1599 tx_info.tx_cnt = tx_cnt;
1600 tx_info.period = period;
1601 tx_info.tx_time = tx_time;
1602 rtw8852a_bb_set_pmac_tx(rtwdev, tx_info: &tx_info, idx, chan);
1603}
1604
1605void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm,
1606 enum rtw89_phy_idx idx)
1607{
1608 rtw89_debug(rtwdev, mask: RTW89_DBG_TSSI, fmt: "PMAC CFG Tx PWR = %d", pwr_dbm);
1609 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, data: 1, phy_idx: idx);
1610 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, data: pwr_dbm, phy_idx: idx);
1611}
1612
1613void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path)
1614{
1615 u32 rst_mask0 = 0;
1616 u32 rst_mask1 = 0;
1617
1618 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, data: 7, phy_idx: RTW89_PHY_0);
1619 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, data: 7, phy_idx: RTW89_PHY_1);
1620 rtw89_debug(rtwdev, mask: RTW89_DBG_TSSI, fmt: "PMAC CFG Tx Path = %d", tx_path);
1621 if (!rtwdev->dbcc_en) {
1622 if (tx_path == RF_PATH_A) {
1623 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
1624 B_TXPATH_SEL_MSK, data: 1);
1625 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
1626 B_TXNSS_MAP_MSK, data: 0);
1627 } else if (tx_path == RF_PATH_B) {
1628 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
1629 B_TXPATH_SEL_MSK, data: 2);
1630 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
1631 B_TXNSS_MAP_MSK, data: 0);
1632 } else if (tx_path == RF_PATH_AB) {
1633 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
1634 B_TXPATH_SEL_MSK, data: 3);
1635 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
1636 B_TXNSS_MAP_MSK, data: 4);
1637 } else {
1638 rtw89_debug(rtwdev, mask: RTW89_DBG_TSSI, fmt: "Error Tx Path");
1639 }
1640 } else {
1641 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK,
1642 data: 1);
1643 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, data: 2,
1644 phy_idx: RTW89_PHY_1);
1645 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK,
1646 data: 0);
1647 rtw89_phy_write32_idx(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, data: 4,
1648 phy_idx: RTW89_PHY_1);
1649 }
1650 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI;
1651 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI;
1652 if (tx_path == RF_PATH_A) {
1653 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask: rst_mask0, data: 1);
1654 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask: rst_mask0, data: 3);
1655 } else {
1656 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask: rst_mask1, data: 1);
1657 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask: rst_mask1, data: 3);
1658 }
1659}
1660
1661void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev,
1662 enum rtw89_phy_idx idx, u8 mode)
1663{
1664 if (mode != 0)
1665 return;
1666 rtw89_debug(rtwdev, mask: RTW89_DBG_TSSI, fmt: "Tx mode switch");
1667 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, data: 0, phy_idx: idx);
1668 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, data: 0, phy_idx: idx);
1669 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, data: 0, phy_idx: idx);
1670 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, data: 0, phy_idx: idx);
1671 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, data: 0, phy_idx: idx);
1672 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, data: 0, phy_idx: idx);
1673 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, data: 0, phy_idx: idx);
1674}
1675
1676static void rtw8852a_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
1677 enum rtw89_phy_idx phy_idx)
1678{
1679 rtw89_phy_write_reg3_tbl(rtwdev, tbl: en ? &rtw8852a_btc_preagc_en_defs_tbl :
1680 &rtw8852a_btc_preagc_dis_defs_tbl);
1681}
1682
1683static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
1684{
1685 if (rtwdev->is_tssi_mode[rf_path]) {
1686 u32 addr = 0x1c10 + (rf_path << 13);
1687
1688 return (u8)rtw89_phy_read32_mask(rtwdev, addr, mask: 0x3F000000);
1689 }
1690
1691 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, data: 0x1);
1692 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, data: 0x0);
1693 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, data: 0x1);
1694
1695 fsleep(usecs: 200);
1696
1697 return (u8)rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
1698}
1699
1700static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev)
1701{
1702 const struct rtw89_btc_ver *ver = rtwdev->btc.ver;
1703 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo;
1704
1705 if (ver->fcxinit == 7) {
1706 md->md_v7.rfe_type = rtwdev->efuse.rfe_type;
1707 md->md_v7.kt_ver = rtwdev->hal.cv;
1708 md->md_v7.bt_solo = 0;
1709 md->md_v7.switch_type = BTC_SWITCH_INTERNAL;
1710
1711 if (md->md_v7.rfe_type > 0)
1712 md->md_v7.ant.num = (md->md_v7.rfe_type % 2 ? 2 : 3);
1713 else
1714 md->md_v7.ant.num = 2;
1715
1716 md->md_v7.ant.diversity = 0;
1717 md->md_v7.ant.isolation = 10;
1718
1719 if (md->md_v7.ant.num == 3) {
1720 md->md_v7.ant.type = BTC_ANT_DEDICATED;
1721 md->md_v7.bt_pos = BTC_BT_ALONE;
1722 } else {
1723 md->md_v7.ant.type = BTC_ANT_SHARED;
1724 md->md_v7.bt_pos = BTC_BT_BTG;
1725 }
1726 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos;
1727 rtwdev->btc.ant_type = md->md_v7.ant.type;
1728 } else {
1729 md->md.rfe_type = rtwdev->efuse.rfe_type;
1730 md->md.cv = rtwdev->hal.cv;
1731 md->md.bt_solo = 0;
1732 md->md.switch_type = BTC_SWITCH_INTERNAL;
1733
1734 if (md->md.rfe_type > 0)
1735 md->md.ant.num = (md->md.rfe_type % 2 ? 2 : 3);
1736 else
1737 md->md.ant.num = 2;
1738
1739 md->md.ant.diversity = 0;
1740 md->md.ant.isolation = 10;
1741
1742 if (md->md.ant.num == 3) {
1743 md->md.ant.type = BTC_ANT_DEDICATED;
1744 md->md.bt_pos = BTC_BT_ALONE;
1745 } else {
1746 md->md.ant.type = BTC_ANT_SHARED;
1747 md->md.bt_pos = BTC_BT_BTG;
1748 }
1749 rtwdev->btc.btg_pos = md->md.ant.btg_pos;
1750 rtwdev->btc.ant_type = md->md.ant.type;
1751 }
1752}
1753
1754static
1755void rtw8852a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
1756{
1757 rtw89_write_rf(rtwdev, rf_path: path, RR_LUTWE, mask: 0xfffff, data: 0x20000);
1758 rtw89_write_rf(rtwdev, rf_path: path, RR_LUTWA, mask: 0xfffff, data: group);
1759 rtw89_write_rf(rtwdev, rf_path: path, RR_LUTWD0, mask: 0xfffff, data: val);
1760 rtw89_write_rf(rtwdev, rf_path: path, RR_LUTWE, mask: 0xfffff, data: 0x0);
1761}
1762
1763static void rtw8852a_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
1764 enum rtw89_phy_idx phy_idx)
1765{
1766 if (en) {
1767 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, data: 0x1);
1768 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, data: 0x3);
1769 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, data: 0x0);
1770 } else {
1771 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, data: 0x0);
1772 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, data: 0x0);
1773 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, data: 0xf);
1774 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, data: 0x4);
1775 }
1776}
1777
1778static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev)
1779{
1780 struct rtw89_btc *btc = &rtwdev->btc;
1781 const struct rtw89_chip_info *chip = rtwdev->chip;
1782 const struct rtw89_mac_ax_coex coex_params = {
1783 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE,
1784 .direction = RTW89_MAC_AX_COEX_INNER,
1785 };
1786
1787 /* PTA init */
1788 rtw89_mac_coex_init(rtwdev, coex: &coex_params);
1789
1790 /* set WL Tx response = Hi-Pri */
1791 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
1792 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
1793
1794 /* set rf gnt debug off */
1795 rtw89_write_rf(rtwdev, rf_path: RF_PATH_A, RR_WLSEL, mask: 0xfffff, data: 0x0);
1796 rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_WLSEL, mask: 0xfffff, data: 0x0);
1797
1798 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */
1799 if (btc->ant_type == BTC_ANT_SHARED) {
1800 rtw8852a_set_trx_mask(rtwdev,
1801 path: RF_PATH_A, group: BTC_BT_SS_GROUP, val: 0x5ff);
1802 rtw8852a_set_trx_mask(rtwdev,
1803 path: RF_PATH_B, group: BTC_BT_SS_GROUP, val: 0x5ff);
1804 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */
1805 rtw8852a_set_trx_mask(rtwdev,
1806 path: RF_PATH_A, group: BTC_BT_TX_GROUP, val: 0x5ff);
1807 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */
1808 rtw8852a_set_trx_mask(rtwdev,
1809 path: RF_PATH_A, group: BTC_BT_SS_GROUP, val: 0x5df);
1810 rtw8852a_set_trx_mask(rtwdev,
1811 path: RF_PATH_B, group: BTC_BT_SS_GROUP, val: 0x5df);
1812 }
1813
1814 /* set PTA break table */
1815 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM);
1816
1817 /* enable BT counter 0xda40[16,2] = 2b'11 */
1818 rtw89_write32_set(rtwdev,
1819 R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN);
1820 btc->cx.wl.status.map.init_ok = true;
1821}
1822
1823static
1824void rtw8852a_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
1825{
1826 u32 bitmap = 0;
1827 u32 reg = 0;
1828
1829 switch (map) {
1830 case BTC_PRI_MASK_TX_RESP:
1831 reg = R_BTC_BT_COEX_MSK_TABLE;
1832 bitmap = B_BTC_PRI_MASK_TX_RESP_V1;
1833 break;
1834 case BTC_PRI_MASK_BEACON:
1835 reg = R_AX_WL_PRI_MSK;
1836 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ;
1837 break;
1838 default:
1839 return;
1840 }
1841
1842 if (state)
1843 rtw89_write32_set(rtwdev, addr: reg, bit: bitmap);
1844 else
1845 rtw89_write32_clr(rtwdev, addr: reg, bit: bitmap);
1846}
1847
1848static inline u32 __btc_ctrl_val_all_time(u32 ctrl)
1849{
1850 return FIELD_GET(GENMASK(15, 0), ctrl);
1851}
1852
1853static inline u32 __btc_ctrl_rst_all_time(u32 cur)
1854{
1855 return cur & ~B_AX_FORCE_PWR_BY_RATE_EN;
1856}
1857
1858static inline u32 __btc_ctrl_gen_all_time(u32 cur, u32 val)
1859{
1860 u32 hv = cur & ~B_AX_FORCE_PWR_BY_RATE_VALUE_MASK;
1861 u32 lv = val & B_AX_FORCE_PWR_BY_RATE_VALUE_MASK;
1862
1863 return hv | lv | B_AX_FORCE_PWR_BY_RATE_EN;
1864}
1865
1866static inline u32 __btc_ctrl_val_gnt_bt(u32 ctrl)
1867{
1868 return FIELD_GET(GENMASK(31, 16), ctrl);
1869}
1870
1871static inline u32 __btc_ctrl_rst_gnt_bt(u32 cur)
1872{
1873 return cur & ~B_AX_TXAGC_BT_EN;
1874}
1875
1876static inline u32 __btc_ctrl_gen_gnt_bt(u32 cur, u32 val)
1877{
1878 u32 ov = cur & ~B_AX_TXAGC_BT_MASK;
1879 u32 iv = FIELD_PREP(B_AX_TXAGC_BT_MASK, val);
1880
1881 return ov | iv | B_AX_TXAGC_BT_EN;
1882}
1883
1884static void
1885rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
1886{
1887 const u32 __btc_cr_all_time = R_AX_PWR_RATE_CTRL;
1888 const u32 __btc_cr_gnt_bt = R_AX_PWR_COEXT_CTRL;
1889
1890#define __do_clr(_chk) ((_chk) == GENMASK(15, 0))
1891#define __handle(_case) \
1892 do { \
1893 const u32 _reg = __btc_cr_ ## _case; \
1894 u32 _val = __btc_ctrl_val_ ## _case(txpwr_val); \
1895 u32 _cur, _wrt; \
1896 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \
1897 "btc ctrl %s: 0x%x\n", #_case, _val); \
1898 if (rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur))\
1899 break; \
1900 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \
1901 "btc ctrl ori 0x%x: 0x%x\n", _reg, _cur); \
1902 _wrt = __do_clr(_val) ? \
1903 __btc_ctrl_rst_ ## _case(_cur) : \
1904 __btc_ctrl_gen_ ## _case(_cur, _val); \
1905 rtw89_mac_txpwr_write32(rtwdev, RTW89_PHY_0, _reg, _wrt);\
1906 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \
1907 "btc ctrl set 0x%x: 0x%x\n", _reg, _wrt); \
1908 } while (0)
1909
1910 __handle(all_time);
1911 __handle(gnt_bt);
1912
1913#undef __handle
1914#undef __do_clr
1915}
1916
1917static
1918s8 rtw8852a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
1919{
1920 /* +6 for compensate offset */
1921 return clamp_t(s8, val + 6, -100, 0) + 100;
1922}
1923
1924static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_ul[] = {
1925 {255, 0, 0, 7}, /* 0 -> original */
1926 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
1927 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
1928 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
1929 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
1930 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
1931 {6, 1, 0, 7},
1932 {13, 1, 0, 7},
1933 {13, 1, 0, 7}
1934};
1935
1936static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_dl[] = {
1937 {255, 0, 0, 7}, /* 0 -> original */
1938 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
1939 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
1940 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
1941 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
1942 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
1943 {255, 1, 0, 7},
1944 {255, 1, 0, 7},
1945 {255, 1, 0, 7}
1946};
1947
1948static const
1949u8 rtw89_btc_8852a_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30};
1950static const
1951u8 rtw89_btc_8852a_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28};
1952
1953static struct rtw89_btc_fbtc_mreg rtw89_btc_8852a_mon_reg[] = {
1954 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
1955 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28),
1956 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c),
1957 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
1958 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
1959 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10),
1960 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20),
1961 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
1962 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4),
1963 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424),
1964 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
1965 RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178),
1966};
1967
1968static
1969void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
1970{
1971 struct rtw89_btc *btc = &rtwdev->btc;
1972 const struct rtw89_btc_ver *ver = btc->ver;
1973 struct rtw89_btc_cx *cx = &btc->cx;
1974 u32 val;
1975
1976 if (ver->fcxbtcrpt != 1)
1977 return;
1978
1979 val = rtw89_read32(rtwdev, R_AX_BT_STAST_HIGH);
1980 cx->cnt_bt[BTC_BCNT_HIPRI_TX] = FIELD_GET(B_AX_STATIS_BT_HI_TX_MASK, val);
1981 cx->cnt_bt[BTC_BCNT_HIPRI_RX] = FIELD_GET(B_AX_STATIS_BT_HI_RX_MASK, val);
1982
1983 val = rtw89_read32(rtwdev, R_AX_BT_STAST_LOW);
1984 cx->cnt_bt[BTC_BCNT_LOPRI_TX] = FIELD_GET(B_AX_STATIS_BT_LO_TX_1_MASK, val);
1985 cx->cnt_bt[BTC_BCNT_LOPRI_RX] = FIELD_GET(B_AX_STATIS_BT_LO_RX_1_MASK, val);
1986
1987 /* clock-gate off before reset counter*/
1988 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G);
1989 rtw89_write32_clr(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST);
1990 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST);
1991 rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G);
1992}
1993
1994static
1995void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
1996{
1997 rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWE, RFREG_MASK, data: 0x80000);
1998 rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWA, RFREG_MASK, data: 0x1);
1999 rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWD1, RFREG_MASK, data: 0x1);
2000
2001 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
2002 if (state)
2003 rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWD0,
2004 RFREG_MASK, data: 0xa2d7c);
2005 else
2006 rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWD0,
2007 RFREG_MASK, data: 0xa2020);
2008
2009 rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWE, RFREG_MASK, data: 0x0);
2010}
2011
2012static void rtw8852a_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level)
2013{
2014 /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB
2015 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB
2016 * To improve BT ACI in co-rx
2017 */
2018
2019 switch (level) {
2020 case 0: /* default */
2021 rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWE, RFREG_MASK, data: 0x1000);
2022 rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWA, RFREG_MASK, data: 0x3);
2023 rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWD0, RFREG_MASK, data: 0x17);
2024 rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWA, RFREG_MASK, data: 0x2);
2025 rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWD0, RFREG_MASK, data: 0x15);
2026 rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWE, RFREG_MASK, data: 0x0);
2027 break;
2028 case 1: /* Fix LNA2=5 */
2029 rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWE, RFREG_MASK, data: 0x1000);
2030 rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWA, RFREG_MASK, data: 0x3);
2031 rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWD0, RFREG_MASK, data: 0x5);
2032 rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWA, RFREG_MASK, data: 0x2);
2033 rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWD0, RFREG_MASK, data: 0x15);
2034 rtw89_write_rf(rtwdev, rf_path: RF_PATH_B, RR_LUTWE, RFREG_MASK, data: 0x0);
2035 break;
2036 }
2037}
2038
2039static void rtw8852a_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
2040{
2041 struct rtw89_btc *btc = &rtwdev->btc;
2042
2043 switch (level) {
2044 case 0: /* original */
2045 default:
2046 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, en: false, phy_idx: RTW89_PHY_0);
2047 btc->dm.wl_lna2 = 0;
2048 break;
2049 case 1: /* for FDD free-run */
2050 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, en: true, phy_idx: RTW89_PHY_0);
2051 btc->dm.wl_lna2 = 0;
2052 break;
2053 case 2: /* for BTG Co-Rx*/
2054 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, en: false, phy_idx: RTW89_PHY_0);
2055 btc->dm.wl_lna2 = 1;
2056 break;
2057 }
2058
2059 rtw8852a_set_wl_lna2(rtwdev, level: btc->dm.wl_lna2);
2060}
2061
2062static void rtw8852a_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
2063 struct rtw89_rx_phy_ppdu *phy_ppdu,
2064 struct ieee80211_rx_status *status)
2065{
2066 u16 chan = phy_ppdu->chan_idx;
2067 u8 band;
2068
2069 if (chan == 0)
2070 return;
2071
2072 band = chan <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
2073 status->freq = ieee80211_channel_to_frequency(chan, band);
2074 status->band = band;
2075}
2076
2077static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev,
2078 struct rtw89_rx_phy_ppdu *phy_ppdu,
2079 struct ieee80211_rx_status *status)
2080{
2081 u8 path;
2082 u8 *rx_power = phy_ppdu->rssi;
2083
2084 if (!status->signal)
2085 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A],
2086 rx_power[RF_PATH_B]));
2087 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2088 status->chains |= BIT(path);
2089 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
2090 }
2091 if (phy_ppdu->valid)
2092 rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
2093}
2094
2095#ifdef CONFIG_PM
2096static const struct wiphy_wowlan_support rtw_wowlan_stub_8852a = {
2097 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
2098 .n_patterns = RTW89_MAX_PATTERN_NUM,
2099 .pattern_max_len = RTW89_MAX_PATTERN_SIZE,
2100 .pattern_min_len = 1,
2101};
2102#endif
2103
2104static const struct rtw89_chip_ops rtw8852a_chip_ops = {
2105 .enable_bb_rf = rtw89_mac_enable_bb_rf,
2106 .disable_bb_rf = rtw89_mac_disable_bb_rf,
2107 .bb_preinit = NULL,
2108 .bb_postinit = NULL,
2109 .bb_reset = rtw8852a_bb_reset,
2110 .bb_sethw = rtw8852a_bb_sethw,
2111 .read_rf = rtw89_phy_read_rf,
2112 .write_rf = rtw89_phy_write_rf,
2113 .set_channel = rtw8852a_set_channel,
2114 .set_channel_help = rtw8852a_set_channel_help,
2115 .read_efuse = rtw8852a_read_efuse,
2116 .read_phycap = rtw8852a_read_phycap,
2117 .fem_setup = rtw8852a_fem_setup,
2118 .rfe_gpio = NULL,
2119 .rfk_hw_init = NULL,
2120 .rfk_init = rtw8852a_rfk_init,
2121 .rfk_init_late = NULL,
2122 .rfk_channel = rtw8852a_rfk_channel,
2123 .rfk_band_changed = rtw8852a_rfk_band_changed,
2124 .rfk_scan = rtw8852a_rfk_scan,
2125 .rfk_track = rtw8852a_rfk_track,
2126 .power_trim = rtw8852a_power_trim,
2127 .set_txpwr = rtw8852a_set_txpwr,
2128 .set_txpwr_ctrl = rtw8852a_set_txpwr_ctrl,
2129 .init_txpwr_unit = rtw8852a_init_txpwr_unit,
2130 .get_thermal = rtw8852a_get_thermal,
2131 .ctrl_btg_bt_rx = rtw8852a_ctrl_btg_bt_rx,
2132 .query_ppdu = rtw8852a_query_ppdu,
2133 .convert_rpl_to_rssi = NULL,
2134 .phy_rpt_to_rssi = NULL,
2135 .ctrl_nbtg_bt_tx = rtw8852a_ctrl_nbtg_bt_tx,
2136 .cfg_txrx_path = NULL,
2137 .set_txpwr_ul_tb_offset = rtw8852a_set_txpwr_ul_tb_offset,
2138 .digital_pwr_comp = NULL,
2139 .pwr_on_func = NULL,
2140 .pwr_off_func = NULL,
2141 .query_rxdesc = rtw89_core_query_rxdesc,
2142 .fill_txdesc = rtw89_core_fill_txdesc,
2143 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc,
2144 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path,
2145 .mac_cfg_gnt = rtw89_mac_cfg_gnt,
2146 .stop_sch_tx = rtw89_mac_stop_sch_tx,
2147 .resume_sch_tx = rtw89_mac_resume_sch_tx,
2148 .h2c_dctl_sec_cam = NULL,
2149 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl,
2150 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl,
2151 .h2c_ampdu_cmac_tbl = NULL,
2152 .h2c_txtime_cmac_tbl = rtw89_fw_h2c_txtime_cmac_tbl,
2153 .h2c_default_dmac_tbl = NULL,
2154 .h2c_update_beacon = rtw89_fw_h2c_update_beacon,
2155 .h2c_ba_cam = rtw89_fw_h2c_ba_cam,
2156
2157 .btc_set_rfe = rtw8852a_btc_set_rfe,
2158 .btc_init_cfg = rtw8852a_btc_init_cfg,
2159 .btc_set_wl_pri = rtw8852a_btc_set_wl_pri,
2160 .btc_set_wl_txpwr_ctrl = rtw8852a_btc_set_wl_txpwr_ctrl,
2161 .btc_get_bt_rssi = rtw8852a_btc_get_bt_rssi,
2162 .btc_update_bt_cnt = rtw8852a_btc_update_bt_cnt,
2163 .btc_wl_s1_standby = rtw8852a_btc_wl_s1_standby,
2164 .btc_set_wl_rx_gain = rtw8852a_btc_set_wl_rx_gain,
2165 .btc_set_policy = rtw89_btc_set_policy,
2166};
2167
2168const struct rtw89_chip_info rtw8852a_chip_info = {
2169 .chip_id = RTL8852A,
2170 .chip_gen = RTW89_CHIP_AX,
2171 .ops = &rtw8852a_chip_ops,
2172 .mac_def = &rtw89_mac_gen_ax,
2173 .phy_def = &rtw89_phy_gen_ax,
2174 .fw_basename = RTW8852A_FW_BASENAME,
2175 .fw_format_max = RTW8852A_FW_FORMAT_MAX,
2176 .try_ce_fw = false,
2177 .bbmcu_nr = 0,
2178 .needed_fw_elms = 0,
2179 .fw_blacklist = NULL,
2180 .fifo_size = 458752,
2181 .small_fifo_size = false,
2182 .dle_scc_rsvd_size = 0,
2183 .max_amsdu_limit = 3500,
2184 .dis_2g_40m_ul_ofdma = true,
2185 .rsvd_ple_ofst = 0x6f800,
2186 .hfc_param_ini = rtw8852a_hfc_param_ini_pcie,
2187 .dle_mem = rtw8852a_dle_mem_pcie,
2188 .wde_qempty_acq_grpnum = 16,
2189 .wde_qempty_mgq_grpsel = 16,
2190 .rf_base_addr = {0xc000, 0xd000},
2191 .thermal_th = {0x32, 0x35},
2192 .pwr_on_seq = pwr_on_seq_8852a,
2193 .pwr_off_seq = pwr_off_seq_8852a,
2194 .bb_table = &rtw89_8852a_phy_bb_table,
2195 .bb_gain_table = NULL,
2196 .rf_table = {&rtw89_8852a_phy_radioa_table,
2197 &rtw89_8852a_phy_radiob_table,},
2198 .nctl_table = &rtw89_8852a_phy_nctl_table,
2199 .nctl_post_table = NULL,
2200 .dflt_parms = &rtw89_8852a_dflt_parms,
2201 .rfe_parms_conf = NULL,
2202 .txpwr_factor_bb = 3,
2203 .txpwr_factor_rf = 2,
2204 .txpwr_factor_mac = 1,
2205 .dig_table = &rtw89_8852a_phy_dig_table,
2206 .dig_regs = &rtw8852a_dig_regs,
2207 .tssi_dbw_table = NULL,
2208 .support_macid_num = RTW89_MAX_MAC_ID_NUM,
2209 .support_link_num = 0,
2210 .support_chanctx_num = 1,
2211 .support_rnr = false,
2212 .support_bands = BIT(NL80211_BAND_2GHZ) |
2213 BIT(NL80211_BAND_5GHZ),
2214 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) |
2215 BIT(NL80211_CHAN_WIDTH_40) |
2216 BIT(NL80211_CHAN_WIDTH_80),
2217 .support_unii4 = false,
2218 .support_ant_gain = false,
2219 .support_tas = false,
2220 .support_sar_by_ant = false,
2221 .ul_tb_waveform_ctrl = false,
2222 .ul_tb_pwr_diff = false,
2223 .rx_freq_frome_ie = true,
2224 .hw_sec_hdr = false,
2225 .hw_mgmt_tx_encrypt = false,
2226 .hw_tkip_crypto = false,
2227 .hw_mlo_bmc_crypto = false,
2228 .rf_path_num = 2,
2229 .tx_nss = 2,
2230 .rx_nss = 2,
2231 .acam_num = 128,
2232 .bcam_num = 10,
2233 .scam_num = 128,
2234 .bacam_num = 2,
2235 .bacam_dynamic_num = 4,
2236 .bacam_ver = RTW89_BACAM_V0,
2237 .ppdu_max_usr = 4,
2238 .sec_ctrl_efuse_size = 4,
2239 .physical_efuse_size = 1216,
2240 .logical_efuse_size = 1536,
2241 .limit_efuse_size = 1152,
2242 .dav_phy_efuse_size = 0,
2243 .dav_log_efuse_size = 0,
2244 .efuse_blocks = NULL,
2245 .phycap_addr = 0x580,
2246 .phycap_size = 128,
2247 .para_ver = 0x0,
2248 .wlcx_desired = 0x06000000,
2249 .btcx_desired = 0x7,
2250 .scbd = 0x1,
2251 .mailbox = 0x1,
2252
2253 .afh_guard_ch = 6,
2254 .wl_rssi_thres = rtw89_btc_8852a_wl_rssi_thres,
2255 .bt_rssi_thres = rtw89_btc_8852a_bt_rssi_thres,
2256 .rssi_tol = 2,
2257 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852a_mon_reg),
2258 .mon_reg = rtw89_btc_8852a_mon_reg,
2259 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_ul),
2260 .rf_para_ulink = rtw89_btc_8852a_rf_ul,
2261 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_dl),
2262 .rf_para_dlink = rtw89_btc_8852a_rf_dl,
2263 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
2264 BIT(RTW89_PS_MODE_CLK_GATED) |
2265 BIT(RTW89_PS_MODE_PWR_GATED),
2266 .low_power_hci_modes = 0,
2267 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD,
2268 .hci_func_en_addr = R_AX_HCI_FUNC_EN,
2269 .h2c_desc_size = sizeof(struct rtw89_txwd_body),
2270 .txwd_body_size = sizeof(struct rtw89_txwd_body),
2271 .txwd_info_size = sizeof(struct rtw89_txwd_info),
2272 .h2c_ctrl_reg = R_AX_H2CREG_CTRL,
2273 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8},
2274 .h2c_regs = rtw8852a_h2c_regs,
2275 .c2h_ctrl_reg = R_AX_C2HREG_CTRL,
2276 .c2h_regs = rtw8852a_c2h_regs,
2277 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
2278 .page_regs = &rtw8852a_page_regs,
2279 .wow_reason_reg = rtw8852a_wow_wakeup_regs,
2280 .cfo_src_fd = false,
2281 .cfo_hw_comp = false,
2282 .dcfo_comp = &rtw8852a_dcfo_comp,
2283 .dcfo_comp_sft = 10,
2284 .imr_info = &rtw8852a_imr_info,
2285 .imr_dmac_table = NULL,
2286 .imr_cmac_table = NULL,
2287 .rrsr_cfgs = &rtw8852a_rrsr_cfgs,
2288 .bss_clr_vld = {R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0},
2289 .bss_clr_map_reg = R_BSS_CLR_MAP,
2290 .rfkill_init = &rtw8852a_rfkill_regs,
2291 .rfkill_get = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9},
2292 .dma_ch_mask = 0,
2293 .edcca_regs = &rtw8852a_edcca_regs,
2294#ifdef CONFIG_PM
2295 .wowlan_stub = &rtw_wowlan_stub_8852a,
2296#endif
2297 .xtal_info = &rtw8852a_xtal_info,
2298};
2299EXPORT_SYMBOL(rtw8852a_chip_info);
2300
2301MODULE_FIRMWARE(RTW8852A_MODULE_FIRMWARE);
2302MODULE_AUTHOR("Realtek Corporation");
2303MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852A driver");
2304MODULE_LICENSE("Dual BSD/GPL");
2305

source code of linux/drivers/net/wireless/realtek/rtw89/rtw8852a.c