1 | /* SPDX-License-Identifier: GPL-2.0-only |
2 | * |
3 | * Copyright (c) 2021, MediaTek Inc. |
4 | * Copyright (c) 2021-2022, Intel Corporation. |
5 | * |
6 | * Authors: |
7 | * Haijun Liu <haijun.liu@mediatek.com> |
8 | * Moises Veleta <moises.veleta@intel.com> |
9 | * Ricardo Martinez <ricardo.martinez@linux.intel.com> |
10 | * |
11 | * Contributors: |
12 | * Amir Hanania <amir.hanania@intel.com> |
13 | * Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
14 | * Chandrashekar Devegowda <chandrashekar.devegowda@intel.com> |
15 | * Eliot Lee <eliot.lee@intel.com> |
16 | */ |
17 | |
18 | #ifndef __T7XX_PORT_H__ |
19 | #define __T7XX_PORT_H__ |
20 | |
21 | #include <linux/bits.h> |
22 | #include <linux/device.h> |
23 | #include <linux/mutex.h> |
24 | #include <linux/sched.h> |
25 | #include <linux/skbuff.h> |
26 | #include <linux/spinlock.h> |
27 | #include <linux/types.h> |
28 | #include <linux/wait.h> |
29 | #include <linux/wwan.h> |
30 | |
31 | #include "t7xx_hif_cldma.h" |
32 | #include "t7xx_pci.h" |
33 | |
34 | #define PORT_CH_ID_MASK GENMASK(7, 0) |
35 | |
36 | /* Channel ID and Message ID definitions. |
37 | * The channel number consists of peer_id(15:12) , channel_id(11:0) |
38 | * peer_id: |
39 | * 0:reserved, 1: to AP, 2: to MD |
40 | */ |
41 | enum port_ch { |
42 | /* to AP */ |
43 | PORT_CH_AP_CONTROL_RX = 0x1000, |
44 | PORT_CH_AP_CONTROL_TX = 0x1001, |
45 | |
46 | /* to MD */ |
47 | PORT_CH_CONTROL_RX = 0x2000, |
48 | PORT_CH_CONTROL_TX = 0x2001, |
49 | PORT_CH_UART1_RX = 0x2006, /* META */ |
50 | PORT_CH_UART1_TX = 0x2008, |
51 | PORT_CH_UART2_RX = 0x200a, /* AT */ |
52 | PORT_CH_UART2_TX = 0x200c, |
53 | PORT_CH_MD_LOG_RX = 0x202a, /* MD logging */ |
54 | PORT_CH_MD_LOG_TX = 0x202b, |
55 | PORT_CH_LB_IT_RX = 0x203e, /* Loop back test */ |
56 | PORT_CH_LB_IT_TX = 0x203f, |
57 | PORT_CH_STATUS_RX = 0x2043, /* Status events */ |
58 | PORT_CH_MIPC_RX = 0x20ce, /* MIPC */ |
59 | PORT_CH_MIPC_TX = 0x20cf, |
60 | PORT_CH_MBIM_RX = 0x20d0, |
61 | PORT_CH_MBIM_TX = 0x20d1, |
62 | PORT_CH_DSS0_RX = 0x20d2, |
63 | PORT_CH_DSS0_TX = 0x20d3, |
64 | PORT_CH_DSS1_RX = 0x20d4, |
65 | PORT_CH_DSS1_TX = 0x20d5, |
66 | PORT_CH_DSS2_RX = 0x20d6, |
67 | PORT_CH_DSS2_TX = 0x20d7, |
68 | PORT_CH_DSS3_RX = 0x20d8, |
69 | PORT_CH_DSS3_TX = 0x20d9, |
70 | PORT_CH_DSS4_RX = 0x20da, |
71 | PORT_CH_DSS4_TX = 0x20db, |
72 | PORT_CH_DSS5_RX = 0x20dc, |
73 | PORT_CH_DSS5_TX = 0x20dd, |
74 | PORT_CH_DSS6_RX = 0x20de, |
75 | PORT_CH_DSS6_TX = 0x20df, |
76 | PORT_CH_DSS7_RX = 0x20e0, |
77 | PORT_CH_DSS7_TX = 0x20e1, |
78 | |
79 | PORT_CH_UNIMPORTANT = 0xffff, |
80 | }; |
81 | |
82 | struct t7xx_port; |
83 | struct port_ops { |
84 | int (*init)(struct t7xx_port *port); |
85 | int (*recv_skb)(struct t7xx_port *port, struct sk_buff *skb); |
86 | void (*md_state_notify)(struct t7xx_port *port, unsigned int md_state); |
87 | void (*uninit)(struct t7xx_port *port); |
88 | int (*enable_chl)(struct t7xx_port *port); |
89 | int (*disable_chl)(struct t7xx_port *port); |
90 | }; |
91 | |
92 | struct t7xx_port_conf { |
93 | enum port_ch tx_ch; |
94 | enum port_ch rx_ch; |
95 | unsigned char txq_index; |
96 | unsigned char rxq_index; |
97 | unsigned char txq_exp_index; |
98 | unsigned char rxq_exp_index; |
99 | enum cldma_id path_id; |
100 | struct port_ops *ops; |
101 | char *name; |
102 | enum wwan_port_type port_type; |
103 | }; |
104 | |
105 | struct t7xx_port { |
106 | /* Members not initialized in definition */ |
107 | const struct t7xx_port_conf *port_conf; |
108 | struct t7xx_pci_dev *t7xx_dev; |
109 | struct device *dev; |
110 | u16 seq_nums[2]; /* TX/RX sequence numbers */ |
111 | atomic_t usage_cnt; |
112 | struct list_head entry; |
113 | struct list_head queue_entry; |
114 | /* TX and RX flows are asymmetric since ports are multiplexed on |
115 | * queues. |
116 | * |
117 | * TX: data blocks are sent directly to a queue. Each port |
118 | * does not maintain a TX list; instead, they only provide |
119 | * a wait_queue_head for blocking writes. |
120 | * |
121 | * RX: Each port uses a RX list to hold packets, |
122 | * allowing the modem to dispatch RX packet as quickly as possible. |
123 | */ |
124 | struct sk_buff_head rx_skb_list; |
125 | spinlock_t port_update_lock; /* Protects port configuration */ |
126 | wait_queue_head_t rx_wq; |
127 | int rx_length_th; |
128 | bool chan_enable; |
129 | struct task_struct *thread; |
130 | union { |
131 | struct { |
132 | struct wwan_port *wwan_port; |
133 | } wwan; |
134 | struct { |
135 | struct rchan *relaych; |
136 | } log; |
137 | }; |
138 | }; |
139 | |
140 | int t7xx_get_port_mtu(struct t7xx_port *port); |
141 | struct sk_buff *t7xx_port_alloc_skb(int payload); |
142 | struct sk_buff *t7xx_ctrl_alloc_skb(int payload); |
143 | int t7xx_port_enqueue_skb(struct t7xx_port *port, struct sk_buff *skb); |
144 | int t7xx_port_send_skb(struct t7xx_port *port, struct sk_buff *skb, unsigned int , |
145 | unsigned int ex_msg); |
146 | int t7xx_port_send_raw_skb(struct t7xx_port *port, struct sk_buff *skb); |
147 | int t7xx_port_send_ctl_skb(struct t7xx_port *port, struct sk_buff *skb, unsigned int msg, |
148 | unsigned int ex_msg); |
149 | |
150 | #endif /* __T7XX_PORT_H__ */ |
151 | |