1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Volume Management Device driver |
4 | * Copyright (c) 2015, Intel Corporation. |
5 | */ |
6 | |
7 | #include <linux/device.h> |
8 | #include <linux/interrupt.h> |
9 | #include <linux/irq.h> |
10 | #include <linux/kernel.h> |
11 | #include <linux/module.h> |
12 | #include <linux/msi.h> |
13 | #include <linux/pci.h> |
14 | #include <linux/pci-acpi.h> |
15 | #include <linux/pci-ecam.h> |
16 | #include <linux/srcu.h> |
17 | #include <linux/rculist.h> |
18 | #include <linux/rcupdate.h> |
19 | |
20 | #include <asm/irqdomain.h> |
21 | |
22 | #define VMD_CFGBAR 0 |
23 | #define VMD_MEMBAR1 2 |
24 | #define VMD_MEMBAR2 4 |
25 | |
26 | #define PCI_REG_VMCAP 0x40 |
27 | #define BUS_RESTRICT_CAP(vmcap) (vmcap & 0x1) |
28 | #define PCI_REG_VMCONFIG 0x44 |
29 | #define BUS_RESTRICT_CFG(vmcfg) ((vmcfg >> 8) & 0x3) |
30 | #define VMCONFIG_MSI_REMAP 0x2 |
31 | #define PCI_REG_VMLOCK 0x70 |
32 | #define MB2_SHADOW_EN(vmlock) (vmlock & 0x2) |
33 | |
34 | #define MB2_SHADOW_OFFSET 0x2000 |
35 | #define MB2_SHADOW_SIZE 16 |
36 | |
37 | enum vmd_features { |
38 | /* |
39 | * Device may contain registers which hint the physical location of the |
40 | * membars, in order to allow proper address translation during |
41 | * resource assignment to enable guest virtualization |
42 | */ |
43 | VMD_FEAT_HAS_MEMBAR_SHADOW = (1 << 0), |
44 | |
45 | /* |
46 | * Device may provide root port configuration information which limits |
47 | * bus numbering |
48 | */ |
49 | VMD_FEAT_HAS_BUS_RESTRICTIONS = (1 << 1), |
50 | |
51 | /* |
52 | * Device contains physical location shadow registers in |
53 | * vendor-specific capability space |
54 | */ |
55 | VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP = (1 << 2), |
56 | |
57 | /* |
58 | * Device may use MSI-X vector 0 for software triggering and will not |
59 | * be used for MSI remapping |
60 | */ |
61 | VMD_FEAT_OFFSET_FIRST_VECTOR = (1 << 3), |
62 | |
63 | /* |
64 | * Device can bypass remapping MSI-X transactions into its MSI-X table, |
65 | * avoiding the requirement of a VMD MSI domain for child device |
66 | * interrupt handling. |
67 | */ |
68 | VMD_FEAT_CAN_BYPASS_MSI_REMAP = (1 << 4), |
69 | |
70 | /* |
71 | * Enable ASPM on the PCIE root ports and set the default LTR of the |
72 | * storage devices on platforms where these values are not configured by |
73 | * BIOS. This is needed for laptops, which require these settings for |
74 | * proper power management of the SoC. |
75 | */ |
76 | VMD_FEAT_BIOS_PM_QUIRK = (1 << 5), |
77 | }; |
78 | |
79 | #define VMD_BIOS_PM_QUIRK_LTR 0x1003 /* 3145728 ns */ |
80 | |
81 | #define VMD_FEATS_CLIENT (VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP | \ |
82 | VMD_FEAT_HAS_BUS_RESTRICTIONS | \ |
83 | VMD_FEAT_OFFSET_FIRST_VECTOR | \ |
84 | VMD_FEAT_BIOS_PM_QUIRK) |
85 | |
86 | static DEFINE_IDA(vmd_instance_ida); |
87 | |
88 | /* |
89 | * Lock for manipulating VMD IRQ lists. |
90 | */ |
91 | static DEFINE_RAW_SPINLOCK(list_lock); |
92 | |
93 | /** |
94 | * struct vmd_irq - private data to map driver IRQ to the VMD shared vector |
95 | * @node: list item for parent traversal. |
96 | * @irq: back pointer to parent. |
97 | * @enabled: true if driver enabled IRQ |
98 | * @virq: the virtual IRQ value provided to the requesting driver. |
99 | * |
100 | * Every MSI/MSI-X IRQ requested for a device in a VMD domain will be mapped to |
101 | * a VMD IRQ using this structure. |
102 | */ |
103 | struct vmd_irq { |
104 | struct list_head node; |
105 | struct vmd_irq_list *irq; |
106 | bool enabled; |
107 | unsigned int virq; |
108 | }; |
109 | |
110 | /** |
111 | * struct vmd_irq_list - list of driver requested IRQs mapping to a VMD vector |
112 | * @irq_list: the list of irq's the VMD one demuxes to. |
113 | * @srcu: SRCU struct for local synchronization. |
114 | * @count: number of child IRQs assigned to this vector; used to track |
115 | * sharing. |
116 | * @virq: The underlying VMD Linux interrupt number |
117 | */ |
118 | struct vmd_irq_list { |
119 | struct list_head irq_list; |
120 | struct srcu_struct srcu; |
121 | unsigned int count; |
122 | unsigned int virq; |
123 | }; |
124 | |
125 | struct vmd_dev { |
126 | struct pci_dev *dev; |
127 | |
128 | spinlock_t cfg_lock; |
129 | void __iomem *cfgbar; |
130 | |
131 | int msix_count; |
132 | struct vmd_irq_list *irqs; |
133 | |
134 | struct pci_sysdata sysdata; |
135 | struct resource resources[3]; |
136 | struct irq_domain *irq_domain; |
137 | struct pci_bus *bus; |
138 | u8 busn_start; |
139 | u8 first_vec; |
140 | char *name; |
141 | int instance; |
142 | }; |
143 | |
144 | static inline struct vmd_dev *vmd_from_bus(struct pci_bus *bus) |
145 | { |
146 | return container_of(bus->sysdata, struct vmd_dev, sysdata); |
147 | } |
148 | |
149 | static inline unsigned int index_from_irqs(struct vmd_dev *vmd, |
150 | struct vmd_irq_list *irqs) |
151 | { |
152 | return irqs - vmd->irqs; |
153 | } |
154 | |
155 | /* |
156 | * Drivers managing a device in a VMD domain allocate their own IRQs as before, |
157 | * but the MSI entry for the hardware it's driving will be programmed with a |
158 | * destination ID for the VMD MSI-X table. The VMD muxes interrupts in its |
159 | * domain into one of its own, and the VMD driver de-muxes these for the |
160 | * handlers sharing that VMD IRQ. The vmd irq_domain provides the operations |
161 | * and irq_chip to set this up. |
162 | */ |
163 | static void vmd_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) |
164 | { |
165 | struct vmd_irq *vmdirq = data->chip_data; |
166 | struct vmd_irq_list *irq = vmdirq->irq; |
167 | struct vmd_dev *vmd = irq_data_get_irq_handler_data(d: data); |
168 | |
169 | memset(msg, 0, sizeof(*msg)); |
170 | msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH; |
171 | msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW; |
172 | msg->arch_addr_lo.destid_0_7 = index_from_irqs(vmd, irqs: irq); |
173 | } |
174 | |
175 | /* |
176 | * We rely on MSI_FLAG_USE_DEF_CHIP_OPS to set the IRQ mask/unmask ops. |
177 | */ |
178 | static void vmd_irq_enable(struct irq_data *data) |
179 | { |
180 | struct vmd_irq *vmdirq = data->chip_data; |
181 | unsigned long flags; |
182 | |
183 | raw_spin_lock_irqsave(&list_lock, flags); |
184 | WARN_ON(vmdirq->enabled); |
185 | list_add_tail_rcu(new: &vmdirq->node, head: &vmdirq->irq->irq_list); |
186 | vmdirq->enabled = true; |
187 | raw_spin_unlock_irqrestore(&list_lock, flags); |
188 | |
189 | data->chip->irq_unmask(data); |
190 | } |
191 | |
192 | static void vmd_irq_disable(struct irq_data *data) |
193 | { |
194 | struct vmd_irq *vmdirq = data->chip_data; |
195 | unsigned long flags; |
196 | |
197 | data->chip->irq_mask(data); |
198 | |
199 | raw_spin_lock_irqsave(&list_lock, flags); |
200 | if (vmdirq->enabled) { |
201 | list_del_rcu(entry: &vmdirq->node); |
202 | vmdirq->enabled = false; |
203 | } |
204 | raw_spin_unlock_irqrestore(&list_lock, flags); |
205 | } |
206 | |
207 | /* |
208 | * XXX: Stubbed until we develop acceptable way to not create conflicts with |
209 | * other devices sharing the same vector. |
210 | */ |
211 | static int vmd_irq_set_affinity(struct irq_data *data, |
212 | const struct cpumask *dest, bool force) |
213 | { |
214 | return -EINVAL; |
215 | } |
216 | |
217 | static struct irq_chip vmd_msi_controller = { |
218 | .name = "VMD-MSI" , |
219 | .irq_enable = vmd_irq_enable, |
220 | .irq_disable = vmd_irq_disable, |
221 | .irq_compose_msi_msg = vmd_compose_msi_msg, |
222 | .irq_set_affinity = vmd_irq_set_affinity, |
223 | }; |
224 | |
225 | static irq_hw_number_t vmd_get_hwirq(struct msi_domain_info *info, |
226 | msi_alloc_info_t *arg) |
227 | { |
228 | return 0; |
229 | } |
230 | |
231 | /* |
232 | * XXX: We can be even smarter selecting the best IRQ once we solve the |
233 | * affinity problem. |
234 | */ |
235 | static struct vmd_irq_list *vmd_next_irq(struct vmd_dev *vmd, struct msi_desc *desc) |
236 | { |
237 | unsigned long flags; |
238 | int i, best; |
239 | |
240 | if (vmd->msix_count == 1 + vmd->first_vec) |
241 | return &vmd->irqs[vmd->first_vec]; |
242 | |
243 | /* |
244 | * White list for fast-interrupt handlers. All others will share the |
245 | * "slow" interrupt vector. |
246 | */ |
247 | switch (msi_desc_to_pci_dev(desc)->class) { |
248 | case PCI_CLASS_STORAGE_EXPRESS: |
249 | break; |
250 | default: |
251 | return &vmd->irqs[vmd->first_vec]; |
252 | } |
253 | |
254 | raw_spin_lock_irqsave(&list_lock, flags); |
255 | best = vmd->first_vec + 1; |
256 | for (i = best; i < vmd->msix_count; i++) |
257 | if (vmd->irqs[i].count < vmd->irqs[best].count) |
258 | best = i; |
259 | vmd->irqs[best].count++; |
260 | raw_spin_unlock_irqrestore(&list_lock, flags); |
261 | |
262 | return &vmd->irqs[best]; |
263 | } |
264 | |
265 | static int vmd_msi_init(struct irq_domain *domain, struct msi_domain_info *info, |
266 | unsigned int virq, irq_hw_number_t hwirq, |
267 | msi_alloc_info_t *arg) |
268 | { |
269 | struct msi_desc *desc = arg->desc; |
270 | struct vmd_dev *vmd = vmd_from_bus(bus: msi_desc_to_pci_dev(desc)->bus); |
271 | struct vmd_irq *vmdirq = kzalloc(size: sizeof(*vmdirq), GFP_KERNEL); |
272 | |
273 | if (!vmdirq) |
274 | return -ENOMEM; |
275 | |
276 | INIT_LIST_HEAD(list: &vmdirq->node); |
277 | vmdirq->irq = vmd_next_irq(vmd, desc); |
278 | vmdirq->virq = virq; |
279 | |
280 | irq_domain_set_info(domain, virq, hwirq: vmdirq->irq->virq, chip: info->chip, chip_data: vmdirq, |
281 | handler: handle_untracked_irq, handler_data: vmd, NULL); |
282 | return 0; |
283 | } |
284 | |
285 | static void vmd_msi_free(struct irq_domain *domain, |
286 | struct msi_domain_info *info, unsigned int virq) |
287 | { |
288 | struct vmd_irq *vmdirq = irq_get_chip_data(irq: virq); |
289 | unsigned long flags; |
290 | |
291 | synchronize_srcu(ssp: &vmdirq->irq->srcu); |
292 | |
293 | /* XXX: Potential optimization to rebalance */ |
294 | raw_spin_lock_irqsave(&list_lock, flags); |
295 | vmdirq->irq->count--; |
296 | raw_spin_unlock_irqrestore(&list_lock, flags); |
297 | |
298 | kfree(objp: vmdirq); |
299 | } |
300 | |
301 | static int vmd_msi_prepare(struct irq_domain *domain, struct device *dev, |
302 | int nvec, msi_alloc_info_t *arg) |
303 | { |
304 | struct pci_dev *pdev = to_pci_dev(dev); |
305 | struct vmd_dev *vmd = vmd_from_bus(bus: pdev->bus); |
306 | |
307 | if (nvec > vmd->msix_count) |
308 | return vmd->msix_count; |
309 | |
310 | memset(arg, 0, sizeof(*arg)); |
311 | return 0; |
312 | } |
313 | |
314 | static void vmd_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc) |
315 | { |
316 | arg->desc = desc; |
317 | } |
318 | |
319 | static struct msi_domain_ops vmd_msi_domain_ops = { |
320 | .get_hwirq = vmd_get_hwirq, |
321 | .msi_init = vmd_msi_init, |
322 | .msi_free = vmd_msi_free, |
323 | .msi_prepare = vmd_msi_prepare, |
324 | .set_desc = vmd_set_desc, |
325 | }; |
326 | |
327 | static struct msi_domain_info vmd_msi_domain_info = { |
328 | .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | |
329 | MSI_FLAG_PCI_MSIX, |
330 | .ops = &vmd_msi_domain_ops, |
331 | .chip = &vmd_msi_controller, |
332 | }; |
333 | |
334 | static void vmd_set_msi_remapping(struct vmd_dev *vmd, bool enable) |
335 | { |
336 | u16 reg; |
337 | |
338 | pci_read_config_word(dev: vmd->dev, PCI_REG_VMCONFIG, val: ®); |
339 | reg = enable ? (reg & ~VMCONFIG_MSI_REMAP) : |
340 | (reg | VMCONFIG_MSI_REMAP); |
341 | pci_write_config_word(dev: vmd->dev, PCI_REG_VMCONFIG, val: reg); |
342 | } |
343 | |
344 | static int vmd_create_irq_domain(struct vmd_dev *vmd) |
345 | { |
346 | struct fwnode_handle *fn; |
347 | |
348 | fn = irq_domain_alloc_named_id_fwnode(name: "VMD-MSI" , id: vmd->sysdata.domain); |
349 | if (!fn) |
350 | return -ENODEV; |
351 | |
352 | vmd->irq_domain = pci_msi_create_irq_domain(fwnode: fn, info: &vmd_msi_domain_info, NULL); |
353 | if (!vmd->irq_domain) { |
354 | irq_domain_free_fwnode(fwnode: fn); |
355 | return -ENODEV; |
356 | } |
357 | |
358 | return 0; |
359 | } |
360 | |
361 | static void vmd_remove_irq_domain(struct vmd_dev *vmd) |
362 | { |
363 | /* |
364 | * Some production BIOS won't enable remapping between soft reboots. |
365 | * Ensure remapping is restored before unloading the driver. |
366 | */ |
367 | if (!vmd->msix_count) |
368 | vmd_set_msi_remapping(vmd, enable: true); |
369 | |
370 | if (vmd->irq_domain) { |
371 | struct fwnode_handle *fn = vmd->irq_domain->fwnode; |
372 | |
373 | irq_domain_remove(host: vmd->irq_domain); |
374 | irq_domain_free_fwnode(fwnode: fn); |
375 | } |
376 | } |
377 | |
378 | static void __iomem *vmd_cfg_addr(struct vmd_dev *vmd, struct pci_bus *bus, |
379 | unsigned int devfn, int reg, int len) |
380 | { |
381 | unsigned int busnr_ecam = bus->number - vmd->busn_start; |
382 | u32 offset = PCIE_ECAM_OFFSET(busnr_ecam, devfn, reg); |
383 | |
384 | if (offset + len >= resource_size(res: &vmd->dev->resource[VMD_CFGBAR])) |
385 | return NULL; |
386 | |
387 | return vmd->cfgbar + offset; |
388 | } |
389 | |
390 | /* |
391 | * CPU may deadlock if config space is not serialized on some versions of this |
392 | * hardware, so all config space access is done under a spinlock. |
393 | */ |
394 | static int vmd_pci_read(struct pci_bus *bus, unsigned int devfn, int reg, |
395 | int len, u32 *value) |
396 | { |
397 | struct vmd_dev *vmd = vmd_from_bus(bus); |
398 | void __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len); |
399 | unsigned long flags; |
400 | int ret = 0; |
401 | |
402 | if (!addr) |
403 | return -EFAULT; |
404 | |
405 | spin_lock_irqsave(&vmd->cfg_lock, flags); |
406 | switch (len) { |
407 | case 1: |
408 | *value = readb(addr); |
409 | break; |
410 | case 2: |
411 | *value = readw(addr); |
412 | break; |
413 | case 4: |
414 | *value = readl(addr); |
415 | break; |
416 | default: |
417 | ret = -EINVAL; |
418 | break; |
419 | } |
420 | spin_unlock_irqrestore(lock: &vmd->cfg_lock, flags); |
421 | return ret; |
422 | } |
423 | |
424 | /* |
425 | * VMD h/w converts non-posted config writes to posted memory writes. The |
426 | * read-back in this function forces the completion so it returns only after |
427 | * the config space was written, as expected. |
428 | */ |
429 | static int vmd_pci_write(struct pci_bus *bus, unsigned int devfn, int reg, |
430 | int len, u32 value) |
431 | { |
432 | struct vmd_dev *vmd = vmd_from_bus(bus); |
433 | void __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len); |
434 | unsigned long flags; |
435 | int ret = 0; |
436 | |
437 | if (!addr) |
438 | return -EFAULT; |
439 | |
440 | spin_lock_irqsave(&vmd->cfg_lock, flags); |
441 | switch (len) { |
442 | case 1: |
443 | writeb(val: value, addr); |
444 | readb(addr); |
445 | break; |
446 | case 2: |
447 | writew(val: value, addr); |
448 | readw(addr); |
449 | break; |
450 | case 4: |
451 | writel(val: value, addr); |
452 | readl(addr); |
453 | break; |
454 | default: |
455 | ret = -EINVAL; |
456 | break; |
457 | } |
458 | spin_unlock_irqrestore(lock: &vmd->cfg_lock, flags); |
459 | return ret; |
460 | } |
461 | |
462 | static struct pci_ops vmd_ops = { |
463 | .read = vmd_pci_read, |
464 | .write = vmd_pci_write, |
465 | }; |
466 | |
467 | #ifdef CONFIG_ACPI |
468 | static struct acpi_device *vmd_acpi_find_companion(struct pci_dev *pci_dev) |
469 | { |
470 | struct pci_host_bridge *bridge; |
471 | u32 busnr, addr; |
472 | |
473 | if (pci_dev->bus->ops != &vmd_ops) |
474 | return NULL; |
475 | |
476 | bridge = pci_find_host_bridge(bus: pci_dev->bus); |
477 | busnr = pci_dev->bus->number - bridge->bus->number; |
478 | /* |
479 | * The address computation below is only applicable to relative bus |
480 | * numbers below 32. |
481 | */ |
482 | if (busnr > 31) |
483 | return NULL; |
484 | |
485 | addr = (busnr << 24) | ((u32)pci_dev->devfn << 16) | 0x8000FFFFU; |
486 | |
487 | dev_dbg(&pci_dev->dev, "Looking for ACPI companion (address 0x%x)\n" , |
488 | addr); |
489 | |
490 | return acpi_find_child_device(ACPI_COMPANION(bridge->dev.parent), address: addr, |
491 | check_children: false); |
492 | } |
493 | |
494 | static bool hook_installed; |
495 | |
496 | static void vmd_acpi_begin(void) |
497 | { |
498 | if (pci_acpi_set_companion_lookup_hook(func: vmd_acpi_find_companion)) |
499 | return; |
500 | |
501 | hook_installed = true; |
502 | } |
503 | |
504 | static void vmd_acpi_end(void) |
505 | { |
506 | if (!hook_installed) |
507 | return; |
508 | |
509 | pci_acpi_clear_companion_lookup_hook(); |
510 | hook_installed = false; |
511 | } |
512 | #else |
513 | static inline void vmd_acpi_begin(void) { } |
514 | static inline void vmd_acpi_end(void) { } |
515 | #endif /* CONFIG_ACPI */ |
516 | |
517 | static void vmd_domain_reset(struct vmd_dev *vmd) |
518 | { |
519 | u16 bus, max_buses = resource_size(res: &vmd->resources[0]); |
520 | u8 dev, functions, fn, hdr_type; |
521 | char __iomem *base; |
522 | |
523 | for (bus = 0; bus < max_buses; bus++) { |
524 | for (dev = 0; dev < 32; dev++) { |
525 | base = vmd->cfgbar + PCIE_ECAM_OFFSET(bus, |
526 | PCI_DEVFN(dev, 0), 0); |
527 | |
528 | hdr_type = readb(addr: base + PCI_HEADER_TYPE); |
529 | |
530 | functions = (hdr_type & PCI_HEADER_TYPE_MFD) ? 8 : 1; |
531 | for (fn = 0; fn < functions; fn++) { |
532 | base = vmd->cfgbar + PCIE_ECAM_OFFSET(bus, |
533 | PCI_DEVFN(dev, fn), 0); |
534 | |
535 | hdr_type = readb(addr: base + PCI_HEADER_TYPE) & |
536 | PCI_HEADER_TYPE_MASK; |
537 | |
538 | if (hdr_type != PCI_HEADER_TYPE_BRIDGE || |
539 | (readw(addr: base + PCI_CLASS_DEVICE) != |
540 | PCI_CLASS_BRIDGE_PCI)) |
541 | continue; |
542 | |
543 | /* |
544 | * Temporarily disable the I/O range before updating |
545 | * PCI_IO_BASE. |
546 | */ |
547 | writel(val: 0x0000ffff, addr: base + PCI_IO_BASE_UPPER16); |
548 | /* Update lower 16 bits of I/O base/limit */ |
549 | writew(val: 0x00f0, addr: base + PCI_IO_BASE); |
550 | /* Update upper 16 bits of I/O base/limit */ |
551 | writel(val: 0, addr: base + PCI_IO_BASE_UPPER16); |
552 | |
553 | /* MMIO Base/Limit */ |
554 | writel(val: 0x0000fff0, addr: base + PCI_MEMORY_BASE); |
555 | |
556 | /* Prefetchable MMIO Base/Limit */ |
557 | writel(val: 0, addr: base + PCI_PREF_LIMIT_UPPER32); |
558 | writel(val: 0x0000fff0, addr: base + PCI_PREF_MEMORY_BASE); |
559 | writel(val: 0xffffffff, addr: base + PCI_PREF_BASE_UPPER32); |
560 | } |
561 | } |
562 | } |
563 | } |
564 | |
565 | static void vmd_attach_resources(struct vmd_dev *vmd) |
566 | { |
567 | vmd->dev->resource[VMD_MEMBAR1].child = &vmd->resources[1]; |
568 | vmd->dev->resource[VMD_MEMBAR2].child = &vmd->resources[2]; |
569 | } |
570 | |
571 | static void vmd_detach_resources(struct vmd_dev *vmd) |
572 | { |
573 | vmd->dev->resource[VMD_MEMBAR1].child = NULL; |
574 | vmd->dev->resource[VMD_MEMBAR2].child = NULL; |
575 | } |
576 | |
577 | /* |
578 | * VMD domains start at 0x10000 to not clash with ACPI _SEG domains. |
579 | * Per ACPI r6.0, sec 6.5.6, _SEG returns an integer, of which the lower |
580 | * 16 bits are the PCI Segment Group (domain) number. Other bits are |
581 | * currently reserved. |
582 | */ |
583 | static int vmd_find_free_domain(void) |
584 | { |
585 | int domain = 0xffff; |
586 | struct pci_bus *bus = NULL; |
587 | |
588 | while ((bus = pci_find_next_bus(from: bus)) != NULL) |
589 | domain = max_t(int, domain, pci_domain_nr(bus)); |
590 | return domain + 1; |
591 | } |
592 | |
593 | static int vmd_get_phys_offsets(struct vmd_dev *vmd, bool native_hint, |
594 | resource_size_t *offset1, |
595 | resource_size_t *offset2) |
596 | { |
597 | struct pci_dev *dev = vmd->dev; |
598 | u64 phys1, phys2; |
599 | |
600 | if (native_hint) { |
601 | u32 vmlock; |
602 | int ret; |
603 | |
604 | ret = pci_read_config_dword(dev, PCI_REG_VMLOCK, val: &vmlock); |
605 | if (ret || PCI_POSSIBLE_ERROR(vmlock)) |
606 | return -ENODEV; |
607 | |
608 | if (MB2_SHADOW_EN(vmlock)) { |
609 | void __iomem *membar2; |
610 | |
611 | membar2 = pci_iomap(dev, VMD_MEMBAR2, max: 0); |
612 | if (!membar2) |
613 | return -ENOMEM; |
614 | phys1 = readq(addr: membar2 + MB2_SHADOW_OFFSET); |
615 | phys2 = readq(addr: membar2 + MB2_SHADOW_OFFSET + 8); |
616 | pci_iounmap(dev, membar2); |
617 | } else |
618 | return 0; |
619 | } else { |
620 | /* Hypervisor-Emulated Vendor-Specific Capability */ |
621 | int pos = pci_find_capability(dev, PCI_CAP_ID_VNDR); |
622 | u32 reg, regu; |
623 | |
624 | pci_read_config_dword(dev, where: pos + 4, val: ®); |
625 | |
626 | /* "SHDW" */ |
627 | if (pos && reg == 0x53484457) { |
628 | pci_read_config_dword(dev, where: pos + 8, val: ®); |
629 | pci_read_config_dword(dev, where: pos + 12, val: ®u); |
630 | phys1 = (u64) regu << 32 | reg; |
631 | |
632 | pci_read_config_dword(dev, where: pos + 16, val: ®); |
633 | pci_read_config_dword(dev, where: pos + 20, val: ®u); |
634 | phys2 = (u64) regu << 32 | reg; |
635 | } else |
636 | return 0; |
637 | } |
638 | |
639 | *offset1 = dev->resource[VMD_MEMBAR1].start - |
640 | (phys1 & PCI_BASE_ADDRESS_MEM_MASK); |
641 | *offset2 = dev->resource[VMD_MEMBAR2].start - |
642 | (phys2 & PCI_BASE_ADDRESS_MEM_MASK); |
643 | |
644 | return 0; |
645 | } |
646 | |
647 | static int vmd_get_bus_number_start(struct vmd_dev *vmd) |
648 | { |
649 | struct pci_dev *dev = vmd->dev; |
650 | u16 reg; |
651 | |
652 | pci_read_config_word(dev, PCI_REG_VMCAP, val: ®); |
653 | if (BUS_RESTRICT_CAP(reg)) { |
654 | pci_read_config_word(dev, PCI_REG_VMCONFIG, val: ®); |
655 | |
656 | switch (BUS_RESTRICT_CFG(reg)) { |
657 | case 0: |
658 | vmd->busn_start = 0; |
659 | break; |
660 | case 1: |
661 | vmd->busn_start = 128; |
662 | break; |
663 | case 2: |
664 | vmd->busn_start = 224; |
665 | break; |
666 | default: |
667 | pci_err(dev, "Unknown Bus Offset Setting (%d)\n" , |
668 | BUS_RESTRICT_CFG(reg)); |
669 | return -ENODEV; |
670 | } |
671 | } |
672 | |
673 | return 0; |
674 | } |
675 | |
676 | static irqreturn_t vmd_irq(int irq, void *data) |
677 | { |
678 | struct vmd_irq_list *irqs = data; |
679 | struct vmd_irq *vmdirq; |
680 | int idx; |
681 | |
682 | idx = srcu_read_lock(ssp: &irqs->srcu); |
683 | list_for_each_entry_rcu(vmdirq, &irqs->irq_list, node) |
684 | generic_handle_irq(irq: vmdirq->virq); |
685 | srcu_read_unlock(ssp: &irqs->srcu, idx); |
686 | |
687 | return IRQ_HANDLED; |
688 | } |
689 | |
690 | static int vmd_alloc_irqs(struct vmd_dev *vmd) |
691 | { |
692 | struct pci_dev *dev = vmd->dev; |
693 | int i, err; |
694 | |
695 | vmd->msix_count = pci_msix_vec_count(dev); |
696 | if (vmd->msix_count < 0) |
697 | return -ENODEV; |
698 | |
699 | vmd->msix_count = pci_alloc_irq_vectors(dev, min_vecs: vmd->first_vec + 1, |
700 | max_vecs: vmd->msix_count, PCI_IRQ_MSIX); |
701 | if (vmd->msix_count < 0) |
702 | return vmd->msix_count; |
703 | |
704 | vmd->irqs = devm_kcalloc(dev: &dev->dev, n: vmd->msix_count, size: sizeof(*vmd->irqs), |
705 | GFP_KERNEL); |
706 | if (!vmd->irqs) |
707 | return -ENOMEM; |
708 | |
709 | for (i = 0; i < vmd->msix_count; i++) { |
710 | err = init_srcu_struct(&vmd->irqs[i].srcu); |
711 | if (err) |
712 | return err; |
713 | |
714 | INIT_LIST_HEAD(list: &vmd->irqs[i].irq_list); |
715 | vmd->irqs[i].virq = pci_irq_vector(dev, nr: i); |
716 | err = devm_request_irq(dev: &dev->dev, irq: vmd->irqs[i].virq, |
717 | handler: vmd_irq, IRQF_NO_THREAD, |
718 | devname: vmd->name, dev_id: &vmd->irqs[i]); |
719 | if (err) |
720 | return err; |
721 | } |
722 | |
723 | return 0; |
724 | } |
725 | |
726 | /* |
727 | * Since VMD is an aperture to regular PCIe root ports, only allow it to |
728 | * control features that the OS is allowed to control on the physical PCI bus. |
729 | */ |
730 | static void vmd_copy_host_bridge_flags(struct pci_host_bridge *root_bridge, |
731 | struct pci_host_bridge *vmd_bridge) |
732 | { |
733 | vmd_bridge->native_pcie_hotplug = root_bridge->native_pcie_hotplug; |
734 | vmd_bridge->native_shpc_hotplug = root_bridge->native_shpc_hotplug; |
735 | vmd_bridge->native_aer = root_bridge->native_aer; |
736 | vmd_bridge->native_pme = root_bridge->native_pme; |
737 | vmd_bridge->native_ltr = root_bridge->native_ltr; |
738 | vmd_bridge->native_dpc = root_bridge->native_dpc; |
739 | } |
740 | |
741 | /* |
742 | * Enable ASPM and LTR settings on devices that aren't configured by BIOS. |
743 | */ |
744 | static int vmd_pm_enable_quirk(struct pci_dev *pdev, void *userdata) |
745 | { |
746 | unsigned long features = *(unsigned long *)userdata; |
747 | u16 ltr = VMD_BIOS_PM_QUIRK_LTR; |
748 | u32 ltr_reg; |
749 | int pos; |
750 | |
751 | if (!(features & VMD_FEAT_BIOS_PM_QUIRK)) |
752 | return 0; |
753 | |
754 | pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL); |
755 | |
756 | pos = pci_find_ext_capability(dev: pdev, PCI_EXT_CAP_ID_LTR); |
757 | if (!pos) |
758 | return 0; |
759 | |
760 | /* |
761 | * Skip if the max snoop LTR is non-zero, indicating BIOS has set it |
762 | * so the LTR quirk is not needed. |
763 | */ |
764 | pci_read_config_dword(dev: pdev, where: pos + PCI_LTR_MAX_SNOOP_LAT, val: <r_reg); |
765 | if (!!(ltr_reg & (PCI_LTR_VALUE_MASK | PCI_LTR_SCALE_MASK))) |
766 | return 0; |
767 | |
768 | /* |
769 | * Set the default values to the maximum required by the platform to |
770 | * allow the deepest power management savings. Write as a DWORD where |
771 | * the lower word is the max snoop latency and the upper word is the |
772 | * max non-snoop latency. |
773 | */ |
774 | ltr_reg = (ltr << 16) | ltr; |
775 | pci_write_config_dword(dev: pdev, where: pos + PCI_LTR_MAX_SNOOP_LAT, val: ltr_reg); |
776 | pci_info(pdev, "VMD: Default LTR value set by driver\n" ); |
777 | |
778 | return 0; |
779 | } |
780 | |
781 | static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features) |
782 | { |
783 | struct pci_sysdata *sd = &vmd->sysdata; |
784 | struct resource *res; |
785 | u32 upper_bits; |
786 | unsigned long flags; |
787 | LIST_HEAD(resources); |
788 | resource_size_t offset[2] = {0}; |
789 | resource_size_t membar2_offset = 0x2000; |
790 | struct pci_bus *child; |
791 | struct pci_dev *dev; |
792 | int ret; |
793 | |
794 | /* |
795 | * Shadow registers may exist in certain VMD device ids which allow |
796 | * guests to correctly assign host physical addresses to the root ports |
797 | * and child devices. These registers will either return the host value |
798 | * or 0, depending on an enable bit in the VMD device. |
799 | */ |
800 | if (features & VMD_FEAT_HAS_MEMBAR_SHADOW) { |
801 | membar2_offset = MB2_SHADOW_OFFSET + MB2_SHADOW_SIZE; |
802 | ret = vmd_get_phys_offsets(vmd, native_hint: true, offset1: &offset[0], offset2: &offset[1]); |
803 | if (ret) |
804 | return ret; |
805 | } else if (features & VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP) { |
806 | ret = vmd_get_phys_offsets(vmd, native_hint: false, offset1: &offset[0], offset2: &offset[1]); |
807 | if (ret) |
808 | return ret; |
809 | } |
810 | |
811 | /* |
812 | * Certain VMD devices may have a root port configuration option which |
813 | * limits the bus range to between 0-127, 128-255, or 224-255 |
814 | */ |
815 | if (features & VMD_FEAT_HAS_BUS_RESTRICTIONS) { |
816 | ret = vmd_get_bus_number_start(vmd); |
817 | if (ret) |
818 | return ret; |
819 | } |
820 | |
821 | res = &vmd->dev->resource[VMD_CFGBAR]; |
822 | vmd->resources[0] = (struct resource) { |
823 | .name = "VMD CFGBAR" , |
824 | .start = vmd->busn_start, |
825 | .end = vmd->busn_start + (resource_size(res) >> 20) - 1, |
826 | .flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED, |
827 | }; |
828 | |
829 | /* |
830 | * If the window is below 4GB, clear IORESOURCE_MEM_64 so we can |
831 | * put 32-bit resources in the window. |
832 | * |
833 | * There's no hardware reason why a 64-bit window *couldn't* |
834 | * contain a 32-bit resource, but pbus_size_mem() computes the |
835 | * bridge window size assuming a 64-bit window will contain no |
836 | * 32-bit resources. __pci_assign_resource() enforces that |
837 | * artificial restriction to make sure everything will fit. |
838 | * |
839 | * The only way we could use a 64-bit non-prefetchable MEMBAR is |
840 | * if its address is <4GB so that we can convert it to a 32-bit |
841 | * resource. To be visible to the host OS, all VMD endpoints must |
842 | * be initially configured by platform BIOS, which includes setting |
843 | * up these resources. We can assume the device is configured |
844 | * according to the platform needs. |
845 | */ |
846 | res = &vmd->dev->resource[VMD_MEMBAR1]; |
847 | upper_bits = upper_32_bits(res->end); |
848 | flags = res->flags & ~IORESOURCE_SIZEALIGN; |
849 | if (!upper_bits) |
850 | flags &= ~IORESOURCE_MEM_64; |
851 | vmd->resources[1] = (struct resource) { |
852 | .name = "VMD MEMBAR1" , |
853 | .start = res->start, |
854 | .end = res->end, |
855 | .flags = flags, |
856 | .parent = res, |
857 | }; |
858 | |
859 | res = &vmd->dev->resource[VMD_MEMBAR2]; |
860 | upper_bits = upper_32_bits(res->end); |
861 | flags = res->flags & ~IORESOURCE_SIZEALIGN; |
862 | if (!upper_bits) |
863 | flags &= ~IORESOURCE_MEM_64; |
864 | vmd->resources[2] = (struct resource) { |
865 | .name = "VMD MEMBAR2" , |
866 | .start = res->start + membar2_offset, |
867 | .end = res->end, |
868 | .flags = flags, |
869 | .parent = res, |
870 | }; |
871 | |
872 | sd->vmd_dev = vmd->dev; |
873 | sd->domain = vmd_find_free_domain(); |
874 | if (sd->domain < 0) |
875 | return sd->domain; |
876 | |
877 | sd->node = pcibus_to_node(vmd->dev->bus); |
878 | |
879 | /* |
880 | * Currently MSI remapping must be enabled in guest passthrough mode |
881 | * due to some missing interrupt remapping plumbing. This is probably |
882 | * acceptable because the guest is usually CPU-limited and MSI |
883 | * remapping doesn't become a performance bottleneck. |
884 | */ |
885 | if (!(features & VMD_FEAT_CAN_BYPASS_MSI_REMAP) || |
886 | offset[0] || offset[1]) { |
887 | ret = vmd_alloc_irqs(vmd); |
888 | if (ret) |
889 | return ret; |
890 | |
891 | vmd_set_msi_remapping(vmd, enable: true); |
892 | |
893 | ret = vmd_create_irq_domain(vmd); |
894 | if (ret) |
895 | return ret; |
896 | |
897 | /* |
898 | * Override the IRQ domain bus token so the domain can be |
899 | * distinguished from a regular PCI/MSI domain. |
900 | */ |
901 | irq_domain_update_bus_token(domain: vmd->irq_domain, bus_token: DOMAIN_BUS_VMD_MSI); |
902 | } else { |
903 | vmd_set_msi_remapping(vmd, enable: false); |
904 | } |
905 | |
906 | pci_add_resource(resources: &resources, res: &vmd->resources[0]); |
907 | pci_add_resource_offset(resources: &resources, res: &vmd->resources[1], offset: offset[0]); |
908 | pci_add_resource_offset(resources: &resources, res: &vmd->resources[2], offset: offset[1]); |
909 | |
910 | vmd->bus = pci_create_root_bus(parent: &vmd->dev->dev, bus: vmd->busn_start, |
911 | ops: &vmd_ops, sysdata: sd, resources: &resources); |
912 | if (!vmd->bus) { |
913 | pci_free_resource_list(resources: &resources); |
914 | vmd_remove_irq_domain(vmd); |
915 | return -ENODEV; |
916 | } |
917 | |
918 | vmd_copy_host_bridge_flags(root_bridge: pci_find_host_bridge(bus: vmd->dev->bus), |
919 | to_pci_host_bridge(vmd->bus->bridge)); |
920 | |
921 | vmd_attach_resources(vmd); |
922 | if (vmd->irq_domain) |
923 | dev_set_msi_domain(dev: &vmd->bus->dev, d: vmd->irq_domain); |
924 | else |
925 | dev_set_msi_domain(dev: &vmd->bus->dev, |
926 | d: dev_get_msi_domain(dev: &vmd->dev->dev)); |
927 | |
928 | vmd_acpi_begin(); |
929 | |
930 | pci_scan_child_bus(bus: vmd->bus); |
931 | vmd_domain_reset(vmd); |
932 | |
933 | /* When Intel VMD is enabled, the OS does not discover the Root Ports |
934 | * owned by Intel VMD within the MMCFG space. pci_reset_bus() applies |
935 | * a reset to the parent of the PCI device supplied as argument. This |
936 | * is why we pass a child device, so the reset can be triggered at |
937 | * the Intel bridge level and propagated to all the children in the |
938 | * hierarchy. |
939 | */ |
940 | list_for_each_entry(child, &vmd->bus->children, node) { |
941 | if (!list_empty(head: &child->devices)) { |
942 | dev = list_first_entry(&child->devices, |
943 | struct pci_dev, bus_list); |
944 | ret = pci_reset_bus(dev); |
945 | if (ret) |
946 | pci_warn(dev, "can't reset device: %d\n" , ret); |
947 | |
948 | break; |
949 | } |
950 | } |
951 | |
952 | pci_assign_unassigned_bus_resources(bus: vmd->bus); |
953 | |
954 | pci_walk_bus(top: vmd->bus, cb: vmd_pm_enable_quirk, userdata: &features); |
955 | |
956 | /* |
957 | * VMD root buses are virtual and don't return true on pci_is_pcie() |
958 | * and will fail pcie_bus_configure_settings() early. It can instead be |
959 | * run on each of the real root ports. |
960 | */ |
961 | list_for_each_entry(child, &vmd->bus->children, node) |
962 | pcie_bus_configure_settings(bus: child); |
963 | |
964 | pci_bus_add_devices(bus: vmd->bus); |
965 | |
966 | vmd_acpi_end(); |
967 | |
968 | WARN(sysfs_create_link(&vmd->dev->dev.kobj, &vmd->bus->dev.kobj, |
969 | "domain" ), "Can't create symlink to domain\n" ); |
970 | return 0; |
971 | } |
972 | |
973 | static int vmd_probe(struct pci_dev *dev, const struct pci_device_id *id) |
974 | { |
975 | unsigned long features = (unsigned long) id->driver_data; |
976 | struct vmd_dev *vmd; |
977 | int err; |
978 | |
979 | if (resource_size(res: &dev->resource[VMD_CFGBAR]) < (1 << 20)) |
980 | return -ENOMEM; |
981 | |
982 | vmd = devm_kzalloc(dev: &dev->dev, size: sizeof(*vmd), GFP_KERNEL); |
983 | if (!vmd) |
984 | return -ENOMEM; |
985 | |
986 | vmd->dev = dev; |
987 | vmd->instance = ida_alloc(ida: &vmd_instance_ida, GFP_KERNEL); |
988 | if (vmd->instance < 0) |
989 | return vmd->instance; |
990 | |
991 | vmd->name = devm_kasprintf(dev: &dev->dev, GFP_KERNEL, fmt: "vmd%d" , |
992 | vmd->instance); |
993 | if (!vmd->name) { |
994 | err = -ENOMEM; |
995 | goto out_release_instance; |
996 | } |
997 | |
998 | err = pcim_enable_device(pdev: dev); |
999 | if (err < 0) |
1000 | goto out_release_instance; |
1001 | |
1002 | vmd->cfgbar = pcim_iomap(pdev: dev, VMD_CFGBAR, maxlen: 0); |
1003 | if (!vmd->cfgbar) { |
1004 | err = -ENOMEM; |
1005 | goto out_release_instance; |
1006 | } |
1007 | |
1008 | pci_set_master(dev); |
1009 | if (dma_set_mask_and_coherent(dev: &dev->dev, DMA_BIT_MASK(64)) && |
1010 | dma_set_mask_and_coherent(dev: &dev->dev, DMA_BIT_MASK(32))) { |
1011 | err = -ENODEV; |
1012 | goto out_release_instance; |
1013 | } |
1014 | |
1015 | if (features & VMD_FEAT_OFFSET_FIRST_VECTOR) |
1016 | vmd->first_vec = 1; |
1017 | |
1018 | spin_lock_init(&vmd->cfg_lock); |
1019 | pci_set_drvdata(pdev: dev, data: vmd); |
1020 | err = vmd_enable_domain(vmd, features); |
1021 | if (err) |
1022 | goto out_release_instance; |
1023 | |
1024 | dev_info(&vmd->dev->dev, "Bound to PCI domain %04x\n" , |
1025 | vmd->sysdata.domain); |
1026 | return 0; |
1027 | |
1028 | out_release_instance: |
1029 | ida_free(&vmd_instance_ida, id: vmd->instance); |
1030 | return err; |
1031 | } |
1032 | |
1033 | static void vmd_cleanup_srcu(struct vmd_dev *vmd) |
1034 | { |
1035 | int i; |
1036 | |
1037 | for (i = 0; i < vmd->msix_count; i++) |
1038 | cleanup_srcu_struct(ssp: &vmd->irqs[i].srcu); |
1039 | } |
1040 | |
1041 | static void vmd_remove(struct pci_dev *dev) |
1042 | { |
1043 | struct vmd_dev *vmd = pci_get_drvdata(pdev: dev); |
1044 | |
1045 | sysfs_remove_link(kobj: &vmd->dev->dev.kobj, name: "domain" ); |
1046 | pci_stop_root_bus(bus: vmd->bus); |
1047 | pci_remove_root_bus(bus: vmd->bus); |
1048 | vmd_cleanup_srcu(vmd); |
1049 | vmd_detach_resources(vmd); |
1050 | vmd_remove_irq_domain(vmd); |
1051 | ida_free(&vmd_instance_ida, id: vmd->instance); |
1052 | } |
1053 | |
1054 | static void vmd_shutdown(struct pci_dev *dev) |
1055 | { |
1056 | struct vmd_dev *vmd = pci_get_drvdata(pdev: dev); |
1057 | |
1058 | vmd_remove_irq_domain(vmd); |
1059 | } |
1060 | |
1061 | #ifdef CONFIG_PM_SLEEP |
1062 | static int vmd_suspend(struct device *dev) |
1063 | { |
1064 | struct pci_dev *pdev = to_pci_dev(dev); |
1065 | struct vmd_dev *vmd = pci_get_drvdata(pdev); |
1066 | int i; |
1067 | |
1068 | for (i = 0; i < vmd->msix_count; i++) |
1069 | devm_free_irq(dev, irq: vmd->irqs[i].virq, dev_id: &vmd->irqs[i]); |
1070 | |
1071 | return 0; |
1072 | } |
1073 | |
1074 | static int vmd_resume(struct device *dev) |
1075 | { |
1076 | struct pci_dev *pdev = to_pci_dev(dev); |
1077 | struct vmd_dev *vmd = pci_get_drvdata(pdev); |
1078 | int err, i; |
1079 | |
1080 | vmd_set_msi_remapping(vmd, enable: !!vmd->irq_domain); |
1081 | |
1082 | for (i = 0; i < vmd->msix_count; i++) { |
1083 | err = devm_request_irq(dev, irq: vmd->irqs[i].virq, |
1084 | handler: vmd_irq, IRQF_NO_THREAD, |
1085 | devname: vmd->name, dev_id: &vmd->irqs[i]); |
1086 | if (err) |
1087 | return err; |
1088 | } |
1089 | |
1090 | return 0; |
1091 | } |
1092 | #endif |
1093 | static SIMPLE_DEV_PM_OPS(vmd_dev_pm_ops, vmd_suspend, vmd_resume); |
1094 | |
1095 | static const struct pci_device_id vmd_ids[] = { |
1096 | {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_201D), |
1097 | .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP,}, |
1098 | {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_28C0), |
1099 | .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW | |
1100 | VMD_FEAT_HAS_BUS_RESTRICTIONS | |
1101 | VMD_FEAT_CAN_BYPASS_MSI_REMAP,}, |
1102 | {PCI_VDEVICE(INTEL, 0x467f), |
1103 | .driver_data = VMD_FEATS_CLIENT,}, |
1104 | {PCI_VDEVICE(INTEL, 0x4c3d), |
1105 | .driver_data = VMD_FEATS_CLIENT,}, |
1106 | {PCI_VDEVICE(INTEL, 0xa77f), |
1107 | .driver_data = VMD_FEATS_CLIENT,}, |
1108 | {PCI_VDEVICE(INTEL, 0x7d0b), |
1109 | .driver_data = VMD_FEATS_CLIENT,}, |
1110 | {PCI_VDEVICE(INTEL, 0xad0b), |
1111 | .driver_data = VMD_FEATS_CLIENT,}, |
1112 | {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_9A0B), |
1113 | .driver_data = VMD_FEATS_CLIENT,}, |
1114 | {0,} |
1115 | }; |
1116 | MODULE_DEVICE_TABLE(pci, vmd_ids); |
1117 | |
1118 | static struct pci_driver vmd_drv = { |
1119 | .name = "vmd" , |
1120 | .id_table = vmd_ids, |
1121 | .probe = vmd_probe, |
1122 | .remove = vmd_remove, |
1123 | .shutdown = vmd_shutdown, |
1124 | .driver = { |
1125 | .pm = &vmd_dev_pm_ops, |
1126 | }, |
1127 | }; |
1128 | module_pci_driver(vmd_drv); |
1129 | |
1130 | MODULE_AUTHOR("Intel Corporation" ); |
1131 | MODULE_LICENSE("GPL v2" ); |
1132 | MODULE_VERSION("0.6" ); |
1133 | |