1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Intel eMMC PHY driver |
4 | * Copyright (C) 2019 Intel, Corp. |
5 | */ |
6 | |
7 | #include <linux/bits.h> |
8 | #include <linux/clk.h> |
9 | #include <linux/delay.h> |
10 | #include <linux/mfd/syscon.h> |
11 | #include <linux/module.h> |
12 | #include <linux/of.h> |
13 | #include <linux/of_address.h> |
14 | #include <linux/phy/phy.h> |
15 | #include <linux/platform_device.h> |
16 | #include <linux/regmap.h> |
17 | |
18 | /* eMMC phy register definitions */ |
19 | #define EMMC_PHYCTRL0_REG 0xa8 |
20 | #define DR_TY_MASK GENMASK(30, 28) |
21 | #define DR_TY_SHIFT(x) (((x) << 28) & DR_TY_MASK) |
22 | #define OTAPDLYENA BIT(14) |
23 | #define OTAPDLYSEL_MASK GENMASK(13, 10) |
24 | #define OTAPDLYSEL_SHIFT(x) (((x) << 10) & OTAPDLYSEL_MASK) |
25 | |
26 | #define EMMC_PHYCTRL1_REG 0xac |
27 | #define PDB_MASK BIT(0) |
28 | #define PDB_SHIFT(x) (((x) << 0) & PDB_MASK) |
29 | #define ENDLL_MASK BIT(7) |
30 | #define ENDLL_SHIFT(x) (((x) << 7) & ENDLL_MASK) |
31 | |
32 | #define EMMC_PHYCTRL2_REG 0xb0 |
33 | #define FRQSEL_25M 0 |
34 | #define FRQSEL_50M 1 |
35 | #define FRQSEL_100M 2 |
36 | #define FRQSEL_150M 3 |
37 | #define FRQSEL_MASK GENMASK(24, 22) |
38 | #define FRQSEL_SHIFT(x) (((x) << 22) & FRQSEL_MASK) |
39 | |
40 | #define EMMC_PHYSTAT_REG 0xbc |
41 | #define CALDONE_MASK BIT(9) |
42 | #define DLLRDY_MASK BIT(8) |
43 | #define IS_CALDONE(x) ((x) & CALDONE_MASK) |
44 | #define IS_DLLRDY(x) ((x) & DLLRDY_MASK) |
45 | |
46 | struct intel_emmc_phy { |
47 | struct regmap *syscfg; |
48 | struct clk *emmcclk; |
49 | }; |
50 | |
51 | static int intel_emmc_phy_power(struct phy *phy, bool on_off) |
52 | { |
53 | struct intel_emmc_phy *priv = phy_get_drvdata(phy); |
54 | unsigned int caldone; |
55 | unsigned int dllrdy; |
56 | unsigned int freqsel; |
57 | unsigned long rate; |
58 | int ret, quot; |
59 | |
60 | /* |
61 | * Keep phyctrl_pdb and phyctrl_endll low to allow |
62 | * initialization of CALIO state M/C DFFs |
63 | */ |
64 | ret = regmap_update_bits(map: priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK, |
65 | PDB_SHIFT(0)); |
66 | if (ret) { |
67 | dev_err(&phy->dev, "CALIO power down bar failed: %d\n" , ret); |
68 | return ret; |
69 | } |
70 | |
71 | /* Already finish power_off above */ |
72 | if (!on_off) |
73 | return 0; |
74 | |
75 | rate = clk_get_rate(clk: priv->emmcclk); |
76 | quot = DIV_ROUND_CLOSEST(rate, 50000000); |
77 | if (quot > FRQSEL_150M) |
78 | dev_warn(&phy->dev, "Unsupported rate: %lu\n" , rate); |
79 | freqsel = clamp_t(int, quot, FRQSEL_25M, FRQSEL_150M); |
80 | |
81 | /* |
82 | * According to the user manual, calpad calibration |
83 | * cycle takes more than 2us without the minimal recommended |
84 | * value, so we may need a little margin here |
85 | */ |
86 | udelay(5); |
87 | |
88 | ret = regmap_update_bits(map: priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK, |
89 | PDB_SHIFT(1)); |
90 | if (ret) { |
91 | dev_err(&phy->dev, "CALIO power down bar failed: %d\n" , ret); |
92 | return ret; |
93 | } |
94 | |
95 | /* |
96 | * According to the user manual, it asks driver to wait 5us for |
97 | * calpad busy trimming. However it is documented that this value is |
98 | * PVT(A.K.A process,voltage and temperature) relevant, so some |
99 | * failure cases are found which indicates we should be more tolerant |
100 | * to calpad busy trimming. |
101 | */ |
102 | ret = regmap_read_poll_timeout(priv->syscfg, EMMC_PHYSTAT_REG, |
103 | caldone, IS_CALDONE(caldone), |
104 | 0, 50); |
105 | if (ret) { |
106 | dev_err(&phy->dev, "caldone failed, ret=%d\n" , ret); |
107 | return ret; |
108 | } |
109 | |
110 | /* Set the frequency of the DLL operation */ |
111 | ret = regmap_update_bits(map: priv->syscfg, EMMC_PHYCTRL2_REG, FRQSEL_MASK, |
112 | FRQSEL_SHIFT(freqsel)); |
113 | if (ret) { |
114 | dev_err(&phy->dev, "set the frequency of dll failed:%d\n" , ret); |
115 | return ret; |
116 | } |
117 | |
118 | /* Turn on the DLL */ |
119 | ret = regmap_update_bits(map: priv->syscfg, EMMC_PHYCTRL1_REG, ENDLL_MASK, |
120 | ENDLL_SHIFT(1)); |
121 | if (ret) { |
122 | dev_err(&phy->dev, "turn on the dll failed: %d\n" , ret); |
123 | return ret; |
124 | } |
125 | |
126 | /* |
127 | * After enabling analog DLL circuits docs say that we need 10.2 us if |
128 | * our source clock is at 50 MHz and that lock time scales linearly |
129 | * with clock speed. If we are powering on the PHY and the card clock |
130 | * is super slow (like 100 kHZ) this could take as long as 5.1 ms as |
131 | * per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms |
132 | * Hopefully we won't be running at 100 kHz, but we should still make |
133 | * sure we wait long enough. |
134 | * |
135 | * NOTE: There appear to be corner cases where the DLL seems to take |
136 | * extra long to lock for reasons that aren't understood. In some |
137 | * extreme cases we've seen it take up to over 10ms (!). We'll be |
138 | * generous and give it 50ms. |
139 | */ |
140 | ret = regmap_read_poll_timeout(priv->syscfg, |
141 | EMMC_PHYSTAT_REG, |
142 | dllrdy, IS_DLLRDY(dllrdy), |
143 | 0, 50 * USEC_PER_MSEC); |
144 | if (ret) { |
145 | dev_err(&phy->dev, "dllrdy failed. ret=%d\n" , ret); |
146 | return ret; |
147 | } |
148 | |
149 | return 0; |
150 | } |
151 | |
152 | static int intel_emmc_phy_init(struct phy *phy) |
153 | { |
154 | struct intel_emmc_phy *priv = phy_get_drvdata(phy); |
155 | |
156 | /* |
157 | * We purposely get the clock here and not in probe to avoid the |
158 | * circular dependency problem. We expect: |
159 | * - PHY driver to probe |
160 | * - SDHCI driver to start probe |
161 | * - SDHCI driver to register it's clock |
162 | * - SDHCI driver to get the PHY |
163 | * - SDHCI driver to init the PHY |
164 | * |
165 | * The clock is optional, so upon any error just return it like |
166 | * any other error to user. |
167 | * |
168 | */ |
169 | priv->emmcclk = clk_get_optional(dev: &phy->dev, id: "emmcclk" ); |
170 | if (IS_ERR(ptr: priv->emmcclk)) { |
171 | dev_err(&phy->dev, "ERROR: getting emmcclk\n" ); |
172 | return PTR_ERR(ptr: priv->emmcclk); |
173 | } |
174 | |
175 | return 0; |
176 | } |
177 | |
178 | static int intel_emmc_phy_exit(struct phy *phy) |
179 | { |
180 | struct intel_emmc_phy *priv = phy_get_drvdata(phy); |
181 | |
182 | clk_put(clk: priv->emmcclk); |
183 | |
184 | return 0; |
185 | } |
186 | |
187 | static int intel_emmc_phy_power_on(struct phy *phy) |
188 | { |
189 | struct intel_emmc_phy *priv = phy_get_drvdata(phy); |
190 | int ret; |
191 | |
192 | /* Drive impedance: 50 Ohm */ |
193 | ret = regmap_update_bits(map: priv->syscfg, EMMC_PHYCTRL0_REG, DR_TY_MASK, |
194 | DR_TY_SHIFT(6)); |
195 | if (ret) { |
196 | dev_err(&phy->dev, "ERROR set drive-impednce-50ohm: %d\n" , ret); |
197 | return ret; |
198 | } |
199 | |
200 | /* Output tap delay: disable */ |
201 | ret = regmap_update_bits(map: priv->syscfg, EMMC_PHYCTRL0_REG, OTAPDLYENA, |
202 | val: 0); |
203 | if (ret) { |
204 | dev_err(&phy->dev, "ERROR Set output tap delay : %d\n" , ret); |
205 | return ret; |
206 | } |
207 | |
208 | /* Output tap delay */ |
209 | ret = regmap_update_bits(map: priv->syscfg, EMMC_PHYCTRL0_REG, |
210 | OTAPDLYSEL_MASK, OTAPDLYSEL_SHIFT(4)); |
211 | if (ret) { |
212 | dev_err(&phy->dev, "ERROR: output tap dly select: %d\n" , ret); |
213 | return ret; |
214 | } |
215 | |
216 | /* Power up eMMC phy analog blocks */ |
217 | return intel_emmc_phy_power(phy, on_off: true); |
218 | } |
219 | |
220 | static int intel_emmc_phy_power_off(struct phy *phy) |
221 | { |
222 | /* Power down eMMC phy analog blocks */ |
223 | return intel_emmc_phy_power(phy, on_off: false); |
224 | } |
225 | |
226 | static const struct phy_ops ops = { |
227 | .init = intel_emmc_phy_init, |
228 | .exit = intel_emmc_phy_exit, |
229 | .power_on = intel_emmc_phy_power_on, |
230 | .power_off = intel_emmc_phy_power_off, |
231 | .owner = THIS_MODULE, |
232 | }; |
233 | |
234 | static int intel_emmc_phy_probe(struct platform_device *pdev) |
235 | { |
236 | struct device *dev = &pdev->dev; |
237 | struct device_node *np = dev->of_node; |
238 | struct intel_emmc_phy *priv; |
239 | struct phy *generic_phy; |
240 | struct phy_provider *phy_provider; |
241 | |
242 | priv = devm_kzalloc(dev, size: sizeof(*priv), GFP_KERNEL); |
243 | if (!priv) |
244 | return -ENOMEM; |
245 | |
246 | /* Get eMMC phy (accessed via chiptop) regmap */ |
247 | priv->syscfg = syscon_regmap_lookup_by_phandle(np, property: "intel,syscon" ); |
248 | if (IS_ERR(ptr: priv->syscfg)) { |
249 | dev_err(dev, "failed to find syscon\n" ); |
250 | return PTR_ERR(ptr: priv->syscfg); |
251 | } |
252 | |
253 | generic_phy = devm_phy_create(dev, node: np, ops: &ops); |
254 | if (IS_ERR(ptr: generic_phy)) { |
255 | dev_err(dev, "failed to create PHY\n" ); |
256 | return PTR_ERR(ptr: generic_phy); |
257 | } |
258 | |
259 | phy_set_drvdata(phy: generic_phy, data: priv); |
260 | phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
261 | |
262 | return PTR_ERR_OR_ZERO(ptr: phy_provider); |
263 | } |
264 | |
265 | static const struct of_device_id intel_emmc_phy_dt_ids[] = { |
266 | { .compatible = "intel,lgm-emmc-phy" }, |
267 | {} |
268 | }; |
269 | |
270 | MODULE_DEVICE_TABLE(of, intel_emmc_phy_dt_ids); |
271 | |
272 | static struct platform_driver intel_emmc_driver = { |
273 | .probe = intel_emmc_phy_probe, |
274 | .driver = { |
275 | .name = "intel-emmc-phy" , |
276 | .of_match_table = intel_emmc_phy_dt_ids, |
277 | }, |
278 | }; |
279 | |
280 | module_platform_driver(intel_emmc_driver); |
281 | |
282 | MODULE_AUTHOR("Peter Harliman Liem <peter.harliman.liem@intel.com>" ); |
283 | MODULE_DESCRIPTION("Intel eMMC PHY driver" ); |
284 | MODULE_LICENSE("GPL v2" ); |
285 | |