| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef QCOM_PHY_QMP_PCS_PCIE_V4_H_ |
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| 7 | #define QCOM_PHY_QMP_PCS_PCIE_V4_H_ |
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| 8 | |
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| 9 | /* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */ |
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| 10 | #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_STATUS 0x00 |
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| 11 | #define QPHY_V4_PCS_PCIE_OSC_DTCT_STATUS 0x04 |
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| 12 | #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG1 0x08 |
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| 13 | #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c |
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| 14 | #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG3 0x10 |
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| 15 | #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 |
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| 16 | #define QPHY_V4_PCS_PCIE_PCS_TX_RX_CONFIG 0x18 |
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| 17 | #define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c |
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| 18 | #define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_CNTRL 0x20 |
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| 19 | #define QPHY_V4_PCS_PCIE_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK 0x24 |
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| 20 | #define QPHY_V4_PCS_PCIE_EPCLK_DLY_COUNT_VAL_L 0x28 |
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| 21 | #define QPHY_V4_PCS_PCIE_EPCLK_DLY_COUNT_VAL_H 0x2c |
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| 22 | #define QPHY_V4_PCS_PCIE_RX_IDLE_DTCT_CNTRL1 0x30 |
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| 23 | #define QPHY_V4_PCS_PCIE_RX_IDLE_DTCT_CNTRL2 0x34 |
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| 24 | #define QPHY_V4_PCS_PCIE_SIGDET_CNTRL 0x38 |
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| 25 | #define QPHY_V4_PCS_PCIE_SIGDET_LOW_2_IDLE_TIME 0x3c |
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| 26 | #define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 |
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| 27 | #define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x44 |
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| 28 | #define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 |
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| 29 | #define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x4c |
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| 30 | #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 |
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| 31 | #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG2 0x54 |
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| 32 | #define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG1 0x58 |
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| 33 | #define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2 0x5c |
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| 34 | #define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG3 0x60 |
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| 35 | #define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG4 0x64 |
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| 36 | #define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG5 0x68 |
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| 37 | #define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG6 0x6c |
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| 38 | #define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG7 0x70 |
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| 39 | #define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG1 0x74 |
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| 40 | #define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x78 |
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| 41 | #define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG3 0x7c |
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| 42 | #define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x80 |
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| 43 | #define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x84 |
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| 44 | #define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x88 |
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| 45 | #define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG7 0x8c |
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| 46 | #define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 |
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| 47 | #define QPHY_V4_PCS_PCIE_LOCAL_FS 0x94 |
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| 48 | #define QPHY_V4_PCS_PCIE_LOCAL_LF 0x98 |
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| 49 | #define QPHY_V4_PCS_PCIE_LOCAL_FS_RS 0x9c |
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| 50 | #define QPHY_V4_PCS_PCIE_EQ_CONFIG1 0xa0 |
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| 51 | #define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 |
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| 52 | #define QPHY_V4_PCS_PCIE_PRESET_P0_P1_PRE 0xa8 |
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| 53 | #define QPHY_V4_PCS_PCIE_PRESET_P2_P3_PRE 0xac |
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| 54 | #define QPHY_V4_PCS_PCIE_PRESET_P4_P5_PRE 0xb0 |
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| 55 | #define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 |
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| 56 | #define QPHY_V4_PCS_PCIE_PRESET_P8_P9_PRE 0xb8 |
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| 57 | #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc |
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| 58 | #define QPHY_V4_PCS_PCIE_PRESET_P1_P3_PRE_RS 0xc0 |
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| 59 | #define QPHY_V4_PCS_PCIE_PRESET_P4_P5_PRE_RS 0xc4 |
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| 60 | #define QPHY_V4_PCS_PCIE_PRESET_P6_P9_PRE_RS 0xc8 |
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| 61 | #define QPHY_V4_PCS_PCIE_PRESET_P0_P1_POST 0xcc |
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| 62 | #define QPHY_V4_PCS_PCIE_PRESET_P2_P3_POST 0xd0 |
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| 63 | #define QPHY_V4_PCS_PCIE_PRESET_P4_P5_POST 0xd4 |
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| 64 | #define QPHY_V4_PCS_PCIE_PRESET_P6_P7_POST 0xd8 |
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| 65 | #define QPHY_V4_PCS_PCIE_PRESET_P8_P9_POST 0xdc |
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| 66 | #define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 |
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| 67 | #define QPHY_V4_PCS_PCIE_PRESET_P1_P3_POST_RS 0xe4 |
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| 68 | #define QPHY_V4_PCS_PCIE_PRESET_P4_P5_POST_RS 0xe8 |
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| 69 | #define QPHY_V4_PCS_PCIE_PRESET_P6_P9_POST_RS 0xec |
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| 70 | #define QPHY_V4_PCS_PCIE_RXEQEVAL_TIME 0xf0 |
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| 71 | |
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| 72 | #endif |
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| 73 | |
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