1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
4 | */ |
5 | |
6 | #include <linux/clk.h> |
7 | #include <linux/clk-provider.h> |
8 | #include <linux/delay.h> |
9 | #include <linux/err.h> |
10 | #include <linux/io.h> |
11 | #include <linux/iopoll.h> |
12 | #include <linux/kernel.h> |
13 | #include <linux/mfd/syscon.h> |
14 | #include <linux/module.h> |
15 | #include <linux/of.h> |
16 | #include <linux/of_address.h> |
17 | #include <linux/phy/pcie.h> |
18 | #include <linux/phy/phy.h> |
19 | #include <linux/platform_device.h> |
20 | #include <linux/regmap.h> |
21 | #include <linux/regulator/consumer.h> |
22 | #include <linux/reset.h> |
23 | #include <linux/slab.h> |
24 | |
25 | #include "phy-qcom-qmp-common.h" |
26 | |
27 | #include "phy-qcom-qmp.h" |
28 | #include "phy-qcom-qmp-pcs-misc-v3.h" |
29 | #include "phy-qcom-qmp-pcs-pcie-v4.h" |
30 | #include "phy-qcom-qmp-pcs-pcie-v4_20.h" |
31 | #include "phy-qcom-qmp-pcs-pcie-v5.h" |
32 | #include "phy-qcom-qmp-pcs-pcie-v5_20.h" |
33 | #include "phy-qcom-qmp-pcs-pcie-v6.h" |
34 | #include "phy-qcom-qmp-pcs-pcie-v6_20.h" |
35 | #include "phy-qcom-qmp-pcie-qhp.h" |
36 | |
37 | #define PHY_INIT_COMPLETE_TIMEOUT 10000 |
38 | |
39 | /* set of registers with offsets different per-PHY */ |
40 | enum qphy_reg_layout { |
41 | /* PCS registers */ |
42 | QPHY_SW_RESET, |
43 | QPHY_START_CTRL, |
44 | QPHY_PCS_STATUS, |
45 | QPHY_PCS_POWER_DOWN_CONTROL, |
46 | /* Keep last to ensure regs_layout arrays are properly initialized */ |
47 | QPHY_LAYOUT_SIZE |
48 | }; |
49 | |
50 | static const unsigned int pciephy_v2_regs_layout[QPHY_LAYOUT_SIZE] = { |
51 | [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET, |
52 | [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL, |
53 | [QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS, |
54 | [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL, |
55 | }; |
56 | |
57 | static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = { |
58 | [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, |
59 | [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, |
60 | [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, |
61 | [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, |
62 | }; |
63 | |
64 | static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { |
65 | [QPHY_SW_RESET] = 0x00, |
66 | [QPHY_START_CTRL] = 0x08, |
67 | [QPHY_PCS_STATUS] = 0x2ac, |
68 | [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, |
69 | }; |
70 | |
71 | static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = { |
72 | [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, |
73 | [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, |
74 | [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, |
75 | [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, |
76 | }; |
77 | |
78 | static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { |
79 | [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, |
80 | [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, |
81 | [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, |
82 | [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, |
83 | }; |
84 | |
85 | static const unsigned int pciephy_v6_regs_layout[QPHY_LAYOUT_SIZE] = { |
86 | [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET, |
87 | [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL, |
88 | [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1, |
89 | [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL, |
90 | }; |
91 | |
92 | static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { |
93 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), |
94 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), |
95 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), |
96 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), |
97 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), |
98 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), |
99 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), |
100 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), |
101 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), |
102 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), |
103 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), |
104 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), |
105 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), |
106 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), |
107 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), |
108 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), |
109 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), |
110 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), |
111 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), |
112 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), |
113 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), |
114 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), |
115 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), |
116 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), |
117 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), |
118 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), |
119 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), |
120 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), |
121 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), |
122 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), |
123 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), |
124 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), |
125 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), |
126 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), |
127 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), |
128 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), |
129 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), |
130 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), |
131 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), |
132 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), |
133 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), |
134 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), |
135 | }; |
136 | |
137 | static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { |
138 | QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), |
139 | QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), |
140 | QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), |
141 | QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), |
142 | }; |
143 | |
144 | static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { |
145 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), |
146 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), |
147 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), |
148 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), |
149 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), |
150 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), |
151 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), |
152 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), |
153 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), |
154 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), |
155 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), |
156 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), |
157 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), |
158 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), |
159 | }; |
160 | |
161 | static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { |
162 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), |
163 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), |
164 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), |
165 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), |
166 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), |
167 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), |
168 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), |
169 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), |
170 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), |
171 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), |
172 | }; |
173 | |
174 | static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { |
175 | QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), |
176 | QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), |
177 | QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), |
178 | QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), |
179 | QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), |
180 | QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), |
181 | QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), |
182 | QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), |
183 | QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), |
184 | QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), |
185 | QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), |
186 | QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), |
187 | QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), |
188 | QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), |
189 | QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), |
190 | QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), |
191 | QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), |
192 | QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), |
193 | QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), |
194 | QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), |
195 | QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), |
196 | QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), |
197 | QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), |
198 | QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), |
199 | QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), |
200 | QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), |
201 | QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), |
202 | QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), |
203 | QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), |
204 | QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), |
205 | QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), |
206 | QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), |
207 | QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), |
208 | QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), |
209 | QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), |
210 | QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), |
211 | QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), |
212 | QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), |
213 | QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), |
214 | QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), |
215 | QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), |
216 | QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), |
217 | QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), |
218 | QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), |
219 | QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), |
220 | QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), |
221 | }; |
222 | |
223 | static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { |
224 | QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), |
225 | QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), |
226 | QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), |
227 | }; |
228 | |
229 | static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { |
230 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), |
231 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), |
232 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), |
233 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), |
234 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), |
235 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), |
236 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), |
237 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), |
238 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), |
239 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), |
240 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), |
241 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), |
242 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), |
243 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), |
244 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), |
245 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01), |
246 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), |
247 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), |
248 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), |
249 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), |
250 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), |
251 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), |
252 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), |
253 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), |
254 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), |
255 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), |
256 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), |
257 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), |
258 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), |
259 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), |
260 | }; |
261 | |
262 | static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { |
263 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), |
264 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), |
265 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), |
266 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), |
267 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
268 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), |
269 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), |
270 | }; |
271 | |
272 | static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = { |
273 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), |
274 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), |
275 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), |
276 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
277 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
278 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), |
279 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), |
280 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), |
281 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), |
282 | }; |
283 | |
284 | static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { |
285 | QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), |
286 | QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), |
287 | QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), |
288 | QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), |
289 | QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), |
290 | QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), |
291 | QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), |
292 | QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), |
293 | QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), |
294 | QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), |
295 | QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), |
296 | QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), |
297 | QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), |
298 | QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), |
299 | QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), |
300 | QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), |
301 | QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), |
302 | QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), |
303 | QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), |
304 | QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), |
305 | QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), |
306 | QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), |
307 | QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), |
308 | QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), |
309 | QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), |
310 | QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), |
311 | QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), |
312 | QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), |
313 | QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), |
314 | QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), |
315 | QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), |
316 | QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), |
317 | QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), |
318 | QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), |
319 | QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), |
320 | QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), |
321 | QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), |
322 | QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), |
323 | QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), |
324 | QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), |
325 | }; |
326 | |
327 | static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { |
328 | QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), |
329 | QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), |
330 | QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), |
331 | QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), |
332 | QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36), |
333 | QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), |
334 | }; |
335 | |
336 | static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { |
337 | QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), |
338 | QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), |
339 | QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), |
340 | QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), |
341 | QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), |
342 | QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), |
343 | QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), |
344 | }; |
345 | |
346 | static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { |
347 | QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4), |
348 | QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0), |
349 | QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), |
350 | QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), |
351 | QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), |
352 | QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), |
353 | QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), |
354 | QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), |
355 | QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), |
356 | QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), |
357 | QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), |
358 | }; |
359 | |
360 | static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = { |
361 | QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), |
362 | QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), |
363 | QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), |
364 | QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), |
365 | QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), |
366 | QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), |
367 | QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), |
368 | QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), |
369 | QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), |
370 | QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), |
371 | QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), |
372 | QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), |
373 | QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), |
374 | QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), |
375 | QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), |
376 | QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82), |
377 | QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03), |
378 | QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355), |
379 | QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555), |
380 | QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a), |
381 | QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a), |
382 | QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb), |
383 | QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), |
384 | QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), |
385 | QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0), |
386 | QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40), |
387 | QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), |
388 | QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), |
389 | QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), |
390 | QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), |
391 | QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa), |
392 | QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), |
393 | QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), |
394 | QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), |
395 | QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), |
396 | QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa), |
397 | QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1), |
398 | QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68), |
399 | QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2), |
400 | QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa), |
401 | QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab), |
402 | QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), |
403 | QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34), |
404 | QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414), |
405 | QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b), |
406 | QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), |
407 | QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), |
408 | QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0), |
409 | QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40), |
410 | QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), |
411 | QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), |
412 | QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), |
413 | QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0), |
414 | QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), |
415 | QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), |
416 | QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), |
417 | QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), |
418 | }; |
419 | |
420 | static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = { |
421 | QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), |
422 | QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), |
423 | QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10), |
424 | QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), |
425 | }; |
426 | |
427 | static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = { |
428 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), |
429 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), |
430 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), |
431 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe), |
432 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4), |
433 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), |
434 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), |
435 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), |
436 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), |
437 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), |
438 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), |
439 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), |
440 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), |
441 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), |
442 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), |
443 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), |
444 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), |
445 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), |
446 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), |
447 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), |
448 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), |
449 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), |
450 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2), |
451 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), |
452 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), |
453 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), |
454 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), |
455 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), |
456 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), |
457 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), |
458 | }; |
459 | |
460 | static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { |
461 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83), |
462 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9), |
463 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42), |
464 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40), |
465 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), |
466 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), |
467 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), |
468 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), |
469 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), |
470 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), |
471 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), |
472 | }; |
473 | |
474 | static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = { |
475 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), |
476 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), |
477 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
478 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), |
479 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
480 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), |
481 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb), |
482 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), |
483 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), |
484 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), |
485 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), |
486 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), |
487 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), |
488 | }; |
489 | |
490 | static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { |
491 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), |
492 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), |
493 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), |
494 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), |
495 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), |
496 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), |
497 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), |
498 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), |
499 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), |
500 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), |
501 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), |
502 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), |
503 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), |
504 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), |
505 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), |
506 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), |
507 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), |
508 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), |
509 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), |
510 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), |
511 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), |
512 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), |
513 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), |
514 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), |
515 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), |
516 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), |
517 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), |
518 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), |
519 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), |
520 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), |
521 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), |
522 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), |
523 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), |
524 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), |
525 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), |
526 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), |
527 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), |
528 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), |
529 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), |
530 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), |
531 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), |
532 | QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), |
533 | }; |
534 | |
535 | static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { |
536 | QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), |
537 | QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), |
538 | QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), |
539 | QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), |
540 | }; |
541 | |
542 | static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { |
543 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), |
544 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), |
545 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), |
546 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), |
547 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), |
548 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), |
549 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), |
550 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), |
551 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), |
552 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), |
553 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), |
554 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), |
555 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), |
556 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), |
557 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), |
558 | QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), |
559 | }; |
560 | |
561 | static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { |
562 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), |
563 | |
564 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), |
565 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), |
566 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), |
567 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), |
568 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), |
569 | |
570 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), |
571 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), |
572 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), |
573 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), |
574 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), |
575 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), |
576 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), |
577 | |
578 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), |
579 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), |
580 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), |
581 | |
582 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), |
583 | }; |
584 | |
585 | static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { |
586 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), |
587 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), |
588 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), |
589 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), |
590 | QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), |
591 | }; |
592 | |
593 | static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { |
594 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), |
595 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), |
596 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), |
597 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), |
598 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), |
599 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), |
600 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), |
601 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), |
602 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), |
603 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), |
604 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), |
605 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), |
606 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), |
607 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), |
608 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), |
609 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), |
610 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), |
611 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), |
612 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), |
613 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), |
614 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), |
615 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), |
616 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), |
617 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), |
618 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), |
619 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), |
620 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), |
621 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), |
622 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), |
623 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), |
624 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), |
625 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), |
626 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), |
627 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), |
628 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), |
629 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), |
630 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), |
631 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), |
632 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), |
633 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), |
634 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), |
635 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), |
636 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), |
637 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), |
638 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), |
639 | }; |
640 | |
641 | static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { |
642 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), |
643 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), |
644 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), |
645 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), |
646 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), |
647 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), |
648 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), |
649 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), |
650 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), |
651 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), |
652 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), |
653 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), |
654 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), |
655 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), |
656 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), |
657 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), |
658 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), |
659 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), |
660 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), |
661 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), |
662 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), |
663 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), |
664 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), |
665 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), |
666 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), |
667 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), |
668 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), |
669 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), |
670 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), |
671 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), |
672 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), |
673 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), |
674 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), |
675 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), |
676 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), |
677 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), |
678 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), |
679 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), |
680 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), |
681 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), |
682 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), |
683 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), |
684 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), |
685 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), |
686 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), |
687 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), |
688 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), |
689 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), |
690 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), |
691 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), |
692 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), |
693 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), |
694 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), |
695 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), |
696 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), |
697 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), |
698 | }; |
699 | |
700 | static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { |
701 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), |
702 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), |
703 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), |
704 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), |
705 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), |
706 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), |
707 | QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), |
708 | }; |
709 | |
710 | static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { |
711 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), |
712 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), |
713 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), |
714 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), |
715 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), |
716 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), |
717 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), |
718 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), |
719 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), |
720 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), |
721 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), |
722 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), |
723 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), |
724 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), |
725 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), |
726 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), |
727 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), |
728 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), |
729 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), |
730 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), |
731 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), |
732 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), |
733 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), |
734 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), |
735 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), |
736 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), |
737 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), |
738 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), |
739 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), |
740 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), |
741 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), |
742 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), |
743 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), |
744 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), |
745 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), |
746 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), |
747 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), |
748 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), |
749 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), |
750 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), |
751 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), |
752 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), |
753 | }; |
754 | |
755 | static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { |
756 | QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), |
757 | QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), |
758 | }; |
759 | |
760 | static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { |
761 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), |
762 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), |
763 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), |
764 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), |
765 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), |
766 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), |
767 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), |
768 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), |
769 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), |
770 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), |
771 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), |
772 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), |
773 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), |
774 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), |
775 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), |
776 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), |
777 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), |
778 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), |
779 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), |
780 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), |
781 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), |
782 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), |
783 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), |
784 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), |
785 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), |
786 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), |
787 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), |
788 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), |
789 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), |
790 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), |
791 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), |
792 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), |
793 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), |
794 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), |
795 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), |
796 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), |
797 | }; |
798 | |
799 | static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { |
800 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
801 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), |
802 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), |
803 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), |
804 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), |
805 | }; |
806 | |
807 | static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { |
808 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), |
809 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
810 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
811 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), |
812 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), |
813 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), |
814 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), |
815 | }; |
816 | |
817 | static const struct qmp_phy_init_tbl sc8280xp_qmp_pcie_serdes_tbl[] = { |
818 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), |
819 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), |
820 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), |
821 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), |
822 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), |
823 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), |
824 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), |
825 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), |
826 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), |
827 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), |
828 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), |
829 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), |
830 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), |
831 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), |
832 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), |
833 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), |
834 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), |
835 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), |
836 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), |
837 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), |
838 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), |
839 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), |
840 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), |
841 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), |
842 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), |
843 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), |
844 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), |
845 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), |
846 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), |
847 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), |
848 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), |
849 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), |
850 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), |
851 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), |
852 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), |
853 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), |
854 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb9), |
855 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), |
856 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x94), |
857 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), |
858 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), |
859 | }; |
860 | |
861 | static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl[] = { |
862 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), |
863 | }; |
864 | |
865 | static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl[] = { |
866 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), |
867 | }; |
868 | |
869 | static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl[] = { |
870 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), |
871 | }; |
872 | |
873 | static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_tx_tbl[] = { |
874 | QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), |
875 | QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), |
876 | QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), |
877 | QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), |
878 | QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), |
879 | }; |
880 | |
881 | static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rx_tbl[] = { |
882 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), |
883 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), |
884 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), |
885 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), |
886 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), |
887 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), |
888 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), |
889 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), |
890 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), |
891 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), |
892 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), |
893 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), |
894 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), |
895 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), |
896 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), |
897 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), |
898 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), |
899 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), |
900 | }; |
901 | |
902 | static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_tbl[] = { |
903 | QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), |
904 | QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), |
905 | QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), |
906 | }; |
907 | |
908 | static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl[] = { |
909 | QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), |
910 | QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), |
911 | QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), |
912 | QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), |
913 | }; |
914 | |
915 | static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_tx_tbl[] = { |
916 | QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1), |
917 | QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2), |
918 | QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5), |
919 | QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), |
920 | QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), |
921 | QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), |
922 | }; |
923 | |
924 | static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rx_tbl[] = { |
925 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), |
926 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), |
927 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), |
928 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34), |
929 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), |
930 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), |
931 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), |
932 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), |
933 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), |
934 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), |
935 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), |
936 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), |
937 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), |
938 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), |
939 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), |
940 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), |
941 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), |
942 | }; |
943 | |
944 | static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_tbl[] = { |
945 | QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), |
946 | QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x88), |
947 | QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), |
948 | QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x0f), |
949 | }; |
950 | |
951 | static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl[] = { |
952 | QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), |
953 | QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), |
954 | QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), |
955 | QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), |
956 | }; |
957 | |
958 | static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_serdes_tbl[] = { |
959 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26), |
960 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), |
961 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), |
962 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), |
963 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), |
964 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), |
965 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), |
966 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), |
967 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), |
968 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), |
969 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), |
970 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), |
971 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12), |
972 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), |
973 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), |
974 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), |
975 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), |
976 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), |
977 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), |
978 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), |
979 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), |
980 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), |
981 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), |
982 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), |
983 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), |
984 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), |
985 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), |
986 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), |
987 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), |
988 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), |
989 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40), |
990 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14), |
991 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), |
992 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), |
993 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), |
994 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), |
995 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46), |
996 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), |
997 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), |
998 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), |
999 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), |
1000 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06), |
1001 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88), |
1002 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), |
1003 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f), |
1004 | }; |
1005 | |
1006 | static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl[] = { |
1007 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), |
1008 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88), |
1009 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x00), |
1010 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x1f), |
1011 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0xd4), |
1012 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), |
1013 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), |
1014 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a), |
1015 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x32), |
1016 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6), |
1017 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64), |
1018 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), |
1019 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), |
1020 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), |
1021 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), |
1022 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), |
1023 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), |
1024 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), |
1025 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), |
1026 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), |
1027 | }; |
1028 | |
1029 | static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_tx_tbl[] = { |
1030 | QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), |
1031 | QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03), |
1032 | QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01), |
1033 | QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x10), |
1034 | QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51), |
1035 | QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34), |
1036 | }; |
1037 | |
1038 | static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_rx_tbl[] = { |
1039 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c), |
1040 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04), |
1041 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), |
1042 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), |
1043 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), |
1044 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), |
1045 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x00), |
1046 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_BKUP_CTRL1, 0x15), |
1047 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_1, 0x01), |
1048 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_2, 0x01), |
1049 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45), |
1050 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0b), |
1051 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), |
1052 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), |
1053 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), |
1054 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), |
1055 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), |
1056 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39), |
1057 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14), |
1058 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3), |
1059 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58), |
1060 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), |
1061 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26), |
1062 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), |
1063 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), |
1064 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xe4), |
1065 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xa4), |
1066 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60), |
1067 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), |
1068 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x4b), |
1069 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), |
1070 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), |
1071 | }; |
1072 | |
1073 | static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_tbl[] = { |
1074 | QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e), |
1075 | QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc), |
1076 | QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00), |
1077 | QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22), |
1078 | }; |
1079 | |
1080 | static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl[] = { |
1081 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), |
1082 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00), |
1083 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16), |
1084 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02), |
1085 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e), |
1086 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03), |
1087 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28), |
1088 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0), |
1089 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d), |
1090 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f), |
1091 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2), |
1092 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2), |
1093 | }; |
1094 | |
1095 | static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { |
1096 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), |
1097 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), |
1098 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), |
1099 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), |
1100 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), |
1101 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), |
1102 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), |
1103 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), |
1104 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), |
1105 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), |
1106 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), |
1107 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), |
1108 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), |
1109 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), |
1110 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), |
1111 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), |
1112 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), |
1113 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), |
1114 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), |
1115 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), |
1116 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), |
1117 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), |
1118 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), |
1119 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), |
1120 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), |
1121 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), |
1122 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), |
1123 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), |
1124 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), |
1125 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), |
1126 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), |
1127 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), |
1128 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), |
1129 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), |
1130 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), |
1131 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), |
1132 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), |
1133 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), |
1134 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), |
1135 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), |
1136 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), |
1137 | }; |
1138 | |
1139 | static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { |
1140 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), |
1141 | }; |
1142 | |
1143 | static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { |
1144 | QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), |
1145 | QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), |
1146 | QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), |
1147 | }; |
1148 | |
1149 | static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { |
1150 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), |
1151 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), |
1152 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), |
1153 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), |
1154 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), |
1155 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), |
1156 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), |
1157 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), |
1158 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), |
1159 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), |
1160 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), |
1161 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), |
1162 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), |
1163 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), |
1164 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), |
1165 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), |
1166 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), |
1167 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), |
1168 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), |
1169 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), |
1170 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), |
1171 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), |
1172 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), |
1173 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), |
1174 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), |
1175 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), |
1176 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), |
1177 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), |
1178 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), |
1179 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), |
1180 | }; |
1181 | |
1182 | static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { |
1183 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), |
1184 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), |
1185 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), |
1186 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), |
1187 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), |
1188 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), |
1189 | }; |
1190 | |
1191 | static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { |
1192 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
1193 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), |
1194 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), |
1195 | }; |
1196 | |
1197 | static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { |
1198 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), |
1199 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), |
1200 | }; |
1201 | |
1202 | static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { |
1203 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), |
1204 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
1205 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
1206 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), |
1207 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), |
1208 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), |
1209 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), |
1210 | }; |
1211 | |
1212 | static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { |
1213 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), |
1214 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), |
1215 | }; |
1216 | |
1217 | static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { |
1218 | QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), |
1219 | }; |
1220 | |
1221 | static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { |
1222 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), |
1223 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), |
1224 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), |
1225 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), |
1226 | }; |
1227 | |
1228 | static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { |
1229 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), |
1230 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), |
1231 | }; |
1232 | |
1233 | static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { |
1234 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), |
1235 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), |
1236 | }; |
1237 | |
1238 | static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { |
1239 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), |
1240 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), |
1241 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), |
1242 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), |
1243 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), |
1244 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), |
1245 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), |
1246 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), |
1247 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), |
1248 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), |
1249 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), |
1250 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), |
1251 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), |
1252 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), |
1253 | }; |
1254 | |
1255 | static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_serdes_tbl[] = { |
1256 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), |
1257 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), |
1258 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), |
1259 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xce), |
1260 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x0b), |
1261 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x97), |
1262 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x0c), |
1263 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), |
1264 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE0, 0x0a), |
1265 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE1, 0x10), |
1266 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), |
1267 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), |
1268 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), |
1269 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), |
1270 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), |
1271 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), |
1272 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), |
1273 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x04), |
1274 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0d), |
1275 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x0a), |
1276 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1a), |
1277 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0xc3), |
1278 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0xd0), |
1279 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x05), |
1280 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55), |
1281 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55), |
1282 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05), |
1283 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), |
1284 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), |
1285 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), |
1286 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xd8), |
1287 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x20), |
1288 | }; |
1289 | |
1290 | static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = { |
1291 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), |
1292 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), |
1293 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), |
1294 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), |
1295 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), |
1296 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), |
1297 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), |
1298 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), |
1299 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), |
1300 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), |
1301 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), |
1302 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), |
1303 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), |
1304 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), |
1305 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), |
1306 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), |
1307 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), |
1308 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), |
1309 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), |
1310 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), |
1311 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), |
1312 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), |
1313 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), |
1314 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), |
1315 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), |
1316 | }; |
1317 | |
1318 | static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { |
1319 | QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), |
1320 | QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), |
1321 | QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), |
1322 | QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), |
1323 | QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), |
1324 | }; |
1325 | |
1326 | static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { |
1327 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), |
1328 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), |
1329 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), |
1330 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), |
1331 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), |
1332 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), |
1333 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), |
1334 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), |
1335 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), |
1336 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), |
1337 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), |
1338 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), |
1339 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), |
1340 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), |
1341 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), |
1342 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), |
1343 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), |
1344 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), |
1345 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), |
1346 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), |
1347 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), |
1348 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), |
1349 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), |
1350 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), |
1351 | QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), |
1352 | }; |
1353 | |
1354 | static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { |
1355 | QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), |
1356 | QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), |
1357 | QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), |
1358 | QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), |
1359 | }; |
1360 | |
1361 | static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { |
1362 | QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), |
1363 | QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), |
1364 | QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), |
1365 | QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), |
1366 | QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), |
1367 | }; |
1368 | |
1369 | static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_pcs_misc_tbl[] = { |
1370 | QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), |
1371 | QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), |
1372 | }; |
1373 | |
1374 | static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] = { |
1375 | QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), |
1376 | QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), |
1377 | }; |
1378 | |
1379 | static const struct qmp_phy_init_tbl sdx65_qmp_pcie_serdes_tbl[] = { |
1380 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), |
1381 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), |
1382 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), |
1383 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), |
1384 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), |
1385 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), |
1386 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), |
1387 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), |
1388 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), |
1389 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), |
1390 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), |
1391 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), |
1392 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), |
1393 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), |
1394 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), |
1395 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), |
1396 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), |
1397 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), |
1398 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), |
1399 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), |
1400 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), |
1401 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), |
1402 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), |
1403 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), |
1404 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), |
1405 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), |
1406 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), |
1407 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), |
1408 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), |
1409 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), |
1410 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), |
1411 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), |
1412 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE_CONTD, 0x00), |
1413 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), |
1414 | }; |
1415 | |
1416 | static const struct qmp_phy_init_tbl sdx65_qmp_pcie_tx_tbl[] = { |
1417 | QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), |
1418 | QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), |
1419 | QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x00), |
1420 | QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_VMODE_CTRL1, 0x00), |
1421 | QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_PI_QEC_CTRL, 0x00), |
1422 | QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), |
1423 | QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), |
1424 | QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RCV_DETECT_LVL_2, 0x12), |
1425 | }; |
1426 | |
1427 | static const struct qmp_phy_init_tbl sdx65_qmp_pcie_rx_tbl[] = { |
1428 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), |
1429 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_1, 0x06), |
1430 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_2, 0x06), |
1431 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH1, 0x3e), |
1432 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH2, 0x1e), |
1433 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), |
1434 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), |
1435 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH1, 0x02), |
1436 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH2, 0x1d), |
1437 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x44), |
1438 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL2, 0x00), |
1439 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), |
1440 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), |
1441 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x74), |
1442 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), |
1443 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_ENABLES, 0x1c), |
1444 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_CNTRL, 0x03), |
1445 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_DEGLITCH_CNTRL, 0x14), |
1446 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x04), |
1447 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), |
1448 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), |
1449 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), |
1450 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x64), |
1451 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), |
1452 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), |
1453 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), |
1454 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DCC_CTRL1, 0x0c), |
1455 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), |
1456 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), |
1457 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), |
1458 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), |
1459 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), |
1460 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), |
1461 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), |
1462 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), |
1463 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), |
1464 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), |
1465 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), |
1466 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), |
1467 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), |
1468 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), |
1469 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), |
1470 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), |
1471 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE2, 0x00), |
1472 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), |
1473 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), |
1474 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), |
1475 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), |
1476 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xac), |
1477 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), |
1478 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), |
1479 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x07), |
1480 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), |
1481 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d), |
1482 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc5), |
1483 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xee), |
1484 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), |
1485 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), |
1486 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), |
1487 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), |
1488 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), |
1489 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_EN_TIMER, 0x28), |
1490 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), |
1491 | }; |
1492 | |
1493 | static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_tbl[] = { |
1494 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), |
1495 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0xaa), |
1496 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG2, 0x0d), |
1497 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), |
1498 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), |
1499 | }; |
1500 | |
1501 | static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_misc_tbl[] = { |
1502 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), |
1503 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), |
1504 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), |
1505 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2, 0x0d), |
1506 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), |
1507 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), |
1508 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), |
1509 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), |
1510 | }; |
1511 | |
1512 | static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = { |
1513 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), |
1514 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), |
1515 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), |
1516 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), |
1517 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), |
1518 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), |
1519 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), |
1520 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), |
1521 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), |
1522 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), |
1523 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), |
1524 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), |
1525 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), |
1526 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), |
1527 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), |
1528 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), |
1529 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), |
1530 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), |
1531 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), |
1532 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), |
1533 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), |
1534 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), |
1535 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), |
1536 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), |
1537 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), |
1538 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), |
1539 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), |
1540 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), |
1541 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), |
1542 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), |
1543 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), |
1544 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), |
1545 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), |
1546 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), |
1547 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), |
1548 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), |
1549 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), |
1550 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), |
1551 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), |
1552 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), |
1553 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), |
1554 | }; |
1555 | |
1556 | static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_serdes_tbl[] = { |
1557 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), |
1558 | }; |
1559 | |
1560 | static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { |
1561 | QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), |
1562 | QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), |
1563 | QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), |
1564 | QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), |
1565 | QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), |
1566 | }; |
1567 | |
1568 | static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_rx_tbl[] = { |
1569 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), |
1570 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), |
1571 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), |
1572 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), |
1573 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), |
1574 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), |
1575 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), |
1576 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), |
1577 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), |
1578 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), |
1579 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), |
1580 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), |
1581 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), |
1582 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), |
1583 | }; |
1584 | |
1585 | static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_rx_tbl[] = { |
1586 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), |
1587 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), |
1588 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), |
1589 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), |
1590 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), |
1591 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), |
1592 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), |
1593 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), |
1594 | }; |
1595 | |
1596 | static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_pcs_tbl[] = { |
1597 | QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), |
1598 | QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), |
1599 | QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), |
1600 | }; |
1601 | |
1602 | static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { |
1603 | QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), |
1604 | QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), |
1605 | QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), |
1606 | QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), |
1607 | }; |
1608 | |
1609 | static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_tx_tbl[] = { |
1610 | QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), |
1611 | QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), |
1612 | QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), |
1613 | QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), |
1614 | QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), |
1615 | }; |
1616 | |
1617 | static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_rx_tbl[] = { |
1618 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), |
1619 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), |
1620 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), |
1621 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), |
1622 | }; |
1623 | |
1624 | static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = { |
1625 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), |
1626 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34), |
1627 | QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), |
1628 | }; |
1629 | |
1630 | static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_tx_tbl[] = { |
1631 | QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1), |
1632 | QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2), |
1633 | QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5), |
1634 | QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), |
1635 | QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), |
1636 | QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), |
1637 | }; |
1638 | |
1639 | static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_pcs_tbl[] = { |
1640 | QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x0f), |
1641 | }; |
1642 | |
1643 | static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { |
1644 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), |
1645 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), |
1646 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), |
1647 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), |
1648 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), |
1649 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), |
1650 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), |
1651 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), |
1652 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), |
1653 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), |
1654 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), |
1655 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), |
1656 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), |
1657 | }; |
1658 | |
1659 | static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_serdes_tbl[] = { |
1660 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), |
1661 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), |
1662 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), |
1663 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), |
1664 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), |
1665 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), |
1666 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), |
1667 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), |
1668 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), |
1669 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), |
1670 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), |
1671 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), |
1672 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), |
1673 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), |
1674 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), |
1675 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), |
1676 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), |
1677 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), |
1678 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), |
1679 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), |
1680 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), |
1681 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), |
1682 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), |
1683 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), |
1684 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), |
1685 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), |
1686 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), |
1687 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), |
1688 | }; |
1689 | |
1690 | static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { |
1691 | QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), |
1692 | QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), |
1693 | QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), |
1694 | QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), |
1695 | }; |
1696 | |
1697 | static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { |
1698 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), |
1699 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), |
1700 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), |
1701 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), |
1702 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), |
1703 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), |
1704 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), |
1705 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), |
1706 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), |
1707 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), |
1708 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), |
1709 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), |
1710 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), |
1711 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), |
1712 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), |
1713 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), |
1714 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), |
1715 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), |
1716 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), |
1717 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), |
1718 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), |
1719 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), |
1720 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), |
1721 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), |
1722 | |
1723 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), |
1724 | |
1725 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), |
1726 | |
1727 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), |
1728 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), |
1729 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), |
1730 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), |
1731 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), |
1732 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), |
1733 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), |
1734 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), |
1735 | |
1736 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), |
1737 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), |
1738 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), |
1739 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), |
1740 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), |
1741 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), |
1742 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), |
1743 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), |
1744 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), |
1745 | }; |
1746 | |
1747 | static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { |
1748 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), |
1749 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), |
1750 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), |
1751 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x99), |
1752 | }; |
1753 | |
1754 | static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { |
1755 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), |
1756 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), |
1757 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), |
1758 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), |
1759 | }; |
1760 | |
1761 | static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl[] = { |
1762 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), |
1763 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), |
1764 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_PRESET_P10_POST, 0x00), |
1765 | }; |
1766 | |
1767 | static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_serdes_tbl[] = { |
1768 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), |
1769 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), |
1770 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), |
1771 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), |
1772 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), |
1773 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), |
1774 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), |
1775 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), |
1776 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), |
1777 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), |
1778 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), |
1779 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), |
1780 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), |
1781 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), |
1782 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), |
1783 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), |
1784 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), |
1785 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), |
1786 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), |
1787 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), |
1788 | }; |
1789 | |
1790 | static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = { |
1791 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), |
1792 | }; |
1793 | |
1794 | static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_serdes_tbl[] = { |
1795 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), |
1796 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), |
1797 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), |
1798 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), |
1799 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), |
1800 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x93), |
1801 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), |
1802 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), |
1803 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), |
1804 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), |
1805 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), |
1806 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), |
1807 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), |
1808 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), |
1809 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), |
1810 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), |
1811 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), |
1812 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), |
1813 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42), |
1814 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), |
1815 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), |
1816 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), |
1817 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), |
1818 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), |
1819 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x34), |
1820 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), |
1821 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), |
1822 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), |
1823 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), |
1824 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55), |
1825 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01), |
1826 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), |
1827 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), |
1828 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), |
1829 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), |
1830 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), |
1831 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f), |
1832 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), |
1833 | }; |
1834 | |
1835 | static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_tx_tbl[] = { |
1836 | QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x15), |
1837 | QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), |
1838 | QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x02), |
1839 | QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x06), |
1840 | QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x18), |
1841 | }; |
1842 | |
1843 | static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_rx_tbl[] = { |
1844 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), |
1845 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x11), |
1846 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf), |
1847 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf), |
1848 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7), |
1849 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea), |
1850 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f), |
1851 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), |
1852 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), |
1853 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a), |
1854 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89), |
1855 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), |
1856 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94), |
1857 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b), |
1858 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a), |
1859 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89), |
1860 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0x00), |
1861 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09), |
1862 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05), |
1863 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), |
1864 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), |
1865 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), |
1866 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x1c), |
1867 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), |
1868 | QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), |
1869 | }; |
1870 | |
1871 | static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_tbl[] = { |
1872 | QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x05), |
1873 | QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x77), |
1874 | QMP_PHY_INIT_CFG(QPHY_V6_PCS_RATE_SLEW_CNTRL1, 0x0b), |
1875 | QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG2, 0x0f), |
1876 | QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x8c), |
1877 | }; |
1878 | |
1879 | static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_misc_tbl[] = { |
1880 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1e), |
1881 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME, 0x27), |
1882 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), |
1883 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), |
1884 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), |
1885 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), |
1886 | }; |
1887 | |
1888 | static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_serdes_tbl[] = { |
1889 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26), |
1890 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), |
1891 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), |
1892 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), |
1893 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), |
1894 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), |
1895 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), |
1896 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), |
1897 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), |
1898 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), |
1899 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), |
1900 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), |
1901 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12), |
1902 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), |
1903 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), |
1904 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), |
1905 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), |
1906 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), |
1907 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), |
1908 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), |
1909 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), |
1910 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), |
1911 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), |
1912 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), |
1913 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), |
1914 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), |
1915 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), |
1916 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), |
1917 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), |
1918 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), |
1919 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40), |
1920 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14), |
1921 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), |
1922 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), |
1923 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), |
1924 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), |
1925 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46), |
1926 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), |
1927 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), |
1928 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), |
1929 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), |
1930 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06), |
1931 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88), |
1932 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), |
1933 | QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f), |
1934 | }; |
1935 | |
1936 | static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = { |
1937 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), |
1938 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00), |
1939 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02), |
1940 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d), |
1941 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12), |
1942 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), |
1943 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), |
1944 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a), |
1945 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38), |
1946 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6), |
1947 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64), |
1948 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), |
1949 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), |
1950 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), |
1951 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), |
1952 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), |
1953 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), |
1954 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), |
1955 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), |
1956 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), |
1957 | QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b), |
1958 | }; |
1959 | |
1960 | static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = { |
1961 | QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), |
1962 | QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03), |
1963 | QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01), |
1964 | QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x00), |
1965 | QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51), |
1966 | QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34), |
1967 | }; |
1968 | |
1969 | static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = { |
1970 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c), |
1971 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), |
1972 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04), |
1973 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), |
1974 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), |
1975 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), |
1976 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c), |
1977 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05), |
1978 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10), |
1979 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a), |
1980 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), |
1981 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), |
1982 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), |
1983 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), |
1984 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), |
1985 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), |
1986 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14), |
1987 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3), |
1988 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58), |
1989 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), |
1990 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26), |
1991 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), |
1992 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), |
1993 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xdb), |
1994 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xdb), |
1995 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0xa0), |
1996 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), |
1997 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78), |
1998 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), |
1999 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), |
2000 | QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00), |
2001 | }; |
2002 | |
2003 | static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = { |
2004 | QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB, 0x17), |
2005 | QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e), |
2006 | QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc), |
2007 | QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00), |
2008 | QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22), |
2009 | QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04), |
2010 | QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02), |
2011 | }; |
2012 | |
2013 | static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_misc_tbl[] = { |
2014 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), |
2015 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00), |
2016 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16), |
2017 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27), |
2018 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27), |
2019 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02), |
2020 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e), |
2021 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03), |
2022 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28), |
2023 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0), |
2024 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d), |
2025 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f), |
2026 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2), |
2027 | QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2), |
2028 | }; |
2029 | |
2030 | static const struct qmp_phy_init_tbl sm8650_qmp_gen4x2_pcie_rx_tbl[] = { |
2031 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a), |
2032 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), |
2033 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), |
2034 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), |
2035 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x82), |
2036 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05), |
2037 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a), |
2038 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), |
2039 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), |
2040 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), |
2041 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), |
2042 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), |
2043 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0xd3), |
2044 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xd3), |
2045 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x00), |
2046 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), |
2047 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x06), |
2048 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), |
2049 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), |
2050 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0x23), |
2051 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0x9b), |
2052 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60), |
2053 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), |
2054 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x43), |
2055 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), |
2056 | QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), |
2057 | }; |
2058 | |
2059 | static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl[] = { |
2060 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), |
2061 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), |
2062 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), |
2063 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), |
2064 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), |
2065 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), |
2066 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), |
2067 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), |
2068 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), |
2069 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), |
2070 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), |
2071 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), |
2072 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), |
2073 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), |
2074 | }; |
2075 | |
2076 | static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl[] = { |
2077 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), |
2078 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), |
2079 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), |
2080 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), |
2081 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), |
2082 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), |
2083 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), |
2084 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), |
2085 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), |
2086 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), |
2087 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), |
2088 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), |
2089 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), |
2090 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), |
2091 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), |
2092 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), |
2093 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), |
2094 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), |
2095 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), |
2096 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), |
2097 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), |
2098 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), |
2099 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), |
2100 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), |
2101 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), |
2102 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), |
2103 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), |
2104 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), |
2105 | }; |
2106 | |
2107 | static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rx_alt_tbl[] = { |
2108 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), |
2109 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), |
2110 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9a), |
2111 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0), |
2112 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x92), |
2113 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0), |
2114 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42), |
2115 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x99), |
2116 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), |
2117 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9a), |
2118 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xfb), |
2119 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0x92), |
2120 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xec), |
2121 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43), |
2122 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd), |
2123 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d), |
2124 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3), |
2125 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf8), |
2126 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xec), |
2127 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd6), |
2128 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83), |
2129 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf5), |
2130 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x5e), |
2131 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), |
2132 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), |
2133 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), |
2134 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00), |
2135 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), |
2136 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), |
2137 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), |
2138 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), |
2139 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), |
2140 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), |
2141 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), |
2142 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), |
2143 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), |
2144 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), |
2145 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), |
2146 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08), |
2147 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04), |
2148 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04), |
2149 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08), |
2150 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), |
2151 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c), |
2152 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), |
2153 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), |
2154 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05), |
2155 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), |
2156 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), |
2157 | }; |
2158 | |
2159 | static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_tx_tbl[] = { |
2160 | QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), |
2161 | QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x07), |
2162 | QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), |
2163 | QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), |
2164 | QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x0f), |
2165 | }; |
2166 | |
2167 | static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_pcs_misc_tbl[] = { |
2168 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), |
2169 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), |
2170 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), |
2171 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), |
2172 | }; |
2173 | |
2174 | static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl[] = { |
2175 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), |
2176 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), |
2177 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), |
2178 | }; |
2179 | |
2180 | static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl[] = { |
2181 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), |
2182 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), |
2183 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), |
2184 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), |
2185 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), |
2186 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66), |
2187 | }; |
2188 | |
2189 | static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rx_alt_tbl[] = { |
2190 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), |
2191 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), |
2192 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00), |
2193 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), |
2194 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), |
2195 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05), |
2196 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), |
2197 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), |
2198 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c), |
2199 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), |
2200 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), |
2201 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), |
2202 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), |
2203 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), |
2204 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), |
2205 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), |
2206 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), |
2207 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), |
2208 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), |
2209 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), |
2210 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x99), |
2211 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0), |
2212 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x92), |
2213 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0), |
2214 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42), |
2215 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00), |
2216 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20), |
2217 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9a), |
2218 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xb6), |
2219 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0x92), |
2220 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xf0), |
2221 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43), |
2222 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd), |
2223 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d), |
2224 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3), |
2225 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf6), |
2226 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xee), |
2227 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd2), |
2228 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83), |
2229 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf9), |
2230 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x3d), |
2231 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), |
2232 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), |
2233 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), |
2234 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08), |
2235 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04), |
2236 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), |
2237 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04), |
2238 | QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08), |
2239 | }; |
2240 | |
2241 | static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl[] = { |
2242 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), |
2243 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), |
2244 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), |
2245 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66), |
2246 | }; |
2247 | |
2248 | static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl[] = { |
2249 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), |
2250 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), |
2251 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), |
2252 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), |
2253 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), |
2254 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), |
2255 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), |
2256 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), |
2257 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), |
2258 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), |
2259 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), |
2260 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), |
2261 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), |
2262 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), |
2263 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), |
2264 | }; |
2265 | |
2266 | |
2267 | static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl[] = { |
2268 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), |
2269 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), |
2270 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), |
2271 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), |
2272 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), |
2273 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), |
2274 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), |
2275 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), |
2276 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), |
2277 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), |
2278 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), |
2279 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), |
2280 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), |
2281 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), |
2282 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), |
2283 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), |
2284 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), |
2285 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), |
2286 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), |
2287 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), |
2288 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), |
2289 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), |
2290 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), |
2291 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), |
2292 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), |
2293 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), |
2294 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), |
2295 | }; |
2296 | |
2297 | static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl[] = { |
2298 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), |
2299 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), |
2300 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), |
2301 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), |
2302 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), |
2303 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), |
2304 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), |
2305 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), |
2306 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), |
2307 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), |
2308 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), |
2309 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), |
2310 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), |
2311 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), |
2312 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), |
2313 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), |
2314 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), |
2315 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), |
2316 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), |
2317 | QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), |
2318 | }; |
2319 | |
2320 | static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl[] = { |
2321 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_MX_CTRL7, 0x00), |
2322 | QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_SW_CTRL7, 0x00), |
2323 | }; |
2324 | |
2325 | struct qmp_pcie_offsets { |
2326 | u16 serdes; |
2327 | u16 pcs; |
2328 | u16 pcs_misc; |
2329 | u16 tx; |
2330 | u16 rx; |
2331 | u16 tx2; |
2332 | u16 rx2; |
2333 | u16 ln_shrd; |
2334 | }; |
2335 | |
2336 | struct qmp_phy_cfg_tbls { |
2337 | const struct qmp_phy_init_tbl *serdes; |
2338 | int serdes_num; |
2339 | const struct qmp_phy_init_tbl *tx; |
2340 | int tx_num; |
2341 | const struct qmp_phy_init_tbl *rx; |
2342 | int rx_num; |
2343 | const struct qmp_phy_init_tbl *pcs; |
2344 | int pcs_num; |
2345 | const struct qmp_phy_init_tbl *pcs_misc; |
2346 | int pcs_misc_num; |
2347 | const struct qmp_phy_init_tbl *ln_shrd; |
2348 | int ln_shrd_num; |
2349 | }; |
2350 | |
2351 | /* struct qmp_phy_cfg - per-PHY initialization config */ |
2352 | struct qmp_phy_cfg { |
2353 | int lanes; |
2354 | |
2355 | const struct qmp_pcie_offsets *offsets; |
2356 | |
2357 | /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ |
2358 | const struct qmp_phy_cfg_tbls tbls; |
2359 | /* |
2360 | * Additional init sequences for PHY blocks, providing additional |
2361 | * register programming. They are used for providing separate sequences |
2362 | * for the Root Complex and End Point use cases. |
2363 | * |
2364 | * If EP mode is not supported, both tables can be left unset. |
2365 | */ |
2366 | const struct qmp_phy_cfg_tbls *tbls_rc; |
2367 | const struct qmp_phy_cfg_tbls *tbls_ep; |
2368 | |
2369 | const struct qmp_phy_init_tbl *serdes_4ln_tbl; |
2370 | int serdes_4ln_num; |
2371 | |
2372 | /* resets to be requested */ |
2373 | const char * const *reset_list; |
2374 | int num_resets; |
2375 | /* regulators to be requested */ |
2376 | const char * const *vreg_list; |
2377 | int num_vregs; |
2378 | |
2379 | /* array of registers with different offsets */ |
2380 | const unsigned int *regs; |
2381 | |
2382 | unsigned int pwrdn_ctrl; |
2383 | /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ |
2384 | unsigned int phy_status; |
2385 | |
2386 | bool skip_start_delay; |
2387 | |
2388 | bool has_nocsr_reset; |
2389 | |
2390 | /* QMP PHY pipe clock interface rate */ |
2391 | unsigned long pipe_clock_rate; |
2392 | }; |
2393 | |
2394 | struct qmp_pcie { |
2395 | struct device *dev; |
2396 | |
2397 | const struct qmp_phy_cfg *cfg; |
2398 | bool tcsr_4ln_config; |
2399 | |
2400 | void __iomem *serdes; |
2401 | void __iomem *pcs; |
2402 | void __iomem *pcs_misc; |
2403 | void __iomem *tx; |
2404 | void __iomem *rx; |
2405 | void __iomem *tx2; |
2406 | void __iomem *rx2; |
2407 | void __iomem *ln_shrd; |
2408 | |
2409 | void __iomem *port_b; |
2410 | |
2411 | struct clk_bulk_data *clks; |
2412 | struct clk_bulk_data pipe_clks[2]; |
2413 | int num_pipe_clks; |
2414 | |
2415 | struct reset_control_bulk_data *resets; |
2416 | struct reset_control *nocsr_reset; |
2417 | struct regulator_bulk_data *vregs; |
2418 | |
2419 | struct phy *phy; |
2420 | int mode; |
2421 | |
2422 | struct clk_fixed_rate pipe_clk_fixed; |
2423 | }; |
2424 | |
2425 | static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) |
2426 | { |
2427 | u32 reg; |
2428 | |
2429 | reg = readl(addr: base + offset); |
2430 | reg |= val; |
2431 | writel(val: reg, addr: base + offset); |
2432 | |
2433 | /* ensure that above write is through */ |
2434 | readl(addr: base + offset); |
2435 | } |
2436 | |
2437 | static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) |
2438 | { |
2439 | u32 reg; |
2440 | |
2441 | reg = readl(addr: base + offset); |
2442 | reg &= ~val; |
2443 | writel(val: reg, addr: base + offset); |
2444 | |
2445 | /* ensure that above write is through */ |
2446 | readl(addr: base + offset); |
2447 | } |
2448 | |
2449 | /* list of clocks required by phy */ |
2450 | static const char * const qmp_pciephy_clk_l[] = { |
2451 | "aux" , "cfg_ahb" , "ref" , "refgen" , "rchng" , "phy_aux" , |
2452 | }; |
2453 | |
2454 | /* list of regulators */ |
2455 | static const char * const qmp_phy_vreg_l[] = { |
2456 | "vdda-phy" , "vdda-pll" , |
2457 | }; |
2458 | |
2459 | static const char * const sm8550_qmp_phy_vreg_l[] = { |
2460 | "vdda-phy" , "vdda-pll" , "vdda-qref" , |
2461 | }; |
2462 | |
2463 | /* list of resets */ |
2464 | static const char * const ipq8074_pciephy_reset_l[] = { |
2465 | "phy" , "common" , |
2466 | }; |
2467 | |
2468 | static const char * const sdm845_pciephy_reset_l[] = { |
2469 | "phy" , |
2470 | }; |
2471 | |
2472 | static const struct qmp_pcie_offsets qmp_pcie_offsets_qhp = { |
2473 | .serdes = 0, |
2474 | .pcs = 0x1800, |
2475 | .tx = 0x0800, |
2476 | /* no .rx for QHP */ |
2477 | }; |
2478 | |
2479 | static const struct qmp_pcie_offsets qmp_pcie_offsets_v2 = { |
2480 | .serdes = 0, |
2481 | .pcs = 0x0800, |
2482 | .tx = 0x0200, |
2483 | .rx = 0x0400, |
2484 | }; |
2485 | |
2486 | static const struct qmp_pcie_offsets qmp_pcie_offsets_v3 = { |
2487 | .serdes = 0, |
2488 | .pcs = 0x0800, |
2489 | .pcs_misc = 0x0600, |
2490 | .tx = 0x0200, |
2491 | .rx = 0x0400, |
2492 | }; |
2493 | |
2494 | static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = { |
2495 | .serdes = 0, |
2496 | .pcs = 0x0800, |
2497 | .pcs_misc = 0x0c00, |
2498 | .tx = 0x0200, |
2499 | .rx = 0x0400, |
2500 | }; |
2501 | |
2502 | static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = { |
2503 | .serdes = 0, |
2504 | .pcs = 0x0a00, |
2505 | .pcs_misc = 0x0e00, |
2506 | .tx = 0x0200, |
2507 | .rx = 0x0400, |
2508 | .tx2 = 0x0600, |
2509 | .rx2 = 0x0800, |
2510 | }; |
2511 | |
2512 | static const struct qmp_pcie_offsets qmp_pcie_offsets_v4_20 = { |
2513 | .serdes = 0x1000, |
2514 | .pcs = 0x1200, |
2515 | .pcs_misc = 0x1600, |
2516 | .tx = 0x0000, |
2517 | .rx = 0x0200, |
2518 | .tx2 = 0x0800, |
2519 | .rx2 = 0x0a00, |
2520 | }; |
2521 | |
2522 | static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = { |
2523 | .serdes = 0, |
2524 | .pcs = 0x0200, |
2525 | .pcs_misc = 0x0600, |
2526 | .tx = 0x0e00, |
2527 | .rx = 0x1000, |
2528 | .tx2 = 0x1600, |
2529 | .rx2 = 0x1800, |
2530 | }; |
2531 | |
2532 | static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_20 = { |
2533 | .serdes = 0x1000, |
2534 | .pcs = 0x1200, |
2535 | .pcs_misc = 0x1400, |
2536 | .tx = 0x0000, |
2537 | .rx = 0x0200, |
2538 | .tx2 = 0x0800, |
2539 | .rx2 = 0x0a00, |
2540 | }; |
2541 | |
2542 | static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_30 = { |
2543 | .serdes = 0x2000, |
2544 | .pcs = 0x2200, |
2545 | .pcs_misc = 0x2400, |
2546 | .tx = 0x0, |
2547 | .rx = 0x0200, |
2548 | .tx2 = 0x3800, |
2549 | .rx2 = 0x3a00, |
2550 | }; |
2551 | |
2552 | static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = { |
2553 | .serdes = 0x1000, |
2554 | .pcs = 0x1200, |
2555 | .pcs_misc = 0x1400, |
2556 | .tx = 0x0000, |
2557 | .rx = 0x0200, |
2558 | .tx2 = 0x0800, |
2559 | .rx2 = 0x0a00, |
2560 | .ln_shrd = 0x0e00, |
2561 | }; |
2562 | |
2563 | static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { |
2564 | .lanes = 1, |
2565 | |
2566 | .offsets = &qmp_pcie_offsets_v2, |
2567 | |
2568 | .tbls = { |
2569 | .serdes = ipq8074_pcie_serdes_tbl, |
2570 | .serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), |
2571 | .tx = ipq8074_pcie_tx_tbl, |
2572 | .tx_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), |
2573 | .rx = ipq8074_pcie_rx_tbl, |
2574 | .rx_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), |
2575 | .pcs = ipq8074_pcie_pcs_tbl, |
2576 | .pcs_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), |
2577 | }, |
2578 | .reset_list = ipq8074_pciephy_reset_l, |
2579 | .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), |
2580 | .vreg_list = NULL, |
2581 | .num_vregs = 0, |
2582 | .regs = pciephy_v2_regs_layout, |
2583 | |
2584 | .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
2585 | .phy_status = PHYSTATUS, |
2586 | }; |
2587 | |
2588 | static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { |
2589 | .lanes = 1, |
2590 | |
2591 | .offsets = &qmp_pcie_offsets_v4x1, |
2592 | |
2593 | .tbls = { |
2594 | .serdes = ipq8074_pcie_gen3_serdes_tbl, |
2595 | .serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), |
2596 | .tx = ipq8074_pcie_gen3_tx_tbl, |
2597 | .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), |
2598 | .rx = ipq8074_pcie_gen3_rx_tbl, |
2599 | .rx_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), |
2600 | .pcs = ipq8074_pcie_gen3_pcs_tbl, |
2601 | .pcs_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), |
2602 | .pcs_misc = ipq8074_pcie_gen3_pcs_misc_tbl, |
2603 | .pcs_misc_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_misc_tbl), |
2604 | }, |
2605 | .reset_list = ipq8074_pciephy_reset_l, |
2606 | .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), |
2607 | .vreg_list = NULL, |
2608 | .num_vregs = 0, |
2609 | .regs = pciephy_v4_regs_layout, |
2610 | |
2611 | .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
2612 | .phy_status = PHYSTATUS, |
2613 | |
2614 | .pipe_clock_rate = 250000000, |
2615 | }; |
2616 | |
2617 | static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { |
2618 | .lanes = 1, |
2619 | |
2620 | .offsets = &qmp_pcie_offsets_v4x1, |
2621 | |
2622 | .tbls = { |
2623 | .serdes = ipq6018_pcie_serdes_tbl, |
2624 | .serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), |
2625 | .tx = ipq6018_pcie_tx_tbl, |
2626 | .tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), |
2627 | .rx = ipq6018_pcie_rx_tbl, |
2628 | .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), |
2629 | .pcs = ipq6018_pcie_pcs_tbl, |
2630 | .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), |
2631 | .pcs_misc = ipq6018_pcie_pcs_misc_tbl, |
2632 | .pcs_misc_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl), |
2633 | }, |
2634 | .reset_list = ipq8074_pciephy_reset_l, |
2635 | .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), |
2636 | .vreg_list = NULL, |
2637 | .num_vregs = 0, |
2638 | .regs = pciephy_v4_regs_layout, |
2639 | |
2640 | .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
2641 | .phy_status = PHYSTATUS, |
2642 | }; |
2643 | |
2644 | static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { |
2645 | .lanes = 1, |
2646 | |
2647 | .offsets = &qmp_pcie_offsets_v3, |
2648 | |
2649 | .tbls = { |
2650 | .serdes = sdm845_qmp_pcie_serdes_tbl, |
2651 | .serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), |
2652 | .tx = sdm845_qmp_pcie_tx_tbl, |
2653 | .tx_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), |
2654 | .rx = sdm845_qmp_pcie_rx_tbl, |
2655 | .rx_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), |
2656 | .pcs = sdm845_qmp_pcie_pcs_tbl, |
2657 | .pcs_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), |
2658 | .pcs_misc = sdm845_qmp_pcie_pcs_misc_tbl, |
2659 | .pcs_misc_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), |
2660 | }, |
2661 | .reset_list = sdm845_pciephy_reset_l, |
2662 | .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
2663 | .vreg_list = qmp_phy_vreg_l, |
2664 | .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
2665 | .regs = pciephy_v3_regs_layout, |
2666 | |
2667 | .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
2668 | .phy_status = PHYSTATUS, |
2669 | }; |
2670 | |
2671 | static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { |
2672 | .lanes = 1, |
2673 | |
2674 | .offsets = &qmp_pcie_offsets_qhp, |
2675 | |
2676 | .tbls = { |
2677 | .serdes = sdm845_qhp_pcie_serdes_tbl, |
2678 | .serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), |
2679 | .tx = sdm845_qhp_pcie_tx_tbl, |
2680 | .tx_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), |
2681 | .pcs = sdm845_qhp_pcie_pcs_tbl, |
2682 | .pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), |
2683 | }, |
2684 | .reset_list = sdm845_pciephy_reset_l, |
2685 | .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
2686 | .vreg_list = qmp_phy_vreg_l, |
2687 | .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
2688 | .regs = sdm845_qhp_pciephy_regs_layout, |
2689 | |
2690 | .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
2691 | .phy_status = PHYSTATUS, |
2692 | }; |
2693 | |
2694 | static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { |
2695 | .lanes = 1, |
2696 | |
2697 | .offsets = &qmp_pcie_offsets_v4x1, |
2698 | |
2699 | .tbls = { |
2700 | .serdes = sm8250_qmp_pcie_serdes_tbl, |
2701 | .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), |
2702 | .tx = sm8250_qmp_pcie_tx_tbl, |
2703 | .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), |
2704 | .rx = sm8250_qmp_pcie_rx_tbl, |
2705 | .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), |
2706 | .pcs = sm8250_qmp_pcie_pcs_tbl, |
2707 | .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), |
2708 | .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, |
2709 | .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), |
2710 | }, |
2711 | .tbls_rc = &(const struct qmp_phy_cfg_tbls) { |
2712 | .serdes = sm8250_qmp_gen3x1_pcie_serdes_tbl, |
2713 | .serdes_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), |
2714 | .rx = sm8250_qmp_gen3x1_pcie_rx_tbl, |
2715 | .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), |
2716 | .pcs = sm8250_qmp_gen3x1_pcie_pcs_tbl, |
2717 | .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), |
2718 | .pcs_misc = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, |
2719 | .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), |
2720 | }, |
2721 | .reset_list = sdm845_pciephy_reset_l, |
2722 | .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
2723 | .vreg_list = qmp_phy_vreg_l, |
2724 | .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
2725 | .regs = pciephy_v4_regs_layout, |
2726 | |
2727 | .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
2728 | .phy_status = PHYSTATUS, |
2729 | }; |
2730 | |
2731 | static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { |
2732 | .lanes = 2, |
2733 | |
2734 | .offsets = &qmp_pcie_offsets_v4x2, |
2735 | |
2736 | .tbls = { |
2737 | .serdes = sm8250_qmp_pcie_serdes_tbl, |
2738 | .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), |
2739 | .tx = sm8250_qmp_pcie_tx_tbl, |
2740 | .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), |
2741 | .rx = sm8250_qmp_pcie_rx_tbl, |
2742 | .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), |
2743 | .pcs = sm8250_qmp_pcie_pcs_tbl, |
2744 | .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), |
2745 | .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, |
2746 | .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), |
2747 | }, |
2748 | .tbls_rc = &(const struct qmp_phy_cfg_tbls) { |
2749 | .tx = sm8250_qmp_gen3x2_pcie_tx_tbl, |
2750 | .tx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), |
2751 | .rx = sm8250_qmp_gen3x2_pcie_rx_tbl, |
2752 | .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), |
2753 | .pcs = sm8250_qmp_gen3x2_pcie_pcs_tbl, |
2754 | .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), |
2755 | .pcs_misc = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, |
2756 | .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), |
2757 | }, |
2758 | .reset_list = sdm845_pciephy_reset_l, |
2759 | .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
2760 | .vreg_list = qmp_phy_vreg_l, |
2761 | .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
2762 | .regs = pciephy_v4_regs_layout, |
2763 | |
2764 | .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
2765 | .phy_status = PHYSTATUS, |
2766 | }; |
2767 | |
2768 | static const struct qmp_phy_cfg msm8998_pciephy_cfg = { |
2769 | .lanes = 1, |
2770 | |
2771 | .offsets = &qmp_pcie_offsets_v3, |
2772 | |
2773 | .tbls = { |
2774 | .serdes = msm8998_pcie_serdes_tbl, |
2775 | .serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), |
2776 | .tx = msm8998_pcie_tx_tbl, |
2777 | .tx_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), |
2778 | .rx = msm8998_pcie_rx_tbl, |
2779 | .rx_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), |
2780 | .pcs = msm8998_pcie_pcs_tbl, |
2781 | .pcs_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), |
2782 | }, |
2783 | .reset_list = ipq8074_pciephy_reset_l, |
2784 | .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), |
2785 | .vreg_list = qmp_phy_vreg_l, |
2786 | .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
2787 | .regs = pciephy_v3_regs_layout, |
2788 | |
2789 | .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
2790 | .phy_status = PHYSTATUS, |
2791 | |
2792 | .skip_start_delay = true, |
2793 | }; |
2794 | |
2795 | static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { |
2796 | .lanes = 2, |
2797 | |
2798 | .offsets = &qmp_pcie_offsets_v4x2, |
2799 | |
2800 | .tbls = { |
2801 | .serdes = sc8180x_qmp_pcie_serdes_tbl, |
2802 | .serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), |
2803 | .tx = sc8180x_qmp_pcie_tx_tbl, |
2804 | .tx_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), |
2805 | .rx = sc8180x_qmp_pcie_rx_tbl, |
2806 | .rx_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), |
2807 | .pcs = sc8180x_qmp_pcie_pcs_tbl, |
2808 | .pcs_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), |
2809 | .pcs_misc = sc8180x_qmp_pcie_pcs_misc_tbl, |
2810 | .pcs_misc_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), |
2811 | }, |
2812 | .reset_list = sdm845_pciephy_reset_l, |
2813 | .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
2814 | .vreg_list = qmp_phy_vreg_l, |
2815 | .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
2816 | .regs = pciephy_v4_regs_layout, |
2817 | |
2818 | .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
2819 | .phy_status = PHYSTATUS, |
2820 | }; |
2821 | |
2822 | static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = { |
2823 | .lanes = 1, |
2824 | |
2825 | .offsets = &qmp_pcie_offsets_v5, |
2826 | |
2827 | .tbls = { |
2828 | .serdes = sc8280xp_qmp_pcie_serdes_tbl, |
2829 | .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), |
2830 | .tx = sc8280xp_qmp_gen3x1_pcie_tx_tbl, |
2831 | .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_tx_tbl), |
2832 | .rx = sc8280xp_qmp_gen3x1_pcie_rx_tbl, |
2833 | .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rx_tbl), |
2834 | .pcs = sc8280xp_qmp_gen3x1_pcie_pcs_tbl, |
2835 | .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_tbl), |
2836 | .pcs_misc = sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl, |
2837 | .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl), |
2838 | }, |
2839 | |
2840 | .tbls_rc = &(const struct qmp_phy_cfg_tbls) { |
2841 | .serdes = sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl, |
2842 | .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl), |
2843 | }, |
2844 | |
2845 | .reset_list = sdm845_pciephy_reset_l, |
2846 | .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
2847 | .vreg_list = qmp_phy_vreg_l, |
2848 | .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
2849 | .regs = pciephy_v5_regs_layout, |
2850 | |
2851 | .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
2852 | .phy_status = PHYSTATUS, |
2853 | }; |
2854 | |
2855 | static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = { |
2856 | .lanes = 2, |
2857 | |
2858 | .offsets = &qmp_pcie_offsets_v5, |
2859 | |
2860 | .tbls = { |
2861 | .serdes = sc8280xp_qmp_pcie_serdes_tbl, |
2862 | .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), |
2863 | .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, |
2864 | .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), |
2865 | .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, |
2866 | .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), |
2867 | .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, |
2868 | .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), |
2869 | .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, |
2870 | .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), |
2871 | }, |
2872 | |
2873 | .tbls_rc = &(const struct qmp_phy_cfg_tbls) { |
2874 | .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, |
2875 | .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), |
2876 | }, |
2877 | |
2878 | .reset_list = sdm845_pciephy_reset_l, |
2879 | .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
2880 | .vreg_list = qmp_phy_vreg_l, |
2881 | .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
2882 | .regs = pciephy_v5_regs_layout, |
2883 | |
2884 | .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
2885 | .phy_status = PHYSTATUS, |
2886 | }; |
2887 | |
2888 | static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = { |
2889 | .lanes = 4, |
2890 | |
2891 | .offsets = &qmp_pcie_offsets_v5, |
2892 | |
2893 | .tbls = { |
2894 | .serdes = sc8280xp_qmp_pcie_serdes_tbl, |
2895 | .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), |
2896 | .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, |
2897 | .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), |
2898 | .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, |
2899 | .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), |
2900 | .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, |
2901 | .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), |
2902 | .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, |
2903 | .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), |
2904 | }, |
2905 | |
2906 | .tbls_rc = &(const struct qmp_phy_cfg_tbls) { |
2907 | .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, |
2908 | .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), |
2909 | }, |
2910 | |
2911 | .serdes_4ln_tbl = sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl, |
2912 | .serdes_4ln_num = ARRAY_SIZE(sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl), |
2913 | |
2914 | .reset_list = sdm845_pciephy_reset_l, |
2915 | .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
2916 | .vreg_list = qmp_phy_vreg_l, |
2917 | .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
2918 | .regs = pciephy_v5_regs_layout, |
2919 | |
2920 | .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
2921 | .phy_status = PHYSTATUS, |
2922 | }; |
2923 | |
2924 | static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { |
2925 | .lanes = 2, |
2926 | |
2927 | .offsets = &qmp_pcie_offsets_v4_20, |
2928 | |
2929 | .tbls = { |
2930 | .serdes = sdx55_qmp_pcie_serdes_tbl, |
2931 | .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), |
2932 | .tx = sdx55_qmp_pcie_tx_tbl, |
2933 | .tx_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), |
2934 | .rx = sdx55_qmp_pcie_rx_tbl, |
2935 | .rx_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), |
2936 | .pcs = sdx55_qmp_pcie_pcs_tbl, |
2937 | .pcs_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), |
2938 | .pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl, |
2939 | .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), |
2940 | }, |
2941 | |
2942 | .tbls_rc = &(const struct qmp_phy_cfg_tbls) { |
2943 | .serdes = sdx55_qmp_pcie_rc_serdes_tbl, |
2944 | .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_serdes_tbl), |
2945 | .pcs_misc = sdx55_qmp_pcie_rc_pcs_misc_tbl, |
2946 | .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_pcs_misc_tbl), |
2947 | }, |
2948 | |
2949 | .tbls_ep = &(const struct qmp_phy_cfg_tbls) { |
2950 | .serdes = sdx55_qmp_pcie_ep_serdes_tbl, |
2951 | .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl), |
2952 | .pcs_misc = sdx55_qmp_pcie_ep_pcs_misc_tbl, |
2953 | .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_misc_tbl), |
2954 | }, |
2955 | |
2956 | .reset_list = sdm845_pciephy_reset_l, |
2957 | .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
2958 | .vreg_list = qmp_phy_vreg_l, |
2959 | .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
2960 | .regs = pciephy_v4_regs_layout, |
2961 | |
2962 | .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
2963 | .phy_status = PHYSTATUS_4_20, |
2964 | }; |
2965 | |
2966 | static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = { |
2967 | .lanes = 1, |
2968 | |
2969 | .offsets = &qmp_pcie_offsets_v5, |
2970 | |
2971 | .tbls = { |
2972 | .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, |
2973 | .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), |
2974 | .tx = sm8350_qmp_gen3x1_pcie_tx_tbl, |
2975 | .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl), |
2976 | .rx = sm8450_qmp_gen3_pcie_rx_tbl, |
2977 | .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), |
2978 | .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, |
2979 | .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), |
2980 | .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, |
2981 | .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), |
2982 | }, |
2983 | |
2984 | .tbls_rc = &(const struct qmp_phy_cfg_tbls) { |
2985 | .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl, |
2986 | .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl), |
2987 | .rx = sm8350_qmp_gen3x1_pcie_rc_rx_tbl, |
2988 | .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl), |
2989 | }, |
2990 | |
2991 | .reset_list = sdm845_pciephy_reset_l, |
2992 | .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
2993 | .vreg_list = qmp_phy_vreg_l, |
2994 | .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
2995 | .regs = pciephy_v5_regs_layout, |
2996 | |
2997 | .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
2998 | .phy_status = PHYSTATUS, |
2999 | }; |
3000 | |
3001 | static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = { |
3002 | .lanes = 2, |
3003 | |
3004 | .offsets = &qmp_pcie_offsets_v5, |
3005 | |
3006 | .tbls = { |
3007 | .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, |
3008 | .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), |
3009 | .tx = sm8350_qmp_gen3x2_pcie_tx_tbl, |
3010 | .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_tx_tbl), |
3011 | .rx = sm8450_qmp_gen3_pcie_rx_tbl, |
3012 | .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), |
3013 | .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, |
3014 | .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), |
3015 | .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, |
3016 | .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), |
3017 | }, |
3018 | |
3019 | .tbls_rc = &(const struct qmp_phy_cfg_tbls) { |
3020 | .rx = sm8350_qmp_gen3x2_pcie_rc_rx_tbl, |
3021 | .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl), |
3022 | .pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl, |
3023 | .pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl), |
3024 | }, |
3025 | |
3026 | .reset_list = sdm845_pciephy_reset_l, |
3027 | .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
3028 | .vreg_list = qmp_phy_vreg_l, |
3029 | .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
3030 | .regs = pciephy_v5_regs_layout, |
3031 | |
3032 | .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
3033 | .phy_status = PHYSTATUS, |
3034 | }; |
3035 | |
3036 | static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg = { |
3037 | .lanes = 2, |
3038 | |
3039 | .offsets = &qmp_pcie_offsets_v6_20, |
3040 | |
3041 | .tbls = { |
3042 | .serdes = sdx65_qmp_pcie_serdes_tbl, |
3043 | .serdes_num = ARRAY_SIZE(sdx65_qmp_pcie_serdes_tbl), |
3044 | .tx = sdx65_qmp_pcie_tx_tbl, |
3045 | .tx_num = ARRAY_SIZE(sdx65_qmp_pcie_tx_tbl), |
3046 | .rx = sdx65_qmp_pcie_rx_tbl, |
3047 | .rx_num = ARRAY_SIZE(sdx65_qmp_pcie_rx_tbl), |
3048 | .pcs = sdx65_qmp_pcie_pcs_tbl, |
3049 | .pcs_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_tbl), |
3050 | .pcs_misc = sdx65_qmp_pcie_pcs_misc_tbl, |
3051 | .pcs_misc_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_misc_tbl), |
3052 | }, |
3053 | .reset_list = sdm845_pciephy_reset_l, |
3054 | .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
3055 | .vreg_list = qmp_phy_vreg_l, |
3056 | .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
3057 | .regs = pciephy_v6_regs_layout, |
3058 | |
3059 | .pwrdn_ctrl = SW_PWRDN, |
3060 | .phy_status = PHYSTATUS_4_20, |
3061 | }; |
3062 | |
3063 | static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { |
3064 | .lanes = 1, |
3065 | |
3066 | .offsets = &qmp_pcie_offsets_v5, |
3067 | |
3068 | .tbls = { |
3069 | .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, |
3070 | .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), |
3071 | .tx = sm8450_qmp_gen3x1_pcie_tx_tbl, |
3072 | .tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), |
3073 | .rx = sm8450_qmp_gen3_pcie_rx_tbl, |
3074 | .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), |
3075 | .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, |
3076 | .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), |
3077 | .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, |
3078 | .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), |
3079 | }, |
3080 | |
3081 | .tbls_rc = &(const struct qmp_phy_cfg_tbls) { |
3082 | .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl, |
3083 | .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl), |
3084 | .rx = sm8450_qmp_gen3x1_pcie_rc_rx_tbl, |
3085 | .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_rx_tbl), |
3086 | }, |
3087 | |
3088 | .reset_list = sdm845_pciephy_reset_l, |
3089 | .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
3090 | .vreg_list = qmp_phy_vreg_l, |
3091 | .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
3092 | .regs = pciephy_v5_regs_layout, |
3093 | |
3094 | .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
3095 | .phy_status = PHYSTATUS, |
3096 | }; |
3097 | |
3098 | static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { |
3099 | .lanes = 2, |
3100 | |
3101 | .offsets = &qmp_pcie_offsets_v5_20, |
3102 | |
3103 | .tbls = { |
3104 | .serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl, |
3105 | .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), |
3106 | .tx = sm8450_qmp_gen4x2_pcie_tx_tbl, |
3107 | .tx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), |
3108 | .rx = sm8450_qmp_gen4x2_pcie_rx_tbl, |
3109 | .rx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), |
3110 | .pcs = sm8450_qmp_gen4x2_pcie_pcs_tbl, |
3111 | .pcs_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), |
3112 | .pcs_misc = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, |
3113 | .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), |
3114 | }, |
3115 | |
3116 | .tbls_rc = &(const struct qmp_phy_cfg_tbls) { |
3117 | .serdes = sm8450_qmp_gen4x2_pcie_rc_serdes_tbl, |
3118 | .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_serdes_tbl), |
3119 | .pcs_misc = sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl, |
3120 | .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl), |
3121 | }, |
3122 | |
3123 | .tbls_ep = &(const struct qmp_phy_cfg_tbls) { |
3124 | .serdes = sm8450_qmp_gen4x2_pcie_ep_serdes_tbl, |
3125 | .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_serdes_tbl), |
3126 | .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, |
3127 | .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), |
3128 | }, |
3129 | |
3130 | .reset_list = sdm845_pciephy_reset_l, |
3131 | .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
3132 | .vreg_list = qmp_phy_vreg_l, |
3133 | .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
3134 | .regs = pciephy_v5_regs_layout, |
3135 | |
3136 | .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
3137 | .phy_status = PHYSTATUS_4_20, |
3138 | }; |
3139 | |
3140 | static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg = { |
3141 | .lanes = 2, |
3142 | |
3143 | .offsets = &qmp_pcie_offsets_v5, |
3144 | |
3145 | .tbls = { |
3146 | .serdes = sm8550_qmp_gen3x2_pcie_serdes_tbl, |
3147 | .serdes_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl), |
3148 | .tx = sm8550_qmp_gen3x2_pcie_tx_tbl, |
3149 | .tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl), |
3150 | .rx = sm8550_qmp_gen3x2_pcie_rx_tbl, |
3151 | .rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl), |
3152 | .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl, |
3153 | .pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl), |
3154 | .pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl, |
3155 | .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl), |
3156 | }, |
3157 | .reset_list = sdm845_pciephy_reset_l, |
3158 | .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
3159 | .vreg_list = qmp_phy_vreg_l, |
3160 | .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
3161 | .regs = pciephy_v5_regs_layout, |
3162 | |
3163 | .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
3164 | .phy_status = PHYSTATUS, |
3165 | }; |
3166 | |
3167 | static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = { |
3168 | .lanes = 2, |
3169 | |
3170 | .offsets = &qmp_pcie_offsets_v6_20, |
3171 | |
3172 | .tbls = { |
3173 | .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl, |
3174 | .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl), |
3175 | .tx = sm8550_qmp_gen4x2_pcie_tx_tbl, |
3176 | .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl), |
3177 | .rx = sm8550_qmp_gen4x2_pcie_rx_tbl, |
3178 | .rx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_rx_tbl), |
3179 | .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl, |
3180 | .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl), |
3181 | .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl, |
3182 | .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl), |
3183 | .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl, |
3184 | .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl), |
3185 | }, |
3186 | .reset_list = sdm845_pciephy_reset_l, |
3187 | .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
3188 | .vreg_list = sm8550_qmp_phy_vreg_l, |
3189 | .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), |
3190 | .regs = pciephy_v6_regs_layout, |
3191 | |
3192 | .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
3193 | .phy_status = PHYSTATUS_4_20, |
3194 | .has_nocsr_reset = true, |
3195 | }; |
3196 | |
3197 | static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pciephy_cfg = { |
3198 | .lanes = 2, |
3199 | |
3200 | .offsets = &qmp_pcie_offsets_v6_20, |
3201 | |
3202 | .tbls = { |
3203 | .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl, |
3204 | .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl), |
3205 | .tx = sm8550_qmp_gen4x2_pcie_tx_tbl, |
3206 | .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl), |
3207 | .rx = sm8650_qmp_gen4x2_pcie_rx_tbl, |
3208 | .rx_num = ARRAY_SIZE(sm8650_qmp_gen4x2_pcie_rx_tbl), |
3209 | .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl, |
3210 | .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl), |
3211 | .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl, |
3212 | .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl), |
3213 | .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl, |
3214 | .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl), |
3215 | }, |
3216 | .reset_list = sdm845_pciephy_reset_l, |
3217 | .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
3218 | .vreg_list = sm8550_qmp_phy_vreg_l, |
3219 | .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), |
3220 | .regs = pciephy_v6_regs_layout, |
3221 | |
3222 | .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
3223 | .phy_status = PHYSTATUS_4_20, |
3224 | .has_nocsr_reset = true, |
3225 | }; |
3226 | |
3227 | static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = { |
3228 | .lanes = 2, |
3229 | .offsets = &qmp_pcie_offsets_v5_20, |
3230 | |
3231 | .tbls = { |
3232 | .serdes = sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl, |
3233 | .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl), |
3234 | .tx = sa8775p_qmp_gen4_pcie_tx_tbl, |
3235 | .tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl), |
3236 | .rx = sa8775p_qmp_gen4x2_pcie_rx_alt_tbl, |
3237 | .rx_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rx_alt_tbl), |
3238 | .pcs = sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl, |
3239 | .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl), |
3240 | .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl, |
3241 | .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl), |
3242 | }, |
3243 | |
3244 | .tbls_rc = &(const struct qmp_phy_cfg_tbls) { |
3245 | .serdes = sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl, |
3246 | .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl), |
3247 | .pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl, |
3248 | .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl), |
3249 | }, |
3250 | |
3251 | .tbls_ep = &(const struct qmp_phy_cfg_tbls) { |
3252 | .serdes = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl, |
3253 | .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl), |
3254 | .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, |
3255 | .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), |
3256 | .pcs = sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl, |
3257 | .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl), |
3258 | }, |
3259 | |
3260 | .reset_list = sdm845_pciephy_reset_l, |
3261 | .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
3262 | .vreg_list = qmp_phy_vreg_l, |
3263 | .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
3264 | .regs = pciephy_v5_regs_layout, |
3265 | |
3266 | .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
3267 | .phy_status = PHYSTATUS_4_20, |
3268 | }; |
3269 | |
3270 | static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pciephy_cfg = { |
3271 | .lanes = 4, |
3272 | .offsets = &qmp_pcie_offsets_v5_30, |
3273 | |
3274 | .tbls = { |
3275 | .serdes = sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl, |
3276 | .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl), |
3277 | .tx = sa8775p_qmp_gen4_pcie_tx_tbl, |
3278 | .tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl), |
3279 | .rx = sa8775p_qmp_gen4x4_pcie_rx_alt_tbl, |
3280 | .rx_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rx_alt_tbl), |
3281 | .pcs = sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl, |
3282 | .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl), |
3283 | .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl, |
3284 | .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl), |
3285 | }, |
3286 | |
3287 | .tbls_rc = &(const struct qmp_phy_cfg_tbls) { |
3288 | .serdes = sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl, |
3289 | .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl), |
3290 | .pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl, |
3291 | .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl), |
3292 | }, |
3293 | |
3294 | .reset_list = sdm845_pciephy_reset_l, |
3295 | .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
3296 | .vreg_list = qmp_phy_vreg_l, |
3297 | .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
3298 | .regs = pciephy_v5_regs_layout, |
3299 | |
3300 | .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
3301 | .phy_status = PHYSTATUS_4_20, |
3302 | }; |
3303 | |
3304 | static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = { |
3305 | .lanes = 2, |
3306 | |
3307 | .offsets = &qmp_pcie_offsets_v6_20, |
3308 | |
3309 | .tbls = { |
3310 | .serdes = x1e80100_qmp_gen4x2_pcie_serdes_tbl, |
3311 | .serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_serdes_tbl), |
3312 | .tx = x1e80100_qmp_gen4x2_pcie_tx_tbl, |
3313 | .tx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_tx_tbl), |
3314 | .rx = x1e80100_qmp_gen4x2_pcie_rx_tbl, |
3315 | .rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_rx_tbl), |
3316 | .pcs = x1e80100_qmp_gen4x2_pcie_pcs_tbl, |
3317 | .pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_tbl), |
3318 | .pcs_misc = x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl, |
3319 | .pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl), |
3320 | .ln_shrd = x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl, |
3321 | .ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl), |
3322 | }, |
3323 | .reset_list = sdm845_pciephy_reset_l, |
3324 | .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
3325 | .vreg_list = sm8550_qmp_phy_vreg_l, |
3326 | .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), |
3327 | .regs = pciephy_v6_regs_layout, |
3328 | |
3329 | .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
3330 | .phy_status = PHYSTATUS_4_20, |
3331 | .has_nocsr_reset = true, |
3332 | }; |
3333 | |
3334 | static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) |
3335 | { |
3336 | const struct qmp_phy_cfg *cfg = qmp->cfg; |
3337 | const struct qmp_pcie_offsets *offs = cfg->offsets; |
3338 | void __iomem *tx3, *rx3, *tx4, *rx4; |
3339 | |
3340 | tx3 = qmp->port_b + offs->tx; |
3341 | rx3 = qmp->port_b + offs->rx; |
3342 | tx4 = qmp->port_b + offs->tx2; |
3343 | rx4 = qmp->port_b + offs->rx2; |
3344 | |
3345 | qmp_configure_lane(base: tx3, tbl: tbls->tx, num: tbls->tx_num, lane_mask: 1); |
3346 | qmp_configure_lane(base: rx3, tbl: tbls->rx, num: tbls->rx_num, lane_mask: 1); |
3347 | |
3348 | qmp_configure_lane(base: tx4, tbl: tbls->tx, num: tbls->tx_num, lane_mask: 2); |
3349 | qmp_configure_lane(base: rx4, tbl: tbls->rx, num: tbls->rx_num, lane_mask: 2); |
3350 | } |
3351 | |
3352 | static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) |
3353 | { |
3354 | const struct qmp_phy_cfg *cfg = qmp->cfg; |
3355 | void __iomem *serdes = qmp->serdes; |
3356 | void __iomem *tx = qmp->tx; |
3357 | void __iomem *rx = qmp->rx; |
3358 | void __iomem *tx2 = qmp->tx2; |
3359 | void __iomem *rx2 = qmp->rx2; |
3360 | void __iomem *pcs = qmp->pcs; |
3361 | void __iomem *pcs_misc = qmp->pcs_misc; |
3362 | void __iomem *ln_shrd = qmp->ln_shrd; |
3363 | |
3364 | if (!tbls) |
3365 | return; |
3366 | |
3367 | qmp_configure(base: serdes, tbl: tbls->serdes, num: tbls->serdes_num); |
3368 | |
3369 | qmp_configure_lane(base: tx, tbl: tbls->tx, num: tbls->tx_num, lane_mask: 1); |
3370 | qmp_configure_lane(base: rx, tbl: tbls->rx, num: tbls->rx_num, lane_mask: 1); |
3371 | |
3372 | if (cfg->lanes >= 2) { |
3373 | qmp_configure_lane(base: tx2, tbl: tbls->tx, num: tbls->tx_num, lane_mask: 2); |
3374 | qmp_configure_lane(base: rx2, tbl: tbls->rx, num: tbls->rx_num, lane_mask: 2); |
3375 | } |
3376 | |
3377 | qmp_configure(base: pcs, tbl: tbls->pcs, num: tbls->pcs_num); |
3378 | qmp_configure(base: pcs_misc, tbl: tbls->pcs_misc, num: tbls->pcs_misc_num); |
3379 | |
3380 | if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) { |
3381 | qmp_configure(base: serdes, tbl: cfg->serdes_4ln_tbl, num: cfg->serdes_4ln_num); |
3382 | qmp_pcie_init_port_b(qmp, tbls); |
3383 | } |
3384 | |
3385 | qmp_configure(base: ln_shrd, tbl: tbls->ln_shrd, num: tbls->ln_shrd_num); |
3386 | } |
3387 | |
3388 | static int qmp_pcie_init(struct phy *phy) |
3389 | { |
3390 | struct qmp_pcie *qmp = phy_get_drvdata(phy); |
3391 | const struct qmp_phy_cfg *cfg = qmp->cfg; |
3392 | int ret; |
3393 | |
3394 | ret = regulator_bulk_enable(num_consumers: cfg->num_vregs, consumers: qmp->vregs); |
3395 | if (ret) { |
3396 | dev_err(qmp->dev, "failed to enable regulators, err=%d\n" , ret); |
3397 | return ret; |
3398 | } |
3399 | |
3400 | ret = reset_control_bulk_assert(num_rstcs: cfg->num_resets, rstcs: qmp->resets); |
3401 | if (ret) { |
3402 | dev_err(qmp->dev, "reset assert failed\n" ); |
3403 | goto err_disable_regulators; |
3404 | } |
3405 | |
3406 | ret = reset_control_assert(rstc: qmp->nocsr_reset); |
3407 | if (ret) { |
3408 | dev_err(qmp->dev, "no-csr reset assert failed\n" ); |
3409 | goto err_assert_reset; |
3410 | } |
3411 | |
3412 | usleep_range(min: 200, max: 300); |
3413 | |
3414 | ret = reset_control_bulk_deassert(num_rstcs: cfg->num_resets, rstcs: qmp->resets); |
3415 | if (ret) { |
3416 | dev_err(qmp->dev, "reset deassert failed\n" ); |
3417 | goto err_assert_reset; |
3418 | } |
3419 | |
3420 | ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), clks: qmp->clks); |
3421 | if (ret) |
3422 | goto err_assert_reset; |
3423 | |
3424 | return 0; |
3425 | |
3426 | err_assert_reset: |
3427 | reset_control_bulk_assert(num_rstcs: cfg->num_resets, rstcs: qmp->resets); |
3428 | err_disable_regulators: |
3429 | regulator_bulk_disable(num_consumers: cfg->num_vregs, consumers: qmp->vregs); |
3430 | |
3431 | return ret; |
3432 | } |
3433 | |
3434 | static int qmp_pcie_exit(struct phy *phy) |
3435 | { |
3436 | struct qmp_pcie *qmp = phy_get_drvdata(phy); |
3437 | const struct qmp_phy_cfg *cfg = qmp->cfg; |
3438 | |
3439 | reset_control_bulk_assert(num_rstcs: cfg->num_resets, rstcs: qmp->resets); |
3440 | |
3441 | clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), clks: qmp->clks); |
3442 | |
3443 | regulator_bulk_disable(num_consumers: cfg->num_vregs, consumers: qmp->vregs); |
3444 | |
3445 | return 0; |
3446 | } |
3447 | |
3448 | static int qmp_pcie_power_on(struct phy *phy) |
3449 | { |
3450 | struct qmp_pcie *qmp = phy_get_drvdata(phy); |
3451 | const struct qmp_phy_cfg *cfg = qmp->cfg; |
3452 | const struct qmp_phy_cfg_tbls *mode_tbls; |
3453 | void __iomem *pcs = qmp->pcs; |
3454 | void __iomem *status; |
3455 | unsigned int mask, val; |
3456 | int ret; |
3457 | |
3458 | qphy_setbits(base: pcs, offset: cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], |
3459 | val: cfg->pwrdn_ctrl); |
3460 | |
3461 | if (qmp->mode == PHY_MODE_PCIE_RC) |
3462 | mode_tbls = cfg->tbls_rc; |
3463 | else |
3464 | mode_tbls = cfg->tbls_ep; |
3465 | |
3466 | qmp_pcie_init_registers(qmp, tbls: &cfg->tbls); |
3467 | qmp_pcie_init_registers(qmp, tbls: mode_tbls); |
3468 | |
3469 | ret = clk_bulk_prepare_enable(num_clks: qmp->num_pipe_clks, clks: qmp->pipe_clks); |
3470 | if (ret) |
3471 | return ret; |
3472 | |
3473 | ret = reset_control_deassert(rstc: qmp->nocsr_reset); |
3474 | if (ret) { |
3475 | dev_err(qmp->dev, "no-csr reset deassert failed\n" ); |
3476 | goto err_disable_pipe_clk; |
3477 | } |
3478 | |
3479 | /* Pull PHY out of reset state */ |
3480 | qphy_clrbits(base: pcs, offset: cfg->regs[QPHY_SW_RESET], SW_RESET); |
3481 | |
3482 | /* start SerDes and Phy-Coding-Sublayer */ |
3483 | qphy_setbits(base: pcs, offset: cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); |
3484 | |
3485 | if (!cfg->skip_start_delay) |
3486 | usleep_range(min: 1000, max: 1200); |
3487 | |
3488 | status = pcs + cfg->regs[QPHY_PCS_STATUS]; |
3489 | mask = cfg->phy_status; |
3490 | ret = readl_poll_timeout(status, val, !(val & mask), 200, |
3491 | PHY_INIT_COMPLETE_TIMEOUT); |
3492 | if (ret) { |
3493 | dev_err(qmp->dev, "phy initialization timed-out\n" ); |
3494 | goto err_disable_pipe_clk; |
3495 | } |
3496 | |
3497 | return 0; |
3498 | |
3499 | err_disable_pipe_clk: |
3500 | clk_bulk_disable_unprepare(num_clks: qmp->num_pipe_clks, clks: qmp->pipe_clks); |
3501 | |
3502 | return ret; |
3503 | } |
3504 | |
3505 | static int qmp_pcie_power_off(struct phy *phy) |
3506 | { |
3507 | struct qmp_pcie *qmp = phy_get_drvdata(phy); |
3508 | const struct qmp_phy_cfg *cfg = qmp->cfg; |
3509 | |
3510 | clk_bulk_disable_unprepare(num_clks: qmp->num_pipe_clks, clks: qmp->pipe_clks); |
3511 | |
3512 | /* PHY reset */ |
3513 | qphy_setbits(base: qmp->pcs, offset: cfg->regs[QPHY_SW_RESET], SW_RESET); |
3514 | |
3515 | /* stop SerDes and Phy-Coding-Sublayer */ |
3516 | qphy_clrbits(base: qmp->pcs, offset: cfg->regs[QPHY_START_CTRL], |
3517 | SERDES_START | PCS_START); |
3518 | |
3519 | /* Put PHY into POWER DOWN state: active low */ |
3520 | qphy_clrbits(base: qmp->pcs, offset: cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], |
3521 | val: cfg->pwrdn_ctrl); |
3522 | |
3523 | return 0; |
3524 | } |
3525 | |
3526 | static int qmp_pcie_enable(struct phy *phy) |
3527 | { |
3528 | int ret; |
3529 | |
3530 | ret = qmp_pcie_init(phy); |
3531 | if (ret) |
3532 | return ret; |
3533 | |
3534 | ret = qmp_pcie_power_on(phy); |
3535 | if (ret) |
3536 | qmp_pcie_exit(phy); |
3537 | |
3538 | return ret; |
3539 | } |
3540 | |
3541 | static int qmp_pcie_disable(struct phy *phy) |
3542 | { |
3543 | int ret; |
3544 | |
3545 | ret = qmp_pcie_power_off(phy); |
3546 | if (ret) |
3547 | return ret; |
3548 | |
3549 | return qmp_pcie_exit(phy); |
3550 | } |
3551 | |
3552 | static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode) |
3553 | { |
3554 | struct qmp_pcie *qmp = phy_get_drvdata(phy); |
3555 | |
3556 | switch (submode) { |
3557 | case PHY_MODE_PCIE_RC: |
3558 | case PHY_MODE_PCIE_EP: |
3559 | qmp->mode = submode; |
3560 | break; |
3561 | default: |
3562 | dev_err(&phy->dev, "Unsupported submode %d\n" , submode); |
3563 | return -EINVAL; |
3564 | } |
3565 | |
3566 | return 0; |
3567 | } |
3568 | |
3569 | static const struct phy_ops qmp_pcie_phy_ops = { |
3570 | .power_on = qmp_pcie_enable, |
3571 | .power_off = qmp_pcie_disable, |
3572 | .set_mode = qmp_pcie_set_mode, |
3573 | .owner = THIS_MODULE, |
3574 | }; |
3575 | |
3576 | static int qmp_pcie_vreg_init(struct qmp_pcie *qmp) |
3577 | { |
3578 | const struct qmp_phy_cfg *cfg = qmp->cfg; |
3579 | struct device *dev = qmp->dev; |
3580 | int num = cfg->num_vregs; |
3581 | int i; |
3582 | |
3583 | qmp->vregs = devm_kcalloc(dev, n: num, size: sizeof(*qmp->vregs), GFP_KERNEL); |
3584 | if (!qmp->vregs) |
3585 | return -ENOMEM; |
3586 | |
3587 | for (i = 0; i < num; i++) |
3588 | qmp->vregs[i].supply = cfg->vreg_list[i]; |
3589 | |
3590 | return devm_regulator_bulk_get(dev, num_consumers: num, consumers: qmp->vregs); |
3591 | } |
3592 | |
3593 | static int qmp_pcie_reset_init(struct qmp_pcie *qmp) |
3594 | { |
3595 | const struct qmp_phy_cfg *cfg = qmp->cfg; |
3596 | struct device *dev = qmp->dev; |
3597 | int i; |
3598 | int ret; |
3599 | |
3600 | qmp->resets = devm_kcalloc(dev, n: cfg->num_resets, |
3601 | size: sizeof(*qmp->resets), GFP_KERNEL); |
3602 | if (!qmp->resets) |
3603 | return -ENOMEM; |
3604 | |
3605 | for (i = 0; i < cfg->num_resets; i++) |
3606 | qmp->resets[i].id = cfg->reset_list[i]; |
3607 | |
3608 | ret = devm_reset_control_bulk_get_exclusive(dev, num_rstcs: cfg->num_resets, rstcs: qmp->resets); |
3609 | if (ret) |
3610 | return dev_err_probe(dev, err: ret, fmt: "failed to get resets\n" ); |
3611 | |
3612 | if (cfg->has_nocsr_reset) { |
3613 | qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, id: "phy_nocsr" ); |
3614 | if (IS_ERR(ptr: qmp->nocsr_reset)) |
3615 | return dev_err_probe(dev, err: PTR_ERR(ptr: qmp->nocsr_reset), |
3616 | fmt: "failed to get no-csr reset\n" ); |
3617 | } |
3618 | |
3619 | return 0; |
3620 | } |
3621 | |
3622 | static int qmp_pcie_clk_init(struct qmp_pcie *qmp) |
3623 | { |
3624 | struct device *dev = qmp->dev; |
3625 | int num = ARRAY_SIZE(qmp_pciephy_clk_l); |
3626 | int i; |
3627 | |
3628 | qmp->clks = devm_kcalloc(dev, n: num, size: sizeof(*qmp->clks), GFP_KERNEL); |
3629 | if (!qmp->clks) |
3630 | return -ENOMEM; |
3631 | |
3632 | for (i = 0; i < num; i++) |
3633 | qmp->clks[i].id = qmp_pciephy_clk_l[i]; |
3634 | |
3635 | return devm_clk_bulk_get_optional(dev, num_clks: num, clks: qmp->clks); |
3636 | } |
3637 | |
3638 | static void phy_clk_release_provider(void *res) |
3639 | { |
3640 | of_clk_del_provider(np: res); |
3641 | } |
3642 | |
3643 | /* |
3644 | * Register a fixed rate pipe clock. |
3645 | * |
3646 | * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate |
3647 | * controls it. The <s>_pipe_clk coming out of the GCC is requested |
3648 | * by the PHY driver for its operations. |
3649 | * We register the <s>_pipe_clksrc here. The gcc driver takes care |
3650 | * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. |
3651 | * Below picture shows this relationship. |
3652 | * |
3653 | * +---------------+ |
3654 | * | PHY block |<<---------------------------------------+ |
3655 | * | | | |
3656 | * | +-------+ | +-----+ | |
3657 | * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ |
3658 | * clk | +-------+ | +-----+ |
3659 | * +---------------+ |
3660 | */ |
3661 | static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np) |
3662 | { |
3663 | struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; |
3664 | struct clk_init_data init = { }; |
3665 | int ret; |
3666 | |
3667 | ret = of_property_read_string(np, propname: "clock-output-names" , out_string: &init.name); |
3668 | if (ret) { |
3669 | dev_err(qmp->dev, "%pOFn: No clock-output-names\n" , np); |
3670 | return ret; |
3671 | } |
3672 | |
3673 | init.ops = &clk_fixed_rate_ops; |
3674 | |
3675 | /* |
3676 | * Controllers using QMP PHY-s use 125MHz pipe clock interface |
3677 | * unless other frequency is specified in the PHY config. |
3678 | */ |
3679 | if (qmp->cfg->pipe_clock_rate) |
3680 | fixed->fixed_rate = qmp->cfg->pipe_clock_rate; |
3681 | else |
3682 | fixed->fixed_rate = 125000000; |
3683 | |
3684 | fixed->hw.init = &init; |
3685 | |
3686 | ret = devm_clk_hw_register(dev: qmp->dev, hw: &fixed->hw); |
3687 | if (ret) |
3688 | return ret; |
3689 | |
3690 | ret = of_clk_add_hw_provider(np, get: of_clk_hw_simple_get, data: &fixed->hw); |
3691 | if (ret) |
3692 | return ret; |
3693 | |
3694 | /* |
3695 | * Roll a devm action because the clock provider is the child node, but |
3696 | * the child node is not actually a device. |
3697 | */ |
3698 | return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); |
3699 | } |
3700 | |
3701 | static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np) |
3702 | { |
3703 | struct platform_device *pdev = to_platform_device(qmp->dev); |
3704 | const struct qmp_phy_cfg *cfg = qmp->cfg; |
3705 | struct device *dev = qmp->dev; |
3706 | struct clk *clk; |
3707 | |
3708 | qmp->serdes = devm_platform_ioremap_resource(pdev, index: 0); |
3709 | if (IS_ERR(ptr: qmp->serdes)) |
3710 | return PTR_ERR(ptr: qmp->serdes); |
3711 | |
3712 | /* |
3713 | * Get memory resources for the PHY: |
3714 | * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. |
3715 | * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 |
3716 | * For single lane PHYs: pcs_misc (optional) -> 3. |
3717 | */ |
3718 | qmp->tx = devm_of_iomap(dev, node: np, index: 0, NULL); |
3719 | if (IS_ERR(ptr: qmp->tx)) |
3720 | return PTR_ERR(ptr: qmp->tx); |
3721 | |
3722 | if (of_device_is_compatible(device: dev->of_node, "qcom,sdm845-qhp-pcie-phy" )) |
3723 | qmp->rx = qmp->tx; |
3724 | else |
3725 | qmp->rx = devm_of_iomap(dev, node: np, index: 1, NULL); |
3726 | if (IS_ERR(ptr: qmp->rx)) |
3727 | return PTR_ERR(ptr: qmp->rx); |
3728 | |
3729 | qmp->pcs = devm_of_iomap(dev, node: np, index: 2, NULL); |
3730 | if (IS_ERR(ptr: qmp->pcs)) |
3731 | return PTR_ERR(ptr: qmp->pcs); |
3732 | |
3733 | if (cfg->lanes >= 2) { |
3734 | qmp->tx2 = devm_of_iomap(dev, node: np, index: 3, NULL); |
3735 | if (IS_ERR(ptr: qmp->tx2)) |
3736 | return PTR_ERR(ptr: qmp->tx2); |
3737 | |
3738 | qmp->rx2 = devm_of_iomap(dev, node: np, index: 4, NULL); |
3739 | if (IS_ERR(ptr: qmp->rx2)) |
3740 | return PTR_ERR(ptr: qmp->rx2); |
3741 | |
3742 | qmp->pcs_misc = devm_of_iomap(dev, node: np, index: 5, NULL); |
3743 | } else { |
3744 | qmp->pcs_misc = devm_of_iomap(dev, node: np, index: 3, NULL); |
3745 | } |
3746 | |
3747 | if (IS_ERR(ptr: qmp->pcs_misc) && |
3748 | of_device_is_compatible(device: dev->of_node, "qcom,ipq6018-qmp-pcie-phy" )) |
3749 | qmp->pcs_misc = qmp->pcs + 0x400; |
3750 | |
3751 | if (IS_ERR(ptr: qmp->pcs_misc)) { |
3752 | if (cfg->tbls.pcs_misc || |
3753 | (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) || |
3754 | (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) { |
3755 | return PTR_ERR(ptr: qmp->pcs_misc); |
3756 | } |
3757 | } |
3758 | |
3759 | clk = devm_get_clk_from_child(dev, np, NULL); |
3760 | if (IS_ERR(ptr: clk)) { |
3761 | return dev_err_probe(dev, err: PTR_ERR(ptr: clk), |
3762 | fmt: "failed to get pipe clock\n" ); |
3763 | } |
3764 | |
3765 | qmp->num_pipe_clks = 1; |
3766 | qmp->pipe_clks[0].id = "pipe" ; |
3767 | qmp->pipe_clks[0].clk = clk; |
3768 | |
3769 | return 0; |
3770 | } |
3771 | |
3772 | static int qmp_pcie_get_4ln_config(struct qmp_pcie *qmp) |
3773 | { |
3774 | struct regmap *tcsr; |
3775 | unsigned int args[2]; |
3776 | int ret; |
3777 | |
3778 | tcsr = syscon_regmap_lookup_by_phandle_args(np: qmp->dev->of_node, |
3779 | property: "qcom,4ln-config-sel" , |
3780 | ARRAY_SIZE(args), out_args: args); |
3781 | if (IS_ERR(ptr: tcsr)) { |
3782 | ret = PTR_ERR(ptr: tcsr); |
3783 | if (ret == -ENOENT) |
3784 | return 0; |
3785 | |
3786 | dev_err(qmp->dev, "failed to lookup syscon: %d\n" , ret); |
3787 | return ret; |
3788 | } |
3789 | |
3790 | ret = regmap_test_bits(map: tcsr, reg: args[0], BIT(args[1])); |
3791 | if (ret < 0) { |
3792 | dev_err(qmp->dev, "failed to read tcsr: %d\n" , ret); |
3793 | return ret; |
3794 | } |
3795 | |
3796 | qmp->tcsr_4ln_config = ret; |
3797 | |
3798 | dev_dbg(qmp->dev, "4ln_config_sel = %d\n" , qmp->tcsr_4ln_config); |
3799 | |
3800 | return 0; |
3801 | } |
3802 | |
3803 | static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) |
3804 | { |
3805 | struct platform_device *pdev = to_platform_device(qmp->dev); |
3806 | const struct qmp_phy_cfg *cfg = qmp->cfg; |
3807 | const struct qmp_pcie_offsets *offs = cfg->offsets; |
3808 | struct device *dev = qmp->dev; |
3809 | void __iomem *base; |
3810 | int ret; |
3811 | |
3812 | if (!offs) |
3813 | return -EINVAL; |
3814 | |
3815 | ret = qmp_pcie_get_4ln_config(qmp); |
3816 | if (ret) |
3817 | return ret; |
3818 | |
3819 | base = devm_platform_ioremap_resource(pdev, index: 0); |
3820 | if (IS_ERR(ptr: base)) |
3821 | return PTR_ERR(ptr: base); |
3822 | |
3823 | qmp->serdes = base + offs->serdes; |
3824 | qmp->pcs = base + offs->pcs; |
3825 | qmp->pcs_misc = base + offs->pcs_misc; |
3826 | qmp->tx = base + offs->tx; |
3827 | qmp->rx = base + offs->rx; |
3828 | |
3829 | if (cfg->lanes >= 2) { |
3830 | qmp->tx2 = base + offs->tx2; |
3831 | qmp->rx2 = base + offs->rx2; |
3832 | } |
3833 | |
3834 | if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) { |
3835 | qmp->port_b = devm_platform_ioremap_resource(pdev, index: 1); |
3836 | if (IS_ERR(ptr: qmp->port_b)) |
3837 | return PTR_ERR(ptr: qmp->port_b); |
3838 | } |
3839 | |
3840 | if (cfg->tbls.ln_shrd) |
3841 | qmp->ln_shrd = base + offs->ln_shrd; |
3842 | |
3843 | qmp->num_pipe_clks = 2; |
3844 | qmp->pipe_clks[0].id = "pipe" ; |
3845 | qmp->pipe_clks[1].id = "pipediv2" ; |
3846 | |
3847 | ret = devm_clk_bulk_get(dev, num_clks: 1, clks: qmp->pipe_clks); |
3848 | if (ret) |
3849 | return ret; |
3850 | |
3851 | ret = devm_clk_bulk_get_optional(dev, num_clks: qmp->num_pipe_clks - 1, clks: qmp->pipe_clks + 1); |
3852 | if (ret) |
3853 | return ret; |
3854 | |
3855 | return 0; |
3856 | } |
3857 | |
3858 | static int qmp_pcie_probe(struct platform_device *pdev) |
3859 | { |
3860 | struct device *dev = &pdev->dev; |
3861 | struct phy_provider *phy_provider; |
3862 | struct device_node *np; |
3863 | struct qmp_pcie *qmp; |
3864 | int ret; |
3865 | |
3866 | qmp = devm_kzalloc(dev, size: sizeof(*qmp), GFP_KERNEL); |
3867 | if (!qmp) |
3868 | return -ENOMEM; |
3869 | |
3870 | qmp->dev = dev; |
3871 | |
3872 | qmp->cfg = of_device_get_match_data(dev); |
3873 | if (!qmp->cfg) |
3874 | return -EINVAL; |
3875 | |
3876 | WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); |
3877 | WARN_ON_ONCE(!qmp->cfg->phy_status); |
3878 | |
3879 | ret = qmp_pcie_clk_init(qmp); |
3880 | if (ret) |
3881 | return ret; |
3882 | |
3883 | ret = qmp_pcie_reset_init(qmp); |
3884 | if (ret) |
3885 | return ret; |
3886 | |
3887 | ret = qmp_pcie_vreg_init(qmp); |
3888 | if (ret) |
3889 | return ret; |
3890 | |
3891 | /* Check for legacy binding with child node. */ |
3892 | np = of_get_next_available_child(node: dev->of_node, NULL); |
3893 | if (np) { |
3894 | ret = qmp_pcie_parse_dt_legacy(qmp, np); |
3895 | } else { |
3896 | np = of_node_get(node: dev->of_node); |
3897 | ret = qmp_pcie_parse_dt(qmp); |
3898 | } |
3899 | if (ret) |
3900 | goto err_node_put; |
3901 | |
3902 | ret = phy_pipe_clk_register(qmp, np); |
3903 | if (ret) |
3904 | goto err_node_put; |
3905 | |
3906 | qmp->mode = PHY_MODE_PCIE_RC; |
3907 | |
3908 | qmp->phy = devm_phy_create(dev, node: np, ops: &qmp_pcie_phy_ops); |
3909 | if (IS_ERR(ptr: qmp->phy)) { |
3910 | ret = PTR_ERR(ptr: qmp->phy); |
3911 | dev_err(dev, "failed to create PHY: %d\n" , ret); |
3912 | goto err_node_put; |
3913 | } |
3914 | |
3915 | phy_set_drvdata(phy: qmp->phy, data: qmp); |
3916 | |
3917 | of_node_put(node: np); |
3918 | |
3919 | phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
3920 | |
3921 | return PTR_ERR_OR_ZERO(ptr: phy_provider); |
3922 | |
3923 | err_node_put: |
3924 | of_node_put(node: np); |
3925 | return ret; |
3926 | } |
3927 | |
3928 | static const struct of_device_id qmp_pcie_of_match_table[] = { |
3929 | { |
3930 | .compatible = "qcom,ipq6018-qmp-pcie-phy" , |
3931 | .data = &ipq6018_pciephy_cfg, |
3932 | }, { |
3933 | .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy" , |
3934 | .data = &ipq8074_pciephy_gen3_cfg, |
3935 | }, { |
3936 | .compatible = "qcom,ipq8074-qmp-pcie-phy" , |
3937 | .data = &ipq8074_pciephy_cfg, |
3938 | }, { |
3939 | .compatible = "qcom,msm8998-qmp-pcie-phy" , |
3940 | .data = &msm8998_pciephy_cfg, |
3941 | }, { |
3942 | .compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy" , |
3943 | .data = &sa8775p_qmp_gen4x2_pciephy_cfg, |
3944 | }, { |
3945 | .compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy" , |
3946 | .data = &sa8775p_qmp_gen4x4_pciephy_cfg, |
3947 | }, { |
3948 | .compatible = "qcom,sc8180x-qmp-pcie-phy" , |
3949 | .data = &sc8180x_pciephy_cfg, |
3950 | }, { |
3951 | .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy" , |
3952 | .data = &sc8280xp_qmp_gen3x1_pciephy_cfg, |
3953 | }, { |
3954 | .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy" , |
3955 | .data = &sc8280xp_qmp_gen3x2_pciephy_cfg, |
3956 | }, { |
3957 | .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy" , |
3958 | .data = &sc8280xp_qmp_gen3x4_pciephy_cfg, |
3959 | }, { |
3960 | .compatible = "qcom,sdm845-qhp-pcie-phy" , |
3961 | .data = &sdm845_qhp_pciephy_cfg, |
3962 | }, { |
3963 | .compatible = "qcom,sdm845-qmp-pcie-phy" , |
3964 | .data = &sdm845_qmp_pciephy_cfg, |
3965 | }, { |
3966 | .compatible = "qcom,sdx55-qmp-pcie-phy" , |
3967 | .data = &sdx55_qmp_pciephy_cfg, |
3968 | }, { |
3969 | .compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy" , |
3970 | .data = &sdx65_qmp_pciephy_cfg, |
3971 | }, { |
3972 | .compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy" , |
3973 | .data = &sm8250_qmp_gen3x1_pciephy_cfg, |
3974 | }, { |
3975 | .compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy" , |
3976 | .data = &sm8250_qmp_gen3x2_pciephy_cfg, |
3977 | }, { |
3978 | .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy" , |
3979 | .data = &sm8250_qmp_gen3x1_pciephy_cfg, |
3980 | }, { |
3981 | .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy" , |
3982 | .data = &sm8250_qmp_gen3x2_pciephy_cfg, |
3983 | }, { |
3984 | .compatible = "qcom,sm8250-qmp-modem-pcie-phy" , |
3985 | .data = &sm8250_qmp_gen3x2_pciephy_cfg, |
3986 | }, { |
3987 | .compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy" , |
3988 | .data = &sm8350_qmp_gen3x1_pciephy_cfg, |
3989 | }, { |
3990 | .compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy" , |
3991 | .data = &sm8350_qmp_gen3x2_pciephy_cfg, |
3992 | }, { |
3993 | .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy" , |
3994 | .data = &sm8450_qmp_gen3x1_pciephy_cfg, |
3995 | }, { |
3996 | .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy" , |
3997 | .data = &sm8450_qmp_gen4x2_pciephy_cfg, |
3998 | }, { |
3999 | .compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy" , |
4000 | .data = &sm8550_qmp_gen3x2_pciephy_cfg, |
4001 | }, { |
4002 | .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy" , |
4003 | .data = &sm8550_qmp_gen4x2_pciephy_cfg, |
4004 | }, { |
4005 | .compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy" , |
4006 | .data = &sm8550_qmp_gen3x2_pciephy_cfg, |
4007 | }, { |
4008 | .compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy" , |
4009 | .data = &sm8650_qmp_gen4x2_pciephy_cfg, |
4010 | }, { |
4011 | .compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy" , |
4012 | .data = &sm8550_qmp_gen3x2_pciephy_cfg, |
4013 | }, { |
4014 | .compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy" , |
4015 | .data = &x1e80100_qmp_gen4x2_pciephy_cfg, |
4016 | }, |
4017 | { }, |
4018 | }; |
4019 | MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table); |
4020 | |
4021 | static struct platform_driver qmp_pcie_driver = { |
4022 | .probe = qmp_pcie_probe, |
4023 | .driver = { |
4024 | .name = "qcom-qmp-pcie-phy" , |
4025 | .of_match_table = qmp_pcie_of_match_table, |
4026 | }, |
4027 | }; |
4028 | |
4029 | module_platform_driver(qmp_pcie_driver); |
4030 | |
4031 | MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>" ); |
4032 | MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver" ); |
4033 | MODULE_LICENSE("GPL v2" ); |
4034 | |