| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2023, Linaro Limited |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef QCOM_PHY_QMP_PCS_PCIE_V6_H_ |
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| 7 | #define QCOM_PHY_QMP_PCS_PCIE_V6_H_ |
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| 8 | |
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| 9 | /* Only for QMP V6 PHY - PCIE have different offsets than V5 */ |
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| 10 | #define QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1 0xa4 |
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| 11 | #define QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME 0xf4 |
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| 12 | #define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2 0x0c |
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| 13 | #define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4 0x14 |
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| 14 | #define QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 |
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| 15 | #define QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 |
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| 16 | |
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| 17 | #endif |
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| 18 | |
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