| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef QCOM_PHY_QMP_PCS_PCIE_V5_20_H_ |
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| 7 | #define QCOM_PHY_QMP_PCS_PCIE_V5_20_H_ |
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| 8 | |
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| 9 | /* Only for QMP V5_20 PHY - PCIe PCS registers */ |
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| 10 | #define QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2 0x00c |
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| 11 | #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c |
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| 12 | #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084 |
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| 13 | #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 |
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| 14 | #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0 |
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| 15 | #define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST 0x0e0 |
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| 16 | #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc |
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| 17 | #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 |
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| 18 | #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c |
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| 19 | #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184 |
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| 20 | #define QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2 0xa24 |
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| 21 | #define QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2 0xa28 |
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| 22 | |
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| 23 | #endif |
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| 24 | |
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