| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2023, Linaro Limited |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef QCOM_PHY_QMP_PCS_PCIE_V6_20_H_ |
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| 7 | #define QCOM_PHY_QMP_PCS_PCIE_V6_20_H_ |
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| 8 | |
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| 9 | /* Only for QMP V6_20 PHY - PCIE have different offsets than V5 */ |
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| 10 | #define QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2 0x00c |
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| 11 | #define QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG 0x018 |
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| 12 | #define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c |
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| 13 | #define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090 |
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| 14 | #define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0 |
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| 15 | #define QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME 0x0f0 |
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| 16 | #define QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME 0x0f4 |
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| 17 | #define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108 |
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| 18 | #define QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN 0x15c |
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| 19 | #define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1 0x17c |
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| 20 | #define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3 0x184 |
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| 21 | #define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5 0x18c |
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| 22 | #define QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5 0x1ac |
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| 23 | #define QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5 0x1c0 |
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| 24 | |
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| 25 | #endif |
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| 26 | |
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