1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* |
3 | * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd. |
4 | * Copyright (c) 2024 Collabora Ltd. |
5 | * |
6 | * Author: Algea Cao <algea.cao@rock-chips.com> |
7 | * Author: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> |
8 | */ |
9 | #include <linux/bitfield.h> |
10 | #include <linux/clk.h> |
11 | #include <linux/delay.h> |
12 | #include <linux/mfd/syscon.h> |
13 | #include <linux/module.h> |
14 | #include <linux/of.h> |
15 | #include <linux/of_platform.h> |
16 | #include <linux/phy/phy.h> |
17 | #include <linux/platform_device.h> |
18 | #include <linux/rational.h> |
19 | #include <linux/regmap.h> |
20 | #include <linux/reset.h> |
21 | |
22 | #define GRF_HDPTX_CON0 0x00 |
23 | #define HDPTX_I_PLL_EN BIT(7) |
24 | #define HDPTX_I_BIAS_EN BIT(6) |
25 | #define HDPTX_I_BGR_EN BIT(5) |
26 | #define GRF_HDPTX_STATUS 0x80 |
27 | #define HDPTX_O_PLL_LOCK_DONE BIT(3) |
28 | #define HDPTX_O_PHY_CLK_RDY BIT(2) |
29 | #define HDPTX_O_PHY_RDY BIT(1) |
30 | #define HDPTX_O_SB_RDY BIT(0) |
31 | |
32 | #define HDTPX_REG(_n, _min, _max) \ |
33 | ( \ |
34 | BUILD_BUG_ON_ZERO((0x##_n) < (0x##_min)) + \ |
35 | BUILD_BUG_ON_ZERO((0x##_n) > (0x##_max)) + \ |
36 | ((0x##_n) * 4) \ |
37 | ) |
38 | |
39 | #define CMN_REG(n) HDTPX_REG(n, 0000, 00a7) |
40 | #define SB_REG(n) HDTPX_REG(n, 0100, 0129) |
41 | #define LNTOP_REG(n) HDTPX_REG(n, 0200, 0229) |
42 | #define LANE_REG(n) HDTPX_REG(n, 0300, 062d) |
43 | |
44 | /* CMN_REG(0008) */ |
45 | #define LCPLL_EN_MASK BIT(6) |
46 | #define LCPLL_LCVCO_MODE_EN_MASK BIT(4) |
47 | /* CMN_REG(001e) */ |
48 | #define LCPLL_PI_EN_MASK BIT(5) |
49 | #define LCPLL_100M_CLK_EN_MASK BIT(0) |
50 | /* CMN_REG(0025) */ |
51 | #define LCPLL_PMS_IQDIV_RSTN BIT(4) |
52 | /* CMN_REG(0028) */ |
53 | #define LCPLL_SDC_FRAC_EN BIT(2) |
54 | #define LCPLL_SDC_FRAC_RSTN BIT(0) |
55 | /* CMN_REG(002d) */ |
56 | #define LCPLL_SDC_N_MASK GENMASK(3, 1) |
57 | /* CMN_REG(002e) */ |
58 | #define LCPLL_SDC_NUMBERATOR_MASK GENMASK(5, 0) |
59 | /* CMN_REG(002f) */ |
60 | #define LCPLL_SDC_DENOMINATOR_MASK GENMASK(7, 2) |
61 | #define LCPLL_SDC_NDIV_RSTN BIT(0) |
62 | /* CMN_REG(003d) */ |
63 | #define ROPLL_LCVCO_EN BIT(4) |
64 | /* CMN_REG(004e) */ |
65 | #define ROPLL_PI_EN BIT(5) |
66 | /* CMN_REG(005c) */ |
67 | #define ROPLL_PMS_IQDIV_RSTN BIT(5) |
68 | /* CMN_REG(005e) */ |
69 | #define ROPLL_SDM_EN_MASK BIT(6) |
70 | #define ROPLL_SDM_FRAC_EN_RBR BIT(3) |
71 | #define ROPLL_SDM_FRAC_EN_HBR BIT(2) |
72 | #define ROPLL_SDM_FRAC_EN_HBR2 BIT(1) |
73 | #define ROPLL_SDM_FRAC_EN_HBR3 BIT(0) |
74 | /* CMN_REG(0064) */ |
75 | #define ROPLL_SDM_NUM_SIGN_RBR_MASK BIT(3) |
76 | /* CMN_REG(0069) */ |
77 | #define ROPLL_SDC_N_RBR_MASK GENMASK(2, 0) |
78 | /* CMN_REG(0074) */ |
79 | #define ROPLL_SDC_NDIV_RSTN BIT(2) |
80 | #define ROPLL_SSC_EN BIT(0) |
81 | /* CMN_REG(0081) */ |
82 | #define OVRD_PLL_CD_CLK_EN BIT(8) |
83 | #define PLL_CD_HSCLK_EAST_EN BIT(0) |
84 | /* CMN_REG(0086) */ |
85 | #define PLL_PCG_POSTDIV_SEL_MASK GENMASK(7, 4) |
86 | #define PLL_PCG_CLK_SEL_MASK GENMASK(3, 1) |
87 | #define PLL_PCG_CLK_EN BIT(0) |
88 | /* CMN_REG(0087) */ |
89 | #define PLL_FRL_MODE_EN BIT(3) |
90 | #define PLL_TX_HS_CLK_EN BIT(2) |
91 | /* CMN_REG(0089) */ |
92 | #define LCPLL_ALONE_MODE BIT(1) |
93 | /* CMN_REG(0097) */ |
94 | #define DIG_CLK_SEL BIT(1) |
95 | #define ROPLL_REF BIT(1) |
96 | #define LCPLL_REF 0 |
97 | /* CMN_REG(0099) */ |
98 | #define CMN_ROPLL_ALONE_MODE BIT(2) |
99 | #define ROPLL_ALONE_MODE BIT(2) |
100 | /* CMN_REG(009a) */ |
101 | #define HS_SPEED_SEL BIT(0) |
102 | #define DIV_10_CLOCK BIT(0) |
103 | /* CMN_REG(009b) */ |
104 | #define IS_SPEED_SEL BIT(4) |
105 | #define LINK_SYMBOL_CLOCK BIT(4) |
106 | #define LINK_SYMBOL_CLOCK1_2 0 |
107 | |
108 | /* SB_REG(0102) */ |
109 | #define OVRD_SB_RXTERM_EN_MASK BIT(5) |
110 | #define SB_RXTERM_EN_MASK BIT(4) |
111 | #define ANA_SB_RXTERM_OFFSP_MASK GENMASK(3, 0) |
112 | /* SB_REG(0103) */ |
113 | #define ANA_SB_RXTERM_OFFSN_MASK GENMASK(6, 3) |
114 | #define OVRD_SB_RX_RESCAL_DONE_MASK BIT(1) |
115 | #define SB_RX_RESCAL_DONE_MASK BIT(0) |
116 | /* SB_REG(0104) */ |
117 | #define OVRD_SB_EN_MASK BIT(5) |
118 | #define SB_EN_MASK BIT(4) |
119 | /* SB_REG(0105) */ |
120 | #define OVRD_SB_EARC_CMDC_EN_MASK BIT(6) |
121 | #define SB_EARC_CMDC_EN_MASK BIT(5) |
122 | #define ANA_SB_TX_HLVL_PROG_MASK GENMASK(2, 0) |
123 | /* SB_REG(0106) */ |
124 | #define ANA_SB_TX_LLVL_PROG_MASK GENMASK(6, 4) |
125 | /* SB_REG(0109) */ |
126 | #define ANA_SB_DMRX_AFC_DIV_RATIO_MASK GENMASK(2, 0) |
127 | /* SB_REG(010f) */ |
128 | #define OVRD_SB_VREG_EN_MASK BIT(7) |
129 | #define SB_VREG_EN_MASK BIT(6) |
130 | #define OVRD_SB_VREG_LPF_BYPASS_MASK BIT(5) |
131 | #define SB_VREG_LPF_BYPASS_MASK BIT(4) |
132 | #define ANA_SB_VREG_GAIN_CTRL_MASK GENMASK(3, 0) |
133 | /* SB_REG(0110) */ |
134 | #define ANA_SB_VREG_REF_SEL_MASK BIT(0) |
135 | /* SB_REG(0113) */ |
136 | #define SB_RX_RCAL_OPT_CODE_MASK GENMASK(5, 4) |
137 | #define SB_RX_RTERM_CTRL_MASK GENMASK(3, 0) |
138 | /* SB_REG(0114) */ |
139 | #define SB_TG_SB_EN_DELAY_TIME_MASK GENMASK(5, 3) |
140 | #define SB_TG_RXTERM_EN_DELAY_TIME_MASK GENMASK(2, 0) |
141 | /* SB_REG(0115) */ |
142 | #define SB_READY_DELAY_TIME_MASK GENMASK(5, 3) |
143 | #define SB_TG_OSC_EN_DELAY_TIME_MASK GENMASK(2, 0) |
144 | /* SB_REG(0116) */ |
145 | #define AFC_RSTN_DELAY_TIME_MASK GENMASK(6, 4) |
146 | /* SB_REG(0117) */ |
147 | #define FAST_PULSE_TIME_MASK GENMASK(3, 0) |
148 | /* SB_REG(011b) */ |
149 | #define SB_EARC_SIG_DET_BYPASS_MASK BIT(4) |
150 | #define SB_AFC_TOL_MASK GENMASK(3, 0) |
151 | /* SB_REG(011f) */ |
152 | #define SB_PWM_AFC_CTRL_MASK GENMASK(7, 2) |
153 | #define SB_RCAL_RSTN_MASK BIT(1) |
154 | /* SB_REG(0120) */ |
155 | #define SB_EARC_EN_MASK BIT(1) |
156 | #define SB_EARC_AFC_EN_MASK BIT(2) |
157 | /* SB_REG(0123) */ |
158 | #define OVRD_SB_READY_MASK BIT(5) |
159 | #define SB_READY_MASK BIT(4) |
160 | |
161 | /* LNTOP_REG(0200) */ |
162 | #define PROTOCOL_SEL BIT(2) |
163 | #define HDMI_MODE BIT(2) |
164 | #define HDMI_TMDS_FRL_SEL BIT(1) |
165 | /* LNTOP_REG(0206) */ |
166 | #define DATA_BUS_SEL BIT(0) |
167 | #define DATA_BUS_36_40 BIT(0) |
168 | /* LNTOP_REG(0207) */ |
169 | #define LANE_EN 0xf |
170 | #define ALL_LANE_EN 0xf |
171 | |
172 | /* LANE_REG(0312) */ |
173 | #define LN0_TX_SER_RATE_SEL_RBR BIT(5) |
174 | #define LN0_TX_SER_RATE_SEL_HBR BIT(4) |
175 | #define LN0_TX_SER_RATE_SEL_HBR2 BIT(3) |
176 | #define LN0_TX_SER_RATE_SEL_HBR3 BIT(2) |
177 | /* LANE_REG(0412) */ |
178 | #define LN1_TX_SER_RATE_SEL_RBR BIT(5) |
179 | #define LN1_TX_SER_RATE_SEL_HBR BIT(4) |
180 | #define LN1_TX_SER_RATE_SEL_HBR2 BIT(3) |
181 | #define LN1_TX_SER_RATE_SEL_HBR3 BIT(2) |
182 | /* LANE_REG(0512) */ |
183 | #define LN2_TX_SER_RATE_SEL_RBR BIT(5) |
184 | #define LN2_TX_SER_RATE_SEL_HBR BIT(4) |
185 | #define LN2_TX_SER_RATE_SEL_HBR2 BIT(3) |
186 | #define LN2_TX_SER_RATE_SEL_HBR3 BIT(2) |
187 | /* LANE_REG(0612) */ |
188 | #define LN3_TX_SER_RATE_SEL_RBR BIT(5) |
189 | #define LN3_TX_SER_RATE_SEL_HBR BIT(4) |
190 | #define LN3_TX_SER_RATE_SEL_HBR2 BIT(3) |
191 | #define LN3_TX_SER_RATE_SEL_HBR3 BIT(2) |
192 | |
193 | struct lcpll_config { |
194 | u32 bit_rate; |
195 | u8 lcvco_mode_en; |
196 | u8 pi_en; |
197 | u8 clk_en_100m; |
198 | u8 pms_mdiv; |
199 | u8 pms_mdiv_afc; |
200 | u8 pms_pdiv; |
201 | u8 pms_refdiv; |
202 | u8 pms_sdiv; |
203 | u8 pi_cdiv_rstn; |
204 | u8 pi_cdiv_sel; |
205 | u8 sdm_en; |
206 | u8 sdm_rstn; |
207 | u8 sdc_frac_en; |
208 | u8 sdc_rstn; |
209 | u8 sdm_deno; |
210 | u8 sdm_num_sign; |
211 | u8 sdm_num; |
212 | u8 sdc_n; |
213 | u8 sdc_n2; |
214 | u8 sdc_num; |
215 | u8 sdc_deno; |
216 | u8 sdc_ndiv_rstn; |
217 | u8 ssc_en; |
218 | u8 ssc_fm_dev; |
219 | u8 ssc_fm_freq; |
220 | u8 ssc_clk_div_sel; |
221 | u8 cd_tx_ser_rate_sel; |
222 | }; |
223 | |
224 | struct ropll_config { |
225 | u32 bit_rate; |
226 | u8 pms_mdiv; |
227 | u8 pms_mdiv_afc; |
228 | u8 pms_pdiv; |
229 | u8 pms_refdiv; |
230 | u8 pms_sdiv; |
231 | u8 pms_iqdiv_rstn; |
232 | u8 ref_clk_sel; |
233 | u8 sdm_en; |
234 | u8 sdm_rstn; |
235 | u8 sdc_frac_en; |
236 | u8 sdc_rstn; |
237 | u8 sdm_clk_div; |
238 | u8 sdm_deno; |
239 | u8 sdm_num_sign; |
240 | u8 sdm_num; |
241 | u8 sdc_n; |
242 | u8 sdc_num; |
243 | u8 sdc_deno; |
244 | u8 sdc_ndiv_rstn; |
245 | u8 ssc_en; |
246 | u8 ssc_fm_dev; |
247 | u8 ssc_fm_freq; |
248 | u8 ssc_clk_div_sel; |
249 | u8 ana_cpp_ctrl; |
250 | u8 ana_lpf_c_sel; |
251 | u8 cd_tx_ser_rate_sel; |
252 | }; |
253 | |
254 | enum rk_hdptx_reset { |
255 | RST_PHY = 0, |
256 | RST_APB, |
257 | RST_INIT, |
258 | RST_CMN, |
259 | RST_LANE, |
260 | RST_ROPLL, |
261 | RST_LCPLL, |
262 | RST_MAX |
263 | }; |
264 | |
265 | struct rk_hdptx_phy { |
266 | struct device *dev; |
267 | struct regmap *regmap; |
268 | struct regmap *grf; |
269 | |
270 | struct phy *phy; |
271 | struct phy_config *phy_cfg; |
272 | struct clk_bulk_data *clks; |
273 | int nr_clks; |
274 | struct reset_control_bulk_data rsts[RST_MAX]; |
275 | }; |
276 | |
277 | static const struct ropll_config ropll_tmds_cfg[] = { |
278 | { 5940000, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, |
279 | 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, |
280 | { 3712500, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, |
281 | 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, |
282 | { 2970000, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, |
283 | 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, |
284 | { 1620000, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10, |
285 | 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, |
286 | { 1856250, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, |
287 | 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, |
288 | { 1540000, 193, 193, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 193, 1, 32, 2, 1, |
289 | 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, |
290 | { 1485000, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5, |
291 | 0x10, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, |
292 | { 1462500, 122, 122, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 2, 1, 1, |
293 | 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, |
294 | { 1190000, 149, 149, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 149, 1, 16, 2, 1, 1, |
295 | 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, |
296 | { 1065000, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1, |
297 | 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, |
298 | { 1080000, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, |
299 | 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, |
300 | { 855000, 214, 214, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 214, 1, 16, 2, 1, |
301 | 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, |
302 | { 835000, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0, |
303 | 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, |
304 | { 928125, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, |
305 | 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, |
306 | { 742500, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, |
307 | 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, |
308 | { 650000, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1, |
309 | 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, |
310 | { 337500, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5, |
311 | 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, |
312 | { 400000, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, |
313 | 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, |
314 | { 270000, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, |
315 | 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, |
316 | { 251750, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1, 1, |
317 | 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, |
318 | }; |
319 | |
320 | static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] = { |
321 | REG_SEQ0(CMN_REG(0009), 0x0c), |
322 | REG_SEQ0(CMN_REG(000a), 0x83), |
323 | REG_SEQ0(CMN_REG(000b), 0x06), |
324 | REG_SEQ0(CMN_REG(000c), 0x20), |
325 | REG_SEQ0(CMN_REG(000d), 0xb8), |
326 | REG_SEQ0(CMN_REG(000e), 0x0f), |
327 | REG_SEQ0(CMN_REG(000f), 0x0f), |
328 | REG_SEQ0(CMN_REG(0010), 0x04), |
329 | REG_SEQ0(CMN_REG(0011), 0x00), |
330 | REG_SEQ0(CMN_REG(0012), 0x26), |
331 | REG_SEQ0(CMN_REG(0013), 0x22), |
332 | REG_SEQ0(CMN_REG(0014), 0x24), |
333 | REG_SEQ0(CMN_REG(0015), 0x77), |
334 | REG_SEQ0(CMN_REG(0016), 0x08), |
335 | REG_SEQ0(CMN_REG(0017), 0x00), |
336 | REG_SEQ0(CMN_REG(0018), 0x04), |
337 | REG_SEQ0(CMN_REG(0019), 0x48), |
338 | REG_SEQ0(CMN_REG(001a), 0x01), |
339 | REG_SEQ0(CMN_REG(001b), 0x00), |
340 | REG_SEQ0(CMN_REG(001c), 0x01), |
341 | REG_SEQ0(CMN_REG(001d), 0x64), |
342 | REG_SEQ0(CMN_REG(001f), 0x00), |
343 | REG_SEQ0(CMN_REG(0026), 0x53), |
344 | REG_SEQ0(CMN_REG(0029), 0x01), |
345 | REG_SEQ0(CMN_REG(0030), 0x00), |
346 | REG_SEQ0(CMN_REG(0031), 0x20), |
347 | REG_SEQ0(CMN_REG(0032), 0x30), |
348 | REG_SEQ0(CMN_REG(0033), 0x0b), |
349 | REG_SEQ0(CMN_REG(0034), 0x23), |
350 | REG_SEQ0(CMN_REG(0035), 0x00), |
351 | REG_SEQ0(CMN_REG(0038), 0x00), |
352 | REG_SEQ0(CMN_REG(0039), 0x00), |
353 | REG_SEQ0(CMN_REG(003a), 0x00), |
354 | REG_SEQ0(CMN_REG(003b), 0x00), |
355 | REG_SEQ0(CMN_REG(003c), 0x80), |
356 | REG_SEQ0(CMN_REG(003e), 0x0c), |
357 | REG_SEQ0(CMN_REG(003f), 0x83), |
358 | REG_SEQ0(CMN_REG(0040), 0x06), |
359 | REG_SEQ0(CMN_REG(0041), 0x20), |
360 | REG_SEQ0(CMN_REG(0042), 0xb8), |
361 | REG_SEQ0(CMN_REG(0043), 0x00), |
362 | REG_SEQ0(CMN_REG(0044), 0x46), |
363 | REG_SEQ0(CMN_REG(0045), 0x24), |
364 | REG_SEQ0(CMN_REG(0046), 0xff), |
365 | REG_SEQ0(CMN_REG(0047), 0x00), |
366 | REG_SEQ0(CMN_REG(0048), 0x44), |
367 | REG_SEQ0(CMN_REG(0049), 0xfa), |
368 | REG_SEQ0(CMN_REG(004a), 0x08), |
369 | REG_SEQ0(CMN_REG(004b), 0x00), |
370 | REG_SEQ0(CMN_REG(004c), 0x01), |
371 | REG_SEQ0(CMN_REG(004d), 0x64), |
372 | REG_SEQ0(CMN_REG(004e), 0x14), |
373 | REG_SEQ0(CMN_REG(004f), 0x00), |
374 | REG_SEQ0(CMN_REG(0050), 0x00), |
375 | REG_SEQ0(CMN_REG(005d), 0x0c), |
376 | REG_SEQ0(CMN_REG(005f), 0x01), |
377 | REG_SEQ0(CMN_REG(006b), 0x04), |
378 | REG_SEQ0(CMN_REG(0073), 0x30), |
379 | REG_SEQ0(CMN_REG(0074), 0x00), |
380 | REG_SEQ0(CMN_REG(0075), 0x20), |
381 | REG_SEQ0(CMN_REG(0076), 0x30), |
382 | REG_SEQ0(CMN_REG(0077), 0x08), |
383 | REG_SEQ0(CMN_REG(0078), 0x0c), |
384 | REG_SEQ0(CMN_REG(0079), 0x00), |
385 | REG_SEQ0(CMN_REG(007b), 0x00), |
386 | REG_SEQ0(CMN_REG(007c), 0x00), |
387 | REG_SEQ0(CMN_REG(007d), 0x00), |
388 | REG_SEQ0(CMN_REG(007e), 0x00), |
389 | REG_SEQ0(CMN_REG(007f), 0x00), |
390 | REG_SEQ0(CMN_REG(0080), 0x00), |
391 | REG_SEQ0(CMN_REG(0081), 0x09), |
392 | REG_SEQ0(CMN_REG(0082), 0x04), |
393 | REG_SEQ0(CMN_REG(0083), 0x24), |
394 | REG_SEQ0(CMN_REG(0084), 0x20), |
395 | REG_SEQ0(CMN_REG(0085), 0x03), |
396 | REG_SEQ0(CMN_REG(0086), 0x01), |
397 | REG_SEQ0(CMN_REG(0087), 0x0c), |
398 | REG_SEQ0(CMN_REG(008a), 0x55), |
399 | REG_SEQ0(CMN_REG(008b), 0x25), |
400 | REG_SEQ0(CMN_REG(008c), 0x2c), |
401 | REG_SEQ0(CMN_REG(008d), 0x22), |
402 | REG_SEQ0(CMN_REG(008e), 0x14), |
403 | REG_SEQ0(CMN_REG(008f), 0x20), |
404 | REG_SEQ0(CMN_REG(0090), 0x00), |
405 | REG_SEQ0(CMN_REG(0091), 0x00), |
406 | REG_SEQ0(CMN_REG(0092), 0x00), |
407 | REG_SEQ0(CMN_REG(0093), 0x00), |
408 | REG_SEQ0(CMN_REG(009a), 0x11), |
409 | REG_SEQ0(CMN_REG(009b), 0x10), |
410 | }; |
411 | |
412 | static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = { |
413 | REG_SEQ0(CMN_REG(0008), 0x00), |
414 | REG_SEQ0(CMN_REG(0011), 0x01), |
415 | REG_SEQ0(CMN_REG(0017), 0x20), |
416 | REG_SEQ0(CMN_REG(001e), 0x14), |
417 | REG_SEQ0(CMN_REG(0020), 0x00), |
418 | REG_SEQ0(CMN_REG(0021), 0x00), |
419 | REG_SEQ0(CMN_REG(0022), 0x11), |
420 | REG_SEQ0(CMN_REG(0023), 0x00), |
421 | REG_SEQ0(CMN_REG(0024), 0x00), |
422 | REG_SEQ0(CMN_REG(0025), 0x53), |
423 | REG_SEQ0(CMN_REG(0026), 0x00), |
424 | REG_SEQ0(CMN_REG(0027), 0x00), |
425 | REG_SEQ0(CMN_REG(0028), 0x01), |
426 | REG_SEQ0(CMN_REG(002a), 0x00), |
427 | REG_SEQ0(CMN_REG(002b), 0x00), |
428 | REG_SEQ0(CMN_REG(002c), 0x00), |
429 | REG_SEQ0(CMN_REG(002d), 0x00), |
430 | REG_SEQ0(CMN_REG(002e), 0x04), |
431 | REG_SEQ0(CMN_REG(002f), 0x00), |
432 | REG_SEQ0(CMN_REG(0030), 0x20), |
433 | REG_SEQ0(CMN_REG(0031), 0x30), |
434 | REG_SEQ0(CMN_REG(0032), 0x0b), |
435 | REG_SEQ0(CMN_REG(0033), 0x23), |
436 | REG_SEQ0(CMN_REG(0034), 0x00), |
437 | REG_SEQ0(CMN_REG(003d), 0x40), |
438 | REG_SEQ0(CMN_REG(0042), 0x78), |
439 | REG_SEQ0(CMN_REG(004e), 0x34), |
440 | REG_SEQ0(CMN_REG(005c), 0x25), |
441 | REG_SEQ0(CMN_REG(005e), 0x4f), |
442 | REG_SEQ0(CMN_REG(0074), 0x04), |
443 | REG_SEQ0(CMN_REG(0081), 0x01), |
444 | REG_SEQ0(CMN_REG(0087), 0x04), |
445 | REG_SEQ0(CMN_REG(0089), 0x00), |
446 | REG_SEQ0(CMN_REG(0095), 0x00), |
447 | REG_SEQ0(CMN_REG(0097), 0x02), |
448 | REG_SEQ0(CMN_REG(0099), 0x04), |
449 | REG_SEQ0(CMN_REG(009b), 0x00), |
450 | }; |
451 | |
452 | static const struct reg_sequence rk_hdtpx_common_sb_init_seq[] = { |
453 | REG_SEQ0(SB_REG(0114), 0x00), |
454 | REG_SEQ0(SB_REG(0115), 0x00), |
455 | REG_SEQ0(SB_REG(0116), 0x00), |
456 | REG_SEQ0(SB_REG(0117), 0x00), |
457 | }; |
458 | |
459 | static const struct reg_sequence rk_hdtpx_tmds_lntop_highbr_seq[] = { |
460 | REG_SEQ0(LNTOP_REG(0201), 0x00), |
461 | REG_SEQ0(LNTOP_REG(0202), 0x00), |
462 | REG_SEQ0(LNTOP_REG(0203), 0x0f), |
463 | REG_SEQ0(LNTOP_REG(0204), 0xff), |
464 | REG_SEQ0(LNTOP_REG(0205), 0xff), |
465 | }; |
466 | |
467 | static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] = { |
468 | REG_SEQ0(LNTOP_REG(0201), 0x07), |
469 | REG_SEQ0(LNTOP_REG(0202), 0xc1), |
470 | REG_SEQ0(LNTOP_REG(0203), 0xf0), |
471 | REG_SEQ0(LNTOP_REG(0204), 0x7c), |
472 | REG_SEQ0(LNTOP_REG(0205), 0x1f), |
473 | }; |
474 | |
475 | static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] = { |
476 | REG_SEQ0(LANE_REG(0303), 0x0c), |
477 | REG_SEQ0(LANE_REG(0307), 0x20), |
478 | REG_SEQ0(LANE_REG(030a), 0x17), |
479 | REG_SEQ0(LANE_REG(030b), 0x77), |
480 | REG_SEQ0(LANE_REG(030c), 0x77), |
481 | REG_SEQ0(LANE_REG(030d), 0x77), |
482 | REG_SEQ0(LANE_REG(030e), 0x38), |
483 | REG_SEQ0(LANE_REG(0310), 0x03), |
484 | REG_SEQ0(LANE_REG(0311), 0x0f), |
485 | REG_SEQ0(LANE_REG(0316), 0x02), |
486 | REG_SEQ0(LANE_REG(031b), 0x01), |
487 | REG_SEQ0(LANE_REG(031f), 0x15), |
488 | REG_SEQ0(LANE_REG(0320), 0xa0), |
489 | REG_SEQ0(LANE_REG(0403), 0x0c), |
490 | REG_SEQ0(LANE_REG(0407), 0x20), |
491 | REG_SEQ0(LANE_REG(040a), 0x17), |
492 | REG_SEQ0(LANE_REG(040b), 0x77), |
493 | REG_SEQ0(LANE_REG(040c), 0x77), |
494 | REG_SEQ0(LANE_REG(040d), 0x77), |
495 | REG_SEQ0(LANE_REG(040e), 0x38), |
496 | REG_SEQ0(LANE_REG(0410), 0x03), |
497 | REG_SEQ0(LANE_REG(0411), 0x0f), |
498 | REG_SEQ0(LANE_REG(0416), 0x02), |
499 | REG_SEQ0(LANE_REG(041b), 0x01), |
500 | REG_SEQ0(LANE_REG(041f), 0x15), |
501 | REG_SEQ0(LANE_REG(0420), 0xa0), |
502 | REG_SEQ0(LANE_REG(0503), 0x0c), |
503 | REG_SEQ0(LANE_REG(0507), 0x20), |
504 | REG_SEQ0(LANE_REG(050a), 0x17), |
505 | REG_SEQ0(LANE_REG(050b), 0x77), |
506 | REG_SEQ0(LANE_REG(050c), 0x77), |
507 | REG_SEQ0(LANE_REG(050d), 0x77), |
508 | REG_SEQ0(LANE_REG(050e), 0x38), |
509 | REG_SEQ0(LANE_REG(0510), 0x03), |
510 | REG_SEQ0(LANE_REG(0511), 0x0f), |
511 | REG_SEQ0(LANE_REG(0516), 0x02), |
512 | REG_SEQ0(LANE_REG(051b), 0x01), |
513 | REG_SEQ0(LANE_REG(051f), 0x15), |
514 | REG_SEQ0(LANE_REG(0520), 0xa0), |
515 | REG_SEQ0(LANE_REG(0603), 0x0c), |
516 | REG_SEQ0(LANE_REG(0607), 0x20), |
517 | REG_SEQ0(LANE_REG(060a), 0x17), |
518 | REG_SEQ0(LANE_REG(060b), 0x77), |
519 | REG_SEQ0(LANE_REG(060c), 0x77), |
520 | REG_SEQ0(LANE_REG(060d), 0x77), |
521 | REG_SEQ0(LANE_REG(060e), 0x38), |
522 | REG_SEQ0(LANE_REG(0610), 0x03), |
523 | REG_SEQ0(LANE_REG(0611), 0x0f), |
524 | REG_SEQ0(LANE_REG(0616), 0x02), |
525 | REG_SEQ0(LANE_REG(061b), 0x01), |
526 | REG_SEQ0(LANE_REG(061f), 0x15), |
527 | REG_SEQ0(LANE_REG(0620), 0xa0), |
528 | }; |
529 | |
530 | static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] = { |
531 | REG_SEQ0(LANE_REG(0312), 0x00), |
532 | REG_SEQ0(LANE_REG(031e), 0x00), |
533 | REG_SEQ0(LANE_REG(0412), 0x00), |
534 | REG_SEQ0(LANE_REG(041e), 0x00), |
535 | REG_SEQ0(LANE_REG(0512), 0x00), |
536 | REG_SEQ0(LANE_REG(051e), 0x00), |
537 | REG_SEQ0(LANE_REG(0612), 0x00), |
538 | REG_SEQ0(LANE_REG(061e), 0x08), |
539 | REG_SEQ0(LANE_REG(0303), 0x2f), |
540 | REG_SEQ0(LANE_REG(0403), 0x2f), |
541 | REG_SEQ0(LANE_REG(0503), 0x2f), |
542 | REG_SEQ0(LANE_REG(0603), 0x2f), |
543 | REG_SEQ0(LANE_REG(0305), 0x03), |
544 | REG_SEQ0(LANE_REG(0405), 0x03), |
545 | REG_SEQ0(LANE_REG(0505), 0x03), |
546 | REG_SEQ0(LANE_REG(0605), 0x03), |
547 | REG_SEQ0(LANE_REG(0306), 0x1c), |
548 | REG_SEQ0(LANE_REG(0406), 0x1c), |
549 | REG_SEQ0(LANE_REG(0506), 0x1c), |
550 | REG_SEQ0(LANE_REG(0606), 0x1c), |
551 | }; |
552 | |
553 | static bool rk_hdptx_phy_is_rw_reg(struct device *dev, unsigned int reg) |
554 | { |
555 | switch (reg) { |
556 | case 0x0000 ... 0x029c: |
557 | case 0x0400 ... 0x04a4: |
558 | case 0x0800 ... 0x08a4: |
559 | case 0x0c00 ... 0x0cb4: |
560 | case 0x1000 ... 0x10b4: |
561 | case 0x1400 ... 0x14b4: |
562 | case 0x1800 ... 0x18b4: |
563 | return true; |
564 | } |
565 | |
566 | return false; |
567 | } |
568 | |
569 | static const struct regmap_config rk_hdptx_phy_regmap_config = { |
570 | .reg_bits = 32, |
571 | .reg_stride = 4, |
572 | .val_bits = 32, |
573 | .writeable_reg = rk_hdptx_phy_is_rw_reg, |
574 | .readable_reg = rk_hdptx_phy_is_rw_reg, |
575 | .fast_io = true, |
576 | .max_register = 0x18b4, |
577 | }; |
578 | |
579 | #define rk_hdptx_multi_reg_write(hdptx, seq) \ |
580 | regmap_multi_reg_write((hdptx)->regmap, seq, ARRAY_SIZE(seq)) |
581 | |
582 | static void rk_hdptx_pre_power_up(struct rk_hdptx_phy *hdptx) |
583 | { |
584 | u32 val; |
585 | |
586 | reset_control_assert(rstc: hdptx->rsts[RST_APB].rstc); |
587 | usleep_range(min: 20, max: 25); |
588 | reset_control_deassert(rstc: hdptx->rsts[RST_APB].rstc); |
589 | |
590 | reset_control_assert(rstc: hdptx->rsts[RST_LANE].rstc); |
591 | reset_control_assert(rstc: hdptx->rsts[RST_CMN].rstc); |
592 | reset_control_assert(rstc: hdptx->rsts[RST_INIT].rstc); |
593 | |
594 | val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16; |
595 | regmap_write(map: hdptx->grf, GRF_HDPTX_CON0, val); |
596 | } |
597 | |
598 | static int rk_hdptx_post_enable_lane(struct rk_hdptx_phy *hdptx) |
599 | { |
600 | u32 val; |
601 | int ret; |
602 | |
603 | reset_control_deassert(rstc: hdptx->rsts[RST_LANE].rstc); |
604 | |
605 | val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 | |
606 | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN; |
607 | regmap_write(map: hdptx->grf, GRF_HDPTX_CON0, val); |
608 | |
609 | ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val, |
610 | (val & HDPTX_O_PHY_RDY) && |
611 | (val & HDPTX_O_PLL_LOCK_DONE), |
612 | 100, 5000); |
613 | if (ret) { |
614 | dev_err(hdptx->dev, "Failed to get PHY lane lock: %d\n" , ret); |
615 | return ret; |
616 | } |
617 | |
618 | dev_dbg(hdptx->dev, "PHY lane locked\n" ); |
619 | |
620 | return 0; |
621 | } |
622 | |
623 | static int rk_hdptx_post_enable_pll(struct rk_hdptx_phy *hdptx) |
624 | { |
625 | u32 val; |
626 | int ret; |
627 | |
628 | val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 | |
629 | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN; |
630 | regmap_write(map: hdptx->grf, GRF_HDPTX_CON0, val); |
631 | |
632 | usleep_range(min: 10, max: 15); |
633 | reset_control_deassert(rstc: hdptx->rsts[RST_INIT].rstc); |
634 | |
635 | usleep_range(min: 10, max: 15); |
636 | val = HDPTX_I_PLL_EN << 16 | HDPTX_I_PLL_EN; |
637 | regmap_write(map: hdptx->grf, GRF_HDPTX_CON0, val); |
638 | |
639 | usleep_range(min: 10, max: 15); |
640 | reset_control_deassert(rstc: hdptx->rsts[RST_CMN].rstc); |
641 | |
642 | ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val, |
643 | val & HDPTX_O_PHY_CLK_RDY, 20, 400); |
644 | if (ret) { |
645 | dev_err(hdptx->dev, "Failed to get PHY clk ready: %d\n" , ret); |
646 | return ret; |
647 | } |
648 | |
649 | dev_dbg(hdptx->dev, "PHY clk ready\n" ); |
650 | |
651 | return 0; |
652 | } |
653 | |
654 | static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx) |
655 | { |
656 | u32 val; |
657 | |
658 | /* reset phy and apb, or phy locked flag may keep 1 */ |
659 | reset_control_assert(rstc: hdptx->rsts[RST_PHY].rstc); |
660 | usleep_range(min: 20, max: 30); |
661 | reset_control_deassert(rstc: hdptx->rsts[RST_PHY].rstc); |
662 | |
663 | reset_control_assert(rstc: hdptx->rsts[RST_APB].rstc); |
664 | usleep_range(min: 20, max: 30); |
665 | reset_control_deassert(rstc: hdptx->rsts[RST_APB].rstc); |
666 | |
667 | regmap_write(map: hdptx->regmap, LANE_REG(0300), val: 0x82); |
668 | regmap_write(map: hdptx->regmap, SB_REG(010f), val: 0xc1); |
669 | regmap_write(map: hdptx->regmap, SB_REG(0110), val: 0x1); |
670 | regmap_write(map: hdptx->regmap, LANE_REG(0301), val: 0x80); |
671 | regmap_write(map: hdptx->regmap, LANE_REG(0401), val: 0x80); |
672 | regmap_write(map: hdptx->regmap, LANE_REG(0501), val: 0x80); |
673 | regmap_write(map: hdptx->regmap, LANE_REG(0601), val: 0x80); |
674 | |
675 | reset_control_assert(rstc: hdptx->rsts[RST_LANE].rstc); |
676 | reset_control_assert(rstc: hdptx->rsts[RST_CMN].rstc); |
677 | reset_control_assert(rstc: hdptx->rsts[RST_INIT].rstc); |
678 | |
679 | val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16; |
680 | regmap_write(map: hdptx->grf, GRF_HDPTX_CON0, val); |
681 | } |
682 | |
683 | static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate, |
684 | struct ropll_config *cfg) |
685 | { |
686 | const unsigned int fout = data_rate / 2, fref = 24000; |
687 | unsigned long k = 0, lc, k_sub, lc_sub; |
688 | unsigned int fvco, sdc; |
689 | u32 mdiv, sdiv, n = 8; |
690 | |
691 | if (fout > 0xfffffff) |
692 | return false; |
693 | |
694 | for (sdiv = 16; sdiv >= 1; sdiv--) { |
695 | if (sdiv % 2 && sdiv != 1) |
696 | continue; |
697 | |
698 | fvco = fout * sdiv; |
699 | |
700 | if (fvco < 2000000 || fvco > 4000000) |
701 | continue; |
702 | |
703 | mdiv = DIV_ROUND_UP(fvco, fref); |
704 | if (mdiv < 20 || mdiv > 255) |
705 | continue; |
706 | |
707 | if (fref * mdiv - fvco) { |
708 | for (sdc = 264000; sdc <= 750000; sdc += fref) |
709 | if (sdc * n > fref * mdiv) |
710 | break; |
711 | |
712 | if (sdc > 750000) |
713 | continue; |
714 | |
715 | rational_best_approximation(given_numerator: fref * mdiv - fvco, |
716 | given_denominator: sdc / 16, |
717 | GENMASK(6, 0), |
718 | GENMASK(7, 0), |
719 | best_numerator: &k, best_denominator: &lc); |
720 | |
721 | rational_best_approximation(given_numerator: sdc * n - fref * mdiv, |
722 | given_denominator: sdc, |
723 | GENMASK(6, 0), |
724 | GENMASK(7, 0), |
725 | best_numerator: &k_sub, best_denominator: &lc_sub); |
726 | } |
727 | |
728 | break; |
729 | } |
730 | |
731 | if (sdiv < 1) |
732 | return false; |
733 | |
734 | if (cfg) { |
735 | cfg->pms_mdiv = mdiv; |
736 | cfg->pms_mdiv_afc = mdiv; |
737 | cfg->pms_pdiv = 1; |
738 | cfg->pms_refdiv = 1; |
739 | cfg->pms_sdiv = sdiv - 1; |
740 | |
741 | cfg->sdm_en = k > 0 ? 1 : 0; |
742 | if (cfg->sdm_en) { |
743 | cfg->sdm_deno = lc; |
744 | cfg->sdm_num_sign = 1; |
745 | cfg->sdm_num = k; |
746 | cfg->sdc_n = n - 3; |
747 | cfg->sdc_num = k_sub; |
748 | cfg->sdc_deno = lc_sub; |
749 | } |
750 | } |
751 | |
752 | return true; |
753 | } |
754 | |
755 | static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx, |
756 | unsigned int rate) |
757 | { |
758 | const struct ropll_config *cfg = NULL; |
759 | struct ropll_config rc = {0}; |
760 | int i; |
761 | |
762 | for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) |
763 | if (rate == ropll_tmds_cfg[i].bit_rate) { |
764 | cfg = &ropll_tmds_cfg[i]; |
765 | break; |
766 | } |
767 | |
768 | if (!cfg) { |
769 | if (rk_hdptx_phy_clk_pll_calc(data_rate: rate, cfg: &rc)) { |
770 | cfg = &rc; |
771 | } else { |
772 | dev_err(hdptx->dev, "%s cannot find pll cfg\n" , __func__); |
773 | return -EINVAL; |
774 | } |
775 | } |
776 | |
777 | dev_dbg(hdptx->dev, "mdiv=%u, sdiv=%u, sdm_en=%u, k_sign=%u, k=%u, lc=%u\n" , |
778 | cfg->pms_mdiv, cfg->pms_sdiv + 1, cfg->sdm_en, |
779 | cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno); |
780 | |
781 | rk_hdptx_pre_power_up(hdptx); |
782 | |
783 | reset_control_assert(rstc: hdptx->rsts[RST_ROPLL].rstc); |
784 | usleep_range(min: 20, max: 30); |
785 | reset_control_deassert(rstc: hdptx->rsts[RST_ROPLL].rstc); |
786 | |
787 | rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq); |
788 | rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_cmn_init_seq); |
789 | |
790 | regmap_write(map: hdptx->regmap, CMN_REG(0051), val: cfg->pms_mdiv); |
791 | regmap_write(map: hdptx->regmap, CMN_REG(0055), val: cfg->pms_mdiv_afc); |
792 | regmap_write(map: hdptx->regmap, CMN_REG(0059), |
793 | val: (cfg->pms_pdiv << 4) | cfg->pms_refdiv); |
794 | regmap_write(map: hdptx->regmap, CMN_REG(005a), val: cfg->pms_sdiv << 4); |
795 | |
796 | regmap_update_bits(map: hdptx->regmap, CMN_REG(005e), ROPLL_SDM_EN_MASK, |
797 | FIELD_PREP(ROPLL_SDM_EN_MASK, cfg->sdm_en)); |
798 | if (!cfg->sdm_en) |
799 | regmap_update_bits(map: hdptx->regmap, CMN_REG(005e), mask: 0xf, val: 0); |
800 | |
801 | regmap_update_bits(map: hdptx->regmap, CMN_REG(0064), ROPLL_SDM_NUM_SIGN_RBR_MASK, |
802 | FIELD_PREP(ROPLL_SDM_NUM_SIGN_RBR_MASK, cfg->sdm_num_sign)); |
803 | |
804 | regmap_write(map: hdptx->regmap, CMN_REG(0060), val: cfg->sdm_deno); |
805 | regmap_write(map: hdptx->regmap, CMN_REG(0065), val: cfg->sdm_num); |
806 | |
807 | regmap_update_bits(map: hdptx->regmap, CMN_REG(0069), ROPLL_SDC_N_RBR_MASK, |
808 | FIELD_PREP(ROPLL_SDC_N_RBR_MASK, cfg->sdc_n)); |
809 | |
810 | regmap_write(map: hdptx->regmap, CMN_REG(006c), val: cfg->sdc_num); |
811 | regmap_write(map: hdptx->regmap, CMN_REG(0070), val: cfg->sdc_deno); |
812 | |
813 | regmap_update_bits(map: hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK, |
814 | FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv)); |
815 | |
816 | regmap_update_bits(map: hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN, |
817 | PLL_PCG_CLK_EN); |
818 | |
819 | return rk_hdptx_post_enable_pll(hdptx); |
820 | } |
821 | |
822 | static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx, |
823 | unsigned int rate) |
824 | { |
825 | u32 val; |
826 | int ret; |
827 | |
828 | ret = regmap_read(map: hdptx->grf, GRF_HDPTX_STATUS, val: &val); |
829 | if (ret) |
830 | return ret; |
831 | |
832 | if (!(val & HDPTX_O_PLL_LOCK_DONE)) { |
833 | ret = rk_hdptx_ropll_tmds_cmn_config(hdptx, rate); |
834 | if (ret) |
835 | return ret; |
836 | } |
837 | |
838 | rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq); |
839 | |
840 | regmap_write(map: hdptx->regmap, LNTOP_REG(0200), val: 0x06); |
841 | |
842 | if (rate >= 3400000) { |
843 | /* For 1/40 bitrate clk */ |
844 | rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq); |
845 | } else { |
846 | /* For 1/10 bitrate clk */ |
847 | rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_lowbr_seq); |
848 | } |
849 | |
850 | regmap_write(map: hdptx->regmap, LNTOP_REG(0206), val: 0x07); |
851 | regmap_write(map: hdptx->regmap, LNTOP_REG(0207), val: 0x0f); |
852 | |
853 | rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq); |
854 | rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lane_init_seq); |
855 | |
856 | return rk_hdptx_post_enable_lane(hdptx); |
857 | } |
858 | |
859 | static int rk_hdptx_phy_power_on(struct phy *phy) |
860 | { |
861 | struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); |
862 | int ret, bus_width = phy_get_bus_width(phy: hdptx->phy); |
863 | /* |
864 | * FIXME: Temporary workaround to pass pixel_clk_rate |
865 | * from the HDMI bridge driver until phy_configure_opts_hdmi |
866 | * becomes available in the PHY API. |
867 | */ |
868 | unsigned int rate = bus_width & 0xfffffff; |
869 | |
870 | dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n" , |
871 | __func__, bus_width, rate); |
872 | |
873 | ret = pm_runtime_resume_and_get(dev: hdptx->dev); |
874 | if (ret) { |
875 | dev_err(hdptx->dev, "Failed to resume phy: %d\n" , ret); |
876 | return ret; |
877 | } |
878 | |
879 | ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate); |
880 | if (ret) |
881 | pm_runtime_put(dev: hdptx->dev); |
882 | |
883 | return ret; |
884 | } |
885 | |
886 | static int rk_hdptx_phy_power_off(struct phy *phy) |
887 | { |
888 | struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); |
889 | u32 val; |
890 | int ret; |
891 | |
892 | ret = regmap_read(map: hdptx->grf, GRF_HDPTX_STATUS, val: &val); |
893 | if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE)) |
894 | rk_hdptx_phy_disable(hdptx); |
895 | |
896 | pm_runtime_put(dev: hdptx->dev); |
897 | |
898 | return ret; |
899 | } |
900 | |
901 | static const struct phy_ops rk_hdptx_phy_ops = { |
902 | .power_on = rk_hdptx_phy_power_on, |
903 | .power_off = rk_hdptx_phy_power_off, |
904 | .owner = THIS_MODULE, |
905 | }; |
906 | |
907 | static int rk_hdptx_phy_runtime_suspend(struct device *dev) |
908 | { |
909 | struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev); |
910 | |
911 | clk_bulk_disable_unprepare(num_clks: hdptx->nr_clks, clks: hdptx->clks); |
912 | |
913 | return 0; |
914 | } |
915 | |
916 | static int rk_hdptx_phy_runtime_resume(struct device *dev) |
917 | { |
918 | struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev); |
919 | int ret; |
920 | |
921 | ret = clk_bulk_prepare_enable(num_clks: hdptx->nr_clks, clks: hdptx->clks); |
922 | if (ret) |
923 | dev_err(hdptx->dev, "Failed to enable clocks: %d\n" , ret); |
924 | |
925 | return ret; |
926 | } |
927 | |
928 | static int rk_hdptx_phy_probe(struct platform_device *pdev) |
929 | { |
930 | struct phy_provider *phy_provider; |
931 | struct device *dev = &pdev->dev; |
932 | struct rk_hdptx_phy *hdptx; |
933 | void __iomem *regs; |
934 | int ret; |
935 | |
936 | hdptx = devm_kzalloc(dev, size: sizeof(*hdptx), GFP_KERNEL); |
937 | if (!hdptx) |
938 | return -ENOMEM; |
939 | |
940 | hdptx->dev = dev; |
941 | |
942 | regs = devm_platform_ioremap_resource(pdev, index: 0); |
943 | if (IS_ERR(ptr: regs)) |
944 | return dev_err_probe(dev, err: PTR_ERR(ptr: regs), |
945 | fmt: "Failed to ioremap resource\n" ); |
946 | |
947 | ret = devm_clk_bulk_get_all(dev, clks: &hdptx->clks); |
948 | if (ret < 0) |
949 | return dev_err_probe(dev, err: ret, fmt: "Failed to get clocks\n" ); |
950 | if (ret == 0) |
951 | return dev_err_probe(dev, err: -EINVAL, fmt: "Missing clocks\n" ); |
952 | |
953 | hdptx->nr_clks = ret; |
954 | |
955 | hdptx->regmap = devm_regmap_init_mmio(dev, regs, |
956 | &rk_hdptx_phy_regmap_config); |
957 | if (IS_ERR(ptr: hdptx->regmap)) |
958 | return dev_err_probe(dev, err: PTR_ERR(ptr: hdptx->regmap), |
959 | fmt: "Failed to init regmap\n" ); |
960 | |
961 | hdptx->rsts[RST_PHY].id = "phy" ; |
962 | hdptx->rsts[RST_APB].id = "apb" ; |
963 | hdptx->rsts[RST_INIT].id = "init" ; |
964 | hdptx->rsts[RST_CMN].id = "cmn" ; |
965 | hdptx->rsts[RST_LANE].id = "lane" ; |
966 | hdptx->rsts[RST_ROPLL].id = "ropll" ; |
967 | hdptx->rsts[RST_LCPLL].id = "lcpll" ; |
968 | |
969 | ret = devm_reset_control_bulk_get_exclusive(dev, num_rstcs: RST_MAX, rstcs: hdptx->rsts); |
970 | if (ret) |
971 | return dev_err_probe(dev, err: ret, fmt: "Failed to get resets\n" ); |
972 | |
973 | hdptx->grf = syscon_regmap_lookup_by_phandle(np: dev->of_node, |
974 | property: "rockchip,grf" ); |
975 | if (IS_ERR(ptr: hdptx->grf)) |
976 | return dev_err_probe(dev, err: PTR_ERR(ptr: hdptx->grf), |
977 | fmt: "Could not get GRF syscon\n" ); |
978 | |
979 | hdptx->phy = devm_phy_create(dev, NULL, ops: &rk_hdptx_phy_ops); |
980 | if (IS_ERR(ptr: hdptx->phy)) |
981 | return dev_err_probe(dev, err: PTR_ERR(ptr: hdptx->phy), |
982 | fmt: "Failed to create HDMI PHY\n" ); |
983 | |
984 | platform_set_drvdata(pdev, data: hdptx); |
985 | phy_set_drvdata(phy: hdptx->phy, data: hdptx); |
986 | phy_set_bus_width(phy: hdptx->phy, bus_width: 8); |
987 | |
988 | ret = devm_pm_runtime_enable(dev); |
989 | if (ret) |
990 | return dev_err_probe(dev, err: ret, fmt: "Failed to enable runtime PM\n" ); |
991 | |
992 | phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
993 | if (IS_ERR(ptr: phy_provider)) |
994 | return dev_err_probe(dev, err: PTR_ERR(ptr: phy_provider), |
995 | fmt: "Failed to register PHY provider\n" ); |
996 | |
997 | reset_control_deassert(rstc: hdptx->rsts[RST_APB].rstc); |
998 | reset_control_deassert(rstc: hdptx->rsts[RST_CMN].rstc); |
999 | reset_control_deassert(rstc: hdptx->rsts[RST_INIT].rstc); |
1000 | |
1001 | return 0; |
1002 | } |
1003 | |
1004 | static const struct dev_pm_ops rk_hdptx_phy_pm_ops = { |
1005 | RUNTIME_PM_OPS(rk_hdptx_phy_runtime_suspend, |
1006 | rk_hdptx_phy_runtime_resume, NULL) |
1007 | }; |
1008 | |
1009 | static const struct of_device_id rk_hdptx_phy_of_match[] = { |
1010 | { .compatible = "rockchip,rk3588-hdptx-phy" , }, |
1011 | {} |
1012 | }; |
1013 | MODULE_DEVICE_TABLE(of, rk_hdptx_phy_of_match); |
1014 | |
1015 | static struct platform_driver rk_hdptx_phy_driver = { |
1016 | .probe = rk_hdptx_phy_probe, |
1017 | .driver = { |
1018 | .name = "rockchip-hdptx-phy" , |
1019 | .pm = &rk_hdptx_phy_pm_ops, |
1020 | .of_match_table = rk_hdptx_phy_of_match, |
1021 | }, |
1022 | }; |
1023 | module_platform_driver(rk_hdptx_phy_driver); |
1024 | |
1025 | MODULE_AUTHOR("Algea Cao <algea.cao@rock-chips.com>" ); |
1026 | MODULE_AUTHOR("Cristian Ciocaltea <cristian.ciocaltea@collabora.com>" ); |
1027 | MODULE_DESCRIPTION("Samsung HDMI/eDP Transmitter Combo PHY Driver" ); |
1028 | MODULE_LICENSE("GPL" ); |
1029 | |