1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Intel Cannon Lake PCH pinctrl/GPIO driver |
4 | * |
5 | * Copyright (C) 2017, Intel Corporation |
6 | * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
7 | * Mika Westerberg <mika.westerberg@linux.intel.com> |
8 | */ |
9 | |
10 | #include <linux/mod_devicetable.h> |
11 | #include <linux/module.h> |
12 | #include <linux/platform_device.h> |
13 | #include <linux/pm.h> |
14 | |
15 | #include <linux/pinctrl/pinctrl.h> |
16 | |
17 | #include "pinctrl-intel.h" |
18 | |
19 | #define CNL_LP_PAD_OWN 0x020 |
20 | #define CNL_LP_PADCFGLOCK 0x080 |
21 | #define CNL_LP_HOSTSW_OWN 0x0b0 |
22 | #define CNL_LP_GPI_IS 0x100 |
23 | #define CNL_LP_GPI_IE 0x120 |
24 | |
25 | #define CNL_H_PAD_OWN 0x020 |
26 | #define CNL_H_PADCFGLOCK 0x080 |
27 | #define CNL_H_HOSTSW_OWN 0x0c0 |
28 | #define CNL_H_GPI_IS 0x100 |
29 | #define CNL_H_GPI_IE 0x120 |
30 | |
31 | #define CNL_GPP(r, s, e, g) \ |
32 | { \ |
33 | .reg_num = (r), \ |
34 | .base = (s), \ |
35 | .size = ((e) - (s) + 1), \ |
36 | .gpio_base = (g), \ |
37 | } |
38 | |
39 | #define (b, s, e, g) \ |
40 | INTEL_COMMUNITY_GPPS(b, s, e, g, CNL_LP) |
41 | |
42 | #define (b, s, e, g) \ |
43 | INTEL_COMMUNITY_GPPS(b, s, e, g, CNL_H) |
44 | |
45 | /* Cannon Lake-H */ |
46 | static const struct pinctrl_pin_desc cnlh_pins[] = { |
47 | /* GPP_A */ |
48 | PINCTRL_PIN(0, "RCINB" ), |
49 | PINCTRL_PIN(1, "LAD_0" ), |
50 | PINCTRL_PIN(2, "LAD_1" ), |
51 | PINCTRL_PIN(3, "LAD_2" ), |
52 | PINCTRL_PIN(4, "LAD_3" ), |
53 | PINCTRL_PIN(5, "LFRAMEB" ), |
54 | PINCTRL_PIN(6, "SERIRQ" ), |
55 | PINCTRL_PIN(7, "PIRQAB" ), |
56 | PINCTRL_PIN(8, "CLKRUNB" ), |
57 | PINCTRL_PIN(9, "CLKOUT_LPC_0" ), |
58 | PINCTRL_PIN(10, "CLKOUT_LPC_1" ), |
59 | PINCTRL_PIN(11, "PMEB" ), |
60 | PINCTRL_PIN(12, "BM_BUSYB" ), |
61 | PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK" ), |
62 | PINCTRL_PIN(14, "SUS_STATB" ), |
63 | PINCTRL_PIN(15, "SUSACKB" ), |
64 | PINCTRL_PIN(16, "CLKOUT_48" ), |
65 | PINCTRL_PIN(17, "SD_VDD1_PWR_EN_B" ), |
66 | PINCTRL_PIN(18, "ISH_GP_0" ), |
67 | PINCTRL_PIN(19, "ISH_GP_1" ), |
68 | PINCTRL_PIN(20, "ISH_GP_2" ), |
69 | PINCTRL_PIN(21, "ISH_GP_3" ), |
70 | PINCTRL_PIN(22, "ISH_GP_4" ), |
71 | PINCTRL_PIN(23, "ISH_GP_5" ), |
72 | PINCTRL_PIN(24, "ESPI_CLK_LOOPBK" ), |
73 | /* GPP_B */ |
74 | PINCTRL_PIN(25, "GSPI0_CS1B" ), |
75 | PINCTRL_PIN(26, "GSPI1_CS1B" ), |
76 | PINCTRL_PIN(27, "VRALERTB" ), |
77 | PINCTRL_PIN(28, "CPU_GP_2" ), |
78 | PINCTRL_PIN(29, "CPU_GP_3" ), |
79 | PINCTRL_PIN(30, "SRCCLKREQB_0" ), |
80 | PINCTRL_PIN(31, "SRCCLKREQB_1" ), |
81 | PINCTRL_PIN(32, "SRCCLKREQB_2" ), |
82 | PINCTRL_PIN(33, "SRCCLKREQB_3" ), |
83 | PINCTRL_PIN(34, "SRCCLKREQB_4" ), |
84 | PINCTRL_PIN(35, "SRCCLKREQB_5" ), |
85 | PINCTRL_PIN(36, "SSP_MCLK" ), |
86 | PINCTRL_PIN(37, "SLP_S0B" ), |
87 | PINCTRL_PIN(38, "PLTRSTB" ), |
88 | PINCTRL_PIN(39, "SPKR" ), |
89 | PINCTRL_PIN(40, "GSPI0_CS0B" ), |
90 | PINCTRL_PIN(41, "GSPI0_CLK" ), |
91 | PINCTRL_PIN(42, "GSPI0_MISO" ), |
92 | PINCTRL_PIN(43, "GSPI0_MOSI" ), |
93 | PINCTRL_PIN(44, "GSPI1_CS0B" ), |
94 | PINCTRL_PIN(45, "GSPI1_CLK" ), |
95 | PINCTRL_PIN(46, "GSPI1_MISO" ), |
96 | PINCTRL_PIN(47, "GSPI1_MOSI" ), |
97 | PINCTRL_PIN(48, "SML1ALERTB" ), |
98 | PINCTRL_PIN(49, "GSPI0_CLK_LOOPBK" ), |
99 | PINCTRL_PIN(50, "GSPI1_CLK_LOOPBK" ), |
100 | /* GPP_C */ |
101 | PINCTRL_PIN(51, "SMBCLK" ), |
102 | PINCTRL_PIN(52, "SMBDATA" ), |
103 | PINCTRL_PIN(53, "SMBALERTB" ), |
104 | PINCTRL_PIN(54, "SML0CLK" ), |
105 | PINCTRL_PIN(55, "SML0DATA" ), |
106 | PINCTRL_PIN(56, "SML0ALERTB" ), |
107 | PINCTRL_PIN(57, "SML1CLK" ), |
108 | PINCTRL_PIN(58, "SML1DATA" ), |
109 | PINCTRL_PIN(59, "UART0_RXD" ), |
110 | PINCTRL_PIN(60, "UART0_TXD" ), |
111 | PINCTRL_PIN(61, "UART0_RTSB" ), |
112 | PINCTRL_PIN(62, "UART0_CTSB" ), |
113 | PINCTRL_PIN(63, "UART1_RXD" ), |
114 | PINCTRL_PIN(64, "UART1_TXD" ), |
115 | PINCTRL_PIN(65, "UART1_RTSB" ), |
116 | PINCTRL_PIN(66, "UART1_CTSB" ), |
117 | PINCTRL_PIN(67, "I2C0_SDA" ), |
118 | PINCTRL_PIN(68, "I2C0_SCL" ), |
119 | PINCTRL_PIN(69, "I2C1_SDA" ), |
120 | PINCTRL_PIN(70, "I2C1_SCL" ), |
121 | PINCTRL_PIN(71, "UART2_RXD" ), |
122 | PINCTRL_PIN(72, "UART2_TXD" ), |
123 | PINCTRL_PIN(73, "UART2_RTSB" ), |
124 | PINCTRL_PIN(74, "UART2_CTSB" ), |
125 | /* GPP_D */ |
126 | PINCTRL_PIN(75, "SPI1_CSB" ), |
127 | PINCTRL_PIN(76, "SPI1_CLK" ), |
128 | PINCTRL_PIN(77, "SPI1_MISO_IO_1" ), |
129 | PINCTRL_PIN(78, "SPI1_MOSI_IO_0" ), |
130 | PINCTRL_PIN(79, "ISH_I2C2_SDA" ), |
131 | PINCTRL_PIN(80, "SSP2_SFRM" ), |
132 | PINCTRL_PIN(81, "SSP2_TXD" ), |
133 | PINCTRL_PIN(82, "SSP2_RXD" ), |
134 | PINCTRL_PIN(83, "SSP2_SCLK" ), |
135 | PINCTRL_PIN(84, "ISH_SPI_CSB" ), |
136 | PINCTRL_PIN(85, "ISH_SPI_CLK" ), |
137 | PINCTRL_PIN(86, "ISH_SPI_MISO" ), |
138 | PINCTRL_PIN(87, "ISH_SPI_MOSI" ), |
139 | PINCTRL_PIN(88, "ISH_UART0_RXD" ), |
140 | PINCTRL_PIN(89, "ISH_UART0_TXD" ), |
141 | PINCTRL_PIN(90, "ISH_UART0_RTSB" ), |
142 | PINCTRL_PIN(91, "ISH_UART0_CTSB" ), |
143 | PINCTRL_PIN(92, "DMIC_CLK_1" ), |
144 | PINCTRL_PIN(93, "DMIC_DATA_1" ), |
145 | PINCTRL_PIN(94, "DMIC_CLK_0" ), |
146 | PINCTRL_PIN(95, "DMIC_DATA_0" ), |
147 | PINCTRL_PIN(96, "SPI1_IO_2" ), |
148 | PINCTRL_PIN(97, "SPI1_IO_3" ), |
149 | PINCTRL_PIN(98, "ISH_I2C2_SCL" ), |
150 | /* GPP_G */ |
151 | PINCTRL_PIN(99, "SD3_CMD" ), |
152 | PINCTRL_PIN(100, "SD3_D0" ), |
153 | PINCTRL_PIN(101, "SD3_D1" ), |
154 | PINCTRL_PIN(102, "SD3_D2" ), |
155 | PINCTRL_PIN(103, "SD3_D3" ), |
156 | PINCTRL_PIN(104, "SD3_CDB" ), |
157 | PINCTRL_PIN(105, "SD3_CLK" ), |
158 | PINCTRL_PIN(106, "SD3_WP" ), |
159 | /* AZA */ |
160 | PINCTRL_PIN(107, "HDA_BCLK" ), |
161 | PINCTRL_PIN(108, "HDA_RSTB" ), |
162 | PINCTRL_PIN(109, "HDA_SYNC" ), |
163 | PINCTRL_PIN(110, "HDA_SDO" ), |
164 | PINCTRL_PIN(111, "HDA_SDI_0" ), |
165 | PINCTRL_PIN(112, "HDA_SDI_1" ), |
166 | PINCTRL_PIN(113, "SSP1_SFRM" ), |
167 | PINCTRL_PIN(114, "SSP1_TXD" ), |
168 | /* vGPIO */ |
169 | PINCTRL_PIN(115, "CNV_BTEN" ), |
170 | PINCTRL_PIN(116, "CNV_GNEN" ), |
171 | PINCTRL_PIN(117, "CNV_WFEN" ), |
172 | PINCTRL_PIN(118, "CNV_WCEN" ), |
173 | PINCTRL_PIN(119, "CNV_BT_HOST_WAKEB" ), |
174 | PINCTRL_PIN(120, "vCNV_GNSS_HOST_WAKEB" ), |
175 | PINCTRL_PIN(121, "vSD3_CD_B" ), |
176 | PINCTRL_PIN(122, "CNV_BT_IF_SELECT" ), |
177 | PINCTRL_PIN(123, "vCNV_BT_UART_TXD" ), |
178 | PINCTRL_PIN(124, "vCNV_BT_UART_RXD" ), |
179 | PINCTRL_PIN(125, "vCNV_BT_UART_CTS_B" ), |
180 | PINCTRL_PIN(126, "vCNV_BT_UART_RTS_B" ), |
181 | PINCTRL_PIN(127, "vCNV_MFUART1_TXD" ), |
182 | PINCTRL_PIN(128, "vCNV_MFUART1_RXD" ), |
183 | PINCTRL_PIN(129, "vCNV_MFUART1_CTS_B" ), |
184 | PINCTRL_PIN(130, "vCNV_MFUART1_RTS_B" ), |
185 | PINCTRL_PIN(131, "vCNV_GNSS_UART_TXD" ), |
186 | PINCTRL_PIN(132, "vCNV_GNSS_UART_RXD" ), |
187 | PINCTRL_PIN(133, "vCNV_GNSS_UART_CTS_B" ), |
188 | PINCTRL_PIN(134, "vCNV_GNSS_UART_RTS_B" ), |
189 | PINCTRL_PIN(135, "vUART0_TXD" ), |
190 | PINCTRL_PIN(136, "vUART0_RXD" ), |
191 | PINCTRL_PIN(137, "vUART0_CTS_B" ), |
192 | PINCTRL_PIN(138, "vUART0_RTSB" ), |
193 | PINCTRL_PIN(139, "vISH_UART0_TXD" ), |
194 | PINCTRL_PIN(140, "vISH_UART0_RXD" ), |
195 | PINCTRL_PIN(141, "vISH_UART0_CTS_B" ), |
196 | PINCTRL_PIN(142, "vISH_UART0_RTSB" ), |
197 | PINCTRL_PIN(143, "vISH_UART1_TXD" ), |
198 | PINCTRL_PIN(144, "vISH_UART1_RXD" ), |
199 | PINCTRL_PIN(145, "vISH_UART1_CTS_B" ), |
200 | PINCTRL_PIN(146, "vISH_UART1_RTS_B" ), |
201 | PINCTRL_PIN(147, "vCNV_BT_I2S_BCLK" ), |
202 | PINCTRL_PIN(148, "vCNV_BT_I2S_WS_SYNC" ), |
203 | PINCTRL_PIN(149, "vCNV_BT_I2S_SDO" ), |
204 | PINCTRL_PIN(150, "vCNV_BT_I2S_SDI" ), |
205 | PINCTRL_PIN(151, "vSSP2_SCLK" ), |
206 | PINCTRL_PIN(152, "vSSP2_SFRM" ), |
207 | PINCTRL_PIN(153, "vSSP2_TXD" ), |
208 | PINCTRL_PIN(154, "vSSP2_RXD" ), |
209 | /* GPP_K */ |
210 | PINCTRL_PIN(155, "FAN_TACH_0" ), |
211 | PINCTRL_PIN(156, "FAN_TACH_1" ), |
212 | PINCTRL_PIN(157, "FAN_TACH_2" ), |
213 | PINCTRL_PIN(158, "FAN_TACH_3" ), |
214 | PINCTRL_PIN(159, "FAN_TACH_4" ), |
215 | PINCTRL_PIN(160, "FAN_TACH_5" ), |
216 | PINCTRL_PIN(161, "FAN_TACH_6" ), |
217 | PINCTRL_PIN(162, "FAN_TACH_7" ), |
218 | PINCTRL_PIN(163, "FAN_PWM_0" ), |
219 | PINCTRL_PIN(164, "FAN_PWM_1" ), |
220 | PINCTRL_PIN(165, "FAN_PWM_2" ), |
221 | PINCTRL_PIN(166, "FAN_PWM_3" ), |
222 | PINCTRL_PIN(167, "GSXDOUT" ), |
223 | PINCTRL_PIN(168, "GSXSLOAD" ), |
224 | PINCTRL_PIN(169, "GSXDIN" ), |
225 | PINCTRL_PIN(170, "GSXSRESETB" ), |
226 | PINCTRL_PIN(171, "GSXCLK" ), |
227 | PINCTRL_PIN(172, "ADR_COMPLETE" ), |
228 | PINCTRL_PIN(173, "NMIB" ), |
229 | PINCTRL_PIN(174, "SMIB" ), |
230 | PINCTRL_PIN(175, "CORE_VID_0" ), |
231 | PINCTRL_PIN(176, "CORE_VID_1" ), |
232 | PINCTRL_PIN(177, "IMGCLKOUT_0" ), |
233 | PINCTRL_PIN(178, "IMGCLKOUT_1" ), |
234 | /* GPP_H */ |
235 | PINCTRL_PIN(179, "SRCCLKREQB_6" ), |
236 | PINCTRL_PIN(180, "SRCCLKREQB_7" ), |
237 | PINCTRL_PIN(181, "SRCCLKREQB_8" ), |
238 | PINCTRL_PIN(182, "SRCCLKREQB_9" ), |
239 | PINCTRL_PIN(183, "SRCCLKREQB_10" ), |
240 | PINCTRL_PIN(184, "SRCCLKREQB_11" ), |
241 | PINCTRL_PIN(185, "SRCCLKREQB_12" ), |
242 | PINCTRL_PIN(186, "SRCCLKREQB_13" ), |
243 | PINCTRL_PIN(187, "SRCCLKREQB_14" ), |
244 | PINCTRL_PIN(188, "SRCCLKREQB_15" ), |
245 | PINCTRL_PIN(189, "SML2CLK" ), |
246 | PINCTRL_PIN(190, "SML2DATA" ), |
247 | PINCTRL_PIN(191, "SML2ALERTB" ), |
248 | PINCTRL_PIN(192, "SML3CLK" ), |
249 | PINCTRL_PIN(193, "SML3DATA" ), |
250 | PINCTRL_PIN(194, "SML3ALERTB" ), |
251 | PINCTRL_PIN(195, "SML4CLK" ), |
252 | PINCTRL_PIN(196, "SML4DATA" ), |
253 | PINCTRL_PIN(197, "SML4ALERTB" ), |
254 | PINCTRL_PIN(198, "ISH_I2C0_SDA" ), |
255 | PINCTRL_PIN(199, "ISH_I2C0_SCL" ), |
256 | PINCTRL_PIN(200, "ISH_I2C1_SDA" ), |
257 | PINCTRL_PIN(201, "ISH_I2C1_SCL" ), |
258 | PINCTRL_PIN(202, "TIME_SYNC_0" ), |
259 | /* GPP_E */ |
260 | PINCTRL_PIN(203, "SATAXPCIE_0" ), |
261 | PINCTRL_PIN(204, "SATAXPCIE_1" ), |
262 | PINCTRL_PIN(205, "SATAXPCIE_2" ), |
263 | PINCTRL_PIN(206, "CPU_GP_0" ), |
264 | PINCTRL_PIN(207, "SATA_DEVSLP_0" ), |
265 | PINCTRL_PIN(208, "SATA_DEVSLP_1" ), |
266 | PINCTRL_PIN(209, "SATA_DEVSLP_2" ), |
267 | PINCTRL_PIN(210, "CPU_GP_1" ), |
268 | PINCTRL_PIN(211, "SATA_LEDB" ), |
269 | PINCTRL_PIN(212, "USB2_OCB_0" ), |
270 | PINCTRL_PIN(213, "USB2_OCB_1" ), |
271 | PINCTRL_PIN(214, "USB2_OCB_2" ), |
272 | PINCTRL_PIN(215, "USB2_OCB_3" ), |
273 | /* GPP_F */ |
274 | PINCTRL_PIN(216, "SATAXPCIE_3" ), |
275 | PINCTRL_PIN(217, "SATAXPCIE_4" ), |
276 | PINCTRL_PIN(218, "SATAXPCIE_5" ), |
277 | PINCTRL_PIN(219, "SATAXPCIE_6" ), |
278 | PINCTRL_PIN(220, "SATAXPCIE_7" ), |
279 | PINCTRL_PIN(221, "SATA_DEVSLP_3" ), |
280 | PINCTRL_PIN(222, "SATA_DEVSLP_4" ), |
281 | PINCTRL_PIN(223, "SATA_DEVSLP_5" ), |
282 | PINCTRL_PIN(224, "SATA_DEVSLP_6" ), |
283 | PINCTRL_PIN(225, "SATA_DEVSLP_7" ), |
284 | PINCTRL_PIN(226, "SATA_SCLOCK" ), |
285 | PINCTRL_PIN(227, "SATA_SLOAD" ), |
286 | PINCTRL_PIN(228, "SATA_SDATAOUT1" ), |
287 | PINCTRL_PIN(229, "SATA_SDATAOUT0" ), |
288 | PINCTRL_PIN(230, "EXT_PWR_GATEB" ), |
289 | PINCTRL_PIN(231, "USB2_OCB_4" ), |
290 | PINCTRL_PIN(232, "USB2_OCB_5" ), |
291 | PINCTRL_PIN(233, "USB2_OCB_6" ), |
292 | PINCTRL_PIN(234, "USB2_OCB_7" ), |
293 | PINCTRL_PIN(235, "L_VDDEN" ), |
294 | PINCTRL_PIN(236, "L_BKLTEN" ), |
295 | PINCTRL_PIN(237, "L_BKLTCTL" ), |
296 | PINCTRL_PIN(238, "DDPF_CTRLCLK" ), |
297 | PINCTRL_PIN(239, "DDPF_CTRLDATA" ), |
298 | /* SPI */ |
299 | PINCTRL_PIN(240, "SPI0_IO_2" ), |
300 | PINCTRL_PIN(241, "SPI0_IO_3" ), |
301 | PINCTRL_PIN(242, "SPI0_MOSI_IO_0" ), |
302 | PINCTRL_PIN(243, "SPI0_MISO_IO_1" ), |
303 | PINCTRL_PIN(244, "SPI0_TPM_CSB" ), |
304 | PINCTRL_PIN(245, "SPI0_FLASH_0_CSB" ), |
305 | PINCTRL_PIN(246, "SPI0_FLASH_1_CSB" ), |
306 | PINCTRL_PIN(247, "SPI0_CLK" ), |
307 | PINCTRL_PIN(248, "SPI0_CLK_LOOPBK" ), |
308 | /* CPU */ |
309 | PINCTRL_PIN(249, "HDACPU_SDI" ), |
310 | PINCTRL_PIN(250, "HDACPU_SDO" ), |
311 | PINCTRL_PIN(251, "HDACPU_SCLK" ), |
312 | PINCTRL_PIN(252, "PM_SYNC" ), |
313 | PINCTRL_PIN(253, "PECI" ), |
314 | PINCTRL_PIN(254, "CPUPWRGD" ), |
315 | PINCTRL_PIN(255, "THRMTRIPB" ), |
316 | PINCTRL_PIN(256, "PLTRST_CPUB" ), |
317 | PINCTRL_PIN(257, "PM_DOWN" ), |
318 | PINCTRL_PIN(258, "TRIGGER_IN" ), |
319 | PINCTRL_PIN(259, "TRIGGER_OUT" ), |
320 | /* JTAG */ |
321 | PINCTRL_PIN(260, "JTAG_TDO" ), |
322 | PINCTRL_PIN(261, "JTAGX" ), |
323 | PINCTRL_PIN(262, "PRDYB" ), |
324 | PINCTRL_PIN(263, "PREQB" ), |
325 | PINCTRL_PIN(264, "CPU_TRSTB" ), |
326 | PINCTRL_PIN(265, "JTAG_TDI" ), |
327 | PINCTRL_PIN(266, "JTAG_TMS" ), |
328 | PINCTRL_PIN(267, "JTAG_TCK" ), |
329 | PINCTRL_PIN(268, "ITP_PMODE" ), |
330 | /* GPP_I */ |
331 | PINCTRL_PIN(269, "DDSP_HPD_0" ), |
332 | PINCTRL_PIN(270, "DDSP_HPD_1" ), |
333 | PINCTRL_PIN(271, "DDSP_HPD_2" ), |
334 | PINCTRL_PIN(272, "DDSP_HPD_3" ), |
335 | PINCTRL_PIN(273, "EDP_HPD" ), |
336 | PINCTRL_PIN(274, "DDPB_CTRLCLK" ), |
337 | PINCTRL_PIN(275, "DDPB_CTRLDATA" ), |
338 | PINCTRL_PIN(276, "DDPC_CTRLCLK" ), |
339 | PINCTRL_PIN(277, "DDPC_CTRLDATA" ), |
340 | PINCTRL_PIN(278, "DDPD_CTRLCLK" ), |
341 | PINCTRL_PIN(279, "DDPD_CTRLDATA" ), |
342 | PINCTRL_PIN(280, "M2_SKT2_CFG_0" ), |
343 | PINCTRL_PIN(281, "M2_SKT2_CFG_1" ), |
344 | PINCTRL_PIN(282, "M2_SKT2_CFG_2" ), |
345 | PINCTRL_PIN(283, "M2_SKT2_CFG_3" ), |
346 | PINCTRL_PIN(284, "SYS_PWROK" ), |
347 | PINCTRL_PIN(285, "SYS_RESETB" ), |
348 | PINCTRL_PIN(286, "MLK_RSTB" ), |
349 | /* GPP_J */ |
350 | PINCTRL_PIN(287, "CNV_PA_BLANKING" ), |
351 | PINCTRL_PIN(288, "CNV_GNSS_FTA" ), |
352 | PINCTRL_PIN(289, "CNV_GNSS_SYSCK" ), |
353 | PINCTRL_PIN(290, "CNV_RF_RESET_B" ), |
354 | PINCTRL_PIN(291, "CNV_BRI_DT" ), |
355 | PINCTRL_PIN(292, "CNV_BRI_RSP" ), |
356 | PINCTRL_PIN(293, "CNV_RGI_DT" ), |
357 | PINCTRL_PIN(294, "CNV_RGI_RSP" ), |
358 | PINCTRL_PIN(295, "CNV_MFUART2_RXD" ), |
359 | PINCTRL_PIN(296, "CNV_MFUART2_TXD" ), |
360 | PINCTRL_PIN(297, "CNV_MODEM_CLKREQ" ), |
361 | PINCTRL_PIN(298, "A4WP_PRESENT" ), |
362 | }; |
363 | |
364 | static const struct intel_padgroup [] = { |
365 | CNL_GPP(0, 0, 24, 0), /* GPP_A */ |
366 | CNL_GPP(1, 25, 50, 32), /* GPP_B */ |
367 | }; |
368 | |
369 | static const struct intel_padgroup [] = { |
370 | CNL_GPP(0, 51, 74, 64), /* GPP_C */ |
371 | CNL_GPP(1, 75, 98, 96), /* GPP_D */ |
372 | CNL_GPP(2, 99, 106, 128), /* GPP_G */ |
373 | CNL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */ |
374 | CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */ |
375 | CNL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */ |
376 | }; |
377 | |
378 | static const struct intel_padgroup [] = { |
379 | CNL_GPP(0, 155, 178, 192), /* GPP_K */ |
380 | CNL_GPP(1, 179, 202, 224), /* GPP_H */ |
381 | CNL_GPP(2, 203, 215, 256), /* GPP_E */ |
382 | CNL_GPP(3, 216, 239, 288), /* GPP_F */ |
383 | CNL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */ |
384 | }; |
385 | |
386 | static const struct intel_padgroup [] = { |
387 | CNL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */ |
388 | CNL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */ |
389 | CNL_GPP(2, 269, 286, 320), /* GPP_I */ |
390 | CNL_GPP(3, 287, 298, 352), /* GPP_J */ |
391 | }; |
392 | |
393 | static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 }; |
394 | static const unsigned int cnlh_spi1_pins[] = { 44, 45, 46, 47 }; |
395 | static const unsigned int cnlh_spi2_pins[] = { 84, 85, 86, 87 }; |
396 | |
397 | static const unsigned int cnlh_uart0_pins[] = { 59, 60, 61, 62 }; |
398 | static const unsigned int cnlh_uart1_pins[] = { 63, 64, 65, 66 }; |
399 | static const unsigned int cnlh_uart2_pins[] = { 71, 72, 73, 74 }; |
400 | |
401 | static const unsigned int cnlh_i2c0_pins[] = { 67, 68 }; |
402 | static const unsigned int cnlh_i2c1_pins[] = { 69, 70 }; |
403 | static const unsigned int cnlh_i2c2_pins[] = { 88, 89 }; |
404 | static const unsigned int cnlh_i2c3_pins[] = { 79, 98 }; |
405 | |
406 | static const struct intel_pingroup cnlh_groups[] = { |
407 | PIN_GROUP("spi0_grp" , cnlh_spi0_pins, 1), |
408 | PIN_GROUP("spi1_grp" , cnlh_spi1_pins, 1), |
409 | PIN_GROUP("spi2_grp" , cnlh_spi2_pins, 3), |
410 | PIN_GROUP("uart0_grp" , cnlh_uart0_pins, 1), |
411 | PIN_GROUP("uart1_grp" , cnlh_uart1_pins, 1), |
412 | PIN_GROUP("uart2_grp" , cnlh_uart2_pins, 1), |
413 | PIN_GROUP("i2c0_grp" , cnlh_i2c0_pins, 1), |
414 | PIN_GROUP("i2c1_grp" , cnlh_i2c1_pins, 1), |
415 | PIN_GROUP("i2c2_grp" , cnlh_i2c2_pins, 3), |
416 | PIN_GROUP("i2c3_grp" , cnlh_i2c3_pins, 2), |
417 | }; |
418 | |
419 | static const char * const cnlh_spi0_groups[] = { "spi0_grp" }; |
420 | static const char * const cnlh_spi1_groups[] = { "spi1_grp" }; |
421 | static const char * const cnlh_spi2_groups[] = { "spi2_grp" }; |
422 | static const char * const cnlh_uart0_groups[] = { "uart0_grp" }; |
423 | static const char * const cnlh_uart1_groups[] = { "uart1_grp" }; |
424 | static const char * const cnlh_uart2_groups[] = { "uart2_grp" }; |
425 | static const char * const cnlh_i2c0_groups[] = { "i2c0_grp" }; |
426 | static const char * const cnlh_i2c1_groups[] = { "i2c1_grp" }; |
427 | static const char * const cnlh_i2c2_groups[] = { "i2c2_grp" }; |
428 | static const char * const cnlh_i2c3_groups[] = { "i2c3_grp" }; |
429 | |
430 | static const struct intel_function cnlh_functions[] = { |
431 | FUNCTION("spi0" , cnlh_spi0_groups), |
432 | FUNCTION("spi1" , cnlh_spi1_groups), |
433 | FUNCTION("spi2" , cnlh_spi2_groups), |
434 | FUNCTION("uart0" , cnlh_uart0_groups), |
435 | FUNCTION("uart1" , cnlh_uart1_groups), |
436 | FUNCTION("uart2" , cnlh_uart2_groups), |
437 | FUNCTION("i2c0" , cnlh_i2c0_groups), |
438 | FUNCTION("i2c1" , cnlh_i2c1_groups), |
439 | FUNCTION("i2c2" , cnlh_i2c2_groups), |
440 | FUNCTION("i2c3" , cnlh_i2c3_groups), |
441 | }; |
442 | |
443 | static const struct intel_community cnlh_communities[] = { |
444 | CNL_H_COMMUNITY(0, 0, 50, cnlh_community0_gpps), |
445 | CNL_H_COMMUNITY(1, 51, 154, cnlh_community1_gpps), |
446 | CNL_H_COMMUNITY(2, 155, 248, cnlh_community3_gpps), |
447 | CNL_H_COMMUNITY(3, 249, 298, cnlh_community4_gpps), |
448 | }; |
449 | |
450 | static const struct intel_pinctrl_soc_data cnlh_soc_data = { |
451 | .pins = cnlh_pins, |
452 | .npins = ARRAY_SIZE(cnlh_pins), |
453 | .groups = cnlh_groups, |
454 | .ngroups = ARRAY_SIZE(cnlh_groups), |
455 | .functions = cnlh_functions, |
456 | .nfunctions = ARRAY_SIZE(cnlh_functions), |
457 | .communities = cnlh_communities, |
458 | .ncommunities = ARRAY_SIZE(cnlh_communities), |
459 | }; |
460 | |
461 | /* Cannon Lake-LP */ |
462 | static const struct pinctrl_pin_desc cnllp_pins[] = { |
463 | /* GPP_A */ |
464 | PINCTRL_PIN(0, "RCINB" ), |
465 | PINCTRL_PIN(1, "LAD_0" ), |
466 | PINCTRL_PIN(2, "LAD_1" ), |
467 | PINCTRL_PIN(3, "LAD_2" ), |
468 | PINCTRL_PIN(4, "LAD_3" ), |
469 | PINCTRL_PIN(5, "LFRAMEB" ), |
470 | PINCTRL_PIN(6, "SERIRQ" ), |
471 | PINCTRL_PIN(7, "PIRQAB" ), |
472 | PINCTRL_PIN(8, "CLKRUNB" ), |
473 | PINCTRL_PIN(9, "CLKOUT_LPC_0" ), |
474 | PINCTRL_PIN(10, "CLKOUT_LPC_1" ), |
475 | PINCTRL_PIN(11, "PMEB" ), |
476 | PINCTRL_PIN(12, "BM_BUSYB" ), |
477 | PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK" ), |
478 | PINCTRL_PIN(14, "SUS_STATB" ), |
479 | PINCTRL_PIN(15, "SUSACKB" ), |
480 | PINCTRL_PIN(16, "SD_1P8_SEL" ), |
481 | PINCTRL_PIN(17, "SD_PWR_EN_B" ), |
482 | PINCTRL_PIN(18, "ISH_GP_0" ), |
483 | PINCTRL_PIN(19, "ISH_GP_1" ), |
484 | PINCTRL_PIN(20, "ISH_GP_2" ), |
485 | PINCTRL_PIN(21, "ISH_GP_3" ), |
486 | PINCTRL_PIN(22, "ISH_GP_4" ), |
487 | PINCTRL_PIN(23, "ISH_GP_5" ), |
488 | PINCTRL_PIN(24, "ESPI_CLK_LOOPBK" ), |
489 | /* GPP_B */ |
490 | PINCTRL_PIN(25, "CORE_VID_0" ), |
491 | PINCTRL_PIN(26, "CORE_VID_1" ), |
492 | PINCTRL_PIN(27, "VRALERTB" ), |
493 | PINCTRL_PIN(28, "CPU_GP_2" ), |
494 | PINCTRL_PIN(29, "CPU_GP_3" ), |
495 | PINCTRL_PIN(30, "SRCCLKREQB_0" ), |
496 | PINCTRL_PIN(31, "SRCCLKREQB_1" ), |
497 | PINCTRL_PIN(32, "SRCCLKREQB_2" ), |
498 | PINCTRL_PIN(33, "SRCCLKREQB_3" ), |
499 | PINCTRL_PIN(34, "SRCCLKREQB_4" ), |
500 | PINCTRL_PIN(35, "SRCCLKREQB_5" ), |
501 | PINCTRL_PIN(36, "EXT_PWR_GATEB" ), |
502 | PINCTRL_PIN(37, "SLP_S0B" ), |
503 | PINCTRL_PIN(38, "PLTRSTB" ), |
504 | PINCTRL_PIN(39, "SPKR" ), |
505 | PINCTRL_PIN(40, "GSPI0_CS0B" ), |
506 | PINCTRL_PIN(41, "GSPI0_CLK" ), |
507 | PINCTRL_PIN(42, "GSPI0_MISO" ), |
508 | PINCTRL_PIN(43, "GSPI0_MOSI" ), |
509 | PINCTRL_PIN(44, "GSPI1_CS0B" ), |
510 | PINCTRL_PIN(45, "GSPI1_CLK" ), |
511 | PINCTRL_PIN(46, "GSPI1_MISO" ), |
512 | PINCTRL_PIN(47, "GSPI1_MOSI" ), |
513 | PINCTRL_PIN(48, "SML1ALERTB" ), |
514 | PINCTRL_PIN(49, "GSPI0_CLK_LOOPBK" ), |
515 | PINCTRL_PIN(50, "GSPI1_CLK_LOOPBK" ), |
516 | /* GPP_G */ |
517 | PINCTRL_PIN(51, "SD3_CMD" ), |
518 | PINCTRL_PIN(52, "SD3_D0_SD4_RCLK_P" ), |
519 | PINCTRL_PIN(53, "SD3_D1_SD4_RCLK_N" ), |
520 | PINCTRL_PIN(54, "SD3_D2" ), |
521 | PINCTRL_PIN(55, "SD3_D3" ), |
522 | PINCTRL_PIN(56, "SD3_CDB" ), |
523 | PINCTRL_PIN(57, "SD3_CLK" ), |
524 | PINCTRL_PIN(58, "SD3_WP" ), |
525 | /* SPI */ |
526 | PINCTRL_PIN(59, "SPI0_IO_2" ), |
527 | PINCTRL_PIN(60, "SPI0_IO_3" ), |
528 | PINCTRL_PIN(61, "SPI0_MOSI_IO_0" ), |
529 | PINCTRL_PIN(62, "SPI0_MISO_IO_1" ), |
530 | PINCTRL_PIN(63, "SPI0_TPM_CSB" ), |
531 | PINCTRL_PIN(64, "SPI0_FLASH_0_CSB" ), |
532 | PINCTRL_PIN(65, "SPI0_FLASH_1_CSB" ), |
533 | PINCTRL_PIN(66, "SPI0_CLK" ), |
534 | PINCTRL_PIN(67, "SPI0_CLK_LOOPBK" ), |
535 | /* GPP_D */ |
536 | PINCTRL_PIN(68, "SPI1_CSB" ), |
537 | PINCTRL_PIN(69, "SPI1_CLK" ), |
538 | PINCTRL_PIN(70, "SPI1_MISO_IO_1" ), |
539 | PINCTRL_PIN(71, "SPI1_MOSI_IO_0" ), |
540 | PINCTRL_PIN(72, "IMGCLKOUT_0" ), |
541 | PINCTRL_PIN(73, "ISH_I2C0_SDA" ), |
542 | PINCTRL_PIN(74, "ISH_I2C0_SCL" ), |
543 | PINCTRL_PIN(75, "ISH_I2C1_SDA" ), |
544 | PINCTRL_PIN(76, "ISH_I2C1_SCL" ), |
545 | PINCTRL_PIN(77, "ISH_SPI_CSB" ), |
546 | PINCTRL_PIN(78, "ISH_SPI_CLK" ), |
547 | PINCTRL_PIN(79, "ISH_SPI_MISO" ), |
548 | PINCTRL_PIN(80, "ISH_SPI_MOSI" ), |
549 | PINCTRL_PIN(81, "ISH_UART0_RXD" ), |
550 | PINCTRL_PIN(82, "ISH_UART0_TXD" ), |
551 | PINCTRL_PIN(83, "ISH_UART0_RTSB" ), |
552 | PINCTRL_PIN(84, "ISH_UART0_CTSB" ), |
553 | PINCTRL_PIN(85, "DMIC_CLK_1" ), |
554 | PINCTRL_PIN(86, "DMIC_DATA_1" ), |
555 | PINCTRL_PIN(87, "DMIC_CLK_0" ), |
556 | PINCTRL_PIN(88, "DMIC_DATA_0" ), |
557 | PINCTRL_PIN(89, "SPI1_IO_2" ), |
558 | PINCTRL_PIN(90, "SPI1_IO_3" ), |
559 | PINCTRL_PIN(91, "SSP_MCLK" ), |
560 | PINCTRL_PIN(92, "GSPI2_CLK_LOOPBK" ), |
561 | /* GPP_F */ |
562 | PINCTRL_PIN(93, "CNV_GNSS_PA_BLANKING" ), |
563 | PINCTRL_PIN(94, "CNV_GNSS_FTA" ), |
564 | PINCTRL_PIN(95, "CNV_GNSS_SYSCK" ), |
565 | PINCTRL_PIN(96, "EMMC_HIP_MON" ), |
566 | PINCTRL_PIN(97, "CNV_BRI_DT" ), |
567 | PINCTRL_PIN(98, "CNV_BRI_RSP" ), |
568 | PINCTRL_PIN(99, "CNV_RGI_DT" ), |
569 | PINCTRL_PIN(100, "CNV_RGI_RSP" ), |
570 | PINCTRL_PIN(101, "CNV_MFUART2_RXD" ), |
571 | PINCTRL_PIN(102, "CNV_MFUART2_TXD" ), |
572 | PINCTRL_PIN(103, "GPP_F_10" ), |
573 | PINCTRL_PIN(104, "EMMC_CMD" ), |
574 | PINCTRL_PIN(105, "EMMC_DATA_0" ), |
575 | PINCTRL_PIN(106, "EMMC_DATA_1" ), |
576 | PINCTRL_PIN(107, "EMMC_DATA_2" ), |
577 | PINCTRL_PIN(108, "EMMC_DATA_3" ), |
578 | PINCTRL_PIN(109, "EMMC_DATA_4" ), |
579 | PINCTRL_PIN(110, "EMMC_DATA_5" ), |
580 | PINCTRL_PIN(111, "EMMC_DATA_6" ), |
581 | PINCTRL_PIN(112, "EMMC_DATA_7" ), |
582 | PINCTRL_PIN(113, "EMMC_RCLK" ), |
583 | PINCTRL_PIN(114, "EMMC_CLK" ), |
584 | PINCTRL_PIN(115, "EMMC_RESETB" ), |
585 | PINCTRL_PIN(116, "A4WP_PRESENT" ), |
586 | /* GPP_H */ |
587 | PINCTRL_PIN(117, "SSP2_SCLK" ), |
588 | PINCTRL_PIN(118, "SSP2_SFRM" ), |
589 | PINCTRL_PIN(119, "SSP2_TXD" ), |
590 | PINCTRL_PIN(120, "SSP2_RXD" ), |
591 | PINCTRL_PIN(121, "I2C2_SDA" ), |
592 | PINCTRL_PIN(122, "I2C2_SCL" ), |
593 | PINCTRL_PIN(123, "I2C3_SDA" ), |
594 | PINCTRL_PIN(124, "I2C3_SCL" ), |
595 | PINCTRL_PIN(125, "I2C4_SDA" ), |
596 | PINCTRL_PIN(126, "I2C4_SCL" ), |
597 | PINCTRL_PIN(127, "I2C5_SDA" ), |
598 | PINCTRL_PIN(128, "I2C5_SCL" ), |
599 | PINCTRL_PIN(129, "M2_SKT2_CFG_0" ), |
600 | PINCTRL_PIN(130, "M2_SKT2_CFG_1" ), |
601 | PINCTRL_PIN(131, "M2_SKT2_CFG_2" ), |
602 | PINCTRL_PIN(132, "M2_SKT2_CFG_3" ), |
603 | PINCTRL_PIN(133, "DDPF_CTRLCLK" ), |
604 | PINCTRL_PIN(134, "DDPF_CTRLDATA" ), |
605 | PINCTRL_PIN(135, "CPU_VCCIO_PWR_GATEB" ), |
606 | PINCTRL_PIN(136, "TIMESYNC_0" ), |
607 | PINCTRL_PIN(137, "IMGCLKOUT_1" ), |
608 | PINCTRL_PIN(138, "GPPC_H_21" ), |
609 | PINCTRL_PIN(139, "GPPC_H_22" ), |
610 | PINCTRL_PIN(140, "GPPC_H_23" ), |
611 | /* vGPIO */ |
612 | PINCTRL_PIN(141, "CNV_BTEN" ), |
613 | PINCTRL_PIN(142, "CNV_GNEN" ), |
614 | PINCTRL_PIN(143, "CNV_WFEN" ), |
615 | PINCTRL_PIN(144, "CNV_WCEN" ), |
616 | PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB" ), |
617 | PINCTRL_PIN(146, "CNV_BT_IF_SELECT" ), |
618 | PINCTRL_PIN(147, "vCNV_BT_UART_TXD" ), |
619 | PINCTRL_PIN(148, "vCNV_BT_UART_RXD" ), |
620 | PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B" ), |
621 | PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B" ), |
622 | PINCTRL_PIN(151, "vCNV_MFUART1_TXD" ), |
623 | PINCTRL_PIN(152, "vCNV_MFUART1_RXD" ), |
624 | PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B" ), |
625 | PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B" ), |
626 | PINCTRL_PIN(155, "vCNV_GNSS_UART_TXD" ), |
627 | PINCTRL_PIN(156, "vCNV_GNSS_UART_RXD" ), |
628 | PINCTRL_PIN(157, "vCNV_GNSS_UART_CTS_B" ), |
629 | PINCTRL_PIN(158, "vCNV_GNSS_UART_RTS_B" ), |
630 | PINCTRL_PIN(159, "vUART0_TXD" ), |
631 | PINCTRL_PIN(160, "vUART0_RXD" ), |
632 | PINCTRL_PIN(161, "vUART0_CTS_B" ), |
633 | PINCTRL_PIN(162, "vUART0_RTS_B" ), |
634 | PINCTRL_PIN(163, "vISH_UART0_TXD" ), |
635 | PINCTRL_PIN(164, "vISH_UART0_RXD" ), |
636 | PINCTRL_PIN(165, "vISH_UART0_CTS_B" ), |
637 | PINCTRL_PIN(166, "vISH_UART0_RTS_B" ), |
638 | PINCTRL_PIN(167, "vISH_UART1_TXD" ), |
639 | PINCTRL_PIN(168, "vISH_UART1_RXD" ), |
640 | PINCTRL_PIN(169, "vISH_UART1_CTS_B" ), |
641 | PINCTRL_PIN(170, "vISH_UART1_RTS_B" ), |
642 | PINCTRL_PIN(171, "vCNV_BT_I2S_BCLK" ), |
643 | PINCTRL_PIN(172, "vCNV_BT_I2S_WS_SYNC" ), |
644 | PINCTRL_PIN(173, "vCNV_BT_I2S_SDO" ), |
645 | PINCTRL_PIN(174, "vCNV_BT_I2S_SDI" ), |
646 | PINCTRL_PIN(175, "vSSP2_SCLK" ), |
647 | PINCTRL_PIN(176, "vSSP2_SFRM" ), |
648 | PINCTRL_PIN(177, "vSSP2_TXD" ), |
649 | PINCTRL_PIN(178, "vSSP2_RXD" ), |
650 | PINCTRL_PIN(179, "vCNV_GNSS_HOST_WAKEB" ), |
651 | PINCTRL_PIN(180, "vSD3_CD_B" ), |
652 | /* GPP_C */ |
653 | PINCTRL_PIN(181, "SMBCLK" ), |
654 | PINCTRL_PIN(182, "SMBDATA" ), |
655 | PINCTRL_PIN(183, "SMBALERTB" ), |
656 | PINCTRL_PIN(184, "SML0CLK" ), |
657 | PINCTRL_PIN(185, "SML0DATA" ), |
658 | PINCTRL_PIN(186, "SML0ALERTB" ), |
659 | PINCTRL_PIN(187, "SML1CLK" ), |
660 | PINCTRL_PIN(188, "SML1DATA" ), |
661 | PINCTRL_PIN(189, "UART0_RXD" ), |
662 | PINCTRL_PIN(190, "UART0_TXD" ), |
663 | PINCTRL_PIN(191, "UART0_RTSB" ), |
664 | PINCTRL_PIN(192, "UART0_CTSB" ), |
665 | PINCTRL_PIN(193, "UART1_RXD" ), |
666 | PINCTRL_PIN(194, "UART1_TXD" ), |
667 | PINCTRL_PIN(195, "UART1_RTSB" ), |
668 | PINCTRL_PIN(196, "UART1_CTSB" ), |
669 | PINCTRL_PIN(197, "I2C0_SDA" ), |
670 | PINCTRL_PIN(198, "I2C0_SCL" ), |
671 | PINCTRL_PIN(199, "I2C1_SDA" ), |
672 | PINCTRL_PIN(200, "I2C1_SCL" ), |
673 | PINCTRL_PIN(201, "UART2_RXD" ), |
674 | PINCTRL_PIN(202, "UART2_TXD" ), |
675 | PINCTRL_PIN(203, "UART2_RTSB" ), |
676 | PINCTRL_PIN(204, "UART2_CTSB" ), |
677 | /* GPP_E */ |
678 | PINCTRL_PIN(205, "SATAXPCIE_0" ), |
679 | PINCTRL_PIN(206, "SATAXPCIE_1" ), |
680 | PINCTRL_PIN(207, "SATAXPCIE_2" ), |
681 | PINCTRL_PIN(208, "CPU_GP_0" ), |
682 | PINCTRL_PIN(209, "SATA_DEVSLP_0" ), |
683 | PINCTRL_PIN(210, "SATA_DEVSLP_1" ), |
684 | PINCTRL_PIN(211, "SATA_DEVSLP_2" ), |
685 | PINCTRL_PIN(212, "CPU_GP_1" ), |
686 | PINCTRL_PIN(213, "SATA_LEDB" ), |
687 | PINCTRL_PIN(214, "USB2_OCB_0" ), |
688 | PINCTRL_PIN(215, "USB2_OCB_1" ), |
689 | PINCTRL_PIN(216, "USB2_OCB_2" ), |
690 | PINCTRL_PIN(217, "USB2_OCB_3" ), |
691 | PINCTRL_PIN(218, "DDSP_HPD_0" ), |
692 | PINCTRL_PIN(219, "DDSP_HPD_1" ), |
693 | PINCTRL_PIN(220, "DDSP_HPD_2" ), |
694 | PINCTRL_PIN(221, "DDSP_HPD_3" ), |
695 | PINCTRL_PIN(222, "EDP_HPD" ), |
696 | PINCTRL_PIN(223, "DDPB_CTRLCLK" ), |
697 | PINCTRL_PIN(224, "DDPB_CTRLDATA" ), |
698 | PINCTRL_PIN(225, "DDPC_CTRLCLK" ), |
699 | PINCTRL_PIN(226, "DDPC_CTRLDATA" ), |
700 | PINCTRL_PIN(227, "DDPD_CTRLCLK" ), |
701 | PINCTRL_PIN(228, "DDPD_CTRLDATA" ), |
702 | /* JTAG */ |
703 | PINCTRL_PIN(229, "JTAG_TDO" ), |
704 | PINCTRL_PIN(230, "JTAGX" ), |
705 | PINCTRL_PIN(231, "PRDYB" ), |
706 | PINCTRL_PIN(232, "PREQB" ), |
707 | PINCTRL_PIN(233, "CPU_TRSTB" ), |
708 | PINCTRL_PIN(234, "JTAG_TDI" ), |
709 | PINCTRL_PIN(235, "JTAG_TMS" ), |
710 | PINCTRL_PIN(236, "JTAG_TCK" ), |
711 | PINCTRL_PIN(237, "ITP_PMODE" ), |
712 | /* HVCMOS */ |
713 | PINCTRL_PIN(238, "L_BKLTEN" ), |
714 | PINCTRL_PIN(239, "L_BKLTCTL" ), |
715 | PINCTRL_PIN(240, "L_VDDEN" ), |
716 | PINCTRL_PIN(241, "SYS_PWROK" ), |
717 | PINCTRL_PIN(242, "SYS_RESETB" ), |
718 | PINCTRL_PIN(243, "MLK_RSTB" ), |
719 | }; |
720 | |
721 | static const unsigned int cnllp_spi0_pins[] = { 40, 41, 42, 43, 7 }; |
722 | static const unsigned int cnllp_spi0_modes[] = { 1, 1, 1, 1, 2 }; |
723 | static const unsigned int cnllp_spi1_pins[] = { 44, 45, 46, 47, 11 }; |
724 | static const unsigned int cnllp_spi1_modes[] = { 1, 1, 1, 1, 2 }; |
725 | static const unsigned int cnllp_spi2_pins[] = { 77, 78, 79, 80, 83 }; |
726 | static const unsigned int cnllp_spi2_modes[] = { 3, 3, 3, 3, 2 }; |
727 | |
728 | static const unsigned int cnllp_i2c0_pins[] = { 197, 198 }; |
729 | static const unsigned int cnllp_i2c1_pins[] = { 199, 200 }; |
730 | static const unsigned int cnllp_i2c2_pins[] = { 121, 122 }; |
731 | static const unsigned int cnllp_i2c3_pins[] = { 123, 124 }; |
732 | static const unsigned int cnllp_i2c4_pins[] = { 125, 126 }; |
733 | static const unsigned int cnllp_i2c5_pins[] = { 127, 128 }; |
734 | |
735 | static const unsigned int cnllp_uart0_pins[] = { 189, 190, 191, 192 }; |
736 | static const unsigned int cnllp_uart1_pins[] = { 193, 194, 195, 196 }; |
737 | static const unsigned int cnllp_uart2_pins[] = { 201, 202, 203, 204 }; |
738 | |
739 | static const struct intel_pingroup cnllp_groups[] = { |
740 | PIN_GROUP("spi0_grp" , cnllp_spi0_pins, cnllp_spi0_modes), |
741 | PIN_GROUP("spi1_grp" , cnllp_spi1_pins, cnllp_spi1_modes), |
742 | PIN_GROUP("spi2_grp" , cnllp_spi2_pins, cnllp_spi2_modes), |
743 | PIN_GROUP("i2c0_grp" , cnllp_i2c0_pins, 1), |
744 | PIN_GROUP("i2c1_grp" , cnllp_i2c1_pins, 1), |
745 | PIN_GROUP("i2c2_grp" , cnllp_i2c2_pins, 1), |
746 | PIN_GROUP("i2c3_grp" , cnllp_i2c3_pins, 1), |
747 | PIN_GROUP("i2c4_grp" , cnllp_i2c4_pins, 1), |
748 | PIN_GROUP("i2c5_grp" , cnllp_i2c5_pins, 1), |
749 | PIN_GROUP("uart0_grp" , cnllp_uart0_pins, 1), |
750 | PIN_GROUP("uart1_grp" , cnllp_uart1_pins, 1), |
751 | PIN_GROUP("uart2_grp" , cnllp_uart2_pins, 1), |
752 | }; |
753 | |
754 | static const char * const cnllp_spi0_groups[] = { "spi0_grp" }; |
755 | static const char * const cnllp_spi1_groups[] = { "spi1_grp" }; |
756 | static const char * const cnllp_spi2_groups[] = { "spi2_grp" }; |
757 | static const char * const cnllp_i2c0_groups[] = { "i2c0_grp" }; |
758 | static const char * const cnllp_i2c1_groups[] = { "i2c1_grp" }; |
759 | static const char * const cnllp_i2c2_groups[] = { "i2c2_grp" }; |
760 | static const char * const cnllp_i2c3_groups[] = { "i2c3_grp" }; |
761 | static const char * const cnllp_i2c4_groups[] = { "i2c4_grp" }; |
762 | static const char * const cnllp_i2c5_groups[] = { "i2c5_grp" }; |
763 | static const char * const cnllp_uart0_groups[] = { "uart0_grp" }; |
764 | static const char * const cnllp_uart1_groups[] = { "uart1_grp" }; |
765 | static const char * const cnllp_uart2_groups[] = { "uart2_grp" }; |
766 | |
767 | static const struct intel_function cnllp_functions[] = { |
768 | FUNCTION("spi0" , cnllp_spi0_groups), |
769 | FUNCTION("spi1" , cnllp_spi1_groups), |
770 | FUNCTION("spi2" , cnllp_spi2_groups), |
771 | FUNCTION("i2c0" , cnllp_i2c0_groups), |
772 | FUNCTION("i2c1" , cnllp_i2c1_groups), |
773 | FUNCTION("i2c2" , cnllp_i2c2_groups), |
774 | FUNCTION("i2c3" , cnllp_i2c3_groups), |
775 | FUNCTION("i2c4" , cnllp_i2c4_groups), |
776 | FUNCTION("i2c5" , cnllp_i2c5_groups), |
777 | FUNCTION("uart0" , cnllp_uart0_groups), |
778 | FUNCTION("uart1" , cnllp_uart1_groups), |
779 | FUNCTION("uart2" , cnllp_uart2_groups), |
780 | }; |
781 | |
782 | static const struct intel_padgroup [] = { |
783 | CNL_GPP(0, 0, 24, 0), /* GPP_A */ |
784 | CNL_GPP(1, 25, 50, 32), /* GPP_B */ |
785 | CNL_GPP(2, 51, 58, 64), /* GPP_G */ |
786 | CNL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */ |
787 | }; |
788 | |
789 | static const struct intel_padgroup [] = { |
790 | CNL_GPP(0, 68, 92, 96), /* GPP_D */ |
791 | CNL_GPP(1, 93, 116, 128), /* GPP_F */ |
792 | CNL_GPP(2, 117, 140, 160), /* GPP_H */ |
793 | CNL_GPP(3, 141, 172, 192), /* vGPIO */ |
794 | CNL_GPP(4, 173, 180, 224), /* vGPIO */ |
795 | }; |
796 | |
797 | static const struct intel_padgroup [] = { |
798 | CNL_GPP(0, 181, 204, 256), /* GPP_C */ |
799 | CNL_GPP(1, 205, 228, 288), /* GPP_E */ |
800 | CNL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */ |
801 | CNL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ |
802 | }; |
803 | |
804 | static const struct intel_community cnllp_communities[] = { |
805 | CNL_LP_COMMUNITY(0, 0, 67, cnllp_community0_gpps), |
806 | CNL_LP_COMMUNITY(1, 68, 180, cnllp_community1_gpps), |
807 | CNL_LP_COMMUNITY(2, 181, 243, cnllp_community4_gpps), |
808 | }; |
809 | |
810 | static const struct intel_pinctrl_soc_data cnllp_soc_data = { |
811 | .pins = cnllp_pins, |
812 | .npins = ARRAY_SIZE(cnllp_pins), |
813 | .groups = cnllp_groups, |
814 | .ngroups = ARRAY_SIZE(cnllp_groups), |
815 | .functions = cnllp_functions, |
816 | .nfunctions = ARRAY_SIZE(cnllp_functions), |
817 | .communities = cnllp_communities, |
818 | .ncommunities = ARRAY_SIZE(cnllp_communities), |
819 | }; |
820 | |
821 | static const struct acpi_device_id cnl_pinctrl_acpi_match[] = { |
822 | { "INT3450" , (kernel_ulong_t)&cnlh_soc_data }, |
823 | { "INT34BB" , (kernel_ulong_t)&cnllp_soc_data }, |
824 | { } |
825 | }; |
826 | MODULE_DEVICE_TABLE(acpi, cnl_pinctrl_acpi_match); |
827 | |
828 | static struct platform_driver cnl_pinctrl_driver = { |
829 | .probe = intel_pinctrl_probe_by_hid, |
830 | .driver = { |
831 | .name = "cannonlake-pinctrl" , |
832 | .acpi_match_table = cnl_pinctrl_acpi_match, |
833 | .pm = pm_sleep_ptr(&intel_pinctrl_pm_ops), |
834 | }, |
835 | }; |
836 | module_platform_driver(cnl_pinctrl_driver); |
837 | |
838 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>" ); |
839 | MODULE_DESCRIPTION("Intel Cannon Lake PCH pinctrl/GPIO driver" ); |
840 | MODULE_LICENSE("GPL v2" ); |
841 | MODULE_IMPORT_NS(PINCTRL_INTEL); |
842 | |