1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (C) 2021 MediaTek Inc. |
4 | * Author: Zhiyong Tao <zhiyong.tao@mediatek.com> |
5 | */ |
6 | |
7 | #include <dt-bindings/pinctrl/mt65xx.h> |
8 | #include <linux/of.h> |
9 | #include <linux/module.h> |
10 | #include <linux/pinctrl/pinctrl.h> |
11 | #include <linux/platform_device.h> |
12 | #include <linux/regmap.h> |
13 | |
14 | #include "pinctrl-mtk-common.h" |
15 | #include "pinctrl-mtk-mt8365.h" |
16 | |
17 | static const struct mtk_drv_group_desc mt8365_drv_grp[] = { |
18 | /* 0E4E8SR 4/8/12/16 */ |
19 | MTK_DRV_GRP(4, 16, 1, 2, 4), |
20 | /* 0E2E4SR 2/4/6/8 */ |
21 | MTK_DRV_GRP(2, 8, 1, 2, 2), |
22 | /* E8E4E2 2/4/6/8/10/12/14/16 */ |
23 | MTK_DRV_GRP(2, 16, 0, 2, 2) |
24 | }; |
25 | |
26 | static const struct mtk_pin_drv_grp mt8365_pin_drv[] = { |
27 | |
28 | MTK_PIN_DRV_GRP(0, 0x710, 0, 2), |
29 | MTK_PIN_DRV_GRP(1, 0x710, 0, 2), |
30 | MTK_PIN_DRV_GRP(2, 0x710, 0, 2), |
31 | MTK_PIN_DRV_GRP(3, 0x710, 0, 2), |
32 | MTK_PIN_DRV_GRP(4, 0x710, 4, 2), |
33 | MTK_PIN_DRV_GRP(5, 0x710, 4, 2), |
34 | MTK_PIN_DRV_GRP(6, 0x710, 4, 2), |
35 | MTK_PIN_DRV_GRP(7, 0x710, 4, 2), |
36 | MTK_PIN_DRV_GRP(8, 0x710, 8, 2), |
37 | MTK_PIN_DRV_GRP(9, 0x710, 8, 2), |
38 | MTK_PIN_DRV_GRP(10, 0x710, 8, 2), |
39 | MTK_PIN_DRV_GRP(11, 0x710, 8, 2), |
40 | MTK_PIN_DRV_GRP(12, 0x710, 12, 2), |
41 | MTK_PIN_DRV_GRP(13, 0x710, 12, 2), |
42 | MTK_PIN_DRV_GRP(14, 0x710, 12, 2), |
43 | MTK_PIN_DRV_GRP(15, 0x710, 12, 2), |
44 | MTK_PIN_DRV_GRP(16, 0x710, 16, 2), |
45 | MTK_PIN_DRV_GRP(17, 0x710, 16, 2), |
46 | MTK_PIN_DRV_GRP(18, 0x710, 16, 2), |
47 | MTK_PIN_DRV_GRP(19, 0x710, 20, 2), |
48 | MTK_PIN_DRV_GRP(20, 0x710, 24, 2), |
49 | MTK_PIN_DRV_GRP(21, 0x710, 24, 2), |
50 | MTK_PIN_DRV_GRP(22, 0x710, 28, 2), |
51 | MTK_PIN_DRV_GRP(23, 0x720, 0, 2), |
52 | MTK_PIN_DRV_GRP(24, 0x720, 0, 2), |
53 | MTK_PIN_DRV_GRP(25, 0x720, 0, 2), |
54 | MTK_PIN_DRV_GRP(26, 0x720, 4, 2), |
55 | MTK_PIN_DRV_GRP(27, 0x720, 4, 2), |
56 | MTK_PIN_DRV_GRP(28, 0x720, 4, 2), |
57 | MTK_PIN_DRV_GRP(29, 0x720, 4, 2), |
58 | MTK_PIN_DRV_GRP(30, 0x720, 8, 2), |
59 | MTK_PIN_DRV_GRP(31, 0x720, 8, 2), |
60 | MTK_PIN_DRV_GRP(32, 0x720, 8, 2), |
61 | MTK_PIN_DRV_GRP(33, 0x720, 8, 2), |
62 | MTK_PIN_DRV_GRP(34, 0x720, 8, 2), |
63 | MTK_PIN_DRV_GRP(35, 0x720, 12, 2), |
64 | MTK_PIN_DRV_GRP(36, 0x720, 12, 2), |
65 | MTK_PIN_DRV_GRP(37, 0x720, 12, 2), |
66 | MTK_PIN_DRV_GRP(38, 0x720, 12, 2), |
67 | MTK_PIN_DRV_GRP(39, 0x720, 12, 2), |
68 | MTK_PIN_DRV_GRP(40, 0x720, 12, 2), |
69 | MTK_PIN_DRV_GRP(41, 0x720, 16, 2), |
70 | MTK_PIN_DRV_GRP(42, 0x720, 16, 2), |
71 | MTK_PIN_DRV_GRP(43, 0x720, 16, 2), |
72 | MTK_PIN_DRV_GRP(44, 0x720, 16, 2), |
73 | MTK_PIN_DRV_GRP(45, 0x720, 20, 2), |
74 | MTK_PIN_DRV_GRP(46, 0x720, 20, 2), |
75 | MTK_PIN_DRV_GRP(47, 0x720, 20, 2), |
76 | MTK_PIN_DRV_GRP(48, 0x720, 20, 2), |
77 | MTK_PIN_DRV_GRP(49, 0x720, 24, 2), |
78 | MTK_PIN_DRV_GRP(50, 0x720, 24, 2), |
79 | MTK_PIN_DRV_GRP(51, 0x720, 24, 2), |
80 | MTK_PIN_DRV_GRP(52, 0x720, 24, 2), |
81 | MTK_PIN_DRV_GRP(53, 0x720, 24, 2), |
82 | MTK_PIN_DRV_GRP(54, 0x720, 24, 2), |
83 | MTK_PIN_DRV_GRP(55, 0x720, 24, 2), |
84 | MTK_PIN_DRV_GRP(56, 0x720, 24, 2), |
85 | MTK_PIN_DRV_GRP(57, 0x720, 28, 2), |
86 | MTK_PIN_DRV_GRP(58, 0x720, 28, 2), |
87 | MTK_PIN_DRV_GRP(59, 0x730, 0, 2), |
88 | MTK_PIN_DRV_GRP(60, 0x730, 0, 2), |
89 | MTK_PIN_DRV_GRP(61, 0x730, 4, 2), |
90 | MTK_PIN_DRV_GRP(62, 0x730, 4, 2), |
91 | MTK_PIN_DRV_GRP(63, 0x730, 8, 2), |
92 | MTK_PIN_DRV_GRP(64, 0x730, 8, 2), |
93 | MTK_PIN_DRV_GRP(65, 0x730, 12, 2), |
94 | MTK_PIN_DRV_GRP(66, 0x730, 12, 2), |
95 | MTK_PIN_DRV_GRP(67, 0x730, 12, 2), |
96 | MTK_PIN_DRV_GRP(68, 0x730, 12, 2), |
97 | MTK_PIN_DRV_GRP(69, 0x730, 12, 2), |
98 | MTK_PIN_DRV_GRP(70, 0x730, 12, 2), |
99 | MTK_PIN_DRV_GRP(71, 0x730, 16, 2), |
100 | MTK_PIN_DRV_GRP(72, 0x730, 16, 2), |
101 | MTK_PIN_DRV_GRP(73, 0x730, 16, 2), |
102 | MTK_PIN_DRV_GRP(74, 0x730, 16, 2), |
103 | MTK_PIN_DRV_GRP(75, 0x730, 16, 2), |
104 | MTK_PIN_DRV_GRP(76, 0x730, 16, 2), |
105 | MTK_PIN_DRV_GRP(77, 0x730, 16, 2), |
106 | MTK_PIN_DRV_GRP(78, 0x730, 16, 2), |
107 | MTK_PIN_DRV_GRP(79, 0x730, 16, 2), |
108 | MTK_PIN_DRV_GRP(80, 0x730, 20, 2), |
109 | MTK_PIN_DRV_GRP(81, 0x730, 24, 2), |
110 | MTK_PIN_DRV_GRP(82, 0x730, 28, 2), |
111 | MTK_PIN_DRV_GRP(83, 0x730, 28, 2), |
112 | MTK_PIN_DRV_GRP(84, 0x730, 28, 2), |
113 | MTK_PIN_DRV_GRP(85, 0x730, 28, 2), |
114 | MTK_PIN_DRV_GRP(86, 0x740, 12, 2), |
115 | MTK_PIN_DRV_GRP(87, 0x740, 16, 2), |
116 | MTK_PIN_DRV_GRP(88, 0x740, 20, 2), |
117 | MTK_PIN_DRV_GRP(89, 0x740, 24, 2), |
118 | MTK_PIN_DRV_GRP(90, 0x740, 24, 2), |
119 | MTK_PIN_DRV_GRP(91, 0x740, 24, 2), |
120 | MTK_PIN_DRV_GRP(92, 0x740, 24, 2), |
121 | MTK_PIN_DRV_GRP(93, 0x750, 8, 2), |
122 | MTK_PIN_DRV_GRP(94, 0x750, 8, 2), |
123 | MTK_PIN_DRV_GRP(95, 0x750, 8, 2), |
124 | MTK_PIN_DRV_GRP(96, 0x750, 8, 2), |
125 | MTK_PIN_DRV_GRP(97, 0x750, 24, 2), |
126 | MTK_PIN_DRV_GRP(98, 0x750, 28, 2), |
127 | MTK_PIN_DRV_GRP(99, 0x760, 0, 2), |
128 | MTK_PIN_DRV_GRP(100, 0x750, 8, 2), |
129 | MTK_PIN_DRV_GRP(101, 0x750, 8, 2), |
130 | MTK_PIN_DRV_GRP(102, 0x750, 8, 2), |
131 | MTK_PIN_DRV_GRP(103, 0x750, 8, 2), |
132 | MTK_PIN_DRV_GRP(104, 0x760, 20, 2), |
133 | MTK_PIN_DRV_GRP(105, 0x760, 24, 2), |
134 | MTK_PIN_DRV_GRP(106, 0x760, 24, 2), |
135 | MTK_PIN_DRV_GRP(107, 0x760, 24, 2), |
136 | MTK_PIN_DRV_GRP(108, 0x760, 24, 2), |
137 | MTK_PIN_DRV_GRP(109, 0x760, 24, 2), |
138 | MTK_PIN_DRV_GRP(110, 0x760, 28, 2), |
139 | MTK_PIN_DRV_GRP(111, 0x760, 28, 2), |
140 | MTK_PIN_DRV_GRP(112, 0x760, 28, 2), |
141 | MTK_PIN_DRV_GRP(113, 0x760, 28, 2), |
142 | MTK_PIN_DRV_GRP(114, 0x770, 0, 2), |
143 | MTK_PIN_DRV_GRP(115, 0x770, 0, 2), |
144 | MTK_PIN_DRV_GRP(116, 0x770, 0, 2), |
145 | MTK_PIN_DRV_GRP(117, 0x770, 4, 2), |
146 | MTK_PIN_DRV_GRP(118, 0x770, 4, 2), |
147 | MTK_PIN_DRV_GRP(119, 0x770, 4, 2), |
148 | MTK_PIN_DRV_GRP(120, 0x770, 8, 2), |
149 | MTK_PIN_DRV_GRP(121, 0x770, 8, 2), |
150 | MTK_PIN_DRV_GRP(122, 0x770, 8, 2), |
151 | MTK_PIN_DRV_GRP(123, 0x770, 12, 2), |
152 | MTK_PIN_DRV_GRP(124, 0x770, 12, 2), |
153 | MTK_PIN_DRV_GRP(125, 0x770, 12, 2), |
154 | MTK_PIN_DRV_GRP(126, 0x770, 16, 2), |
155 | MTK_PIN_DRV_GRP(127, 0x770, 16, 2), |
156 | MTK_PIN_DRV_GRP(128, 0x770, 16, 2), |
157 | MTK_PIN_DRV_GRP(129, 0x770, 20, 2), |
158 | MTK_PIN_DRV_GRP(130, 0x770, 20, 2), |
159 | MTK_PIN_DRV_GRP(131, 0x770, 20, 2), |
160 | MTK_PIN_DRV_GRP(132, 0x770, 20, 2), |
161 | MTK_PIN_DRV_GRP(133, 0x770, 20, 2), |
162 | MTK_PIN_DRV_GRP(134, 0x770, 20, 2), |
163 | MTK_PIN_DRV_GRP(135, 0x770, 20, 2), |
164 | MTK_PIN_DRV_GRP(136, 0x770, 24, 2), |
165 | MTK_PIN_DRV_GRP(137, 0x770, 24, 2), |
166 | MTK_PIN_DRV_GRP(138, 0x770, 24, 2), |
167 | MTK_PIN_DRV_GRP(139, 0x770, 24, 2), |
168 | MTK_PIN_DRV_GRP(140, 0x770, 24, 2), |
169 | MTK_PIN_DRV_GRP(141, 0x770, 24, 2), |
170 | MTK_PIN_DRV_GRP(142, 0x770, 24, 2), |
171 | MTK_PIN_DRV_GRP(143, 0x770, 24, 2), |
172 | MTK_PIN_DRV_GRP(144, 0x770, 24, 2), |
173 | }; |
174 | |
175 | static const struct mtk_pin_spec_pupd_set_samereg mt8365_spec_pupd[] = { |
176 | MTK_PIN_PUPD_SPEC_SR(22, 0x070, 0, 2, 1), |
177 | MTK_PIN_PUPD_SPEC_SR(23, 0x070, 3, 5, 4), |
178 | MTK_PIN_PUPD_SPEC_SR(24, 0x070, 6, 8, 7), |
179 | MTK_PIN_PUPD_SPEC_SR(25, 0x070, 9, 11, 10), |
180 | MTK_PIN_PUPD_SPEC_SR(80, 0x070, 14, 13, 12), |
181 | MTK_PIN_PUPD_SPEC_SR(81, 0x070, 17, 16, 15), |
182 | MTK_PIN_PUPD_SPEC_SR(82, 0x070, 20, 19, 18), |
183 | MTK_PIN_PUPD_SPEC_SR(83, 0x070, 23, 22, 21), |
184 | MTK_PIN_PUPD_SPEC_SR(84, 0x070, 26, 25, 24), |
185 | MTK_PIN_PUPD_SPEC_SR(85, 0x070, 29, 28, 27), |
186 | MTK_PIN_PUPD_SPEC_SR(86, 0x080, 2, 1, 0), |
187 | MTK_PIN_PUPD_SPEC_SR(87, 0x080, 5, 4, 3), |
188 | MTK_PIN_PUPD_SPEC_SR(88, 0x080, 8, 7, 6), |
189 | MTK_PIN_PUPD_SPEC_SR(89, 0x080, 11, 10, 9), |
190 | MTK_PIN_PUPD_SPEC_SR(90, 0x080, 14, 13, 12), |
191 | MTK_PIN_PUPD_SPEC_SR(91, 0x080, 17, 16, 15), |
192 | MTK_PIN_PUPD_SPEC_SR(92, 0x080, 20, 19, 18), |
193 | MTK_PIN_PUPD_SPEC_SR(93, 0x080, 23, 22, 21), |
194 | MTK_PIN_PUPD_SPEC_SR(94, 0x080, 26, 25, 24), |
195 | MTK_PIN_PUPD_SPEC_SR(95, 0x080, 29, 28, 27), |
196 | MTK_PIN_PUPD_SPEC_SR(96, 0x090, 2, 1, 0), |
197 | MTK_PIN_PUPD_SPEC_SR(97, 0x090, 5, 4, 3), |
198 | MTK_PIN_PUPD_SPEC_SR(98, 0x090, 8, 7, 6), |
199 | MTK_PIN_PUPD_SPEC_SR(99, 0x090, 11, 10, 9), |
200 | MTK_PIN_PUPD_SPEC_SR(100, 0x090, 14, 13, 12), |
201 | MTK_PIN_PUPD_SPEC_SR(101, 0x090, 17, 16, 15), |
202 | MTK_PIN_PUPD_SPEC_SR(102, 0x090, 20, 19, 18), |
203 | MTK_PIN_PUPD_SPEC_SR(103, 0x090, 23, 22, 21), |
204 | MTK_PIN_PUPD_SPEC_SR(104, 0x090, 26, 25, 24), |
205 | MTK_PIN_PUPD_SPEC_SR(105, 0x090, 29, 28, 27), |
206 | MTK_PIN_PUPD_SPEC_SR(106, 0x0F0, 2, 1, 0), |
207 | MTK_PIN_PUPD_SPEC_SR(107, 0x0F0, 5, 4, 3), |
208 | MTK_PIN_PUPD_SPEC_SR(108, 0x0F0, 8, 7, 6), |
209 | MTK_PIN_PUPD_SPEC_SR(109, 0x0F0, 11, 10, 9), |
210 | }; |
211 | |
212 | static const struct mtk_pin_ies_smt_set mt8365_ies_set[] = { |
213 | MTK_PIN_IES_SMT_SPEC(0, 3, 0x410, 0), |
214 | MTK_PIN_IES_SMT_SPEC(4, 7, 0x410, 1), |
215 | MTK_PIN_IES_SMT_SPEC(8, 11, 0x410, 2), |
216 | MTK_PIN_IES_SMT_SPEC(12, 15, 0x410, 3), |
217 | MTK_PIN_IES_SMT_SPEC(16, 18, 0x410, 4), |
218 | MTK_PIN_IES_SMT_SPEC(19, 19, 0x410, 5), |
219 | MTK_PIN_IES_SMT_SPEC(20, 21, 0x410, 6), |
220 | MTK_PIN_IES_SMT_SPEC(22, 22, 0x410, 7), |
221 | MTK_PIN_IES_SMT_SPEC(23, 25, 0x410, 8), |
222 | MTK_PIN_IES_SMT_SPEC(26, 29, 0x410, 9), |
223 | MTK_PIN_IES_SMT_SPEC(30, 34, 0x410, 10), |
224 | MTK_PIN_IES_SMT_SPEC(35, 40, 0x410, 11), |
225 | MTK_PIN_IES_SMT_SPEC(41, 44, 0x410, 12), |
226 | MTK_PIN_IES_SMT_SPEC(45, 48, 0x410, 13), |
227 | MTK_PIN_IES_SMT_SPEC(49, 56, 0x410, 14), |
228 | MTK_PIN_IES_SMT_SPEC(57, 58, 0x410, 15), |
229 | MTK_PIN_IES_SMT_SPEC(59, 60, 0x410, 16), |
230 | MTK_PIN_IES_SMT_SPEC(61, 62, 0x410, 17), |
231 | MTK_PIN_IES_SMT_SPEC(63, 64, 0x410, 18), |
232 | MTK_PIN_IES_SMT_SPEC(65, 70, 0x410, 19), |
233 | MTK_PIN_IES_SMT_SPEC(71, 79, 0x410, 20), |
234 | MTK_PIN_IES_SMT_SPEC(80, 80, 0x410, 21), |
235 | MTK_PIN_IES_SMT_SPEC(81, 81, 0x410, 22), |
236 | MTK_PIN_IES_SMT_SPEC(82, 82, 0x410, 23), |
237 | MTK_PIN_IES_SMT_SPEC(83, 83, 0x410, 24), |
238 | MTK_PIN_IES_SMT_SPEC(84, 84, 0x410, 25), |
239 | MTK_PIN_IES_SMT_SPEC(85, 85, 0x410, 26), |
240 | MTK_PIN_IES_SMT_SPEC(86, 86, 0x410, 27), |
241 | MTK_PIN_IES_SMT_SPEC(87, 87, 0x410, 28), |
242 | MTK_PIN_IES_SMT_SPEC(88, 88, 0x410, 29), |
243 | MTK_PIN_IES_SMT_SPEC(89, 89, 0x410, 30), |
244 | MTK_PIN_IES_SMT_SPEC(90, 90, 0x410, 31), |
245 | MTK_PIN_IES_SMT_SPEC(91, 91, 0x420, 0), |
246 | MTK_PIN_IES_SMT_SPEC(92, 92, 0x420, 1), |
247 | MTK_PIN_IES_SMT_SPEC(93, 93, 0x420, 2), |
248 | MTK_PIN_IES_SMT_SPEC(94, 94, 0x420, 3), |
249 | MTK_PIN_IES_SMT_SPEC(95, 95, 0x420, 4), |
250 | MTK_PIN_IES_SMT_SPEC(96, 96, 0x420, 5), |
251 | MTK_PIN_IES_SMT_SPEC(97, 97, 0x420, 6), |
252 | MTK_PIN_IES_SMT_SPEC(98, 98, 0x420, 7), |
253 | MTK_PIN_IES_SMT_SPEC(99, 99, 0x420, 8), |
254 | MTK_PIN_IES_SMT_SPEC(100, 100, 0x420, 9), |
255 | MTK_PIN_IES_SMT_SPEC(101, 101, 0x420, 10), |
256 | MTK_PIN_IES_SMT_SPEC(102, 102, 0x420, 11), |
257 | MTK_PIN_IES_SMT_SPEC(103, 103, 0x420, 12), |
258 | MTK_PIN_IES_SMT_SPEC(104, 104, 0x420, 13), |
259 | MTK_PIN_IES_SMT_SPEC(105, 109, 0x420, 14), |
260 | MTK_PIN_IES_SMT_SPEC(110, 113, 0x420, 15), |
261 | MTK_PIN_IES_SMT_SPEC(114, 116, 0x420, 16), |
262 | MTK_PIN_IES_SMT_SPEC(117, 119, 0x420, 17), |
263 | MTK_PIN_IES_SMT_SPEC(120, 122, 0x420, 18), |
264 | MTK_PIN_IES_SMT_SPEC(123, 125, 0x420, 19), |
265 | MTK_PIN_IES_SMT_SPEC(126, 128, 0x420, 20), |
266 | MTK_PIN_IES_SMT_SPEC(129, 135, 0x420, 21), |
267 | MTK_PIN_IES_SMT_SPEC(136, 144, 0x420, 22), |
268 | }; |
269 | |
270 | static const struct mtk_pin_ies_smt_set mt8365_smt_set[] = { |
271 | MTK_PIN_IES_SMT_SPEC(0, 0, 0x470, 0), |
272 | MTK_PIN_IES_SMT_SPEC(1, 1, 0x470, 0), |
273 | MTK_PIN_IES_SMT_SPEC(2, 2, 0x470, 0), |
274 | MTK_PIN_IES_SMT_SPEC(3, 3, 0x470, 0), |
275 | MTK_PIN_IES_SMT_SPEC(4, 4, 0x470, 1), |
276 | MTK_PIN_IES_SMT_SPEC(5, 5, 0x470, 1), |
277 | MTK_PIN_IES_SMT_SPEC(6, 6, 0x470, 1), |
278 | MTK_PIN_IES_SMT_SPEC(7, 7, 0x470, 1), |
279 | MTK_PIN_IES_SMT_SPEC(8, 8, 0x470, 2), |
280 | MTK_PIN_IES_SMT_SPEC(9, 9, 0x470, 2), |
281 | MTK_PIN_IES_SMT_SPEC(10, 10, 0x470, 2), |
282 | MTK_PIN_IES_SMT_SPEC(11, 11, 0x470, 2), |
283 | MTK_PIN_IES_SMT_SPEC(12, 12, 0x470, 3), |
284 | MTK_PIN_IES_SMT_SPEC(13, 13, 0x470, 3), |
285 | MTK_PIN_IES_SMT_SPEC(14, 14, 0x470, 3), |
286 | MTK_PIN_IES_SMT_SPEC(15, 15, 0x470, 3), |
287 | MTK_PIN_IES_SMT_SPEC(16, 16, 0x470, 4), |
288 | MTK_PIN_IES_SMT_SPEC(17, 17, 0x470, 4), |
289 | MTK_PIN_IES_SMT_SPEC(18, 18, 0x470, 4), |
290 | MTK_PIN_IES_SMT_SPEC(19, 19, 0x470, 5), |
291 | MTK_PIN_IES_SMT_SPEC(20, 20, 0x470, 6), |
292 | MTK_PIN_IES_SMT_SPEC(21, 21, 0x470, 6), |
293 | MTK_PIN_IES_SMT_SPEC(22, 22, 0x470, 7), |
294 | MTK_PIN_IES_SMT_SPEC(23, 23, 0x470, 8), |
295 | MTK_PIN_IES_SMT_SPEC(24, 24, 0x470, 8), |
296 | MTK_PIN_IES_SMT_SPEC(25, 25, 0x470, 8), |
297 | MTK_PIN_IES_SMT_SPEC(26, 26, 0x470, 9), |
298 | MTK_PIN_IES_SMT_SPEC(27, 27, 0x470, 9), |
299 | MTK_PIN_IES_SMT_SPEC(28, 28, 0x470, 9), |
300 | MTK_PIN_IES_SMT_SPEC(29, 29, 0x470, 9), |
301 | MTK_PIN_IES_SMT_SPEC(30, 30, 0x470, 10), |
302 | MTK_PIN_IES_SMT_SPEC(31, 31, 0x470, 10), |
303 | MTK_PIN_IES_SMT_SPEC(32, 32, 0x470, 10), |
304 | MTK_PIN_IES_SMT_SPEC(33, 33, 0x470, 10), |
305 | MTK_PIN_IES_SMT_SPEC(34, 34, 0x470, 10), |
306 | MTK_PIN_IES_SMT_SPEC(35, 35, 0x470, 11), |
307 | MTK_PIN_IES_SMT_SPEC(36, 36, 0x470, 11), |
308 | MTK_PIN_IES_SMT_SPEC(37, 37, 0x470, 11), |
309 | MTK_PIN_IES_SMT_SPEC(38, 38, 0x470, 11), |
310 | MTK_PIN_IES_SMT_SPEC(39, 39, 0x470, 11), |
311 | MTK_PIN_IES_SMT_SPEC(40, 40, 0x470, 11), |
312 | MTK_PIN_IES_SMT_SPEC(41, 41, 0x470, 12), |
313 | MTK_PIN_IES_SMT_SPEC(42, 42, 0x470, 12), |
314 | MTK_PIN_IES_SMT_SPEC(43, 43, 0x470, 12), |
315 | MTK_PIN_IES_SMT_SPEC(44, 44, 0x470, 12), |
316 | MTK_PIN_IES_SMT_SPEC(45, 45, 0x470, 13), |
317 | MTK_PIN_IES_SMT_SPEC(46, 46, 0x470, 13), |
318 | MTK_PIN_IES_SMT_SPEC(47, 47, 0x470, 13), |
319 | MTK_PIN_IES_SMT_SPEC(48, 48, 0x470, 13), |
320 | MTK_PIN_IES_SMT_SPEC(49, 49, 0x470, 14), |
321 | MTK_PIN_IES_SMT_SPEC(50, 50, 0x470, 14), |
322 | MTK_PIN_IES_SMT_SPEC(51, 51, 0x470, 14), |
323 | MTK_PIN_IES_SMT_SPEC(52, 52, 0x470, 14), |
324 | MTK_PIN_IES_SMT_SPEC(53, 53, 0x470, 14), |
325 | MTK_PIN_IES_SMT_SPEC(54, 54, 0x470, 14), |
326 | MTK_PIN_IES_SMT_SPEC(55, 55, 0x470, 14), |
327 | MTK_PIN_IES_SMT_SPEC(56, 56, 0x470, 14), |
328 | MTK_PIN_IES_SMT_SPEC(57, 57, 0x470, 15), |
329 | MTK_PIN_IES_SMT_SPEC(58, 58, 0x470, 15), |
330 | MTK_PIN_IES_SMT_SPEC(59, 59, 0x470, 16), |
331 | MTK_PIN_IES_SMT_SPEC(60, 60, 0x470, 16), |
332 | MTK_PIN_IES_SMT_SPEC(61, 61, 0x470, 17), |
333 | MTK_PIN_IES_SMT_SPEC(62, 62, 0x470, 17), |
334 | MTK_PIN_IES_SMT_SPEC(63, 63, 0x470, 18), |
335 | MTK_PIN_IES_SMT_SPEC(64, 64, 0x470, 18), |
336 | MTK_PIN_IES_SMT_SPEC(65, 65, 0x470, 19), |
337 | MTK_PIN_IES_SMT_SPEC(66, 66, 0x470, 19), |
338 | MTK_PIN_IES_SMT_SPEC(67, 67, 0x470, 19), |
339 | MTK_PIN_IES_SMT_SPEC(68, 68, 0x470, 19), |
340 | MTK_PIN_IES_SMT_SPEC(69, 69, 0x470, 19), |
341 | MTK_PIN_IES_SMT_SPEC(70, 70, 0x470, 19), |
342 | MTK_PIN_IES_SMT_SPEC(71, 71, 0x470, 20), |
343 | MTK_PIN_IES_SMT_SPEC(72, 72, 0x470, 20), |
344 | MTK_PIN_IES_SMT_SPEC(73, 73, 0x470, 20), |
345 | MTK_PIN_IES_SMT_SPEC(74, 74, 0x470, 20), |
346 | MTK_PIN_IES_SMT_SPEC(75, 75, 0x470, 20), |
347 | MTK_PIN_IES_SMT_SPEC(76, 76, 0x470, 20), |
348 | MTK_PIN_IES_SMT_SPEC(77, 77, 0x470, 20), |
349 | MTK_PIN_IES_SMT_SPEC(78, 78, 0x470, 20), |
350 | MTK_PIN_IES_SMT_SPEC(79, 79, 0x470, 20), |
351 | MTK_PIN_IES_SMT_SPEC(80, 80, 0x470, 21), |
352 | MTK_PIN_IES_SMT_SPEC(81, 81, 0x470, 22), |
353 | MTK_PIN_IES_SMT_SPEC(82, 82, 0x470, 23), |
354 | MTK_PIN_IES_SMT_SPEC(83, 83, 0x470, 24), |
355 | MTK_PIN_IES_SMT_SPEC(84, 84, 0x470, 25), |
356 | MTK_PIN_IES_SMT_SPEC(85, 85, 0x470, 26), |
357 | MTK_PIN_IES_SMT_SPEC(86, 86, 0x470, 27), |
358 | MTK_PIN_IES_SMT_SPEC(87, 87, 0x470, 28), |
359 | MTK_PIN_IES_SMT_SPEC(88, 88, 0x470, 29), |
360 | MTK_PIN_IES_SMT_SPEC(89, 89, 0x470, 30), |
361 | MTK_PIN_IES_SMT_SPEC(90, 90, 0x470, 31), |
362 | MTK_PIN_IES_SMT_SPEC(91, 91, 0x480, 0), |
363 | MTK_PIN_IES_SMT_SPEC(92, 92, 0x480, 1), |
364 | MTK_PIN_IES_SMT_SPEC(93, 93, 0x480, 2), |
365 | MTK_PIN_IES_SMT_SPEC(94, 94, 0x480, 3), |
366 | MTK_PIN_IES_SMT_SPEC(95, 95, 0x480, 4), |
367 | MTK_PIN_IES_SMT_SPEC(96, 96, 0x480, 5), |
368 | MTK_PIN_IES_SMT_SPEC(97, 97, 0x480, 6), |
369 | MTK_PIN_IES_SMT_SPEC(98, 98, 0x480, 7), |
370 | MTK_PIN_IES_SMT_SPEC(99, 99, 0x480, 8), |
371 | MTK_PIN_IES_SMT_SPEC(100, 100, 0x480, 9), |
372 | MTK_PIN_IES_SMT_SPEC(101, 101, 0x480, 10), |
373 | MTK_PIN_IES_SMT_SPEC(102, 102, 0x480, 11), |
374 | MTK_PIN_IES_SMT_SPEC(103, 103, 0x480, 12), |
375 | MTK_PIN_IES_SMT_SPEC(104, 104, 0x480, 13), |
376 | MTK_PIN_IES_SMT_SPEC(105, 105, 0x480, 14), |
377 | MTK_PIN_IES_SMT_SPEC(106, 106, 0x480, 14), |
378 | MTK_PIN_IES_SMT_SPEC(107, 107, 0x480, 14), |
379 | MTK_PIN_IES_SMT_SPEC(108, 108, 0x480, 14), |
380 | MTK_PIN_IES_SMT_SPEC(109, 109, 0x480, 14), |
381 | MTK_PIN_IES_SMT_SPEC(110, 110, 0x480, 15), |
382 | MTK_PIN_IES_SMT_SPEC(111, 111, 0x480, 15), |
383 | MTK_PIN_IES_SMT_SPEC(112, 112, 0x480, 15), |
384 | MTK_PIN_IES_SMT_SPEC(113, 113, 0x480, 15), |
385 | MTK_PIN_IES_SMT_SPEC(114, 114, 0x480, 16), |
386 | MTK_PIN_IES_SMT_SPEC(115, 115, 0x480, 16), |
387 | MTK_PIN_IES_SMT_SPEC(116, 116, 0x480, 16), |
388 | MTK_PIN_IES_SMT_SPEC(117, 117, 0x480, 17), |
389 | MTK_PIN_IES_SMT_SPEC(118, 118, 0x480, 17), |
390 | MTK_PIN_IES_SMT_SPEC(119, 119, 0x480, 17), |
391 | MTK_PIN_IES_SMT_SPEC(120, 120, 0x480, 18), |
392 | MTK_PIN_IES_SMT_SPEC(121, 121, 0x480, 18), |
393 | MTK_PIN_IES_SMT_SPEC(122, 122, 0x480, 18), |
394 | MTK_PIN_IES_SMT_SPEC(123, 123, 0x480, 19), |
395 | MTK_PIN_IES_SMT_SPEC(124, 124, 0x480, 19), |
396 | MTK_PIN_IES_SMT_SPEC(125, 125, 0x480, 19), |
397 | MTK_PIN_IES_SMT_SPEC(126, 126, 0x480, 20), |
398 | MTK_PIN_IES_SMT_SPEC(127, 127, 0x480, 20), |
399 | MTK_PIN_IES_SMT_SPEC(128, 128, 0x480, 20), |
400 | MTK_PIN_IES_SMT_SPEC(129, 129, 0x480, 21), |
401 | MTK_PIN_IES_SMT_SPEC(130, 130, 0x480, 21), |
402 | MTK_PIN_IES_SMT_SPEC(131, 131, 0x480, 21), |
403 | MTK_PIN_IES_SMT_SPEC(132, 132, 0x480, 21), |
404 | MTK_PIN_IES_SMT_SPEC(133, 133, 0x480, 21), |
405 | MTK_PIN_IES_SMT_SPEC(134, 134, 0x480, 21), |
406 | MTK_PIN_IES_SMT_SPEC(135, 135, 0x480, 21), |
407 | MTK_PIN_IES_SMT_SPEC(136, 136, 0x480, 22), |
408 | MTK_PIN_IES_SMT_SPEC(137, 137, 0x480, 22), |
409 | MTK_PIN_IES_SMT_SPEC(138, 138, 0x480, 22), |
410 | MTK_PIN_IES_SMT_SPEC(139, 139, 0x480, 22), |
411 | MTK_PIN_IES_SMT_SPEC(140, 140, 0x480, 22), |
412 | MTK_PIN_IES_SMT_SPEC(141, 141, 0x480, 22), |
413 | MTK_PIN_IES_SMT_SPEC(142, 142, 0x480, 22), |
414 | MTK_PIN_IES_SMT_SPEC(143, 143, 0x480, 22), |
415 | MTK_PIN_IES_SMT_SPEC(144, 144, 0x480, 22), |
416 | }; |
417 | |
418 | static int mt8365_set_clr_mode(struct regmap *regmap, |
419 | unsigned int bit, unsigned int reg_pullen, unsigned int reg_pullsel, |
420 | bool enable, bool isup) |
421 | { |
422 | int ret; |
423 | |
424 | ret = regmap_update_bits(map: regmap, reg: reg_pullen, BIT(bit), val: enable << bit); |
425 | if (ret) |
426 | return -EINVAL; |
427 | |
428 | ret = regmap_update_bits(map: regmap, reg: reg_pullsel, BIT(bit), val: isup << bit); |
429 | if (ret) |
430 | return -EINVAL; |
431 | |
432 | return 0; |
433 | } |
434 | |
435 | static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = { |
436 | .pins = mtk_pins_mt8365, |
437 | .npins = ARRAY_SIZE(mtk_pins_mt8365), |
438 | .grp_desc = mt8365_drv_grp, |
439 | .n_grp_cls = ARRAY_SIZE(mt8365_drv_grp), |
440 | .pin_drv_grp = mt8365_pin_drv, |
441 | .n_pin_drv_grps = ARRAY_SIZE(mt8365_pin_drv), |
442 | .spec_ies = mt8365_ies_set, |
443 | .n_spec_ies = ARRAY_SIZE(mt8365_ies_set), |
444 | .spec_smt = mt8365_smt_set, |
445 | .n_spec_smt = ARRAY_SIZE(mt8365_smt_set), |
446 | .spec_pupd = mt8365_spec_pupd, |
447 | .n_spec_pupd = ARRAY_SIZE(mt8365_spec_pupd), |
448 | .spec_pull_set = mtk_pctrl_spec_pull_set_samereg, |
449 | .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range, |
450 | .mt8365_set_clr_mode = mt8365_set_clr_mode, |
451 | .dir_offset = 0x0140, |
452 | .dout_offset = 0x00A0, |
453 | .din_offset = 0x0000, |
454 | .pinmux_offset = 0x01E0, |
455 | .ies_offset = 0x0410, |
456 | .smt_offset = 0x0470, |
457 | .pullen_offset = 0x0860, |
458 | .pullsel_offset = 0x0900, |
459 | .drv_offset = 0x0710, |
460 | .type1_start = 145, |
461 | .type1_end = 145, |
462 | .port_shf = 4, |
463 | .port_mask = 0x1f, |
464 | .port_align = 4, |
465 | .mode_mask = 0x1f, |
466 | .mode_per_reg = 10, |
467 | .mode_shf = 5, |
468 | .eint_hw = { |
469 | .port_mask = 7, |
470 | .ports = 5, |
471 | .ap_num = 160, |
472 | .db_cnt = 160, |
473 | .db_time = debounce_time_mt6765, |
474 | }, |
475 | }; |
476 | |
477 | static const struct of_device_id mt8365_pctrl_match[] = { |
478 | { .compatible = "mediatek,mt8365-pinctrl" , .data = &mt8365_pinctrl_data }, |
479 | {} |
480 | }; |
481 | |
482 | static struct platform_driver mtk_pinctrl_driver = { |
483 | .probe = mtk_pctrl_common_probe, |
484 | .driver = { |
485 | .name = "mediatek-mt8365-pinctrl" , |
486 | .of_match_table = mt8365_pctrl_match, |
487 | .pm = pm_sleep_ptr(&mtk_eint_pm_ops), |
488 | }, |
489 | }; |
490 | |
491 | static int __init mtk_pinctrl_init(void) |
492 | { |
493 | return platform_driver_register(&mtk_pinctrl_driver); |
494 | } |
495 | arch_initcall(mtk_pinctrl_init); |
496 | |
497 | MODULE_DESCRIPTION("MediaTek MT8365 Pinctrl Driver" ); |
498 | MODULE_AUTHOR("Zhiyong Tao <zhiyong.tao@mediatek.com>" ); |
499 | |