1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright(c) 2019 Intel Corporation.
4 */
5
6#ifndef __PINCTRL_EQUILIBRIUM_H
7#define __PINCTRL_EQUILIBRIUM_H
8
9/* PINPAD register offset */
10#define REG_PMX_BASE 0x0 /* Port Multiplexer Control Register */
11#define REG_PUEN 0x80 /* PULL UP Enable Register */
12#define REG_PDEN 0x84 /* PULL DOWN Enable Register */
13#define REG_SRC 0x88 /* Slew Rate Control Register */
14#define REG_DCC0 0x8C /* Drive Current Control Register 0 */
15#define REG_DCC1 0x90 /* Drive Current Control Register 1 */
16#define REG_OD 0x94 /* Open Drain Enable Register */
17#define REG_AVAIL 0x98 /* Pad Control Availability Register */
18#define DRV_CUR_PINS 16 /* Drive Current pin number per register */
19#define REG_DRCC(x) (REG_DCC0 + (x) * 4) /* Driver current macro */
20
21/* GPIO register offset */
22#define GPIO_OUT 0x0 /* Data Output Register */
23#define GPIO_IN 0x4 /* Data Input Register */
24#define GPIO_DIR 0x8 /* Direction Register */
25#define GPIO_EXINTCR0 0x18 /* External Interrupt Control Register 0 */
26#define GPIO_EXINTCR1 0x1C /* External Interrupt Control Register 1 */
27#define GPIO_IRNCR 0x20 /* IRN Capture Register */
28#define GPIO_IRNICR 0x24 /* IRN Interrupt Control Register */
29#define GPIO_IRNEN 0x28 /* IRN Interrupt Enable Register */
30#define GPIO_IRNCFG 0x2C /* IRN Interrupt Configuration Register */
31#define GPIO_IRNRNSET 0x30 /* IRN Interrupt Enable Set Register */
32#define GPIO_IRNENCLR 0x34 /* IRN Interrupt Enable Clear Register */
33#define GPIO_OUTSET 0x40 /* Output Set Register */
34#define GPIO_OUTCLR 0x44 /* Output Clear Register */
35#define GPIO_DIRSET 0x48 /* Direction Set Register */
36#define GPIO_DIRCLR 0x4C /* Direction Clear Register */
37
38/* parse given pin's driver current value */
39#define PARSE_DRV_CURRENT(val, pin) (((val) >> ((pin) * 2)) & 0x3)
40
41#define GPIO_EDGE_TRIG 0
42#define GPIO_LEVEL_TRIG 1
43#define GPIO_SINGLE_EDGE 0
44#define GPIO_BOTH_EDGE 1
45#define GPIO_POSITIVE_TRIG 0
46#define GPIO_NEGATIVE_TRIG 1
47
48#define EQBR_GPIO_MODE 0
49
50typedef enum {
51 OP_COUNT_NR_FUNCS,
52 OP_ADD_FUNCS,
53 OP_COUNT_NR_FUNC_GRPS,
54 OP_ADD_FUNC_GRPS,
55 OP_NONE,
56} funcs_util_ops;
57
58/**
59 * struct gpio_irq_type: gpio irq configuration
60 * @trig_type: level trigger or edge trigger
61 * @edge_type: sigle edge or both edge
62 * @logic_type: positive trigger or negative trigger
63 */
64struct gpio_irq_type {
65 unsigned int trig_type;
66 unsigned int edge_type;
67 unsigned int logic_type;
68};
69
70/**
71 * struct eqbr_pmx_func: represent a pin function.
72 * @name: name of the pin function, used to lookup the function.
73 * @groups: one or more names of pin groups that provide this function.
74 * @nr_groups: number of groups included in @groups.
75 */
76struct eqbr_pmx_func {
77 const char *name;
78 const char **groups;
79 unsigned int nr_groups;
80};
81
82/**
83 * struct eqbr_pin_bank: represent a pin bank.
84 * @membase: base address of the pin bank register.
85 * @id: bank id, to idenify the unique bank.
86 * @pin_base: starting pin number of the pin bank.
87 * @nr_pins: number of the pins of the pin bank.
88 * @aval_pinmap: available pin bitmap of the pin bank.
89 */
90struct eqbr_pin_bank {
91 void __iomem *membase;
92 unsigned int id;
93 unsigned int pin_base;
94 unsigned int nr_pins;
95 u32 aval_pinmap;
96};
97
98struct fwnode_handle;
99
100/**
101 * struct eqbr_gpio_ctrl: represent a gpio controller.
102 * @chip: gpio chip.
103 * @fwnode: firmware node of gpio controller.
104 * @bank: pointer to corresponding pin bank.
105 * @membase: base address of the gpio controller.
106 * @name: gpio chip name.
107 * @virq: irq number of the gpio chip to parent's irq domain.
108 * @lock: spin lock to protect gpio register write.
109 */
110struct eqbr_gpio_ctrl {
111 struct gpio_chip chip;
112 struct fwnode_handle *fwnode;
113 struct eqbr_pin_bank *bank;
114 void __iomem *membase;
115 const char *name;
116 unsigned int virq;
117 raw_spinlock_t lock; /* protect gpio register */
118};
119
120/**
121 * struct eqbr_pinctrl_drv_data:
122 * @dev: device instance representing the controller.
123 * @pctl_desc: pin controller descriptor.
124 * @pctl_dev: pin control class device
125 * @membase: base address of pin controller
126 * @pin_banks: list of pin banks of the driver.
127 * @nr_banks: number of pin banks.
128 * @gpio_ctrls: list of gpio controllers.
129 * @nr_gpio_ctrls: number of gpio controllers.
130 * @lock: protect pinctrl register write
131 */
132struct eqbr_pinctrl_drv_data {
133 struct device *dev;
134 struct pinctrl_desc pctl_desc;
135 struct pinctrl_dev *pctl_dev;
136 void __iomem *membase;
137 struct eqbr_pin_bank *pin_banks;
138 unsigned int nr_banks;
139 struct eqbr_gpio_ctrl *gpio_ctrls;
140 unsigned int nr_gpio_ctrls;
141 raw_spinlock_t lock; /* protect pinpad register */
142};
143
144#endif /* __PINCTRL_EQUILIBRIUM_H */
145

source code of linux/drivers/pinctrl/pinctrl-equilibrium.h