1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2016, BayLibre, SAS. All rights reserved. |
4 | * Author: Neil Armstrong <narmstrong@baylibre.com> |
5 | * |
6 | * Copyright (c) 2010, Code Aurora Forum. All rights reserved. |
7 | * |
8 | * Driver for Semtech SX150X I2C GPIO Expanders |
9 | * The handling of the 4-bit chips (SX1501/SX1504/SX1507) is untested. |
10 | * |
11 | * Author: Gregory Bean <gbean@codeaurora.org> |
12 | */ |
13 | |
14 | #include <linux/regmap.h> |
15 | #include <linux/i2c.h> |
16 | #include <linux/init.h> |
17 | #include <linux/interrupt.h> |
18 | #include <linux/irq.h> |
19 | #include <linux/mutex.h> |
20 | #include <linux/slab.h> |
21 | #include <linux/of.h> |
22 | #include <linux/gpio/driver.h> |
23 | #include <linux/pinctrl/pinconf.h> |
24 | #include <linux/pinctrl/pinctrl.h> |
25 | #include <linux/pinctrl/pinmux.h> |
26 | #include <linux/pinctrl/pinconf-generic.h> |
27 | |
28 | #include "core.h" |
29 | #include "pinconf.h" |
30 | #include "pinctrl-utils.h" |
31 | |
32 | /* The chip models of sx150x */ |
33 | enum { |
34 | SX150X_123 = 0, |
35 | SX150X_456, |
36 | SX150X_789, |
37 | }; |
38 | enum { |
39 | SX150X_789_REG_MISC_AUTOCLEAR_OFF = 1 << 0, |
40 | SX150X_MAX_REGISTER = 0xad, |
41 | SX150X_IRQ_TYPE_EDGE_RISING = 0x1, |
42 | SX150X_IRQ_TYPE_EDGE_FALLING = 0x2, |
43 | SX150X_789_RESET_KEY1 = 0x12, |
44 | SX150X_789_RESET_KEY2 = 0x34, |
45 | }; |
46 | |
47 | struct sx150x_123_pri { |
48 | u8 reg_pld_mode; |
49 | u8 reg_pld_table0; |
50 | u8 reg_pld_table1; |
51 | u8 reg_pld_table2; |
52 | u8 reg_pld_table3; |
53 | u8 reg_pld_table4; |
54 | u8 reg_advanced; |
55 | }; |
56 | |
57 | struct sx150x_456_pri { |
58 | u8 reg_pld_mode; |
59 | u8 reg_pld_table0; |
60 | u8 reg_pld_table1; |
61 | u8 reg_pld_table2; |
62 | u8 reg_pld_table3; |
63 | u8 reg_pld_table4; |
64 | u8 reg_advanced; |
65 | }; |
66 | |
67 | struct sx150x_789_pri { |
68 | u8 reg_drain; |
69 | u8 reg_polarity; |
70 | u8 reg_clock; |
71 | u8 reg_misc; |
72 | u8 reg_reset; |
73 | u8 ngpios; |
74 | }; |
75 | |
76 | struct sx150x_device_data { |
77 | u8 model; |
78 | u8 reg_pullup; |
79 | u8 reg_pulldn; |
80 | u8 reg_dir; |
81 | u8 reg_data; |
82 | u8 reg_irq_mask; |
83 | u8 reg_irq_src; |
84 | u8 reg_sense; |
85 | u8 ngpios; |
86 | union { |
87 | struct sx150x_123_pri x123; |
88 | struct sx150x_456_pri x456; |
89 | struct sx150x_789_pri x789; |
90 | } pri; |
91 | const struct pinctrl_pin_desc *pins; |
92 | unsigned int npins; |
93 | }; |
94 | |
95 | struct sx150x_pinctrl { |
96 | struct device *dev; |
97 | struct i2c_client *client; |
98 | struct pinctrl_dev *pctldev; |
99 | struct pinctrl_desc pinctrl_desc; |
100 | struct gpio_chip gpio; |
101 | struct regmap *regmap; |
102 | struct { |
103 | u32 sense; |
104 | u32 masked; |
105 | } irq; |
106 | struct mutex lock; |
107 | const struct sx150x_device_data *data; |
108 | }; |
109 | |
110 | static const struct pinctrl_pin_desc sx150x_4_pins[] = { |
111 | PINCTRL_PIN(0, "gpio0" ), |
112 | PINCTRL_PIN(1, "gpio1" ), |
113 | PINCTRL_PIN(2, "gpio2" ), |
114 | PINCTRL_PIN(3, "gpio3" ), |
115 | PINCTRL_PIN(4, "oscio" ), |
116 | }; |
117 | |
118 | static const struct pinctrl_pin_desc sx150x_8_pins[] = { |
119 | PINCTRL_PIN(0, "gpio0" ), |
120 | PINCTRL_PIN(1, "gpio1" ), |
121 | PINCTRL_PIN(2, "gpio2" ), |
122 | PINCTRL_PIN(3, "gpio3" ), |
123 | PINCTRL_PIN(4, "gpio4" ), |
124 | PINCTRL_PIN(5, "gpio5" ), |
125 | PINCTRL_PIN(6, "gpio6" ), |
126 | PINCTRL_PIN(7, "gpio7" ), |
127 | PINCTRL_PIN(8, "oscio" ), |
128 | }; |
129 | |
130 | static const struct pinctrl_pin_desc sx150x_16_pins[] = { |
131 | PINCTRL_PIN(0, "gpio0" ), |
132 | PINCTRL_PIN(1, "gpio1" ), |
133 | PINCTRL_PIN(2, "gpio2" ), |
134 | PINCTRL_PIN(3, "gpio3" ), |
135 | PINCTRL_PIN(4, "gpio4" ), |
136 | PINCTRL_PIN(5, "gpio5" ), |
137 | PINCTRL_PIN(6, "gpio6" ), |
138 | PINCTRL_PIN(7, "gpio7" ), |
139 | PINCTRL_PIN(8, "gpio8" ), |
140 | PINCTRL_PIN(9, "gpio9" ), |
141 | PINCTRL_PIN(10, "gpio10" ), |
142 | PINCTRL_PIN(11, "gpio11" ), |
143 | PINCTRL_PIN(12, "gpio12" ), |
144 | PINCTRL_PIN(13, "gpio13" ), |
145 | PINCTRL_PIN(14, "gpio14" ), |
146 | PINCTRL_PIN(15, "gpio15" ), |
147 | PINCTRL_PIN(16, "oscio" ), |
148 | }; |
149 | |
150 | static const struct sx150x_device_data sx1501q_device_data = { |
151 | .model = SX150X_123, |
152 | .reg_pullup = 0x02, |
153 | .reg_pulldn = 0x03, |
154 | .reg_dir = 0x01, |
155 | .reg_data = 0x00, |
156 | .reg_irq_mask = 0x05, |
157 | .reg_irq_src = 0x08, |
158 | .reg_sense = 0x07, |
159 | .pri.x123 = { |
160 | .reg_pld_mode = 0x10, |
161 | .reg_pld_table0 = 0x11, |
162 | .reg_pld_table2 = 0x13, |
163 | .reg_advanced = 0xad, |
164 | }, |
165 | .ngpios = 4, |
166 | .pins = sx150x_4_pins, |
167 | .npins = 4, /* oscio not available */ |
168 | }; |
169 | |
170 | static const struct sx150x_device_data sx1502q_device_data = { |
171 | .model = SX150X_123, |
172 | .reg_pullup = 0x02, |
173 | .reg_pulldn = 0x03, |
174 | .reg_dir = 0x01, |
175 | .reg_data = 0x00, |
176 | .reg_irq_mask = 0x05, |
177 | .reg_irq_src = 0x08, |
178 | .reg_sense = 0x06, |
179 | .pri.x123 = { |
180 | .reg_pld_mode = 0x10, |
181 | .reg_pld_table0 = 0x11, |
182 | .reg_pld_table1 = 0x12, |
183 | .reg_pld_table2 = 0x13, |
184 | .reg_pld_table3 = 0x14, |
185 | .reg_pld_table4 = 0x15, |
186 | .reg_advanced = 0xad, |
187 | }, |
188 | .ngpios = 8, |
189 | .pins = sx150x_8_pins, |
190 | .npins = 8, /* oscio not available */ |
191 | }; |
192 | |
193 | static const struct sx150x_device_data sx1503q_device_data = { |
194 | .model = SX150X_123, |
195 | .reg_pullup = 0x04, |
196 | .reg_pulldn = 0x06, |
197 | .reg_dir = 0x02, |
198 | .reg_data = 0x00, |
199 | .reg_irq_mask = 0x08, |
200 | .reg_irq_src = 0x0e, |
201 | .reg_sense = 0x0a, |
202 | .pri.x123 = { |
203 | .reg_pld_mode = 0x20, |
204 | .reg_pld_table0 = 0x22, |
205 | .reg_pld_table1 = 0x24, |
206 | .reg_pld_table2 = 0x26, |
207 | .reg_pld_table3 = 0x28, |
208 | .reg_pld_table4 = 0x2a, |
209 | .reg_advanced = 0xad, |
210 | }, |
211 | .ngpios = 16, |
212 | .pins = sx150x_16_pins, |
213 | .npins = 16, /* oscio not available */ |
214 | }; |
215 | |
216 | static const struct sx150x_device_data sx1504q_device_data = { |
217 | .model = SX150X_456, |
218 | .reg_pullup = 0x02, |
219 | .reg_pulldn = 0x03, |
220 | .reg_dir = 0x01, |
221 | .reg_data = 0x00, |
222 | .reg_irq_mask = 0x05, |
223 | .reg_irq_src = 0x08, |
224 | .reg_sense = 0x07, |
225 | .pri.x456 = { |
226 | .reg_pld_mode = 0x10, |
227 | .reg_pld_table0 = 0x11, |
228 | .reg_pld_table2 = 0x13, |
229 | }, |
230 | .ngpios = 4, |
231 | .pins = sx150x_4_pins, |
232 | .npins = 4, /* oscio not available */ |
233 | }; |
234 | |
235 | static const struct sx150x_device_data sx1505q_device_data = { |
236 | .model = SX150X_456, |
237 | .reg_pullup = 0x02, |
238 | .reg_pulldn = 0x03, |
239 | .reg_dir = 0x01, |
240 | .reg_data = 0x00, |
241 | .reg_irq_mask = 0x05, |
242 | .reg_irq_src = 0x08, |
243 | .reg_sense = 0x06, |
244 | .pri.x456 = { |
245 | .reg_pld_mode = 0x10, |
246 | .reg_pld_table0 = 0x11, |
247 | .reg_pld_table1 = 0x12, |
248 | .reg_pld_table2 = 0x13, |
249 | .reg_pld_table3 = 0x14, |
250 | .reg_pld_table4 = 0x15, |
251 | }, |
252 | .ngpios = 8, |
253 | .pins = sx150x_8_pins, |
254 | .npins = 8, /* oscio not available */ |
255 | }; |
256 | |
257 | static const struct sx150x_device_data sx1506q_device_data = { |
258 | .model = SX150X_456, |
259 | .reg_pullup = 0x04, |
260 | .reg_pulldn = 0x06, |
261 | .reg_dir = 0x02, |
262 | .reg_data = 0x00, |
263 | .reg_irq_mask = 0x08, |
264 | .reg_irq_src = 0x0e, |
265 | .reg_sense = 0x0a, |
266 | .pri.x456 = { |
267 | .reg_pld_mode = 0x20, |
268 | .reg_pld_table0 = 0x22, |
269 | .reg_pld_table1 = 0x24, |
270 | .reg_pld_table2 = 0x26, |
271 | .reg_pld_table3 = 0x28, |
272 | .reg_pld_table4 = 0x2a, |
273 | .reg_advanced = 0xad, |
274 | }, |
275 | .ngpios = 16, |
276 | .pins = sx150x_16_pins, |
277 | .npins = 16, /* oscio not available */ |
278 | }; |
279 | |
280 | static const struct sx150x_device_data sx1507q_device_data = { |
281 | .model = SX150X_789, |
282 | .reg_pullup = 0x03, |
283 | .reg_pulldn = 0x04, |
284 | .reg_dir = 0x07, |
285 | .reg_data = 0x08, |
286 | .reg_irq_mask = 0x09, |
287 | .reg_irq_src = 0x0b, |
288 | .reg_sense = 0x0a, |
289 | .pri.x789 = { |
290 | .reg_drain = 0x05, |
291 | .reg_polarity = 0x06, |
292 | .reg_clock = 0x0d, |
293 | .reg_misc = 0x0e, |
294 | .reg_reset = 0x7d, |
295 | }, |
296 | .ngpios = 4, |
297 | .pins = sx150x_4_pins, |
298 | .npins = ARRAY_SIZE(sx150x_4_pins), |
299 | }; |
300 | |
301 | static const struct sx150x_device_data sx1508q_device_data = { |
302 | .model = SX150X_789, |
303 | .reg_pullup = 0x03, |
304 | .reg_pulldn = 0x04, |
305 | .reg_dir = 0x07, |
306 | .reg_data = 0x08, |
307 | .reg_irq_mask = 0x09, |
308 | .reg_irq_src = 0x0c, |
309 | .reg_sense = 0x0a, |
310 | .pri.x789 = { |
311 | .reg_drain = 0x05, |
312 | .reg_polarity = 0x06, |
313 | .reg_clock = 0x0f, |
314 | .reg_misc = 0x10, |
315 | .reg_reset = 0x7d, |
316 | }, |
317 | .ngpios = 8, |
318 | .pins = sx150x_8_pins, |
319 | .npins = ARRAY_SIZE(sx150x_8_pins), |
320 | }; |
321 | |
322 | static const struct sx150x_device_data sx1509q_device_data = { |
323 | .model = SX150X_789, |
324 | .reg_pullup = 0x06, |
325 | .reg_pulldn = 0x08, |
326 | .reg_dir = 0x0e, |
327 | .reg_data = 0x10, |
328 | .reg_irq_mask = 0x12, |
329 | .reg_irq_src = 0x18, |
330 | .reg_sense = 0x14, |
331 | .pri.x789 = { |
332 | .reg_drain = 0x0a, |
333 | .reg_polarity = 0x0c, |
334 | .reg_clock = 0x1e, |
335 | .reg_misc = 0x1f, |
336 | .reg_reset = 0x7d, |
337 | }, |
338 | .ngpios = 16, |
339 | .pins = sx150x_16_pins, |
340 | .npins = ARRAY_SIZE(sx150x_16_pins), |
341 | }; |
342 | |
343 | static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) |
344 | { |
345 | return 0; |
346 | } |
347 | |
348 | static const char *sx150x_pinctrl_get_group_name(struct pinctrl_dev *pctldev, |
349 | unsigned int group) |
350 | { |
351 | return NULL; |
352 | } |
353 | |
354 | static int sx150x_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, |
355 | unsigned int group, |
356 | const unsigned int **pins, |
357 | unsigned int *num_pins) |
358 | { |
359 | return -ENOTSUPP; |
360 | } |
361 | |
362 | static const struct pinctrl_ops sx150x_pinctrl_ops = { |
363 | .get_groups_count = sx150x_pinctrl_get_groups_count, |
364 | .get_group_name = sx150x_pinctrl_get_group_name, |
365 | .get_group_pins = sx150x_pinctrl_get_group_pins, |
366 | #ifdef CONFIG_OF |
367 | .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, |
368 | .dt_free_map = pinctrl_utils_free_map, |
369 | #endif |
370 | }; |
371 | |
372 | static bool sx150x_pin_is_oscio(struct sx150x_pinctrl *pctl, unsigned int pin) |
373 | { |
374 | if (pin >= pctl->data->npins) |
375 | return false; |
376 | |
377 | /* OSCIO pin is only present in 789 devices */ |
378 | if (pctl->data->model != SX150X_789) |
379 | return false; |
380 | |
381 | return !strcmp(pctl->data->pins[pin].name, "oscio" ); |
382 | } |
383 | |
384 | static int sx150x_gpio_get_direction(struct gpio_chip *chip, |
385 | unsigned int offset) |
386 | { |
387 | struct sx150x_pinctrl *pctl = gpiochip_get_data(gc: chip); |
388 | unsigned int value; |
389 | int ret; |
390 | |
391 | if (sx150x_pin_is_oscio(pctl, pin: offset)) |
392 | return GPIO_LINE_DIRECTION_OUT; |
393 | |
394 | ret = regmap_read(map: pctl->regmap, reg: pctl->data->reg_dir, val: &value); |
395 | if (ret < 0) |
396 | return ret; |
397 | |
398 | if (value & BIT(offset)) |
399 | return GPIO_LINE_DIRECTION_IN; |
400 | |
401 | return GPIO_LINE_DIRECTION_OUT; |
402 | } |
403 | |
404 | static int sx150x_gpio_get(struct gpio_chip *chip, unsigned int offset) |
405 | { |
406 | struct sx150x_pinctrl *pctl = gpiochip_get_data(gc: chip); |
407 | unsigned int value; |
408 | int ret; |
409 | |
410 | if (sx150x_pin_is_oscio(pctl, pin: offset)) |
411 | return -EINVAL; |
412 | |
413 | ret = regmap_read(map: pctl->regmap, reg: pctl->data->reg_data, val: &value); |
414 | if (ret < 0) |
415 | return ret; |
416 | |
417 | return !!(value & BIT(offset)); |
418 | } |
419 | |
420 | static int __sx150x_gpio_set(struct sx150x_pinctrl *pctl, unsigned int offset, |
421 | int value) |
422 | { |
423 | return regmap_write_bits(map: pctl->regmap, reg: pctl->data->reg_data, |
424 | BIT(offset), val: value ? BIT(offset) : 0); |
425 | } |
426 | |
427 | static int sx150x_gpio_oscio_set(struct sx150x_pinctrl *pctl, |
428 | int value) |
429 | { |
430 | return regmap_write(map: pctl->regmap, |
431 | reg: pctl->data->pri.x789.reg_clock, |
432 | val: (value ? 0x1f : 0x10)); |
433 | } |
434 | |
435 | static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset, |
436 | int value) |
437 | { |
438 | struct sx150x_pinctrl *pctl = gpiochip_get_data(gc: chip); |
439 | |
440 | if (sx150x_pin_is_oscio(pctl, pin: offset)) |
441 | sx150x_gpio_oscio_set(pctl, value); |
442 | else |
443 | __sx150x_gpio_set(pctl, offset, value); |
444 | } |
445 | |
446 | static void sx150x_gpio_set_multiple(struct gpio_chip *chip, |
447 | unsigned long *mask, |
448 | unsigned long *bits) |
449 | { |
450 | struct sx150x_pinctrl *pctl = gpiochip_get_data(gc: chip); |
451 | |
452 | regmap_write_bits(map: pctl->regmap, reg: pctl->data->reg_data, mask: *mask, val: *bits); |
453 | } |
454 | |
455 | static int sx150x_gpio_direction_input(struct gpio_chip *chip, |
456 | unsigned int offset) |
457 | { |
458 | struct sx150x_pinctrl *pctl = gpiochip_get_data(gc: chip); |
459 | |
460 | if (sx150x_pin_is_oscio(pctl, pin: offset)) |
461 | return -EINVAL; |
462 | |
463 | return regmap_write_bits(map: pctl->regmap, |
464 | reg: pctl->data->reg_dir, |
465 | BIT(offset), BIT(offset)); |
466 | } |
467 | |
468 | static int sx150x_gpio_direction_output(struct gpio_chip *chip, |
469 | unsigned int offset, int value) |
470 | { |
471 | struct sx150x_pinctrl *pctl = gpiochip_get_data(gc: chip); |
472 | int ret; |
473 | |
474 | if (sx150x_pin_is_oscio(pctl, pin: offset)) |
475 | return sx150x_gpio_oscio_set(pctl, value); |
476 | |
477 | ret = __sx150x_gpio_set(pctl, offset, value); |
478 | if (ret < 0) |
479 | return ret; |
480 | |
481 | return regmap_write_bits(map: pctl->regmap, |
482 | reg: pctl->data->reg_dir, |
483 | BIT(offset), val: 0); |
484 | } |
485 | |
486 | static void sx150x_irq_mask(struct irq_data *d) |
487 | { |
488 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
489 | struct sx150x_pinctrl *pctl = gpiochip_get_data(gc); |
490 | unsigned int n = irqd_to_hwirq(d); |
491 | |
492 | pctl->irq.masked |= BIT(n); |
493 | gpiochip_disable_irq(gc, offset: n); |
494 | } |
495 | |
496 | static void sx150x_irq_unmask(struct irq_data *d) |
497 | { |
498 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
499 | struct sx150x_pinctrl *pctl = gpiochip_get_data(gc); |
500 | unsigned int n = irqd_to_hwirq(d); |
501 | |
502 | gpiochip_enable_irq(gc, offset: n); |
503 | pctl->irq.masked &= ~BIT(n); |
504 | } |
505 | |
506 | static void sx150x_irq_set_sense(struct sx150x_pinctrl *pctl, |
507 | unsigned int line, unsigned int sense) |
508 | { |
509 | /* |
510 | * Every interrupt line is represented by two bits shifted |
511 | * proportionally to the line number |
512 | */ |
513 | const unsigned int n = line * 2; |
514 | const unsigned int mask = ~((SX150X_IRQ_TYPE_EDGE_RISING | |
515 | SX150X_IRQ_TYPE_EDGE_FALLING) << n); |
516 | |
517 | pctl->irq.sense &= mask; |
518 | pctl->irq.sense |= sense << n; |
519 | } |
520 | |
521 | static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type) |
522 | { |
523 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
524 | struct sx150x_pinctrl *pctl = gpiochip_get_data(gc); |
525 | unsigned int n, val = 0; |
526 | |
527 | if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) |
528 | return -EINVAL; |
529 | |
530 | n = irqd_to_hwirq(d); |
531 | |
532 | if (flow_type & IRQ_TYPE_EDGE_RISING) |
533 | val |= SX150X_IRQ_TYPE_EDGE_RISING; |
534 | if (flow_type & IRQ_TYPE_EDGE_FALLING) |
535 | val |= SX150X_IRQ_TYPE_EDGE_FALLING; |
536 | |
537 | sx150x_irq_set_sense(pctl, line: n, sense: val); |
538 | return 0; |
539 | } |
540 | |
541 | static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id) |
542 | { |
543 | struct sx150x_pinctrl *pctl = (struct sx150x_pinctrl *)dev_id; |
544 | unsigned long n, status; |
545 | unsigned int val; |
546 | int err; |
547 | |
548 | err = regmap_read(map: pctl->regmap, reg: pctl->data->reg_irq_src, val: &val); |
549 | if (err < 0) |
550 | return IRQ_NONE; |
551 | |
552 | err = regmap_write(map: pctl->regmap, reg: pctl->data->reg_irq_src, val); |
553 | if (err < 0) |
554 | return IRQ_NONE; |
555 | |
556 | status = val; |
557 | for_each_set_bit(n, &status, pctl->data->ngpios) |
558 | handle_nested_irq(irq: irq_find_mapping(domain: pctl->gpio.irq.domain, hwirq: n)); |
559 | |
560 | return IRQ_HANDLED; |
561 | } |
562 | |
563 | static void sx150x_irq_bus_lock(struct irq_data *d) |
564 | { |
565 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
566 | struct sx150x_pinctrl *pctl = gpiochip_get_data(gc); |
567 | |
568 | mutex_lock(&pctl->lock); |
569 | } |
570 | |
571 | static void sx150x_irq_bus_sync_unlock(struct irq_data *d) |
572 | { |
573 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
574 | struct sx150x_pinctrl *pctl = gpiochip_get_data(gc); |
575 | |
576 | regmap_write(map: pctl->regmap, reg: pctl->data->reg_irq_mask, val: pctl->irq.masked); |
577 | regmap_write(map: pctl->regmap, reg: pctl->data->reg_sense, val: pctl->irq.sense); |
578 | mutex_unlock(lock: &pctl->lock); |
579 | } |
580 | |
581 | |
582 | static void sx150x_irq_print_chip(struct irq_data *d, struct seq_file *p) |
583 | { |
584 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
585 | struct sx150x_pinctrl *pctl = gpiochip_get_data(gc); |
586 | |
587 | seq_printf(m: p, fmt: pctl->client->name); |
588 | } |
589 | |
590 | static const struct irq_chip sx150x_irq_chip = { |
591 | .irq_mask = sx150x_irq_mask, |
592 | .irq_unmask = sx150x_irq_unmask, |
593 | .irq_set_type = sx150x_irq_set_type, |
594 | .irq_bus_lock = sx150x_irq_bus_lock, |
595 | .irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock, |
596 | .irq_print_chip = sx150x_irq_print_chip, |
597 | .flags = IRQCHIP_IMMUTABLE, |
598 | GPIOCHIP_IRQ_RESOURCE_HELPERS, |
599 | }; |
600 | |
601 | static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, |
602 | unsigned long *config) |
603 | { |
604 | struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
605 | unsigned int param = pinconf_to_config_param(config: *config); |
606 | int ret; |
607 | u32 arg; |
608 | unsigned int data; |
609 | |
610 | if (sx150x_pin_is_oscio(pctl, pin)) { |
611 | switch (param) { |
612 | case PIN_CONFIG_DRIVE_PUSH_PULL: |
613 | case PIN_CONFIG_OUTPUT: |
614 | ret = regmap_read(map: pctl->regmap, |
615 | reg: pctl->data->pri.x789.reg_clock, |
616 | val: &data); |
617 | if (ret < 0) |
618 | return ret; |
619 | |
620 | if (param == PIN_CONFIG_DRIVE_PUSH_PULL) |
621 | arg = (data & 0x1f) ? 1 : 0; |
622 | else { |
623 | if ((data & 0x1f) == 0x1f) |
624 | arg = 1; |
625 | else if ((data & 0x1f) == 0x10) |
626 | arg = 0; |
627 | else |
628 | return -EINVAL; |
629 | } |
630 | |
631 | break; |
632 | default: |
633 | return -ENOTSUPP; |
634 | } |
635 | |
636 | goto out; |
637 | } |
638 | |
639 | switch (param) { |
640 | case PIN_CONFIG_BIAS_PULL_DOWN: |
641 | ret = regmap_read(map: pctl->regmap, |
642 | reg: pctl->data->reg_pulldn, |
643 | val: &data); |
644 | data &= BIT(pin); |
645 | |
646 | if (ret < 0) |
647 | return ret; |
648 | |
649 | if (!ret) |
650 | return -EINVAL; |
651 | |
652 | arg = 1; |
653 | break; |
654 | |
655 | case PIN_CONFIG_BIAS_PULL_UP: |
656 | ret = regmap_read(map: pctl->regmap, |
657 | reg: pctl->data->reg_pullup, |
658 | val: &data); |
659 | data &= BIT(pin); |
660 | |
661 | if (ret < 0) |
662 | return ret; |
663 | |
664 | if (!ret) |
665 | return -EINVAL; |
666 | |
667 | arg = 1; |
668 | break; |
669 | |
670 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
671 | if (pctl->data->model != SX150X_789) |
672 | return -ENOTSUPP; |
673 | |
674 | ret = regmap_read(map: pctl->regmap, |
675 | reg: pctl->data->pri.x789.reg_drain, |
676 | val: &data); |
677 | data &= BIT(pin); |
678 | |
679 | if (ret < 0) |
680 | return ret; |
681 | |
682 | if (!data) |
683 | return -EINVAL; |
684 | |
685 | arg = 1; |
686 | break; |
687 | |
688 | case PIN_CONFIG_DRIVE_PUSH_PULL: |
689 | if (pctl->data->model != SX150X_789) |
690 | arg = true; |
691 | else { |
692 | ret = regmap_read(map: pctl->regmap, |
693 | reg: pctl->data->pri.x789.reg_drain, |
694 | val: &data); |
695 | data &= BIT(pin); |
696 | |
697 | if (ret < 0) |
698 | return ret; |
699 | |
700 | if (data) |
701 | return -EINVAL; |
702 | |
703 | arg = 1; |
704 | } |
705 | break; |
706 | |
707 | case PIN_CONFIG_OUTPUT: |
708 | ret = sx150x_gpio_get_direction(chip: &pctl->gpio, offset: pin); |
709 | if (ret < 0) |
710 | return ret; |
711 | |
712 | if (ret == GPIO_LINE_DIRECTION_IN) |
713 | return -EINVAL; |
714 | |
715 | ret = sx150x_gpio_get(chip: &pctl->gpio, offset: pin); |
716 | if (ret < 0) |
717 | return ret; |
718 | |
719 | arg = ret; |
720 | break; |
721 | |
722 | default: |
723 | return -ENOTSUPP; |
724 | } |
725 | |
726 | out: |
727 | *config = pinconf_to_config_packed(param, argument: arg); |
728 | |
729 | return 0; |
730 | } |
731 | |
732 | static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, |
733 | unsigned long *configs, unsigned int num_configs) |
734 | { |
735 | struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
736 | enum pin_config_param param; |
737 | u32 arg; |
738 | int i; |
739 | int ret; |
740 | |
741 | for (i = 0; i < num_configs; i++) { |
742 | param = pinconf_to_config_param(config: configs[i]); |
743 | arg = pinconf_to_config_argument(config: configs[i]); |
744 | |
745 | if (sx150x_pin_is_oscio(pctl, pin)) { |
746 | if (param == PIN_CONFIG_OUTPUT) { |
747 | ret = sx150x_gpio_direction_output(chip: &pctl->gpio, |
748 | offset: pin, value: arg); |
749 | if (ret < 0) |
750 | return ret; |
751 | |
752 | continue; |
753 | } else |
754 | return -ENOTSUPP; |
755 | } |
756 | |
757 | switch (param) { |
758 | case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: |
759 | case PIN_CONFIG_BIAS_DISABLE: |
760 | ret = regmap_write_bits(map: pctl->regmap, |
761 | reg: pctl->data->reg_pulldn, |
762 | BIT(pin), val: 0); |
763 | if (ret < 0) |
764 | return ret; |
765 | |
766 | ret = regmap_write_bits(map: pctl->regmap, |
767 | reg: pctl->data->reg_pullup, |
768 | BIT(pin), val: 0); |
769 | if (ret < 0) |
770 | return ret; |
771 | |
772 | break; |
773 | |
774 | case PIN_CONFIG_BIAS_PULL_UP: |
775 | ret = regmap_write_bits(map: pctl->regmap, |
776 | reg: pctl->data->reg_pullup, |
777 | BIT(pin), BIT(pin)); |
778 | if (ret < 0) |
779 | return ret; |
780 | |
781 | break; |
782 | |
783 | case PIN_CONFIG_BIAS_PULL_DOWN: |
784 | ret = regmap_write_bits(map: pctl->regmap, |
785 | reg: pctl->data->reg_pulldn, |
786 | BIT(pin), BIT(pin)); |
787 | if (ret < 0) |
788 | return ret; |
789 | |
790 | break; |
791 | |
792 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
793 | if (pctl->data->model != SX150X_789 || |
794 | sx150x_pin_is_oscio(pctl, pin)) |
795 | return -ENOTSUPP; |
796 | |
797 | ret = regmap_write_bits(map: pctl->regmap, |
798 | reg: pctl->data->pri.x789.reg_drain, |
799 | BIT(pin), BIT(pin)); |
800 | if (ret < 0) |
801 | return ret; |
802 | |
803 | break; |
804 | |
805 | case PIN_CONFIG_DRIVE_PUSH_PULL: |
806 | if (pctl->data->model != SX150X_789 || |
807 | sx150x_pin_is_oscio(pctl, pin)) |
808 | return 0; |
809 | |
810 | ret = regmap_write_bits(map: pctl->regmap, |
811 | reg: pctl->data->pri.x789.reg_drain, |
812 | BIT(pin), val: 0); |
813 | if (ret < 0) |
814 | return ret; |
815 | |
816 | break; |
817 | |
818 | case PIN_CONFIG_OUTPUT: |
819 | ret = sx150x_gpio_direction_output(chip: &pctl->gpio, |
820 | offset: pin, value: arg); |
821 | if (ret < 0) |
822 | return ret; |
823 | |
824 | break; |
825 | |
826 | default: |
827 | return -ENOTSUPP; |
828 | } |
829 | } /* for each config */ |
830 | |
831 | return 0; |
832 | } |
833 | |
834 | static const struct pinconf_ops sx150x_pinconf_ops = { |
835 | .pin_config_get = sx150x_pinconf_get, |
836 | .pin_config_set = sx150x_pinconf_set, |
837 | .is_generic = true, |
838 | }; |
839 | |
840 | static const struct i2c_device_id sx150x_id[] = { |
841 | {"sx1501q" , (kernel_ulong_t) &sx1501q_device_data }, |
842 | {"sx1502q" , (kernel_ulong_t) &sx1502q_device_data }, |
843 | {"sx1503q" , (kernel_ulong_t) &sx1503q_device_data }, |
844 | {"sx1504q" , (kernel_ulong_t) &sx1504q_device_data }, |
845 | {"sx1505q" , (kernel_ulong_t) &sx1505q_device_data }, |
846 | {"sx1506q" , (kernel_ulong_t) &sx1506q_device_data }, |
847 | {"sx1507q" , (kernel_ulong_t) &sx1507q_device_data }, |
848 | {"sx1508q" , (kernel_ulong_t) &sx1508q_device_data }, |
849 | {"sx1509q" , (kernel_ulong_t) &sx1509q_device_data }, |
850 | {} |
851 | }; |
852 | |
853 | static const struct of_device_id sx150x_of_match[] = { |
854 | { .compatible = "semtech,sx1501q" , .data = &sx1501q_device_data }, |
855 | { .compatible = "semtech,sx1502q" , .data = &sx1502q_device_data }, |
856 | { .compatible = "semtech,sx1503q" , .data = &sx1503q_device_data }, |
857 | { .compatible = "semtech,sx1504q" , .data = &sx1504q_device_data }, |
858 | { .compatible = "semtech,sx1505q" , .data = &sx1505q_device_data }, |
859 | { .compatible = "semtech,sx1506q" , .data = &sx1506q_device_data }, |
860 | { .compatible = "semtech,sx1507q" , .data = &sx1507q_device_data }, |
861 | { .compatible = "semtech,sx1508q" , .data = &sx1508q_device_data }, |
862 | { .compatible = "semtech,sx1509q" , .data = &sx1509q_device_data }, |
863 | {}, |
864 | }; |
865 | |
866 | static int sx150x_reset(struct sx150x_pinctrl *pctl) |
867 | { |
868 | int err; |
869 | |
870 | err = i2c_smbus_write_byte_data(client: pctl->client, |
871 | command: pctl->data->pri.x789.reg_reset, |
872 | value: SX150X_789_RESET_KEY1); |
873 | if (err < 0) |
874 | return err; |
875 | |
876 | err = i2c_smbus_write_byte_data(client: pctl->client, |
877 | command: pctl->data->pri.x789.reg_reset, |
878 | value: SX150X_789_RESET_KEY2); |
879 | return err; |
880 | } |
881 | |
882 | static int sx150x_init_misc(struct sx150x_pinctrl *pctl) |
883 | { |
884 | u8 reg, value; |
885 | |
886 | switch (pctl->data->model) { |
887 | case SX150X_789: |
888 | reg = pctl->data->pri.x789.reg_misc; |
889 | value = SX150X_789_REG_MISC_AUTOCLEAR_OFF; |
890 | break; |
891 | case SX150X_456: |
892 | reg = pctl->data->pri.x456.reg_advanced; |
893 | value = 0x00; |
894 | |
895 | /* |
896 | * Only SX1506 has RegAdvanced, SX1504/5 are expected |
897 | * to initialize this offset to zero |
898 | */ |
899 | if (!reg) |
900 | return 0; |
901 | break; |
902 | case SX150X_123: |
903 | reg = pctl->data->pri.x123.reg_advanced; |
904 | value = 0x00; |
905 | break; |
906 | default: |
907 | WARN(1, "Unknown chip model %d\n" , pctl->data->model); |
908 | return -EINVAL; |
909 | } |
910 | |
911 | return regmap_write(map: pctl->regmap, reg, val: value); |
912 | } |
913 | |
914 | static int sx150x_init_hw(struct sx150x_pinctrl *pctl) |
915 | { |
916 | const u8 reg[] = { |
917 | [SX150X_789] = pctl->data->pri.x789.reg_polarity, |
918 | [SX150X_456] = pctl->data->pri.x456.reg_pld_mode, |
919 | [SX150X_123] = pctl->data->pri.x123.reg_pld_mode, |
920 | }; |
921 | int err; |
922 | |
923 | if (pctl->data->model == SX150X_789 && |
924 | of_property_read_bool(np: pctl->dev->of_node, propname: "semtech,probe-reset" )) { |
925 | err = sx150x_reset(pctl); |
926 | if (err < 0) |
927 | return err; |
928 | } |
929 | |
930 | err = sx150x_init_misc(pctl); |
931 | if (err < 0) |
932 | return err; |
933 | |
934 | /* Set all pins to work in normal mode */ |
935 | return regmap_write(map: pctl->regmap, reg: reg[pctl->data->model], val: 0); |
936 | } |
937 | |
938 | static int sx150x_regmap_reg_width(struct sx150x_pinctrl *pctl, |
939 | unsigned int reg) |
940 | { |
941 | const struct sx150x_device_data *data = pctl->data; |
942 | |
943 | if (reg == data->reg_sense) { |
944 | /* |
945 | * RegSense packs two bits of configuration per GPIO, |
946 | * so we'd need to read twice as many bits as there |
947 | * are GPIO in our chip |
948 | */ |
949 | return 2 * data->ngpios; |
950 | } else if ((data->model == SX150X_789 && |
951 | (reg == data->pri.x789.reg_misc || |
952 | reg == data->pri.x789.reg_clock || |
953 | reg == data->pri.x789.reg_reset)) |
954 | || |
955 | (data->model == SX150X_123 && |
956 | reg == data->pri.x123.reg_advanced) |
957 | || |
958 | (data->model == SX150X_456 && |
959 | data->pri.x456.reg_advanced && |
960 | reg == data->pri.x456.reg_advanced)) { |
961 | return 8; |
962 | } else { |
963 | return data->ngpios; |
964 | } |
965 | } |
966 | |
967 | static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl, |
968 | unsigned int reg, unsigned int val) |
969 | { |
970 | unsigned int a, b; |
971 | const struct sx150x_device_data *data = pctl->data; |
972 | |
973 | /* |
974 | * Whereas SX1509 presents RegSense in a simple layout as such: |
975 | * reg [ f f e e d d c c ] |
976 | * reg + 1 [ b b a a 9 9 8 8 ] |
977 | * reg + 2 [ 7 7 6 6 5 5 4 4 ] |
978 | * reg + 3 [ 3 3 2 2 1 1 0 0 ] |
979 | * |
980 | * SX1503 and SX1506 deviate from that data layout, instead storing |
981 | * their contents as follows: |
982 | * |
983 | * reg [ f f e e d d c c ] |
984 | * reg + 1 [ 7 7 6 6 5 5 4 4 ] |
985 | * reg + 2 [ b b a a 9 9 8 8 ] |
986 | * reg + 3 [ 3 3 2 2 1 1 0 0 ] |
987 | * |
988 | * so, taking that into account, we swap two |
989 | * inner bytes of a 4-byte result |
990 | */ |
991 | |
992 | if (reg == data->reg_sense && |
993 | data->ngpios == 16 && |
994 | (data->model == SX150X_123 || |
995 | data->model == SX150X_456)) { |
996 | a = val & 0x00ff0000; |
997 | b = val & 0x0000ff00; |
998 | |
999 | val &= 0xff0000ff; |
1000 | val |= b << 8; |
1001 | val |= a >> 8; |
1002 | } |
1003 | |
1004 | return val; |
1005 | } |
1006 | |
1007 | /* |
1008 | * In order to mask the differences between 16 and 8 bit expander |
1009 | * devices we set up a sligthly ficticious regmap that pretends to be |
1010 | * a set of 32-bit (to accommodate RegSenseLow/RegSenseHigh |
1011 | * pair/quartet) registers and transparently reconstructs those |
1012 | * registers via multiple I2C/SMBus reads |
1013 | * |
1014 | * This way the rest of the driver code, interfacing with the chip via |
1015 | * regmap API, can work assuming that each GPIO pin is represented by |
1016 | * a group of bits at an offset proportional to GPIO number within a |
1017 | * given register. |
1018 | */ |
1019 | static int sx150x_regmap_reg_read(void *context, unsigned int reg, |
1020 | unsigned int *result) |
1021 | { |
1022 | int ret, n; |
1023 | struct sx150x_pinctrl *pctl = context; |
1024 | struct i2c_client *i2c = pctl->client; |
1025 | const int width = sx150x_regmap_reg_width(pctl, reg); |
1026 | unsigned int idx, val; |
1027 | |
1028 | /* |
1029 | * There are four potential cases covered by this function: |
1030 | * |
1031 | * 1) 8-pin chip, single configuration bit register |
1032 | * |
1033 | * This is trivial the code below just needs to read: |
1034 | * reg [ 7 6 5 4 3 2 1 0 ] |
1035 | * |
1036 | * 2) 8-pin chip, double configuration bit register (RegSense) |
1037 | * |
1038 | * The read will be done as follows: |
1039 | * reg [ 7 7 6 6 5 5 4 4 ] |
1040 | * reg + 1 [ 3 3 2 2 1 1 0 0 ] |
1041 | * |
1042 | * 3) 16-pin chip, single configuration bit register |
1043 | * |
1044 | * The read will be done as follows: |
1045 | * reg [ f e d c b a 9 8 ] |
1046 | * reg + 1 [ 7 6 5 4 3 2 1 0 ] |
1047 | * |
1048 | * 4) 16-pin chip, double configuration bit register (RegSense) |
1049 | * |
1050 | * The read will be done as follows: |
1051 | * reg [ f f e e d d c c ] |
1052 | * reg + 1 [ b b a a 9 9 8 8 ] |
1053 | * reg + 2 [ 7 7 6 6 5 5 4 4 ] |
1054 | * reg + 3 [ 3 3 2 2 1 1 0 0 ] |
1055 | */ |
1056 | |
1057 | for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx++) { |
1058 | val <<= 8; |
1059 | |
1060 | ret = i2c_smbus_read_byte_data(client: i2c, command: idx); |
1061 | if (ret < 0) |
1062 | return ret; |
1063 | |
1064 | val |= ret; |
1065 | } |
1066 | |
1067 | *result = sx150x_maybe_swizzle(pctl, reg, val); |
1068 | |
1069 | return 0; |
1070 | } |
1071 | |
1072 | static int sx150x_regmap_reg_write(void *context, unsigned int reg, |
1073 | unsigned int val) |
1074 | { |
1075 | int ret, n; |
1076 | struct sx150x_pinctrl *pctl = context; |
1077 | struct i2c_client *i2c = pctl->client; |
1078 | const int width = sx150x_regmap_reg_width(pctl, reg); |
1079 | |
1080 | val = sx150x_maybe_swizzle(pctl, reg, val); |
1081 | |
1082 | n = (width - 1) & ~7; |
1083 | do { |
1084 | const u8 byte = (val >> n) & 0xff; |
1085 | |
1086 | ret = i2c_smbus_write_byte_data(client: i2c, command: reg, value: byte); |
1087 | if (ret < 0) |
1088 | return ret; |
1089 | |
1090 | reg++; |
1091 | n -= 8; |
1092 | } while (n >= 0); |
1093 | |
1094 | return 0; |
1095 | } |
1096 | |
1097 | static bool sx150x_reg_volatile(struct device *dev, unsigned int reg) |
1098 | { |
1099 | struct sx150x_pinctrl *pctl = i2c_get_clientdata(to_i2c_client(dev)); |
1100 | |
1101 | return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data; |
1102 | } |
1103 | |
1104 | static const struct regmap_config sx150x_regmap_config = { |
1105 | .reg_bits = 8, |
1106 | .val_bits = 32, |
1107 | |
1108 | .cache_type = REGCACHE_RBTREE, |
1109 | |
1110 | .reg_read = sx150x_regmap_reg_read, |
1111 | .reg_write = sx150x_regmap_reg_write, |
1112 | |
1113 | .max_register = SX150X_MAX_REGISTER, |
1114 | .volatile_reg = sx150x_reg_volatile, |
1115 | }; |
1116 | |
1117 | static int sx150x_probe(struct i2c_client *client) |
1118 | { |
1119 | static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA | |
1120 | I2C_FUNC_SMBUS_WRITE_WORD_DATA; |
1121 | struct device *dev = &client->dev; |
1122 | struct sx150x_pinctrl *pctl; |
1123 | int ret; |
1124 | |
1125 | if (!i2c_check_functionality(adap: client->adapter, func: i2c_funcs)) |
1126 | return -ENOSYS; |
1127 | |
1128 | pctl = devm_kzalloc(dev, size: sizeof(*pctl), GFP_KERNEL); |
1129 | if (!pctl) |
1130 | return -ENOMEM; |
1131 | |
1132 | i2c_set_clientdata(client, data: pctl); |
1133 | |
1134 | pctl->dev = dev; |
1135 | pctl->client = client; |
1136 | |
1137 | pctl->data = i2c_get_match_data(client); |
1138 | if (!pctl->data) |
1139 | return -EINVAL; |
1140 | |
1141 | pctl->regmap = devm_regmap_init(dev, NULL, pctl, |
1142 | &sx150x_regmap_config); |
1143 | if (IS_ERR(ptr: pctl->regmap)) { |
1144 | ret = PTR_ERR(ptr: pctl->regmap); |
1145 | dev_err(dev, "Failed to allocate register map: %d\n" , |
1146 | ret); |
1147 | return ret; |
1148 | } |
1149 | |
1150 | mutex_init(&pctl->lock); |
1151 | |
1152 | ret = sx150x_init_hw(pctl); |
1153 | if (ret) |
1154 | return ret; |
1155 | |
1156 | /* Pinctrl_desc */ |
1157 | pctl->pinctrl_desc.name = "sx150x-pinctrl" ; |
1158 | pctl->pinctrl_desc.pctlops = &sx150x_pinctrl_ops; |
1159 | pctl->pinctrl_desc.confops = &sx150x_pinconf_ops; |
1160 | pctl->pinctrl_desc.pins = pctl->data->pins; |
1161 | pctl->pinctrl_desc.npins = pctl->data->npins; |
1162 | pctl->pinctrl_desc.owner = THIS_MODULE; |
1163 | |
1164 | ret = devm_pinctrl_register_and_init(dev, pctldesc: &pctl->pinctrl_desc, |
1165 | driver_data: pctl, pctldev: &pctl->pctldev); |
1166 | if (ret) { |
1167 | dev_err(dev, "Failed to register pinctrl device\n" ); |
1168 | return ret; |
1169 | } |
1170 | |
1171 | /* Register GPIO controller */ |
1172 | pctl->gpio.base = -1; |
1173 | pctl->gpio.ngpio = pctl->data->npins; |
1174 | pctl->gpio.get_direction = sx150x_gpio_get_direction; |
1175 | pctl->gpio.direction_input = sx150x_gpio_direction_input; |
1176 | pctl->gpio.direction_output = sx150x_gpio_direction_output; |
1177 | pctl->gpio.get = sx150x_gpio_get; |
1178 | pctl->gpio.set = sx150x_gpio_set; |
1179 | pctl->gpio.set_config = gpiochip_generic_config; |
1180 | pctl->gpio.parent = dev; |
1181 | pctl->gpio.can_sleep = true; |
1182 | pctl->gpio.label = devm_kstrdup(dev, s: client->name, GFP_KERNEL); |
1183 | if (!pctl->gpio.label) |
1184 | return -ENOMEM; |
1185 | |
1186 | /* |
1187 | * Setting multiple pins is not safe when all pins are not |
1188 | * handled by the same regmap register. The oscio pin (present |
1189 | * on the SX150X_789 chips) lives in its own register, so |
1190 | * would require locking that is not in place at this time. |
1191 | */ |
1192 | if (pctl->data->model != SX150X_789) |
1193 | pctl->gpio.set_multiple = sx150x_gpio_set_multiple; |
1194 | |
1195 | /* Add Interrupt support if an irq is specified */ |
1196 | if (client->irq > 0) { |
1197 | struct gpio_irq_chip *girq; |
1198 | |
1199 | pctl->irq.masked = ~0; |
1200 | pctl->irq.sense = 0; |
1201 | /* |
1202 | * Because sx150x_irq_threaded_fn invokes all of the |
1203 | * nested interrupt handlers via handle_nested_irq, |
1204 | * any "handler" assigned to struct gpio_irq_chip |
1205 | * below is going to be ignored, so the choice of the |
1206 | * function does not matter that much. |
1207 | * |
1208 | * We set it to handle_bad_irq to avoid confusion, |
1209 | * plus it will be instantly noticeable if it is ever |
1210 | * called (should not happen) |
1211 | */ |
1212 | girq = &pctl->gpio.irq; |
1213 | gpio_irq_chip_set_chip(girq, chip: &sx150x_irq_chip); |
1214 | /* This will let us handle the parent IRQ in the driver */ |
1215 | girq->parent_handler = NULL; |
1216 | girq->num_parents = 0; |
1217 | girq->parents = NULL; |
1218 | girq->default_type = IRQ_TYPE_NONE; |
1219 | girq->handler = handle_bad_irq; |
1220 | girq->threaded = true; |
1221 | |
1222 | ret = devm_request_threaded_irq(dev, irq: client->irq, NULL, |
1223 | thread_fn: sx150x_irq_thread_fn, |
1224 | IRQF_ONESHOT | IRQF_SHARED | |
1225 | IRQF_TRIGGER_FALLING, |
1226 | devname: client->name, dev_id: pctl); |
1227 | if (ret < 0) |
1228 | return ret; |
1229 | } |
1230 | |
1231 | ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl); |
1232 | if (ret) |
1233 | return ret; |
1234 | |
1235 | /* |
1236 | * Pin control functions need to be enabled AFTER registering the |
1237 | * GPIO chip because sx150x_pinconf_set() calls |
1238 | * sx150x_gpio_direction_output(). |
1239 | */ |
1240 | ret = pinctrl_enable(pctldev: pctl->pctldev); |
1241 | if (ret) { |
1242 | dev_err(dev, "Failed to enable pinctrl device\n" ); |
1243 | return ret; |
1244 | } |
1245 | |
1246 | ret = gpiochip_add_pin_range(gc: &pctl->gpio, pinctl_name: dev_name(dev), |
1247 | gpio_offset: 0, pin_offset: 0, npins: pctl->data->npins); |
1248 | if (ret) |
1249 | return ret; |
1250 | |
1251 | return 0; |
1252 | } |
1253 | |
1254 | static struct i2c_driver sx150x_driver = { |
1255 | .driver = { |
1256 | .name = "sx150x-pinctrl" , |
1257 | .of_match_table = sx150x_of_match, |
1258 | }, |
1259 | .probe = sx150x_probe, |
1260 | .id_table = sx150x_id, |
1261 | }; |
1262 | |
1263 | static int __init sx150x_init(void) |
1264 | { |
1265 | return i2c_add_driver(&sx150x_driver); |
1266 | } |
1267 | subsys_initcall(sx150x_init); |
1268 | |