1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. |
4 | */ |
5 | |
6 | #include <linux/module.h> |
7 | #include <linux/of.h> |
8 | #include <linux/platform_device.h> |
9 | |
10 | #include "pinctrl-msm.h" |
11 | |
12 | #define REG_SIZE 0x1000 |
13 | |
14 | #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ |
15 | { \ |
16 | .grp = PINCTRL_PINGROUP("gpio" #id, \ |
17 | gpio##id##_pins, \ |
18 | ARRAY_SIZE(gpio##id##_pins)), \ |
19 | .funcs = (int[]){ \ |
20 | msm_mux_gpio, /* gpio mode */ \ |
21 | msm_mux_##f1, \ |
22 | msm_mux_##f2, \ |
23 | msm_mux_##f3, \ |
24 | msm_mux_##f4, \ |
25 | msm_mux_##f5, \ |
26 | msm_mux_##f6, \ |
27 | msm_mux_##f7, \ |
28 | msm_mux_##f8, \ |
29 | msm_mux_##f9 \ |
30 | }, \ |
31 | .nfuncs = 10, \ |
32 | .ctl_reg = REG_SIZE * id, \ |
33 | .io_reg = 0x4 + REG_SIZE * id, \ |
34 | .intr_cfg_reg = 0x8 + REG_SIZE * id, \ |
35 | .intr_status_reg = 0xc + REG_SIZE * id, \ |
36 | .intr_target_reg = 0x8 + REG_SIZE * id, \ |
37 | .mux_bit = 2, \ |
38 | .pull_bit = 0, \ |
39 | .drv_bit = 6, \ |
40 | .oe_bit = 9, \ |
41 | .in_bit = 0, \ |
42 | .out_bit = 1, \ |
43 | .intr_enable_bit = 0, \ |
44 | .intr_status_bit = 0, \ |
45 | .intr_target_bit = 5, \ |
46 | .intr_target_kpss_val = 3, \ |
47 | .intr_raw_status_bit = 4, \ |
48 | .intr_polarity_bit = 1, \ |
49 | .intr_detection_bit = 2, \ |
50 | .intr_detection_width = 2, \ |
51 | } |
52 | |
53 | #define SDC_PINGROUP(pg_name, ctl, pull, drv) \ |
54 | { \ |
55 | .grp = PINCTRL_PINGROUP(#pg_name, \ |
56 | pg_name##_pins, \ |
57 | ARRAY_SIZE(pg_name##_pins)), \ |
58 | .ctl_reg = ctl, \ |
59 | .io_reg = 0, \ |
60 | .intr_cfg_reg = 0, \ |
61 | .intr_status_reg = 0, \ |
62 | .intr_target_reg = 0, \ |
63 | .mux_bit = -1, \ |
64 | .pull_bit = pull, \ |
65 | .drv_bit = drv, \ |
66 | .oe_bit = -1, \ |
67 | .in_bit = -1, \ |
68 | .out_bit = -1, \ |
69 | .intr_enable_bit = -1, \ |
70 | .intr_status_bit = -1, \ |
71 | .intr_target_bit = -1, \ |
72 | .intr_raw_status_bit = -1, \ |
73 | .intr_polarity_bit = -1, \ |
74 | .intr_detection_bit = -1, \ |
75 | .intr_detection_width = -1, \ |
76 | } |
77 | |
78 | static const struct pinctrl_pin_desc sdx55_pins[] = { |
79 | PINCTRL_PIN(0, "GPIO_0" ), |
80 | PINCTRL_PIN(1, "GPIO_1" ), |
81 | PINCTRL_PIN(2, "GPIO_2" ), |
82 | PINCTRL_PIN(3, "GPIO_3" ), |
83 | PINCTRL_PIN(4, "GPIO_4" ), |
84 | PINCTRL_PIN(5, "GPIO_5" ), |
85 | PINCTRL_PIN(6, "GPIO_6" ), |
86 | PINCTRL_PIN(7, "GPIO_7" ), |
87 | PINCTRL_PIN(8, "GPIO_8" ), |
88 | PINCTRL_PIN(9, "GPIO_9" ), |
89 | PINCTRL_PIN(10, "GPIO_10" ), |
90 | PINCTRL_PIN(11, "GPIO_11" ), |
91 | PINCTRL_PIN(12, "GPIO_12" ), |
92 | PINCTRL_PIN(13, "GPIO_13" ), |
93 | PINCTRL_PIN(14, "GPIO_14" ), |
94 | PINCTRL_PIN(15, "GPIO_15" ), |
95 | PINCTRL_PIN(16, "GPIO_16" ), |
96 | PINCTRL_PIN(17, "GPIO_17" ), |
97 | PINCTRL_PIN(18, "GPIO_18" ), |
98 | PINCTRL_PIN(19, "GPIO_19" ), |
99 | PINCTRL_PIN(20, "GPIO_20" ), |
100 | PINCTRL_PIN(21, "GPIO_21" ), |
101 | PINCTRL_PIN(22, "GPIO_22" ), |
102 | PINCTRL_PIN(23, "GPIO_23" ), |
103 | PINCTRL_PIN(24, "GPIO_24" ), |
104 | PINCTRL_PIN(25, "GPIO_25" ), |
105 | PINCTRL_PIN(26, "GPIO_26" ), |
106 | PINCTRL_PIN(27, "GPIO_27" ), |
107 | PINCTRL_PIN(28, "GPIO_28" ), |
108 | PINCTRL_PIN(29, "GPIO_29" ), |
109 | PINCTRL_PIN(30, "GPIO_30" ), |
110 | PINCTRL_PIN(31, "GPIO_31" ), |
111 | PINCTRL_PIN(32, "GPIO_32" ), |
112 | PINCTRL_PIN(33, "GPIO_33" ), |
113 | PINCTRL_PIN(34, "GPIO_34" ), |
114 | PINCTRL_PIN(35, "GPIO_35" ), |
115 | PINCTRL_PIN(36, "GPIO_36" ), |
116 | PINCTRL_PIN(37, "GPIO_37" ), |
117 | PINCTRL_PIN(38, "GPIO_38" ), |
118 | PINCTRL_PIN(39, "GPIO_39" ), |
119 | PINCTRL_PIN(40, "GPIO_40" ), |
120 | PINCTRL_PIN(41, "GPIO_41" ), |
121 | PINCTRL_PIN(42, "GPIO_42" ), |
122 | PINCTRL_PIN(43, "GPIO_43" ), |
123 | PINCTRL_PIN(44, "GPIO_44" ), |
124 | PINCTRL_PIN(45, "GPIO_45" ), |
125 | PINCTRL_PIN(46, "GPIO_46" ), |
126 | PINCTRL_PIN(47, "GPIO_47" ), |
127 | PINCTRL_PIN(48, "GPIO_48" ), |
128 | PINCTRL_PIN(49, "GPIO_49" ), |
129 | PINCTRL_PIN(50, "GPIO_50" ), |
130 | PINCTRL_PIN(51, "GPIO_51" ), |
131 | PINCTRL_PIN(52, "GPIO_52" ), |
132 | PINCTRL_PIN(53, "GPIO_53" ), |
133 | PINCTRL_PIN(54, "GPIO_54" ), |
134 | PINCTRL_PIN(55, "GPIO_55" ), |
135 | PINCTRL_PIN(56, "GPIO_56" ), |
136 | PINCTRL_PIN(57, "GPIO_57" ), |
137 | PINCTRL_PIN(58, "GPIO_58" ), |
138 | PINCTRL_PIN(59, "GPIO_59" ), |
139 | PINCTRL_PIN(60, "GPIO_60" ), |
140 | PINCTRL_PIN(61, "GPIO_61" ), |
141 | PINCTRL_PIN(62, "GPIO_62" ), |
142 | PINCTRL_PIN(63, "GPIO_63" ), |
143 | PINCTRL_PIN(64, "GPIO_64" ), |
144 | PINCTRL_PIN(65, "GPIO_65" ), |
145 | PINCTRL_PIN(66, "GPIO_66" ), |
146 | PINCTRL_PIN(67, "GPIO_67" ), |
147 | PINCTRL_PIN(68, "GPIO_68" ), |
148 | PINCTRL_PIN(69, "GPIO_69" ), |
149 | PINCTRL_PIN(70, "GPIO_70" ), |
150 | PINCTRL_PIN(71, "GPIO_71" ), |
151 | PINCTRL_PIN(72, "GPIO_72" ), |
152 | PINCTRL_PIN(73, "GPIO_73" ), |
153 | PINCTRL_PIN(74, "GPIO_74" ), |
154 | PINCTRL_PIN(75, "GPIO_75" ), |
155 | PINCTRL_PIN(76, "GPIO_76" ), |
156 | PINCTRL_PIN(77, "GPIO_77" ), |
157 | PINCTRL_PIN(78, "GPIO_78" ), |
158 | PINCTRL_PIN(79, "GPIO_79" ), |
159 | PINCTRL_PIN(80, "GPIO_80" ), |
160 | PINCTRL_PIN(81, "GPIO_81" ), |
161 | PINCTRL_PIN(82, "GPIO_82" ), |
162 | PINCTRL_PIN(83, "GPIO_83" ), |
163 | PINCTRL_PIN(84, "GPIO_84" ), |
164 | PINCTRL_PIN(85, "GPIO_85" ), |
165 | PINCTRL_PIN(86, "GPIO_86" ), |
166 | PINCTRL_PIN(87, "GPIO_87" ), |
167 | PINCTRL_PIN(88, "GPIO_88" ), |
168 | PINCTRL_PIN(89, "GPIO_89" ), |
169 | PINCTRL_PIN(90, "GPIO_90" ), |
170 | PINCTRL_PIN(91, "GPIO_91" ), |
171 | PINCTRL_PIN(92, "GPIO_92" ), |
172 | PINCTRL_PIN(93, "GPIO_93" ), |
173 | PINCTRL_PIN(94, "GPIO_94" ), |
174 | PINCTRL_PIN(95, "GPIO_95" ), |
175 | PINCTRL_PIN(96, "GPIO_96" ), |
176 | PINCTRL_PIN(97, "GPIO_97" ), |
177 | PINCTRL_PIN(98, "GPIO_98" ), |
178 | PINCTRL_PIN(99, "GPIO_99" ), |
179 | PINCTRL_PIN(100, "GPIO_100" ), |
180 | PINCTRL_PIN(101, "GPIO_101" ), |
181 | PINCTRL_PIN(102, "GPIO_102" ), |
182 | PINCTRL_PIN(103, "GPIO_103" ), |
183 | PINCTRL_PIN(104, "GPIO_104" ), |
184 | PINCTRL_PIN(105, "GPIO_105" ), |
185 | PINCTRL_PIN(106, "GPIO_106" ), |
186 | PINCTRL_PIN(107, "GPIO_107" ), |
187 | PINCTRL_PIN(108, "SDC1_RCLK" ), |
188 | PINCTRL_PIN(109, "SDC1_CLK" ), |
189 | PINCTRL_PIN(110, "SDC1_CMD" ), |
190 | PINCTRL_PIN(111, "SDC1_DATA" ), |
191 | }; |
192 | |
193 | #define DECLARE_MSM_GPIO_PINS(pin) \ |
194 | static const unsigned int gpio##pin##_pins[] = { pin } |
195 | DECLARE_MSM_GPIO_PINS(0); |
196 | DECLARE_MSM_GPIO_PINS(1); |
197 | DECLARE_MSM_GPIO_PINS(2); |
198 | DECLARE_MSM_GPIO_PINS(3); |
199 | DECLARE_MSM_GPIO_PINS(4); |
200 | DECLARE_MSM_GPIO_PINS(5); |
201 | DECLARE_MSM_GPIO_PINS(6); |
202 | DECLARE_MSM_GPIO_PINS(7); |
203 | DECLARE_MSM_GPIO_PINS(8); |
204 | DECLARE_MSM_GPIO_PINS(9); |
205 | DECLARE_MSM_GPIO_PINS(10); |
206 | DECLARE_MSM_GPIO_PINS(11); |
207 | DECLARE_MSM_GPIO_PINS(12); |
208 | DECLARE_MSM_GPIO_PINS(13); |
209 | DECLARE_MSM_GPIO_PINS(14); |
210 | DECLARE_MSM_GPIO_PINS(15); |
211 | DECLARE_MSM_GPIO_PINS(16); |
212 | DECLARE_MSM_GPIO_PINS(17); |
213 | DECLARE_MSM_GPIO_PINS(18); |
214 | DECLARE_MSM_GPIO_PINS(19); |
215 | DECLARE_MSM_GPIO_PINS(20); |
216 | DECLARE_MSM_GPIO_PINS(21); |
217 | DECLARE_MSM_GPIO_PINS(22); |
218 | DECLARE_MSM_GPIO_PINS(23); |
219 | DECLARE_MSM_GPIO_PINS(24); |
220 | DECLARE_MSM_GPIO_PINS(25); |
221 | DECLARE_MSM_GPIO_PINS(26); |
222 | DECLARE_MSM_GPIO_PINS(27); |
223 | DECLARE_MSM_GPIO_PINS(28); |
224 | DECLARE_MSM_GPIO_PINS(29); |
225 | DECLARE_MSM_GPIO_PINS(30); |
226 | DECLARE_MSM_GPIO_PINS(31); |
227 | DECLARE_MSM_GPIO_PINS(32); |
228 | DECLARE_MSM_GPIO_PINS(33); |
229 | DECLARE_MSM_GPIO_PINS(34); |
230 | DECLARE_MSM_GPIO_PINS(35); |
231 | DECLARE_MSM_GPIO_PINS(36); |
232 | DECLARE_MSM_GPIO_PINS(37); |
233 | DECLARE_MSM_GPIO_PINS(38); |
234 | DECLARE_MSM_GPIO_PINS(39); |
235 | DECLARE_MSM_GPIO_PINS(40); |
236 | DECLARE_MSM_GPIO_PINS(41); |
237 | DECLARE_MSM_GPIO_PINS(42); |
238 | DECLARE_MSM_GPIO_PINS(43); |
239 | DECLARE_MSM_GPIO_PINS(44); |
240 | DECLARE_MSM_GPIO_PINS(45); |
241 | DECLARE_MSM_GPIO_PINS(46); |
242 | DECLARE_MSM_GPIO_PINS(47); |
243 | DECLARE_MSM_GPIO_PINS(48); |
244 | DECLARE_MSM_GPIO_PINS(49); |
245 | DECLARE_MSM_GPIO_PINS(50); |
246 | DECLARE_MSM_GPIO_PINS(51); |
247 | DECLARE_MSM_GPIO_PINS(52); |
248 | DECLARE_MSM_GPIO_PINS(53); |
249 | DECLARE_MSM_GPIO_PINS(54); |
250 | DECLARE_MSM_GPIO_PINS(55); |
251 | DECLARE_MSM_GPIO_PINS(56); |
252 | DECLARE_MSM_GPIO_PINS(57); |
253 | DECLARE_MSM_GPIO_PINS(58); |
254 | DECLARE_MSM_GPIO_PINS(59); |
255 | DECLARE_MSM_GPIO_PINS(60); |
256 | DECLARE_MSM_GPIO_PINS(61); |
257 | DECLARE_MSM_GPIO_PINS(62); |
258 | DECLARE_MSM_GPIO_PINS(63); |
259 | DECLARE_MSM_GPIO_PINS(64); |
260 | DECLARE_MSM_GPIO_PINS(65); |
261 | DECLARE_MSM_GPIO_PINS(66); |
262 | DECLARE_MSM_GPIO_PINS(67); |
263 | DECLARE_MSM_GPIO_PINS(68); |
264 | DECLARE_MSM_GPIO_PINS(69); |
265 | DECLARE_MSM_GPIO_PINS(70); |
266 | DECLARE_MSM_GPIO_PINS(71); |
267 | DECLARE_MSM_GPIO_PINS(72); |
268 | DECLARE_MSM_GPIO_PINS(73); |
269 | DECLARE_MSM_GPIO_PINS(74); |
270 | DECLARE_MSM_GPIO_PINS(75); |
271 | DECLARE_MSM_GPIO_PINS(76); |
272 | DECLARE_MSM_GPIO_PINS(77); |
273 | DECLARE_MSM_GPIO_PINS(78); |
274 | DECLARE_MSM_GPIO_PINS(79); |
275 | DECLARE_MSM_GPIO_PINS(80); |
276 | DECLARE_MSM_GPIO_PINS(81); |
277 | DECLARE_MSM_GPIO_PINS(82); |
278 | DECLARE_MSM_GPIO_PINS(83); |
279 | DECLARE_MSM_GPIO_PINS(84); |
280 | DECLARE_MSM_GPIO_PINS(85); |
281 | DECLARE_MSM_GPIO_PINS(86); |
282 | DECLARE_MSM_GPIO_PINS(87); |
283 | DECLARE_MSM_GPIO_PINS(88); |
284 | DECLARE_MSM_GPIO_PINS(89); |
285 | DECLARE_MSM_GPIO_PINS(90); |
286 | DECLARE_MSM_GPIO_PINS(91); |
287 | DECLARE_MSM_GPIO_PINS(92); |
288 | DECLARE_MSM_GPIO_PINS(93); |
289 | DECLARE_MSM_GPIO_PINS(94); |
290 | DECLARE_MSM_GPIO_PINS(95); |
291 | DECLARE_MSM_GPIO_PINS(96); |
292 | DECLARE_MSM_GPIO_PINS(97); |
293 | DECLARE_MSM_GPIO_PINS(98); |
294 | DECLARE_MSM_GPIO_PINS(99); |
295 | DECLARE_MSM_GPIO_PINS(100); |
296 | DECLARE_MSM_GPIO_PINS(101); |
297 | DECLARE_MSM_GPIO_PINS(102); |
298 | DECLARE_MSM_GPIO_PINS(103); |
299 | DECLARE_MSM_GPIO_PINS(104); |
300 | DECLARE_MSM_GPIO_PINS(105); |
301 | DECLARE_MSM_GPIO_PINS(106); |
302 | DECLARE_MSM_GPIO_PINS(107); |
303 | |
304 | static const unsigned int sdc1_rclk_pins[] = { 108 }; |
305 | static const unsigned int sdc1_clk_pins[] = { 109 }; |
306 | static const unsigned int sdc1_cmd_pins[] = { 110 }; |
307 | static const unsigned int sdc1_data_pins[] = { 111 }; |
308 | |
309 | enum sdx55_functions { |
310 | msm_mux_adsp_ext, |
311 | msm_mux_atest, |
312 | msm_mux_audio_ref, |
313 | msm_mux_bimc_dte0, |
314 | msm_mux_bimc_dte1, |
315 | msm_mux_blsp_i2c1, |
316 | msm_mux_blsp_i2c2, |
317 | msm_mux_blsp_i2c3, |
318 | msm_mux_blsp_i2c4, |
319 | msm_mux_blsp_spi1, |
320 | msm_mux_blsp_spi2, |
321 | msm_mux_blsp_spi3, |
322 | msm_mux_blsp_spi4, |
323 | msm_mux_blsp_uart1, |
324 | msm_mux_blsp_uart2, |
325 | msm_mux_blsp_uart3, |
326 | msm_mux_blsp_uart4, |
327 | msm_mux_char_exec, |
328 | msm_mux_coex_uart, |
329 | msm_mux_coex_uart2, |
330 | msm_mux_cri_trng, |
331 | msm_mux_cri_trng0, |
332 | msm_mux_cri_trng1, |
333 | msm_mux_dbg_out, |
334 | msm_mux_ddr_bist, |
335 | msm_mux_ddr_pxi0, |
336 | msm_mux_ebi0_wrcdc, |
337 | msm_mux_ebi2_a, |
338 | msm_mux_ebi2_lcd, |
339 | msm_mux_emac_gcc0, |
340 | msm_mux_emac_gcc1, |
341 | msm_mux_emac_pps0, |
342 | msm_mux_emac_pps1, |
343 | msm_mux_ext_dbg, |
344 | msm_mux_gcc_gp1, |
345 | msm_mux_gcc_gp2, |
346 | msm_mux_gcc_gp3, |
347 | msm_mux_gcc_plltest, |
348 | msm_mux_gpio, |
349 | msm_mux_i2s_mclk, |
350 | msm_mux_jitter_bist, |
351 | msm_mux_ldo_en, |
352 | msm_mux_ldo_update, |
353 | msm_mux_mgpi_clk, |
354 | msm_mux_m_voc, |
355 | msm_mux_native_char, |
356 | msm_mux_native_char0, |
357 | msm_mux_native_char1, |
358 | msm_mux_native_char2, |
359 | msm_mux_native_char3, |
360 | msm_mux_native_tsens, |
361 | msm_mux_native_tsense, |
362 | msm_mux_nav_gpio, |
363 | msm_mux_pa_indicator, |
364 | msm_mux_pcie_clkreq, |
365 | msm_mux_pci_e, |
366 | msm_mux_pll_bist, |
367 | msm_mux_pll_ref, |
368 | msm_mux_pll_test, |
369 | msm_mux_pri_mi2s, |
370 | msm_mux_prng_rosc, |
371 | msm_mux_qdss_cti, |
372 | msm_mux_qdss_gpio, |
373 | msm_mux_qdss_stm, |
374 | msm_mux_qlink0_en, |
375 | msm_mux_qlink0_req, |
376 | msm_mux_qlink0_wmss, |
377 | msm_mux_qlink1_en, |
378 | msm_mux_qlink1_req, |
379 | msm_mux_qlink1_wmss, |
380 | msm_mux_spmi_coex, |
381 | msm_mux_sec_mi2s, |
382 | msm_mux_spmi_vgi, |
383 | msm_mux_tgu_ch0, |
384 | msm_mux_uim1_clk, |
385 | msm_mux_uim1_data, |
386 | msm_mux_uim1_present, |
387 | msm_mux_uim1_reset, |
388 | msm_mux_uim2_clk, |
389 | msm_mux_uim2_data, |
390 | msm_mux_uim2_present, |
391 | msm_mux_uim2_reset, |
392 | msm_mux_usb2phy_ac, |
393 | msm_mux_vsense_trigger, |
394 | msm_mux__, |
395 | }; |
396 | |
397 | static const char * const gpio_groups[] = { |
398 | "gpio0" , "gpio1" , "gpio2" , "gpio3" , "gpio4" , "gpio5" , "gpio6" , "gpio7" , |
399 | "gpio8" , "gpio9" , "gpio10" , "gpio11" , "gpio12" , "gpio13" , "gpio14" , |
400 | "gpio15" , "gpio16" , "gpio17" , "gpio18" , "gpio19" , "gpio20" , "gpio21" , |
401 | "gpio22" , "gpio23" , "gpio24" , "gpio25" , "gpio26" , "gpio27" , "gpio28" , |
402 | "gpio29" , "gpio30" , "gpio31" , "gpio32" , "gpio33" , "gpio34" , "gpio35" , |
403 | "gpio36" , "gpio37" , "gpio38" , "gpio39" , "gpio40" , "gpio41" , "gpio42" , |
404 | "gpio43" , "gpio44" , "gpio45" , "gpio46" , "gpio47" , "gpio48" , "gpio49" , |
405 | "gpio50" , "gpio51" , "gpio52" , "gpio53" , "gpio54" , "gpio55" , "gpio56" , |
406 | "gpio57" , "gpio58" , "gpio59" , "gpio60" , "gpio61" , "gpio62" , "gpio63" , |
407 | "gpio64" , "gpio65" , "gpio66" , "gpio67" , "gpio68" , "gpio69" , "gpio70" , |
408 | "gpio71" , "gpio72" , "gpio73" , "gpio74" , "gpio75" , "gpio76" , "gpio77" , |
409 | "gpio78" , "gpio79" , "gpio80" , "gpio81" , "gpio82" , "gpio83" , "gpio84" , |
410 | "gpio85" , "gpio86" , "gpio87" , "gpio88" , "gpio89" , "gpio90" , "gpio91" , |
411 | "gpio92" , "gpio93" , "gpio94" , "gpio95" , "gpio96" , "gpio97" , "gpio98" , |
412 | "gpio99" , "gpio100" , "gpio101" , "gpio102" , "gpio103" , "gpio104" , |
413 | "gpio105" , "gpio106" , "gpio107" , |
414 | }; |
415 | |
416 | static const char * const qdss_stm_groups[] = { |
417 | "gpio0" , "gpio1" , "gpio2" , "gpio3" , "gpio4" , "gpio5" , "gpio6" , "gpio7" , "gpio12" , "gpio13" , |
418 | "gpio14" , "gpio15" , "gpio16" , "gpio17" , "gpio18" , "gpio19" , "gpio20" , "gpio21" , "gpio22" , |
419 | "gpio23" , "gpio44" , "gpio45" , "gpio52" , "gpio53" , "gpio56" , "gpio57" , "gpio61" , "gpio62" , |
420 | "gpio63" , "gpio64" , "gpio65" , "gpio66" , |
421 | }; |
422 | |
423 | static const char * const ddr_pxi0_groups[] = { |
424 | "gpio45" , "gpio46" , |
425 | }; |
426 | |
427 | static const char * const m_voc_groups[] = { |
428 | "gpio46" , "gpio48" , "gpio49" , "gpio59" , "gpio60" , |
429 | }; |
430 | |
431 | static const char * const ddr_bist_groups[] = { |
432 | "gpio46" , "gpio47" , "gpio48" , "gpio49" , |
433 | }; |
434 | |
435 | static const char * const blsp_spi1_groups[] = { |
436 | "gpio52" , "gpio62" , "gpio71" , "gpio80" , "gpio81" , "gpio82" , "gpio83" , |
437 | }; |
438 | |
439 | static const char * const pci_e_groups[] = { |
440 | "gpio53" , |
441 | }; |
442 | |
443 | static const char * const tgu_ch0_groups[] = { |
444 | "gpio55" , |
445 | }; |
446 | |
447 | static const char * const pcie_clkreq_groups[] = { |
448 | "gpio56" , |
449 | }; |
450 | |
451 | static const char * const mgpi_clk_groups[] = { |
452 | "gpio61" , "gpio71" , |
453 | }; |
454 | |
455 | static const char * const i2s_mclk_groups[] = { |
456 | "gpio62" , |
457 | }; |
458 | |
459 | static const char * const audio_ref_groups[] = { |
460 | "gpio62" , |
461 | }; |
462 | |
463 | static const char * const ldo_update_groups[] = { |
464 | "gpio62" , |
465 | }; |
466 | |
467 | static const char * const atest_groups[] = { |
468 | "gpio63" , "gpio64" , "gpio65" , "gpio66" , "gpio67" , |
469 | }; |
470 | |
471 | static const char * const uim1_data_groups[] = { |
472 | "gpio67" , |
473 | }; |
474 | |
475 | static const char * const uim1_present_groups[] = { |
476 | "gpio68" , |
477 | }; |
478 | |
479 | static const char * const uim1_reset_groups[] = { |
480 | "gpio69" , |
481 | }; |
482 | |
483 | static const char * const uim1_clk_groups[] = { |
484 | "gpio70" , |
485 | }; |
486 | |
487 | static const char * const qlink1_en_groups[] = { |
488 | "gpio72" , |
489 | }; |
490 | |
491 | static const char * const qlink1_req_groups[] = { |
492 | "gpio73" , |
493 | }; |
494 | |
495 | static const char * const qlink1_wmss_groups[] = { |
496 | "gpio74" , |
497 | }; |
498 | |
499 | static const char * const coex_uart2_groups[] = { |
500 | "gpio75" , "gpio76" , |
501 | }; |
502 | |
503 | static const char * const spmi_vgi_groups[] = { |
504 | "gpio78" , "gpio79" , |
505 | }; |
506 | |
507 | static const char * const gcc_plltest_groups[] = { |
508 | "gpio81" , "gpio82" , |
509 | }; |
510 | |
511 | static const char * const usb2phy_ac_groups[] = { |
512 | "gpio93" , |
513 | }; |
514 | |
515 | static const char * const emac_pps1_groups[] = { |
516 | "gpio95" , |
517 | }; |
518 | |
519 | static const char * const emac_pps0_groups[] = { |
520 | "gpio106" , |
521 | }; |
522 | |
523 | static const char * const uim2_data_groups[] = { |
524 | "gpio0" , |
525 | }; |
526 | |
527 | static const char * const ebi0_wrcdc_groups[] = { |
528 | "gpio0" , "gpio2" , |
529 | }; |
530 | |
531 | static const char * const uim2_present_groups[] = { |
532 | "gpio1" , |
533 | }; |
534 | |
535 | static const char * const blsp_uart1_groups[] = { |
536 | "gpio0" , "gpio1" , "gpio2" , "gpio3" , "gpio20" , "gpio21" , "gpio22" , |
537 | "gpio23" , |
538 | }; |
539 | |
540 | static const char * const uim2_reset_groups[] = { |
541 | "gpio2" , |
542 | }; |
543 | |
544 | static const char * const blsp_i2c1_groups[] = { |
545 | "gpio2" , "gpio3" , "gpio82" , "gpio83" , |
546 | }; |
547 | |
548 | static const char * const uim2_clk_groups[] = { |
549 | "gpio3" , |
550 | }; |
551 | |
552 | static const char * const blsp_spi2_groups[] = { |
553 | "gpio4" , "gpio5" , "gpio6" , "gpio7" , "gpio52" , "gpio62" , "gpio71" , |
554 | }; |
555 | |
556 | static const char * const blsp_uart2_groups[] = { |
557 | "gpio4" , "gpio5" , "gpio6" , "gpio7" , "gpio63" , "gpio64" , "gpio65" , |
558 | "gpio66" , |
559 | }; |
560 | |
561 | static const char * const blsp_i2c2_groups[] = { |
562 | "gpio6" , "gpio7" , "gpio65" , "gpio66" , |
563 | }; |
564 | |
565 | static const char * const char_exec_groups[] = { |
566 | "gpio6" , "gpio7" , |
567 | }; |
568 | |
569 | static const char * const pri_mi2s_groups[] = { |
570 | "gpio8" , "gpio9" , "gpio10" , "gpio11" , "gpio12" , "gpio13" , "gpio14" , |
571 | "gpio15" , |
572 | }; |
573 | |
574 | static const char * const blsp_spi3_groups[] = { |
575 | "gpio8" , "gpio9" , "gpio10" , "gpio11" , "gpio52" , "gpio62" , "gpio71" , |
576 | }; |
577 | |
578 | static const char * const blsp_uart3_groups[] = { |
579 | "gpio8" , "gpio9" , "gpio10" , "gpio11" , |
580 | }; |
581 | |
582 | static const char * const ext_dbg_groups[] = { |
583 | "gpio8" , "gpio9" , "gpio10" , "gpio11" , |
584 | }; |
585 | |
586 | static const char * const ldo_en_groups[] = { |
587 | "gpio8" , |
588 | }; |
589 | |
590 | static const char * const blsp_i2c3_groups[] = { |
591 | "gpio10" , "gpio11" , |
592 | }; |
593 | |
594 | static const char * const gcc_gp3_groups[] = { |
595 | "gpio11" , |
596 | }; |
597 | |
598 | static const char * const emac_gcc1_groups[] = { |
599 | "gpio14" , |
600 | }; |
601 | |
602 | static const char * const bimc_dte0_groups[] = { |
603 | "gpio14" , "gpio59" , |
604 | }; |
605 | |
606 | static const char * const native_tsens_groups[] = { |
607 | "gpio14" , |
608 | }; |
609 | |
610 | static const char * const vsense_trigger_groups[] = { |
611 | "gpio14" , |
612 | }; |
613 | |
614 | static const char * const emac_gcc0_groups[] = { |
615 | "gpio15" , |
616 | }; |
617 | |
618 | static const char * const bimc_dte1_groups[] = { |
619 | "gpio15" , "gpio61" , |
620 | }; |
621 | |
622 | static const char * const sec_mi2s_groups[] = { |
623 | "gpio16" , "gpio17" , "gpio18" , "gpio19" , "gpio20" , "gpio21" , "gpio22" , |
624 | "gpio23" , |
625 | }; |
626 | |
627 | static const char * const blsp_spi4_groups[] = { |
628 | "gpio16" , "gpio17" , "gpio18" , "gpio19" , "gpio52" , "gpio62" , "gpio71" , |
629 | }; |
630 | |
631 | static const char * const blsp_uart4_groups[] = { |
632 | "gpio16" , "gpio17" , "gpio18" , "gpio19" , "gpio20" , "gpio21" , "gpio22" , |
633 | "gpio23" , |
634 | }; |
635 | |
636 | static const char * const qdss_cti_groups[] = { |
637 | "gpio16" , "gpio16" , "gpio17" , "gpio17" , "gpio22" , "gpio22" , "gpio23" , |
638 | "gpio23" , "gpio54" , "gpio54" , "gpio55" , "gpio55" , "gpio59" , "gpio60" , |
639 | "gpio94" , "gpio94" , "gpio95" , "gpio95" , |
640 | }; |
641 | |
642 | static const char * const blsp_i2c4_groups[] = { |
643 | "gpio18" , "gpio19" , "gpio78" , "gpio79" , |
644 | }; |
645 | |
646 | static const char * const gcc_gp1_groups[] = { |
647 | "gpio18" , |
648 | }; |
649 | |
650 | static const char * const jitter_bist_groups[] = { |
651 | "gpio19" , |
652 | }; |
653 | |
654 | static const char * const gcc_gp2_groups[] = { |
655 | "gpio19" , |
656 | }; |
657 | |
658 | static const char * const ebi2_a_groups[] = { |
659 | "gpio20" , |
660 | }; |
661 | |
662 | static const char * const ebi2_lcd_groups[] = { |
663 | "gpio21" , "gpio22" , "gpio23" , |
664 | }; |
665 | |
666 | static const char * const pll_bist_groups[] = { |
667 | "gpio22" , |
668 | }; |
669 | |
670 | static const char * const adsp_ext_groups[] = { |
671 | "gpio24" , "gpio25" , |
672 | }; |
673 | |
674 | static const char * const native_char_groups[] = { |
675 | "gpio26" , |
676 | }; |
677 | |
678 | static const char * const qlink0_wmss_groups[] = { |
679 | "gpio28" , |
680 | }; |
681 | |
682 | static const char * const native_char3_groups[] = { |
683 | "gpio28" , |
684 | }; |
685 | |
686 | static const char * const native_char2_groups[] = { |
687 | "gpio29" , |
688 | }; |
689 | |
690 | static const char * const native_tsense_groups[] = { |
691 | "gpio29" , |
692 | }; |
693 | |
694 | static const char * const nav_gpio_groups[] = { |
695 | "gpio31" , "gpio32" , "gpio76" , |
696 | }; |
697 | |
698 | static const char * const pll_ref_groups[] = { |
699 | "gpio32" , |
700 | }; |
701 | |
702 | static const char * const pa_indicator_groups[] = { |
703 | "gpio33" , |
704 | }; |
705 | |
706 | static const char * const native_char0_groups[] = { |
707 | "gpio33" , |
708 | }; |
709 | |
710 | static const char * const qlink0_en_groups[] = { |
711 | "gpio34" , |
712 | }; |
713 | |
714 | static const char * const qlink0_req_groups[] = { |
715 | "gpio35" , |
716 | }; |
717 | |
718 | static const char * const pll_test_groups[] = { |
719 | "gpio35" , |
720 | }; |
721 | |
722 | static const char * const cri_trng_groups[] = { |
723 | "gpio36" , |
724 | }; |
725 | |
726 | static const char * const dbg_out_groups[] = { |
727 | "gpio36" , |
728 | }; |
729 | |
730 | static const char * const prng_rosc_groups[] = { |
731 | "gpio38" , |
732 | }; |
733 | |
734 | static const char * const cri_trng0_groups[] = { |
735 | "gpio40" , |
736 | }; |
737 | |
738 | static const char * const cri_trng1_groups[] = { |
739 | "gpio41" , |
740 | }; |
741 | |
742 | static const char * const qdss_gpio_groups[] = { |
743 | "gpio4" , "gpio5" , "gpio6" , "gpio7" , |
744 | "gpio12" , "gpio13" , "gpio14" , "gpio15" , "gpio16" , "gpio17" , "gpio18" , "gpio19" , |
745 | "gpio42" , "gpio61" , "gpio63" , "gpio64" , "gpio65" , "gpio66" , |
746 | }; |
747 | |
748 | static const char * const native_char1_groups[] = { |
749 | "gpio42" , |
750 | }; |
751 | |
752 | static const char * const coex_uart_groups[] = { |
753 | "gpio44" , "gpio45" , |
754 | }; |
755 | |
756 | static const char * const spmi_coex_groups[] = { |
757 | "gpio44" , "gpio45" , |
758 | }; |
759 | |
760 | static const struct pinfunction sdx55_functions[] = { |
761 | MSM_PIN_FUNCTION(adsp_ext), |
762 | MSM_PIN_FUNCTION(atest), |
763 | MSM_PIN_FUNCTION(audio_ref), |
764 | MSM_PIN_FUNCTION(bimc_dte0), |
765 | MSM_PIN_FUNCTION(bimc_dte1), |
766 | MSM_PIN_FUNCTION(blsp_i2c1), |
767 | MSM_PIN_FUNCTION(blsp_i2c2), |
768 | MSM_PIN_FUNCTION(blsp_i2c3), |
769 | MSM_PIN_FUNCTION(blsp_i2c4), |
770 | MSM_PIN_FUNCTION(blsp_spi1), |
771 | MSM_PIN_FUNCTION(blsp_spi2), |
772 | MSM_PIN_FUNCTION(blsp_spi3), |
773 | MSM_PIN_FUNCTION(blsp_spi4), |
774 | MSM_PIN_FUNCTION(blsp_uart1), |
775 | MSM_PIN_FUNCTION(blsp_uart2), |
776 | MSM_PIN_FUNCTION(blsp_uart3), |
777 | MSM_PIN_FUNCTION(blsp_uart4), |
778 | MSM_PIN_FUNCTION(char_exec), |
779 | MSM_PIN_FUNCTION(coex_uart), |
780 | MSM_PIN_FUNCTION(coex_uart2), |
781 | MSM_PIN_FUNCTION(cri_trng), |
782 | MSM_PIN_FUNCTION(cri_trng0), |
783 | MSM_PIN_FUNCTION(cri_trng1), |
784 | MSM_PIN_FUNCTION(dbg_out), |
785 | MSM_PIN_FUNCTION(ddr_bist), |
786 | MSM_PIN_FUNCTION(ddr_pxi0), |
787 | MSM_PIN_FUNCTION(ebi0_wrcdc), |
788 | MSM_PIN_FUNCTION(ebi2_a), |
789 | MSM_PIN_FUNCTION(ebi2_lcd), |
790 | MSM_PIN_FUNCTION(emac_gcc0), |
791 | MSM_PIN_FUNCTION(emac_gcc1), |
792 | MSM_PIN_FUNCTION(emac_pps0), |
793 | MSM_PIN_FUNCTION(emac_pps1), |
794 | MSM_PIN_FUNCTION(ext_dbg), |
795 | MSM_PIN_FUNCTION(gcc_gp1), |
796 | MSM_PIN_FUNCTION(gcc_gp2), |
797 | MSM_PIN_FUNCTION(gcc_gp3), |
798 | MSM_PIN_FUNCTION(gcc_plltest), |
799 | MSM_PIN_FUNCTION(gpio), |
800 | MSM_PIN_FUNCTION(i2s_mclk), |
801 | MSM_PIN_FUNCTION(jitter_bist), |
802 | MSM_PIN_FUNCTION(ldo_en), |
803 | MSM_PIN_FUNCTION(ldo_update), |
804 | MSM_PIN_FUNCTION(mgpi_clk), |
805 | MSM_PIN_FUNCTION(m_voc), |
806 | MSM_PIN_FUNCTION(native_char), |
807 | MSM_PIN_FUNCTION(native_char0), |
808 | MSM_PIN_FUNCTION(native_char1), |
809 | MSM_PIN_FUNCTION(native_char2), |
810 | MSM_PIN_FUNCTION(native_char3), |
811 | MSM_PIN_FUNCTION(native_tsens), |
812 | MSM_PIN_FUNCTION(native_tsense), |
813 | MSM_PIN_FUNCTION(nav_gpio), |
814 | MSM_PIN_FUNCTION(pa_indicator), |
815 | MSM_PIN_FUNCTION(pcie_clkreq), |
816 | MSM_PIN_FUNCTION(pci_e), |
817 | MSM_PIN_FUNCTION(pll_bist), |
818 | MSM_PIN_FUNCTION(pll_ref), |
819 | MSM_PIN_FUNCTION(pll_test), |
820 | MSM_PIN_FUNCTION(pri_mi2s), |
821 | MSM_PIN_FUNCTION(prng_rosc), |
822 | MSM_PIN_FUNCTION(qdss_cti), |
823 | MSM_PIN_FUNCTION(qdss_gpio), |
824 | MSM_PIN_FUNCTION(qdss_stm), |
825 | MSM_PIN_FUNCTION(qlink0_en), |
826 | MSM_PIN_FUNCTION(qlink0_req), |
827 | MSM_PIN_FUNCTION(qlink0_wmss), |
828 | MSM_PIN_FUNCTION(qlink1_en), |
829 | MSM_PIN_FUNCTION(qlink1_req), |
830 | MSM_PIN_FUNCTION(qlink1_wmss), |
831 | MSM_PIN_FUNCTION(spmi_coex), |
832 | MSM_PIN_FUNCTION(sec_mi2s), |
833 | MSM_PIN_FUNCTION(spmi_vgi), |
834 | MSM_PIN_FUNCTION(tgu_ch0), |
835 | MSM_PIN_FUNCTION(uim1_clk), |
836 | MSM_PIN_FUNCTION(uim1_data), |
837 | MSM_PIN_FUNCTION(uim1_present), |
838 | MSM_PIN_FUNCTION(uim1_reset), |
839 | MSM_PIN_FUNCTION(uim2_clk), |
840 | MSM_PIN_FUNCTION(uim2_data), |
841 | MSM_PIN_FUNCTION(uim2_present), |
842 | MSM_PIN_FUNCTION(uim2_reset), |
843 | MSM_PIN_FUNCTION(usb2phy_ac), |
844 | MSM_PIN_FUNCTION(vsense_trigger), |
845 | }; |
846 | |
847 | /* Every pin is maintained as a single group, and missing or non-existing pin |
848 | * would be maintained as dummy group to synchronize pin group index with |
849 | * pin descriptor registered with pinctrl core. |
850 | * Clients would not be able to request these dummy pin groups. |
851 | */ |
852 | static const struct msm_pingroup sdx55_groups[] = { |
853 | [0] = PINGROUP(0, uim2_data, blsp_uart1, qdss_stm, ebi0_wrcdc, _, _, _, _, _), |
854 | [1] = PINGROUP(1, uim2_present, blsp_uart1, qdss_stm, _, _, _, _, _, _), |
855 | [2] = PINGROUP(2, uim2_reset, blsp_uart1, blsp_i2c1, qdss_stm, ebi0_wrcdc, _, _, _, _), |
856 | [3] = PINGROUP(3, uim2_clk, blsp_uart1, blsp_i2c1, qdss_stm, _, _, _, _, _), |
857 | [4] = PINGROUP(4, blsp_spi2, blsp_uart2, _, qdss_stm, qdss_gpio, _, _, _, _), |
858 | [5] = PINGROUP(5, blsp_spi2, blsp_uart2, _, qdss_stm, qdss_gpio, _, _, _, _), |
859 | [6] = PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_stm, qdss_gpio, _, _), |
860 | [7] = PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_stm, qdss_gpio, _, _), |
861 | [8] = PINGROUP(8, pri_mi2s, blsp_spi3, blsp_uart3, ext_dbg, ldo_en, _, _, _, _), |
862 | [9] = PINGROUP(9, pri_mi2s, blsp_spi3, blsp_uart3, ext_dbg, _, _, _, _, _), |
863 | [10] = PINGROUP(10, pri_mi2s, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, _, _, _, _), |
864 | [11] = PINGROUP(11, pri_mi2s, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, gcc_gp3, _, _, _), |
865 | [12] = PINGROUP(12, pri_mi2s, _, qdss_stm, qdss_gpio, _, _, _, _, _), |
866 | [13] = PINGROUP(13, pri_mi2s, _, qdss_stm, qdss_gpio, _, _, _, _, _), |
867 | [14] = PINGROUP(14, pri_mi2s, emac_gcc1, _, _, qdss_stm, qdss_gpio, bimc_dte0, native_tsens, vsense_trigger), |
868 | [15] = PINGROUP(15, pri_mi2s, emac_gcc0, _, _, qdss_stm, qdss_gpio, bimc_dte1, _, _), |
869 | [16] = PINGROUP(16, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, _, qdss_stm, qdss_gpio), |
870 | [17] = PINGROUP(17, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, qdss_stm, qdss_gpio, _), |
871 | [18] = PINGROUP(18, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, gcc_gp1, qdss_stm, qdss_gpio, _, _), |
872 | [19] = PINGROUP(19, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, jitter_bist, gcc_gp2, _, qdss_stm, qdss_gpio), |
873 | [20] = PINGROUP(20, sec_mi2s, ebi2_a, blsp_uart1, blsp_uart4, qdss_stm, _, _, _, _), |
874 | [21] = PINGROUP(21, sec_mi2s, ebi2_lcd, blsp_uart1, blsp_uart4, _, qdss_stm, _, _, _), |
875 | [22] = PINGROUP(22, sec_mi2s, ebi2_lcd, blsp_uart1, qdss_cti, qdss_cti, blsp_uart4, pll_bist, _, qdss_stm), |
876 | [23] = PINGROUP(23, sec_mi2s, ebi2_lcd, qdss_cti, qdss_cti, blsp_uart1, blsp_uart4, qdss_stm, _, _), |
877 | [24] = PINGROUP(24, adsp_ext, _, _, _, _, _, _, _, _), |
878 | [25] = PINGROUP(25, adsp_ext, _, _, _, _, _, _, _, _), |
879 | [26] = PINGROUP(26, _, _, _, native_char, _, _, _, _, _), |
880 | [27] = PINGROUP(27, _, _, _, _, _, _, _, _, _), |
881 | [28] = PINGROUP(28, qlink0_wmss, _, native_char3, _, _, _, _, _, _), |
882 | [29] = PINGROUP(29, _, _, _, native_char2, native_tsense, _, _, _, _), |
883 | [30] = PINGROUP(30, _, _, _, _, _, _, _, _, _), |
884 | [31] = PINGROUP(31, nav_gpio, _, _, _, _, _, _, _, _), |
885 | [32] = PINGROUP(32, nav_gpio, pll_ref, _, _, _, _, _, _, _), |
886 | [33] = PINGROUP(33, _, pa_indicator, native_char0, _, _, _, _, _, _), |
887 | [34] = PINGROUP(34, qlink0_en, _, _, _, _, _, _, _, _), |
888 | [35] = PINGROUP(35, qlink0_req, pll_test, _, _, _, _, _, _, _), |
889 | [36] = PINGROUP(36, _, _, cri_trng, dbg_out, _, _, _, _, _), |
890 | [37] = PINGROUP(37, _, _, _, _, _, _, _, _, _), |
891 | [38] = PINGROUP(38, _, _, prng_rosc, _, _, _, _, _, _), |
892 | [39] = PINGROUP(39, _, _, _, _, _, _, _, _, _), |
893 | [40] = PINGROUP(40, _, _, cri_trng0, _, _, _, _, _, _), |
894 | [41] = PINGROUP(41, _, _, cri_trng1, _, _, _, _, _, _), |
895 | [42] = PINGROUP(42, _, qdss_gpio, native_char1, _, _, _, _, _, _), |
896 | [43] = PINGROUP(43, _, _, _, _, _, _, _, _, _), |
897 | [44] = PINGROUP(44, coex_uart, spmi_coex, _, qdss_stm, _, _, _, _, _), |
898 | [45] = PINGROUP(45, coex_uart, spmi_coex, qdss_stm, ddr_pxi0, _, _, _, _, _), |
899 | [46] = PINGROUP(46, m_voc, ddr_bist, ddr_pxi0, _, _, _, _, _, _), |
900 | [47] = PINGROUP(47, ddr_bist, _, _, _, _, _, _, _, _), |
901 | [48] = PINGROUP(48, m_voc, ddr_bist, _, _, _, _, _, _, _), |
902 | [49] = PINGROUP(49, m_voc, ddr_bist, _, _, _, _, _, _, _), |
903 | [50] = PINGROUP(50, _, _, _, _, _, _, _, _, _), |
904 | [51] = PINGROUP(51, _, _, _, _, _, _, _, _, _), |
905 | [52] = PINGROUP(52, blsp_spi2, blsp_spi1, blsp_spi3, blsp_spi4, _, _, qdss_stm, _, _), |
906 | [53] = PINGROUP(53, pci_e, _, _, qdss_stm, _, _, _, _, _), |
907 | [54] = PINGROUP(54, qdss_cti, qdss_cti, _, _, _, _, _, _, _), |
908 | [55] = PINGROUP(55, qdss_cti, qdss_cti, tgu_ch0, _, _, _, _, _, _), |
909 | [56] = PINGROUP(56, pcie_clkreq, _, qdss_stm, _, _, _, _, _, _), |
910 | [57] = PINGROUP(57, _, qdss_stm, _, _, _, _, _, _, _), |
911 | [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _), |
912 | [59] = PINGROUP(59, qdss_cti, m_voc, bimc_dte0, _, _, _, _, _, _), |
913 | [60] = PINGROUP(60, qdss_cti, _, m_voc, _, _, _, _, _, _), |
914 | [61] = PINGROUP(61, mgpi_clk, qdss_stm, qdss_gpio, bimc_dte1, _, _, _, _, _), |
915 | [62] = PINGROUP(62, i2s_mclk, audio_ref, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, ldo_update, qdss_stm, _), |
916 | [63] = PINGROUP(63, blsp_uart2, _, qdss_stm, qdss_gpio, atest, _, _, _, _), |
917 | [64] = PINGROUP(64, blsp_uart2, qdss_stm, qdss_gpio, atest, _, _, _, _, _), |
918 | [65] = PINGROUP(65, blsp_uart2, blsp_i2c2, _, qdss_stm, qdss_gpio, atest, _, _, _), |
919 | [66] = PINGROUP(66, blsp_uart2, blsp_i2c2, qdss_stm, qdss_gpio, atest, _, _, _, _), |
920 | [67] = PINGROUP(67, uim1_data, atest, _, _, _, _, _, _, _), |
921 | [68] = PINGROUP(68, uim1_present, _, _, _, _, _, _, _, _), |
922 | [69] = PINGROUP(69, uim1_reset, _, _, _, _, _, _, _, _), |
923 | [70] = PINGROUP(70, uim1_clk, _, _, _, _, _, _, _, _), |
924 | [71] = PINGROUP(71, mgpi_clk, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, _, _, _, _), |
925 | [72] = PINGROUP(72, qlink1_en, _, _, _, _, _, _, _, _), |
926 | [73] = PINGROUP(73, qlink1_req, _, _, _, _, _, _, _, _), |
927 | [74] = PINGROUP(74, qlink1_wmss, _, _, _, _, _, _, _, _), |
928 | [75] = PINGROUP(75, coex_uart2, _, _, _, _, _, _, _, _), |
929 | [76] = PINGROUP(76, coex_uart2, nav_gpio, _, _, _, _, _, _, _), |
930 | [77] = PINGROUP(77, _, _, _, _, _, _, _, _, _), |
931 | [78] = PINGROUP(78, spmi_vgi, blsp_i2c4, _, _, _, _, _, _, _), |
932 | [79] = PINGROUP(79, spmi_vgi, blsp_i2c4, _, _, _, _, _, _, _), |
933 | [80] = PINGROUP(80, _, blsp_spi1, _, _, _, _, _, _, _), |
934 | [81] = PINGROUP(81, _, blsp_spi1, _, gcc_plltest, _, _, _, _, _), |
935 | [82] = PINGROUP(82, _, blsp_spi1, _, blsp_i2c1, gcc_plltest, _, _, _, _), |
936 | [83] = PINGROUP(83, _, blsp_spi1, _, blsp_i2c1, _, _, _, _, _), |
937 | [84] = PINGROUP(84, _, _, _, _, _, _, _, _, _), |
938 | [85] = PINGROUP(85, _, _, _, _, _, _, _, _, _), |
939 | [86] = PINGROUP(86, _, _, _, _, _, _, _, _, _), |
940 | [87] = PINGROUP(87, _, _, _, _, _, _, _, _, _), |
941 | [88] = PINGROUP(88, _, _, _, _, _, _, _, _, _), |
942 | [89] = PINGROUP(89, _, _, _, _, _, _, _, _, _), |
943 | [90] = PINGROUP(90, _, _, _, _, _, _, _, _, _), |
944 | [91] = PINGROUP(91, _, _, _, _, _, _, _, _, _), |
945 | [92] = PINGROUP(92, _, _, _, _, _, _, _, _, _), |
946 | [93] = PINGROUP(93, _, _, usb2phy_ac, _, _, _, _, _, _), |
947 | [94] = PINGROUP(94, qdss_cti, qdss_cti, _, _, _, _, _, _, _), |
948 | [95] = PINGROUP(95, qdss_cti, qdss_cti, emac_pps1, _, _, _, _, _, _), |
949 | [96] = PINGROUP(96, _, _, _, _, _, _, _, _, _), |
950 | [97] = PINGROUP(97, _, _, _, _, _, _, _, _, _), |
951 | [98] = PINGROUP(98, _, _, _, _, _, _, _, _, _), |
952 | [99] = PINGROUP(99, _, _, _, _, _, _, _, _, _), |
953 | [100] = PINGROUP(100, _, _, _, _, _, _, _, _, _), |
954 | [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _), |
955 | [102] = PINGROUP(102, _, _, _, _, _, _, _, _, _), |
956 | [103] = PINGROUP(103, _, _, _, _, _, _, _, _, _), |
957 | [104] = PINGROUP(104, _, _, _, _, _, _, _, _, _), |
958 | [105] = PINGROUP(105, _, _, _, _, _, _, _, _, _), |
959 | [106] = PINGROUP(106, emac_pps0, _, _, _, _, _, _, _, _), |
960 | [107] = PINGROUP(107, _, _, _, _, _, _, _, _, _), |
961 | [109] = SDC_PINGROUP(sdc1_rclk, 0x9a000, 15, 0), |
962 | [110] = SDC_PINGROUP(sdc1_clk, 0x9a000, 13, 6), |
963 | [111] = SDC_PINGROUP(sdc1_cmd, 0x9a000, 11, 3), |
964 | [112] = SDC_PINGROUP(sdc1_data, 0x9a000, 9, 0), |
965 | }; |
966 | |
967 | static const struct msm_pinctrl_soc_data sdx55_pinctrl = { |
968 | .pins = sdx55_pins, |
969 | .npins = ARRAY_SIZE(sdx55_pins), |
970 | .functions = sdx55_functions, |
971 | .nfunctions = ARRAY_SIZE(sdx55_functions), |
972 | .groups = sdx55_groups, |
973 | .ngroups = ARRAY_SIZE(sdx55_groups), |
974 | .ngpios = 108, |
975 | }; |
976 | |
977 | static int sdx55_pinctrl_probe(struct platform_device *pdev) |
978 | { |
979 | return msm_pinctrl_probe(pdev, soc_data: &sdx55_pinctrl); |
980 | } |
981 | |
982 | static const struct of_device_id sdx55_pinctrl_of_match[] = { |
983 | { .compatible = "qcom,sdx55-pinctrl" , }, |
984 | { }, |
985 | }; |
986 | |
987 | static struct platform_driver sdx55_pinctrl_driver = { |
988 | .driver = { |
989 | .name = "sdx55-pinctrl" , |
990 | .of_match_table = sdx55_pinctrl_of_match, |
991 | }, |
992 | .probe = sdx55_pinctrl_probe, |
993 | .remove_new = msm_pinctrl_remove, |
994 | }; |
995 | |
996 | static int __init sdx55_pinctrl_init(void) |
997 | { |
998 | return platform_driver_register(&sdx55_pinctrl_driver); |
999 | } |
1000 | arch_initcall(sdx55_pinctrl_init); |
1001 | |
1002 | static void __exit sdx55_pinctrl_exit(void) |
1003 | { |
1004 | platform_driver_unregister(&sdx55_pinctrl_driver); |
1005 | } |
1006 | module_exit(sdx55_pinctrl_exit); |
1007 | |
1008 | MODULE_DESCRIPTION("QTI sdx55 pinctrl driver" ); |
1009 | MODULE_LICENSE("GPL v2" ); |
1010 | MODULE_DEVICE_TABLE(of, sdx55_pinctrl_of_match); |
1011 | |