1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6#include <linux/module.h>
7#include <linux/of.h>
8#include <linux/platform_device.h>
9
10#include "pinctrl-msm.h"
11
12#define REG_SIZE 0x1000
13
14#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
15 { \
16 .grp = PINCTRL_PINGROUP("gpio" #id, \
17 gpio##id##_pins, \
18 ARRAY_SIZE(gpio##id##_pins)), \
19 .funcs = (int[]){ \
20 msm_mux_gpio, /* gpio mode */ \
21 msm_mux_##f1, \
22 msm_mux_##f2, \
23 msm_mux_##f3, \
24 msm_mux_##f4, \
25 msm_mux_##f5, \
26 msm_mux_##f6, \
27 msm_mux_##f7, \
28 msm_mux_##f8, \
29 msm_mux_##f9 \
30 }, \
31 .nfuncs = 10, \
32 .ctl_reg = REG_SIZE * id, \
33 .io_reg = 0x4 + REG_SIZE * id, \
34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
35 .intr_status_reg = 0xc + REG_SIZE * id, \
36 .intr_target_reg = 0x8 + REG_SIZE * id, \
37 .mux_bit = 2, \
38 .pull_bit = 0, \
39 .drv_bit = 6, \
40 .egpio_enable = 12, \
41 .egpio_present = 11, \
42 .oe_bit = 9, \
43 .in_bit = 0, \
44 .out_bit = 1, \
45 .intr_enable_bit = 0, \
46 .intr_status_bit = 0, \
47 .intr_target_bit = 5, \
48 .intr_target_kpss_val = 3, \
49 .intr_raw_status_bit = 4, \
50 .intr_polarity_bit = 1, \
51 .intr_detection_bit = 2, \
52 .intr_detection_width = 2, \
53 }
54
55#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
56 { \
57 .grp = PINCTRL_PINGROUP(#pg_name, \
58 pg_name##_pins, \
59 ARRAY_SIZE(pg_name##_pins)), \
60 .ctl_reg = ctl, \
61 .io_reg = 0, \
62 .intr_cfg_reg = 0, \
63 .intr_status_reg = 0, \
64 .intr_target_reg = 0, \
65 .mux_bit = -1, \
66 .pull_bit = pull, \
67 .drv_bit = drv, \
68 .oe_bit = -1, \
69 .in_bit = -1, \
70 .out_bit = -1, \
71 .intr_enable_bit = -1, \
72 .intr_status_bit = -1, \
73 .intr_target_bit = -1, \
74 .intr_raw_status_bit = -1, \
75 .intr_polarity_bit = -1, \
76 .intr_detection_bit = -1, \
77 .intr_detection_width = -1, \
78 }
79
80#define UFS_RESET(pg_name, offset) \
81 { \
82 .grp = PINCTRL_PINGROUP(#pg_name, \
83 pg_name##_pins, \
84 ARRAY_SIZE(pg_name##_pins)), \
85 .ctl_reg = offset, \
86 .io_reg = offset + 0x4, \
87 .intr_cfg_reg = 0, \
88 .intr_status_reg = 0, \
89 .intr_target_reg = 0, \
90 .mux_bit = -1, \
91 .pull_bit = 3, \
92 .drv_bit = 0, \
93 .oe_bit = -1, \
94 .in_bit = -1, \
95 .out_bit = 0, \
96 .intr_enable_bit = -1, \
97 .intr_status_bit = -1, \
98 .intr_target_bit = -1, \
99 .intr_raw_status_bit = -1, \
100 .intr_polarity_bit = -1, \
101 .intr_detection_bit = -1, \
102 .intr_detection_width = -1, \
103 }
104
105#define QUP_I3C(qup_mode, qup_offset) \
106 { \
107 .mode = qup_mode, \
108 .offset = qup_offset, \
109 }
110
111
112static const struct pinctrl_pin_desc sm4450_pins[] = {
113 PINCTRL_PIN(0, "GPIO_0"),
114 PINCTRL_PIN(1, "GPIO_1"),
115 PINCTRL_PIN(2, "GPIO_2"),
116 PINCTRL_PIN(3, "GPIO_3"),
117 PINCTRL_PIN(4, "GPIO_4"),
118 PINCTRL_PIN(5, "GPIO_5"),
119 PINCTRL_PIN(6, "GPIO_6"),
120 PINCTRL_PIN(7, "GPIO_7"),
121 PINCTRL_PIN(8, "GPIO_8"),
122 PINCTRL_PIN(9, "GPIO_9"),
123 PINCTRL_PIN(10, "GPIO_10"),
124 PINCTRL_PIN(11, "GPIO_11"),
125 PINCTRL_PIN(12, "GPIO_12"),
126 PINCTRL_PIN(13, "GPIO_13"),
127 PINCTRL_PIN(14, "GPIO_14"),
128 PINCTRL_PIN(15, "GPIO_15"),
129 PINCTRL_PIN(16, "GPIO_16"),
130 PINCTRL_PIN(17, "GPIO_17"),
131 PINCTRL_PIN(18, "GPIO_18"),
132 PINCTRL_PIN(19, "GPIO_19"),
133 PINCTRL_PIN(20, "GPIO_20"),
134 PINCTRL_PIN(21, "GPIO_21"),
135 PINCTRL_PIN(22, "GPIO_22"),
136 PINCTRL_PIN(23, "GPIO_23"),
137 PINCTRL_PIN(24, "GPIO_24"),
138 PINCTRL_PIN(25, "GPIO_25"),
139 PINCTRL_PIN(26, "GPIO_26"),
140 PINCTRL_PIN(27, "GPIO_27"),
141 PINCTRL_PIN(28, "GPIO_28"),
142 PINCTRL_PIN(29, "GPIO_29"),
143 PINCTRL_PIN(30, "GPIO_30"),
144 PINCTRL_PIN(31, "GPIO_31"),
145 PINCTRL_PIN(32, "GPIO_32"),
146 PINCTRL_PIN(33, "GPIO_33"),
147 PINCTRL_PIN(34, "GPIO_34"),
148 PINCTRL_PIN(35, "GPIO_35"),
149 PINCTRL_PIN(36, "GPIO_36"),
150 PINCTRL_PIN(37, "GPIO_37"),
151 PINCTRL_PIN(38, "GPIO_38"),
152 PINCTRL_PIN(39, "GPIO_39"),
153 PINCTRL_PIN(40, "GPIO_40"),
154 PINCTRL_PIN(41, "GPIO_41"),
155 PINCTRL_PIN(42, "GPIO_42"),
156 PINCTRL_PIN(43, "GPIO_43"),
157 PINCTRL_PIN(44, "GPIO_44"),
158 PINCTRL_PIN(45, "GPIO_45"),
159 PINCTRL_PIN(46, "GPIO_46"),
160 PINCTRL_PIN(47, "GPIO_47"),
161 PINCTRL_PIN(48, "GPIO_48"),
162 PINCTRL_PIN(49, "GPIO_49"),
163 PINCTRL_PIN(50, "GPIO_50"),
164 PINCTRL_PIN(51, "GPIO_51"),
165 PINCTRL_PIN(52, "GPIO_52"),
166 PINCTRL_PIN(53, "GPIO_53"),
167 PINCTRL_PIN(54, "GPIO_54"),
168 PINCTRL_PIN(55, "GPIO_55"),
169 PINCTRL_PIN(56, "GPIO_56"),
170 PINCTRL_PIN(57, "GPIO_57"),
171 PINCTRL_PIN(58, "GPIO_58"),
172 PINCTRL_PIN(59, "GPIO_59"),
173 PINCTRL_PIN(60, "GPIO_60"),
174 PINCTRL_PIN(61, "GPIO_61"),
175 PINCTRL_PIN(62, "GPIO_62"),
176 PINCTRL_PIN(63, "GPIO_63"),
177 PINCTRL_PIN(64, "GPIO_64"),
178 PINCTRL_PIN(65, "GPIO_65"),
179 PINCTRL_PIN(66, "GPIO_66"),
180 PINCTRL_PIN(67, "GPIO_67"),
181 PINCTRL_PIN(68, "GPIO_68"),
182 PINCTRL_PIN(69, "GPIO_69"),
183 PINCTRL_PIN(70, "GPIO_70"),
184 PINCTRL_PIN(71, "GPIO_71"),
185 PINCTRL_PIN(72, "GPIO_72"),
186 PINCTRL_PIN(73, "GPIO_73"),
187 PINCTRL_PIN(74, "GPIO_74"),
188 PINCTRL_PIN(75, "GPIO_75"),
189 PINCTRL_PIN(76, "GPIO_76"),
190 PINCTRL_PIN(77, "GPIO_77"),
191 PINCTRL_PIN(78, "GPIO_78"),
192 PINCTRL_PIN(79, "GPIO_79"),
193 PINCTRL_PIN(80, "GPIO_80"),
194 PINCTRL_PIN(81, "GPIO_81"),
195 PINCTRL_PIN(82, "GPIO_82"),
196 PINCTRL_PIN(83, "GPIO_83"),
197 PINCTRL_PIN(84, "GPIO_84"),
198 PINCTRL_PIN(85, "GPIO_85"),
199 PINCTRL_PIN(86, "GPIO_86"),
200 PINCTRL_PIN(87, "GPIO_87"),
201 PINCTRL_PIN(88, "GPIO_88"),
202 PINCTRL_PIN(89, "GPIO_89"),
203 PINCTRL_PIN(90, "GPIO_90"),
204 PINCTRL_PIN(91, "GPIO_91"),
205 PINCTRL_PIN(92, "GPIO_92"),
206 PINCTRL_PIN(93, "GPIO_93"),
207 PINCTRL_PIN(94, "GPIO_94"),
208 PINCTRL_PIN(95, "GPIO_95"),
209 PINCTRL_PIN(96, "GPIO_96"),
210 PINCTRL_PIN(97, "GPIO_97"),
211 PINCTRL_PIN(98, "GPIO_98"),
212 PINCTRL_PIN(99, "GPIO_99"),
213 PINCTRL_PIN(100, "GPIO_100"),
214 PINCTRL_PIN(101, "GPIO_101"),
215 PINCTRL_PIN(102, "GPIO_102"),
216 PINCTRL_PIN(103, "GPIO_103"),
217 PINCTRL_PIN(104, "GPIO_104"),
218 PINCTRL_PIN(105, "GPIO_105"),
219 PINCTRL_PIN(106, "GPIO_106"),
220 PINCTRL_PIN(107, "GPIO_107"),
221 PINCTRL_PIN(108, "GPIO_108"),
222 PINCTRL_PIN(109, "GPIO_109"),
223 PINCTRL_PIN(110, "GPIO_110"),
224 PINCTRL_PIN(111, "GPIO_111"),
225 PINCTRL_PIN(112, "GPIO_112"),
226 PINCTRL_PIN(113, "GPIO_113"),
227 PINCTRL_PIN(114, "GPIO_114"),
228 PINCTRL_PIN(115, "GPIO_115"),
229 PINCTRL_PIN(116, "GPIO_116"),
230 PINCTRL_PIN(117, "GPIO_117"),
231 PINCTRL_PIN(118, "GPIO_118"),
232 PINCTRL_PIN(119, "GPIO_119"),
233 PINCTRL_PIN(120, "GPIO_120"),
234 PINCTRL_PIN(121, "GPIO_121"),
235 PINCTRL_PIN(122, "GPIO_122"),
236 PINCTRL_PIN(123, "GPIO_123"),
237 PINCTRL_PIN(124, "GPIO_124"),
238 PINCTRL_PIN(125, "GPIO_125"),
239 PINCTRL_PIN(126, "GPIO_126"),
240 PINCTRL_PIN(127, "GPIO_127"),
241 PINCTRL_PIN(128, "GPIO_128"),
242 PINCTRL_PIN(129, "GPIO_129"),
243 PINCTRL_PIN(130, "GPIO_130"),
244 PINCTRL_PIN(131, "GPIO_131"),
245 PINCTRL_PIN(132, "GPIO_132"),
246 PINCTRL_PIN(133, "GPIO_133"),
247 PINCTRL_PIN(134, "GPIO_134"),
248 PINCTRL_PIN(135, "GPIO_135"),
249 PINCTRL_PIN(136, "UFS_RESET"),
250 PINCTRL_PIN(137, "SDC1_RCLK"),
251 PINCTRL_PIN(138, "SDC1_CLK"),
252 PINCTRL_PIN(139, "SDC1_CMD"),
253 PINCTRL_PIN(140, "SDC1_DATA"),
254 PINCTRL_PIN(141, "SDC2_CLK"),
255 PINCTRL_PIN(142, "SDC2_CMD"),
256 PINCTRL_PIN(143, "SDC2_DATA"),
257};
258
259#define DECLARE_MSM_GPIO_PINS(pin) \
260 static const unsigned int gpio##pin##_pins[] = { pin }
261DECLARE_MSM_GPIO_PINS(0);
262DECLARE_MSM_GPIO_PINS(1);
263DECLARE_MSM_GPIO_PINS(2);
264DECLARE_MSM_GPIO_PINS(3);
265DECLARE_MSM_GPIO_PINS(4);
266DECLARE_MSM_GPIO_PINS(5);
267DECLARE_MSM_GPIO_PINS(6);
268DECLARE_MSM_GPIO_PINS(7);
269DECLARE_MSM_GPIO_PINS(8);
270DECLARE_MSM_GPIO_PINS(9);
271DECLARE_MSM_GPIO_PINS(10);
272DECLARE_MSM_GPIO_PINS(11);
273DECLARE_MSM_GPIO_PINS(12);
274DECLARE_MSM_GPIO_PINS(13);
275DECLARE_MSM_GPIO_PINS(14);
276DECLARE_MSM_GPIO_PINS(15);
277DECLARE_MSM_GPIO_PINS(16);
278DECLARE_MSM_GPIO_PINS(17);
279DECLARE_MSM_GPIO_PINS(18);
280DECLARE_MSM_GPIO_PINS(19);
281DECLARE_MSM_GPIO_PINS(20);
282DECLARE_MSM_GPIO_PINS(21);
283DECLARE_MSM_GPIO_PINS(22);
284DECLARE_MSM_GPIO_PINS(23);
285DECLARE_MSM_GPIO_PINS(24);
286DECLARE_MSM_GPIO_PINS(25);
287DECLARE_MSM_GPIO_PINS(26);
288DECLARE_MSM_GPIO_PINS(27);
289DECLARE_MSM_GPIO_PINS(28);
290DECLARE_MSM_GPIO_PINS(29);
291DECLARE_MSM_GPIO_PINS(30);
292DECLARE_MSM_GPIO_PINS(31);
293DECLARE_MSM_GPIO_PINS(32);
294DECLARE_MSM_GPIO_PINS(33);
295DECLARE_MSM_GPIO_PINS(34);
296DECLARE_MSM_GPIO_PINS(35);
297DECLARE_MSM_GPIO_PINS(36);
298DECLARE_MSM_GPIO_PINS(37);
299DECLARE_MSM_GPIO_PINS(38);
300DECLARE_MSM_GPIO_PINS(39);
301DECLARE_MSM_GPIO_PINS(40);
302DECLARE_MSM_GPIO_PINS(41);
303DECLARE_MSM_GPIO_PINS(42);
304DECLARE_MSM_GPIO_PINS(43);
305DECLARE_MSM_GPIO_PINS(44);
306DECLARE_MSM_GPIO_PINS(45);
307DECLARE_MSM_GPIO_PINS(46);
308DECLARE_MSM_GPIO_PINS(47);
309DECLARE_MSM_GPIO_PINS(48);
310DECLARE_MSM_GPIO_PINS(49);
311DECLARE_MSM_GPIO_PINS(50);
312DECLARE_MSM_GPIO_PINS(51);
313DECLARE_MSM_GPIO_PINS(52);
314DECLARE_MSM_GPIO_PINS(53);
315DECLARE_MSM_GPIO_PINS(54);
316DECLARE_MSM_GPIO_PINS(55);
317DECLARE_MSM_GPIO_PINS(56);
318DECLARE_MSM_GPIO_PINS(57);
319DECLARE_MSM_GPIO_PINS(58);
320DECLARE_MSM_GPIO_PINS(59);
321DECLARE_MSM_GPIO_PINS(60);
322DECLARE_MSM_GPIO_PINS(61);
323DECLARE_MSM_GPIO_PINS(62);
324DECLARE_MSM_GPIO_PINS(63);
325DECLARE_MSM_GPIO_PINS(64);
326DECLARE_MSM_GPIO_PINS(65);
327DECLARE_MSM_GPIO_PINS(66);
328DECLARE_MSM_GPIO_PINS(67);
329DECLARE_MSM_GPIO_PINS(68);
330DECLARE_MSM_GPIO_PINS(69);
331DECLARE_MSM_GPIO_PINS(70);
332DECLARE_MSM_GPIO_PINS(71);
333DECLARE_MSM_GPIO_PINS(72);
334DECLARE_MSM_GPIO_PINS(73);
335DECLARE_MSM_GPIO_PINS(74);
336DECLARE_MSM_GPIO_PINS(75);
337DECLARE_MSM_GPIO_PINS(76);
338DECLARE_MSM_GPIO_PINS(77);
339DECLARE_MSM_GPIO_PINS(78);
340DECLARE_MSM_GPIO_PINS(79);
341DECLARE_MSM_GPIO_PINS(80);
342DECLARE_MSM_GPIO_PINS(81);
343DECLARE_MSM_GPIO_PINS(82);
344DECLARE_MSM_GPIO_PINS(83);
345DECLARE_MSM_GPIO_PINS(84);
346DECLARE_MSM_GPIO_PINS(85);
347DECLARE_MSM_GPIO_PINS(86);
348DECLARE_MSM_GPIO_PINS(87);
349DECLARE_MSM_GPIO_PINS(88);
350DECLARE_MSM_GPIO_PINS(89);
351DECLARE_MSM_GPIO_PINS(90);
352DECLARE_MSM_GPIO_PINS(91);
353DECLARE_MSM_GPIO_PINS(92);
354DECLARE_MSM_GPIO_PINS(93);
355DECLARE_MSM_GPIO_PINS(94);
356DECLARE_MSM_GPIO_PINS(95);
357DECLARE_MSM_GPIO_PINS(96);
358DECLARE_MSM_GPIO_PINS(97);
359DECLARE_MSM_GPIO_PINS(98);
360DECLARE_MSM_GPIO_PINS(99);
361DECLARE_MSM_GPIO_PINS(100);
362DECLARE_MSM_GPIO_PINS(101);
363DECLARE_MSM_GPIO_PINS(102);
364DECLARE_MSM_GPIO_PINS(103);
365DECLARE_MSM_GPIO_PINS(104);
366DECLARE_MSM_GPIO_PINS(105);
367DECLARE_MSM_GPIO_PINS(106);
368DECLARE_MSM_GPIO_PINS(107);
369DECLARE_MSM_GPIO_PINS(108);
370DECLARE_MSM_GPIO_PINS(109);
371DECLARE_MSM_GPIO_PINS(110);
372DECLARE_MSM_GPIO_PINS(111);
373DECLARE_MSM_GPIO_PINS(112);
374DECLARE_MSM_GPIO_PINS(113);
375DECLARE_MSM_GPIO_PINS(114);
376DECLARE_MSM_GPIO_PINS(115);
377DECLARE_MSM_GPIO_PINS(116);
378DECLARE_MSM_GPIO_PINS(117);
379DECLARE_MSM_GPIO_PINS(118);
380DECLARE_MSM_GPIO_PINS(119);
381DECLARE_MSM_GPIO_PINS(120);
382DECLARE_MSM_GPIO_PINS(121);
383DECLARE_MSM_GPIO_PINS(122);
384DECLARE_MSM_GPIO_PINS(123);
385DECLARE_MSM_GPIO_PINS(124);
386DECLARE_MSM_GPIO_PINS(125);
387DECLARE_MSM_GPIO_PINS(126);
388DECLARE_MSM_GPIO_PINS(127);
389DECLARE_MSM_GPIO_PINS(128);
390DECLARE_MSM_GPIO_PINS(129);
391DECLARE_MSM_GPIO_PINS(130);
392DECLARE_MSM_GPIO_PINS(131);
393DECLARE_MSM_GPIO_PINS(132);
394DECLARE_MSM_GPIO_PINS(133);
395DECLARE_MSM_GPIO_PINS(134);
396DECLARE_MSM_GPIO_PINS(135);
397
398static const unsigned int ufs_reset_pins[] = { 136 };
399static const unsigned int sdc1_rclk_pins[] = { 137 };
400static const unsigned int sdc1_clk_pins[] = { 138 };
401static const unsigned int sdc1_cmd_pins[] = { 139 };
402static const unsigned int sdc1_data_pins[] = { 140 };
403static const unsigned int sdc2_clk_pins[] = { 141 };
404static const unsigned int sdc2_cmd_pins[] = { 142 };
405static const unsigned int sdc2_data_pins[] = { 143 };
406
407enum sm4450_functions {
408 msm_mux_gpio,
409 msm_mux_atest_char,
410 msm_mux_atest_usb0,
411 msm_mux_audio_ref_clk,
412 msm_mux_cam_mclk,
413 msm_mux_cci_async_in0,
414 msm_mux_cci_i2c,
415 msm_mux_cci,
416 msm_mux_cmu_rng,
417 msm_mux_coex_uart1_rx,
418 msm_mux_coex_uart1_tx,
419 msm_mux_cri_trng,
420 msm_mux_dbg_out_clk,
421 msm_mux_ddr_bist,
422 msm_mux_ddr_pxi0_test,
423 msm_mux_ddr_pxi1_test,
424 msm_mux_gcc_gp1_clk,
425 msm_mux_gcc_gp2_clk,
426 msm_mux_gcc_gp3_clk,
427 msm_mux_host2wlan_sol,
428 msm_mux_ibi_i3c_qup0,
429 msm_mux_ibi_i3c_qup1,
430 msm_mux_jitter_bist_ref,
431 msm_mux_mdp_vsync0_out,
432 msm_mux_mdp_vsync1_out,
433 msm_mux_mdp_vsync2_out,
434 msm_mux_mdp_vsync3_out,
435 msm_mux_mdp_vsync,
436 msm_mux_nav,
437 msm_mux_pcie0_clk_req,
438 msm_mux_phase_flag,
439 msm_mux_pll_bist_sync,
440 msm_mux_pll_clk_aux,
441 msm_mux_prng_rosc,
442 msm_mux_qdss_cti_trig0,
443 msm_mux_qdss_cti_trig1,
444 msm_mux_qdss_gpio,
445 msm_mux_qlink0_enable,
446 msm_mux_qlink0_request,
447 msm_mux_qlink0_wmss_reset,
448 msm_mux_qup0_se0,
449 msm_mux_qup0_se1,
450 msm_mux_qup0_se2,
451 msm_mux_qup0_se3,
452 msm_mux_qup0_se4,
453 msm_mux_qup1_se0,
454 msm_mux_qup1_se1,
455 msm_mux_qup1_se2,
456 msm_mux_qup1_se3,
457 msm_mux_qup1_se4,
458 msm_mux_sd_write_protect,
459 msm_mux_tb_trig_sdc1,
460 msm_mux_tb_trig_sdc2,
461 msm_mux_tgu_ch0_trigout,
462 msm_mux_tgu_ch1_trigout,
463 msm_mux_tgu_ch2_trigout,
464 msm_mux_tgu_ch3_trigout,
465 msm_mux_tmess_prng,
466 msm_mux_tsense_pwm1_out,
467 msm_mux_tsense_pwm2_out,
468 msm_mux_uim0,
469 msm_mux_uim1,
470 msm_mux_usb0_hs_ac,
471 msm_mux_usb0_phy_ps,
472 msm_mux_vfr_0_mira,
473 msm_mux_vfr_0_mirb,
474 msm_mux_vfr_1,
475 msm_mux_vsense_trigger_mirnat,
476 msm_mux_wlan1_adc_dtest0,
477 msm_mux_wlan1_adc_dtest1,
478 msm_mux__,
479};
480
481static const char * const gpio_groups[] = {
482 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
483 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
484 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
485 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
486 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
487 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
488 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
489 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
490 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
491 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
492 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
493 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
494 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
495 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
496 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
497 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
498 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
499 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
500 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
501 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
502 "gpio135",
503};
504static const char * const atest_char_groups[] = {
505 "gpio95", "gpio97", "gpio98", "gpio99", "gpio100",
506};
507static const char * const atest_usb0_groups[] = {
508 "gpio75", "gpio10", "gpio78", "gpio79", "gpio80",
509};
510static const char * const audio_ref_clk_groups[] = {
511 "gpio71",
512};
513static const char * const cam_mclk_groups[] = {
514 "gpio36", "gpio37", "gpio38", "gpio39",
515};
516static const char * const cci_async_in0_groups[] = {
517 "gpio40",
518};
519static const char * const cci_i2c_groups[] = {
520 "gpio45", "gpio47", "gpio49", "gpio44",
521 "gpio46", "gpio48",
522};
523static const char * const cci_groups[] = {
524 "gpio40", "gpio41", "gpio42", "gpio43",
525};
526static const char * const cmu_rng_groups[] = {
527 "gpio28", "gpio3", "gpio1", "gpio0",
528};
529static const char * const coex_uart1_rx_groups[] = {
530 "gpio54",
531};
532static const char * const coex_uart1_tx_groups[] = {
533 "gpio55",
534};
535static const char * const cri_trng_groups[] = {
536 "gpio42", "gpio40", "gpio41",
537};
538static const char * const dbg_out_clk_groups[] = {
539 "gpio80",
540};
541static const char * const ddr_bist_groups[] = {
542 "gpio32", "gpio29", "gpio30", "gpio31",
543};
544static const char * const ddr_pxi0_test_groups[] = {
545 "gpio90", "gpio127",
546};
547static const char * const ddr_pxi1_test_groups[] = {
548 "gpio118", "gpio122",
549};
550static const char * const gcc_gp1_clk_groups[] = {
551 "gpio37", "gpio48",
552};
553static const char * const gcc_gp2_clk_groups[] = {
554 "gpio30", "gpio49",
555};
556static const char * const gcc_gp3_clk_groups[] = {
557 "gpio3", "gpio50",
558};
559static const char * const host2wlan_sol_groups[] = {
560 "gpio106",
561};
562static const char * const ibi_i3c_qup0_groups[] = {
563 "gpio4", "gpio5",
564};
565static const char * const ibi_i3c_qup1_groups[] = {
566 "gpio0", "gpio1",
567};
568static const char * const jitter_bist_ref_groups[] = {
569 "gpio90",
570};
571static const char * const mdp_vsync0_out_groups[] = {
572 "gpio93",
573};
574static const char * const mdp_vsync1_out_groups[] = {
575 "gpio93",
576};
577static const char * const mdp_vsync2_out_groups[] = {
578 "gpio22",
579};
580static const char * const mdp_vsync3_out_groups[] = {
581 "gpio22",
582};
583static const char * const mdp_vsync_groups[] = {
584 "gpio26", "gpio22", "gpio30", "gpio34", "gpio93", "gpio97",
585};
586static const char * const nav_groups[] = {
587 "gpio81", "gpio83", "gpio84",
588};
589static const char * const pcie0_clk_req_groups[] = {
590 "gpio107",
591};
592static const char * const phase_flag_groups[] = {
593 "gpio7", "gpio8", "gpio9", "gpio11", "gpio13", "gpio14", "gpio15",
594 "gpio17", "gpio18", "gpio19", "gpio21", "gpio24", "gpio25", "gpio31",
595 "gpio32", "gpio33", "gpio35", "gpio61", "gpio72", "gpio82", "gpio91",
596 "gpio95", "gpio97", "gpio98", "gpio99", "gpio100", "gpio105", "gpio115",
597 "gpio116", "gpio117", "gpio133", "gpio135",
598};
599static const char * const pll_bist_sync_groups[] = {
600 "gpio73",
601};
602static const char * const pll_clk_aux_groups[] = {
603 "gpio108",
604};
605static const char * const prng_rosc_groups[] = {
606 "gpio36", "gpio37", "gpio38", "gpio39",
607};
608static const char * const qdss_cti_trig0_groups[] = {
609 "gpio26", "gpio60", "gpio113", "gpio114",
610};
611static const char * const qdss_cti_trig1_groups[] = {
612 "gpio6", "gpio27", "gpio57", "gpio58",
613};
614static const char * const qdss_gpio_groups[] = {
615 "gpio0", "gpio1", "gpio3", "gpio4", "gpio5", "gpio7", "gpio8",
616 "gpio9", "gpio14", "gpio15", "gpio17", "gpio23", "gpio31", "gpio32",
617 "gpio33", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40",
618 "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47",
619 "gpio49", "gpio59", "gpio62", "gpio118", "gpio121", "gpio122", "gpio126",
620 "gpio127",
621};
622static const char * const qlink0_enable_groups[] = {
623 "gpio88",
624};
625static const char * const qlink0_request_groups[] = {
626 "gpio87",
627};
628static const char * const qlink0_wmss_reset_groups[] = {
629 "gpio89",
630};
631static const char * const qup0_se0_groups[] = {
632 "gpio4", "gpio5", "gpio34", "gpio35",
633};
634static const char * const qup0_se1_groups[] = {
635 "gpio10", "gpio11", "gpio12", "gpio13",
636};
637static const char * const qup0_se2_groups[] = {
638 "gpio14", "gpio15", "gpio16", "gpio17",
639};
640static const char * const qup0_se3_groups[] = {
641 "gpio18", "gpio19", "gpio20", "gpio21",
642};
643static const char * const qup0_se4_groups[] = {
644 "gpio6", "gpio7", "gpio8", "gpio9",
645 "gpio26", "gpio27", "gpio34",
646};
647static const char * const qup1_se0_groups[] = {
648 "gpio0", "gpio1", "gpio2", "gpio3",
649};
650static const char * const qup1_se1_groups[] = {
651 "gpio26", "gpio27", "gpio50", "gpio51",
652};
653static const char * const qup1_se2_groups[] = {
654 "gpio22", "gpio23", "gpio31", "gpio32",
655};
656static const char * const qup1_se3_groups[] = {
657 "gpio24", "gpio25", "gpio51", "gpio50",
658};
659static const char * const qup1_se4_groups[] = {
660 "gpio43", "gpio48", "gpio49", "gpio90",
661 "gpio91",
662};
663static const char * const sd_write_protect_groups[] = {
664 "gpio102",
665};
666static const char * const tb_trig_sdc1_groups[] = {
667 "gpio128",
668};
669static const char * const tb_trig_sdc2_groups[] = {
670 "gpio51",
671};
672static const char * const tgu_ch0_trigout_groups[] = {
673 "gpio20",
674};
675static const char * const tgu_ch1_trigout_groups[] = {
676 "gpio21",
677};
678static const char * const tgu_ch2_trigout_groups[] = {
679 "gpio22",
680};
681static const char * const tgu_ch3_trigout_groups[] = {
682 "gpio23",
683};
684static const char * const tmess_prng_groups[] = {
685 "gpio57", "gpio58", "gpio59", "gpio60",
686};
687static const char * const tsense_pwm1_out_groups[] = {
688 "gpio134",
689};
690static const char * const tsense_pwm2_out_groups[] = {
691 "gpio134",
692};
693static const char * const uim0_groups[] = {
694 "gpio64", "gpio63", "gpio66", "gpio65",
695};
696static const char * const uim1_groups[] = {
697 "gpio68", "gpio67", "gpio69", "gpio70",
698};
699static const char * const usb0_hs_ac_groups[] = {
700 "gpio99",
701};
702static const char * const usb0_phy_ps_groups[] = {
703 "gpio94",
704};
705static const char * const vfr_0_mira_groups[] = {
706 "gpio19",
707};
708static const char * const vfr_0_mirb_groups[] = {
709 "gpio100",
710};
711static const char * const vfr_1_groups[] = {
712 "gpio84",
713};
714static const char * const vsense_trigger_mirnat_groups[] = {
715 "gpio75",
716};
717static const char * const wlan1_adc_dtest0_groups[] = {
718 "gpio79",
719};
720static const char * const wlan1_adc_dtest1_groups[] = {
721 "gpio80",
722};
723
724static const struct pinfunction sm4450_functions[] = {
725 MSM_GPIO_PIN_FUNCTION(gpio),
726 MSM_PIN_FUNCTION(atest_char),
727 MSM_PIN_FUNCTION(atest_usb0),
728 MSM_PIN_FUNCTION(audio_ref_clk),
729 MSM_PIN_FUNCTION(cam_mclk),
730 MSM_PIN_FUNCTION(cci_async_in0),
731 MSM_PIN_FUNCTION(cci_i2c),
732 MSM_PIN_FUNCTION(cci),
733 MSM_PIN_FUNCTION(cmu_rng),
734 MSM_PIN_FUNCTION(coex_uart1_rx),
735 MSM_PIN_FUNCTION(coex_uart1_tx),
736 MSM_PIN_FUNCTION(cri_trng),
737 MSM_PIN_FUNCTION(dbg_out_clk),
738 MSM_PIN_FUNCTION(ddr_bist),
739 MSM_PIN_FUNCTION(ddr_pxi0_test),
740 MSM_PIN_FUNCTION(ddr_pxi1_test),
741 MSM_PIN_FUNCTION(gcc_gp1_clk),
742 MSM_PIN_FUNCTION(gcc_gp2_clk),
743 MSM_PIN_FUNCTION(gcc_gp3_clk),
744 MSM_PIN_FUNCTION(host2wlan_sol),
745 MSM_PIN_FUNCTION(ibi_i3c_qup0),
746 MSM_PIN_FUNCTION(ibi_i3c_qup1),
747 MSM_PIN_FUNCTION(jitter_bist_ref),
748 MSM_PIN_FUNCTION(mdp_vsync0_out),
749 MSM_PIN_FUNCTION(mdp_vsync1_out),
750 MSM_PIN_FUNCTION(mdp_vsync2_out),
751 MSM_PIN_FUNCTION(mdp_vsync3_out),
752 MSM_PIN_FUNCTION(mdp_vsync),
753 MSM_PIN_FUNCTION(nav),
754 MSM_PIN_FUNCTION(pcie0_clk_req),
755 MSM_PIN_FUNCTION(phase_flag),
756 MSM_PIN_FUNCTION(pll_bist_sync),
757 MSM_PIN_FUNCTION(pll_clk_aux),
758 MSM_PIN_FUNCTION(prng_rosc),
759 MSM_PIN_FUNCTION(qdss_cti_trig0),
760 MSM_PIN_FUNCTION(qdss_cti_trig1),
761 MSM_PIN_FUNCTION(qdss_gpio),
762 MSM_PIN_FUNCTION(qlink0_enable),
763 MSM_PIN_FUNCTION(qlink0_request),
764 MSM_PIN_FUNCTION(qlink0_wmss_reset),
765 MSM_PIN_FUNCTION(qup0_se0),
766 MSM_PIN_FUNCTION(qup0_se1),
767 MSM_PIN_FUNCTION(qup0_se2),
768 MSM_PIN_FUNCTION(qup0_se3),
769 MSM_PIN_FUNCTION(qup0_se4),
770 MSM_PIN_FUNCTION(qup1_se0),
771 MSM_PIN_FUNCTION(qup1_se1),
772 MSM_PIN_FUNCTION(qup1_se2),
773 MSM_PIN_FUNCTION(qup1_se3),
774 MSM_PIN_FUNCTION(qup1_se4),
775 MSM_PIN_FUNCTION(sd_write_protect),
776 MSM_PIN_FUNCTION(tb_trig_sdc1),
777 MSM_PIN_FUNCTION(tb_trig_sdc2),
778 MSM_PIN_FUNCTION(tgu_ch0_trigout),
779 MSM_PIN_FUNCTION(tgu_ch1_trigout),
780 MSM_PIN_FUNCTION(tgu_ch2_trigout),
781 MSM_PIN_FUNCTION(tgu_ch3_trigout),
782 MSM_PIN_FUNCTION(tmess_prng),
783 MSM_PIN_FUNCTION(tsense_pwm1_out),
784 MSM_PIN_FUNCTION(tsense_pwm2_out),
785 MSM_PIN_FUNCTION(uim0),
786 MSM_PIN_FUNCTION(uim1),
787 MSM_PIN_FUNCTION(usb0_hs_ac),
788 MSM_PIN_FUNCTION(usb0_phy_ps),
789 MSM_PIN_FUNCTION(vfr_0_mira),
790 MSM_PIN_FUNCTION(vfr_0_mirb),
791 MSM_PIN_FUNCTION(vfr_1),
792 MSM_PIN_FUNCTION(vsense_trigger_mirnat),
793 MSM_PIN_FUNCTION(wlan1_adc_dtest0),
794 MSM_PIN_FUNCTION(wlan1_adc_dtest1),
795};
796
797/*
798 * Every pin is maintained as a single group, and missing or non-existing pin
799 * would be maintained as dummy group to synchronize pin group index with
800 * pin descriptor registered with pinctrl core.
801 * Clients would not be able to request these dummy pin groups.
802 */
803static const struct msm_pingroup sm4450_groups[] = {
804 [0] = PINGROUP(0, qup1_se0, ibi_i3c_qup1, cmu_rng, qdss_gpio, _, _, _, _, _),
805 [1] = PINGROUP(1, qup1_se0, ibi_i3c_qup1, cmu_rng, qdss_gpio, _, _, _, _, _),
806 [2] = PINGROUP(2, qup1_se0, _, _, _, _, _, _, _, _),
807 [3] = PINGROUP(3, qup1_se0, gcc_gp3_clk, cmu_rng, qdss_gpio, _, _, _, _, _),
808 [4] = PINGROUP(4, qup0_se0, ibi_i3c_qup0, qdss_gpio, _, _, _, _, _, _),
809 [5] = PINGROUP(5, qup0_se0, ibi_i3c_qup0, qdss_gpio, _, _, _, _, _, _),
810 [6] = PINGROUP(6, qup0_se4, qdss_cti_trig1, _, _, _, _, _, _, _),
811 [7] = PINGROUP(7, qup0_se4, _, phase_flag, qdss_gpio, _, _, _, _, _),
812 [8] = PINGROUP(8, qup0_se4, _, phase_flag, qdss_gpio, _, _, _, _, _),
813 [9] = PINGROUP(9, qup0_se4, _, phase_flag, qdss_gpio, _, _, _, _, _),
814 [10] = PINGROUP(10, qup0_se1, _, atest_usb0, _, _, _, _, _, _),
815 [11] = PINGROUP(11, qup0_se1, _, phase_flag, _, _, _, _, _, _),
816 [12] = PINGROUP(12, qup0_se1, _, _, _, _, _, _, _, _),
817 [13] = PINGROUP(13, qup0_se1, _, phase_flag, _, _, _, _, _, _),
818 [14] = PINGROUP(14, qup0_se2, _, phase_flag, _, qdss_gpio, _, _, _, _),
819 [15] = PINGROUP(15, qup0_se2, _, phase_flag, _, qdss_gpio, _, _, _, _),
820 [16] = PINGROUP(16, qup0_se2, _, _, _, _, _, _, _, _),
821 [17] = PINGROUP(17, qup0_se2, _, phase_flag, _, qdss_gpio, _, _, _, _),
822 [18] = PINGROUP(18, qup0_se3, _, phase_flag, _, _, _, _, _, _),
823 [19] = PINGROUP(19, qup0_se3, vfr_0_mira, _, phase_flag, _, _, _, _, _),
824 [20] = PINGROUP(20, qup0_se3, tgu_ch0_trigout, _, _, _, _, _, _, _),
825 [21] = PINGROUP(21, qup0_se3, _, phase_flag, tgu_ch1_trigout, _, _, _, _, _),
826 [22] = PINGROUP(22, qup1_se2, mdp_vsync, mdp_vsync2_out, mdp_vsync3_out, tgu_ch2_trigout, _, _, _, _),
827 [23] = PINGROUP(23, qup1_se2, tgu_ch3_trigout, qdss_gpio, _, _, _, _, _, _),
828 [24] = PINGROUP(24, qup1_se3, _, phase_flag, _, _, _, _, _, _),
829 [25] = PINGROUP(25, qup1_se3, _, phase_flag, _, _, _, _, _, _),
830 [26] = PINGROUP(26, qup1_se1, mdp_vsync, qup0_se4, qdss_cti_trig0, _, _, _, _, _),
831 [27] = PINGROUP(27, qup1_se1, qup0_se4, qdss_cti_trig1, _, _, _, _, _, _),
832 [28] = PINGROUP(28, cmu_rng, _, _, _, _, _, _, _, _),
833 [29] = PINGROUP(29, ddr_bist, _, _, _, _, _, _, _, _),
834 [30] = PINGROUP(30, mdp_vsync, gcc_gp2_clk, ddr_bist, _, _, _, _, _, _),
835 [31] = PINGROUP(31, qup1_se2, _, phase_flag, ddr_bist, qdss_gpio, _, _, _, _),
836 [32] = PINGROUP(32, qup1_se2, _, phase_flag, ddr_bist, qdss_gpio, _, _, _, _),
837 [33] = PINGROUP(33, _, phase_flag, qdss_gpio, _, _, _, _, _, _),
838 [34] = PINGROUP(34, qup0_se0, qup0_se4, mdp_vsync, _, _, _, _, _, _),
839 [35] = PINGROUP(35, qup0_se0, _, phase_flag, qdss_gpio, _, _, _, _, _),
840 [36] = PINGROUP(36, cam_mclk, prng_rosc, qdss_gpio, _, _, _, _, _, _),
841 [37] = PINGROUP(37, cam_mclk, gcc_gp1_clk, prng_rosc, qdss_gpio, _, _, _, _, _),
842 [38] = PINGROUP(38, cam_mclk, prng_rosc, qdss_gpio, _, _, _, _, _, _),
843 [39] = PINGROUP(39, cam_mclk, prng_rosc, qdss_gpio, _, _, _, _, _, _),
844 [40] = PINGROUP(40, cci, cci_async_in0, cri_trng, qdss_gpio, _, _, _, _, _),
845 [41] = PINGROUP(41, cci, cri_trng, qdss_gpio, _, _, _, _, _, _),
846 [42] = PINGROUP(42, cci, cri_trng, qdss_gpio, _, _, _, _, _, _),
847 [43] = PINGROUP(43, cci, qup1_se4, qdss_gpio, _, _, _, _, _, _),
848 [44] = PINGROUP(44, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
849 [45] = PINGROUP(45, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
850 [46] = PINGROUP(46, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
851 [47] = PINGROUP(47, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
852 [48] = PINGROUP(48, cci_i2c, qup1_se4, gcc_gp1_clk, _, _, _, _, _, _),
853 [49] = PINGROUP(49, cci_i2c, qup1_se4, gcc_gp2_clk, qdss_gpio, _, _, _, _, _),
854 [50] = PINGROUP(50, qup1_se1, qup1_se3, _, gcc_gp3_clk, _, _, _, _, _),
855 [51] = PINGROUP(51, qup1_se1, qup1_se3, _, tb_trig_sdc2, _, _, _, _, _),
856 [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _),
857 [53] = PINGROUP(53, _, _, _, _, _, _, _, _, _),
858 [54] = PINGROUP(54, coex_uart1_rx, _, _, _, _, _, _, _, _),
859 [55] = PINGROUP(55, coex_uart1_tx, _, _, _, _, _, _, _, _),
860 [56] = PINGROUP(56, _, _, _, _, _, _, _, _, _),
861 [57] = PINGROUP(57, tmess_prng, qdss_cti_trig1, _, _, _, _, _, _, _),
862 [58] = PINGROUP(58, tmess_prng, qdss_cti_trig1, _, _, _, _, _, _, _),
863 [59] = PINGROUP(59, tmess_prng, qdss_gpio, _, _, _, _, _, _, _),
864 [60] = PINGROUP(60, tmess_prng, qdss_cti_trig0, _, _, _, _, _, _, _),
865 [61] = PINGROUP(61, _, phase_flag, _, _, _, _, _, _, _),
866 [62] = PINGROUP(62, qdss_gpio, _, _, _, _, _, _, _, _),
867 [63] = PINGROUP(63, uim0, _, _, _, _, _, _, _, _),
868 [64] = PINGROUP(64, uim0, _, _, _, _, _, _, _, _),
869 [65] = PINGROUP(65, uim0, _, _, _, _, _, _, _, _),
870 [66] = PINGROUP(66, uim0, _, _, _, _, _, _, _, _),
871 [67] = PINGROUP(67, uim1, _, _, _, _, _, _, _, _),
872 [68] = PINGROUP(68, uim1, _, _, _, _, _, _, _, _),
873 [69] = PINGROUP(69, uim1, _, _, _, _, _, _, _, _),
874 [70] = PINGROUP(70, uim1, _, _, _, _, _, _, _, _),
875 [71] = PINGROUP(71, _, _, _, audio_ref_clk, _, _, _, _, _),
876 [72] = PINGROUP(72, _, _, _, phase_flag, _, _, _, _, _),
877 [73] = PINGROUP(73, _, _, _, pll_bist_sync, _, _, _, _, _),
878 [74] = PINGROUP(74, _, _, _, _, _, _, _, _, _),
879 [75] = PINGROUP(75, _, _, _, vsense_trigger_mirnat, atest_usb0, _, _, _, _),
880 [76] = PINGROUP(76, _, _, _, _, _, _, _, _, _),
881 [77] = PINGROUP(77, _, _, _, _, _, _, _, _, _),
882 [78] = PINGROUP(78, _, _, _, atest_usb0, _, _, _, _, _),
883 [79] = PINGROUP(79, _, _, _, wlan1_adc_dtest0, atest_usb0, _, _, _, _),
884 [80] = PINGROUP(80, _, _, dbg_out_clk, wlan1_adc_dtest1, atest_usb0, _, _, _, _),
885 [81] = PINGROUP(81, _, nav, _, _, _, _, _, _, _),
886 [82] = PINGROUP(82, _, _, phase_flag, _, _, _, _, _, _),
887 [83] = PINGROUP(83, nav, _, _, _, _, _, _, _, _),
888 [84] = PINGROUP(84, nav, vfr_1, _, _, _, _, _, _, _),
889 [85] = PINGROUP(85, _, _, _, _, _, _, _, _, _),
890 [86] = PINGROUP(86, _, _, _, _, _, _, _, _, _),
891 [87] = PINGROUP(87, qlink0_request, _, _, _, _, _, _, _, _),
892 [88] = PINGROUP(88, qlink0_enable, _, _, _, _, _, _, _, _),
893 [89] = PINGROUP(89, qlink0_wmss_reset, _, _, _, _, _, _, _, _),
894 [90] = PINGROUP(90, qup1_se4, jitter_bist_ref, ddr_pxi0_test, _, _, _, _, _, _),
895 [91] = PINGROUP(91, qup1_se4, _, phase_flag, _, _, _, _, _, _),
896 [92] = PINGROUP(92, _, _, _, _, _, _, _, _, _),
897 [93] = PINGROUP(93, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, _, _, _, _, _, _),
898 [94] = PINGROUP(94, usb0_phy_ps, _, _, _, _, _, _, _, _),
899 [95] = PINGROUP(95, _, phase_flag, atest_char, _, _, _, _, _, _),
900 [96] = PINGROUP(96, _, _, _, _, _, _, _, _, _),
901 [97] = PINGROUP(97, mdp_vsync, _, phase_flag, atest_char, _, _, _, _, _),
902 [98] = PINGROUP(98, _, phase_flag, atest_char, _, _, _, _, _, _),
903 [99] = PINGROUP(99, usb0_hs_ac, _, phase_flag, atest_char, _, _, _, _, _),
904 [100] = PINGROUP(100, vfr_0_mirb, _, phase_flag, atest_char, _, _, _, _, _),
905 [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _),
906 [102] = PINGROUP(102, sd_write_protect, _, _, _, _, _, _, _, _),
907 [103] = PINGROUP(103, _, _, _, _, _, _, _, _, _),
908 [104] = PINGROUP(104, _, _, _, _, _, _, _, _, _),
909 [105] = PINGROUP(105, _, phase_flag, _, _, _, _, _, _, _),
910 [106] = PINGROUP(106, host2wlan_sol, _, _, _, _, _, _, _, _),
911 [107] = PINGROUP(107, pcie0_clk_req, _, _, _, _, _, _, _, _),
912 [108] = PINGROUP(108, pll_clk_aux, _, _, _, _, _, _, _, _),
913 [109] = PINGROUP(109, _, _, _, _, _, _, _, _, _),
914 [110] = PINGROUP(110, _, _, _, _, _, _, _, _, _),
915 [111] = PINGROUP(111, _, _, _, _, _, _, _, _, _),
916 [112] = PINGROUP(112, _, _, _, _, _, _, _, _, _),
917 [113] = PINGROUP(113, qdss_cti_trig0, _, _, _, _, _, _, _, _),
918 [114] = PINGROUP(114, qdss_cti_trig0, _, _, _, _, _, _, _, _),
919 [115] = PINGROUP(115, _, phase_flag, _, _, _, _, _, _, _),
920 [116] = PINGROUP(116, _, phase_flag, _, _, _, _, _, _, _),
921 [117] = PINGROUP(117, _, phase_flag, _, _, _, _, _, _, _),
922 [118] = PINGROUP(118, qdss_gpio, _, ddr_pxi1_test, _, _, _, _, _, _),
923 [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _),
924 [120] = PINGROUP(120, _, _, _, _, _, _, _, _, _),
925 [121] = PINGROUP(121, qdss_gpio, _, _, _, _, _, _, _, _),
926 [122] = PINGROUP(122, qdss_gpio, _, ddr_pxi1_test, _, _, _, _, _, _),
927 [123] = PINGROUP(123, _, _, _, _, _, _, _, _, _),
928 [124] = PINGROUP(124, _, _, _, _, _, _, _, _, _),
929 [125] = PINGROUP(125, _, _, _, _, _, _, _, _, _),
930 [126] = PINGROUP(126, qdss_gpio, _, _, _, _, _, _, _, _),
931 [127] = PINGROUP(127, qdss_gpio, ddr_pxi0_test, _, _, _, _, _, _, _),
932 [128] = PINGROUP(128, tb_trig_sdc1, _, _, _, _, _, _, _, _),
933 [129] = PINGROUP(129, _, _, _, _, _, _, _, _, _),
934 [130] = PINGROUP(130, _, _, _, _, _, _, _, _, _),
935 [131] = PINGROUP(131, _, _, _, _, _, _, _, _, _),
936 [132] = PINGROUP(132, _, _, _, _, _, _, _, _, _),
937 [133] = PINGROUP(133, _, phase_flag, _, _, _, _, _, _, _),
938 [134] = PINGROUP(134, tsense_pwm1_out, tsense_pwm2_out, _, _, _, _, _, _, _),
939 [135] = PINGROUP(135, _, phase_flag, _, _, _, _, _, _, _),
940 [136] = UFS_RESET(ufs_reset, 0x97000),
941 [137] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x8c004, 0, 0),
942 [138] = SDC_QDSD_PINGROUP(sdc1_clk, 0x8c000, 13, 6),
943 [139] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x8c000, 11, 3),
944 [140] = SDC_QDSD_PINGROUP(sdc1_data, 0x8c000, 9, 0),
945 [141] = SDC_QDSD_PINGROUP(sdc2_clk, 0x8f000, 14, 6),
946 [142] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x8f000, 11, 3),
947 [143] = SDC_QDSD_PINGROUP(sdc2_data, 0x8f000, 9, 0),
948};
949
950static const struct msm_gpio_wakeirq_map sm4450_pdc_map[] = {
951 { 0, 67 }, { 3, 82 }, { 4, 69 }, { 5, 70 }, { 6, 44 }, { 7, 43 },
952 { 8, 71 }, { 9, 86 }, { 10, 48 }, { 11, 77 }, { 12, 90 },
953 { 13, 54 }, { 14, 91 }, { 17, 97 }, { 18, 102 }, { 21, 103 },
954 { 22, 104 }, { 23, 105 }, { 24, 53 }, { 25, 106 }, { 26, 65 },
955 { 27, 55 }, { 28, 89 }, { 30, 80 }, { 31, 109 }, { 33, 87 },
956 { 34, 81 }, { 35, 75 }, { 40, 88 }, { 41, 98 }, { 42, 110 },
957 { 43, 95 }, { 47, 118 }, { 50, 111 }, { 52, 52 }, { 53, 114 },
958 { 54, 115 }, { 55, 99 }, { 56, 45 }, { 57, 85 }, { 58, 56 },
959 { 59, 84 }, { 60, 83 }, { 61, 96 }, { 62, 93 }, { 66, 116 },
960 { 67, 113 }, { 70, 42 }, { 71, 122 }, { 73, 119 }, { 75, 121 },
961 { 77, 120 }, { 79, 123 }, { 81, 124 }, { 83, 64 }, { 84, 128 },
962 { 86, 129 }, { 87, 63 }, { 91, 92 }, { 92, 66 }, { 93, 125 },
963 { 94, 76 }, { 95, 62 }, { 96, 132 }, { 97, 135 }, { 98, 73 },
964 { 99, 133 }, { 101, 46 }, { 102, 134 }, { 103, 49 }, { 105, 58 },
965 { 107, 94 }, { 110, 59 }, { 113, 57 }, { 114, 60 }, { 118, 107 },
966 { 120, 61 }, { 121, 108 }, { 123, 68 }, { 125, 72 }, { 128, 112 },
967};
968
969static const struct msm_pinctrl_soc_data sm4450_tlmm = {
970 .pins = sm4450_pins,
971 .npins = ARRAY_SIZE(sm4450_pins),
972 .functions = sm4450_functions,
973 .nfunctions = ARRAY_SIZE(sm4450_functions),
974 .groups = sm4450_groups,
975 .ngroups = ARRAY_SIZE(sm4450_groups),
976 .ngpios = 137,
977 .wakeirq_map = sm4450_pdc_map,
978 .nwakeirq_map = ARRAY_SIZE(sm4450_pdc_map),
979};
980
981static int sm4450_tlmm_probe(struct platform_device *pdev)
982{
983 return msm_pinctrl_probe(pdev, soc_data: &sm4450_tlmm);
984}
985
986static const struct of_device_id sm4450_tlmm_of_match[] = {
987 { .compatible = "qcom,sm4450-tlmm", },
988 { }
989};
990
991static struct platform_driver sm4450_tlmm_driver = {
992 .driver = {
993 .name = "sm4450-tlmm",
994 .of_match_table = sm4450_tlmm_of_match,
995 },
996 .probe = sm4450_tlmm_probe,
997};
998MODULE_DEVICE_TABLE(of, sm4450_tlmm_of_match);
999
1000static int __init sm4450_tlmm_init(void)
1001{
1002 return platform_driver_register(&sm4450_tlmm_driver);
1003}
1004arch_initcall(sm4450_tlmm_init);
1005
1006static void __exit sm4450_tlmm_exit(void)
1007{
1008 platform_driver_unregister(&sm4450_tlmm_driver);
1009}
1010module_exit(sm4450_tlmm_exit);
1011
1012MODULE_DESCRIPTION("QTI SM4450 TLMM driver");
1013MODULE_LICENSE("GPL");
1014

source code of linux/drivers/pinctrl/qcom/pinctrl-sm4450.c