1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2019, The Linux Foundation. All rights reserved. |
4 | */ |
5 | |
6 | #include <linux/module.h> |
7 | #include <linux/of.h> |
8 | #include <linux/platform_device.h> |
9 | |
10 | #include "pinctrl-msm.h" |
11 | |
12 | static const char * const sm6115_tiles[] = { |
13 | "south" , |
14 | "east" , |
15 | "west" |
16 | }; |
17 | |
18 | enum { |
19 | SOUTH, |
20 | EAST, |
21 | WEST |
22 | }; |
23 | |
24 | #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ |
25 | { \ |
26 | .grp = PINCTRL_PINGROUP("gpio" #id, \ |
27 | gpio##id##_pins, \ |
28 | ARRAY_SIZE(gpio##id##_pins)), \ |
29 | .funcs = (int[]){ \ |
30 | msm_mux_gpio, /* gpio mode */ \ |
31 | msm_mux_##f1, \ |
32 | msm_mux_##f2, \ |
33 | msm_mux_##f3, \ |
34 | msm_mux_##f4, \ |
35 | msm_mux_##f5, \ |
36 | msm_mux_##f6, \ |
37 | msm_mux_##f7, \ |
38 | msm_mux_##f8, \ |
39 | msm_mux_##f9 \ |
40 | }, \ |
41 | .nfuncs = 10, \ |
42 | .ctl_reg = 0x1000 * id, \ |
43 | .io_reg = 0x4 + 0x1000 * id, \ |
44 | .intr_cfg_reg = 0x8 + 0x1000 * id, \ |
45 | .intr_status_reg = 0xc + 0x1000 * id, \ |
46 | .intr_target_reg = 0x8 + 0x1000 * id, \ |
47 | .tile = _tile, \ |
48 | .mux_bit = 2, \ |
49 | .pull_bit = 0, \ |
50 | .drv_bit = 6, \ |
51 | .oe_bit = 9, \ |
52 | .in_bit = 0, \ |
53 | .out_bit = 1, \ |
54 | .intr_enable_bit = 0, \ |
55 | .intr_status_bit = 0, \ |
56 | .intr_target_bit = 5, \ |
57 | .intr_target_kpss_val = 3, \ |
58 | .intr_raw_status_bit = 4, \ |
59 | .intr_polarity_bit = 1, \ |
60 | .intr_detection_bit = 2, \ |
61 | .intr_detection_width = 2, \ |
62 | } |
63 | |
64 | #define SDC_QDSD_PINGROUP(pg_name, _tile, ctl, pull, drv) \ |
65 | { \ |
66 | .grp = PINCTRL_PINGROUP(#pg_name, \ |
67 | pg_name##_pins, \ |
68 | ARRAY_SIZE(pg_name##_pins)), \ |
69 | .ctl_reg = ctl, \ |
70 | .io_reg = 0, \ |
71 | .intr_cfg_reg = 0, \ |
72 | .intr_status_reg = 0, \ |
73 | .intr_target_reg = 0, \ |
74 | .tile = _tile, \ |
75 | .mux_bit = -1, \ |
76 | .pull_bit = pull, \ |
77 | .drv_bit = drv, \ |
78 | .oe_bit = -1, \ |
79 | .in_bit = -1, \ |
80 | .out_bit = -1, \ |
81 | .intr_enable_bit = -1, \ |
82 | .intr_status_bit = -1, \ |
83 | .intr_target_bit = -1, \ |
84 | .intr_raw_status_bit = -1, \ |
85 | .intr_polarity_bit = -1, \ |
86 | .intr_detection_bit = -1, \ |
87 | .intr_detection_width = -1, \ |
88 | } |
89 | |
90 | #define UFS_RESET(pg_name, offset) \ |
91 | { \ |
92 | .grp = PINCTRL_PINGROUP(#pg_name, \ |
93 | pg_name##_pins, \ |
94 | ARRAY_SIZE(pg_name##_pins)), \ |
95 | .ctl_reg = offset, \ |
96 | .io_reg = offset + 0x4, \ |
97 | .intr_cfg_reg = 0, \ |
98 | .intr_status_reg = 0, \ |
99 | .intr_target_reg = 0, \ |
100 | .tile = WEST, \ |
101 | .mux_bit = -1, \ |
102 | .pull_bit = 3, \ |
103 | .drv_bit = 0, \ |
104 | .oe_bit = -1, \ |
105 | .in_bit = -1, \ |
106 | .out_bit = 0, \ |
107 | .intr_enable_bit = -1, \ |
108 | .intr_status_bit = -1, \ |
109 | .intr_target_bit = -1, \ |
110 | .intr_raw_status_bit = -1, \ |
111 | .intr_polarity_bit = -1, \ |
112 | .intr_detection_bit = -1, \ |
113 | .intr_detection_width = -1, \ |
114 | } |
115 | static const struct pinctrl_pin_desc sm6115_pins[] = { |
116 | PINCTRL_PIN(0, "GPIO_0" ), |
117 | PINCTRL_PIN(1, "GPIO_1" ), |
118 | PINCTRL_PIN(2, "GPIO_2" ), |
119 | PINCTRL_PIN(3, "GPIO_3" ), |
120 | PINCTRL_PIN(4, "GPIO_4" ), |
121 | PINCTRL_PIN(5, "GPIO_5" ), |
122 | PINCTRL_PIN(6, "GPIO_6" ), |
123 | PINCTRL_PIN(7, "GPIO_7" ), |
124 | PINCTRL_PIN(8, "GPIO_8" ), |
125 | PINCTRL_PIN(9, "GPIO_9" ), |
126 | PINCTRL_PIN(10, "GPIO_10" ), |
127 | PINCTRL_PIN(11, "GPIO_11" ), |
128 | PINCTRL_PIN(12, "GPIO_12" ), |
129 | PINCTRL_PIN(13, "GPIO_13" ), |
130 | PINCTRL_PIN(14, "GPIO_14" ), |
131 | PINCTRL_PIN(15, "GPIO_15" ), |
132 | PINCTRL_PIN(16, "GPIO_16" ), |
133 | PINCTRL_PIN(17, "GPIO_17" ), |
134 | PINCTRL_PIN(18, "GPIO_18" ), |
135 | PINCTRL_PIN(19, "GPIO_19" ), |
136 | PINCTRL_PIN(20, "GPIO_20" ), |
137 | PINCTRL_PIN(21, "GPIO_21" ), |
138 | PINCTRL_PIN(22, "GPIO_22" ), |
139 | PINCTRL_PIN(23, "GPIO_23" ), |
140 | PINCTRL_PIN(24, "GPIO_24" ), |
141 | PINCTRL_PIN(25, "GPIO_25" ), |
142 | PINCTRL_PIN(26, "GPIO_26" ), |
143 | PINCTRL_PIN(27, "GPIO_27" ), |
144 | PINCTRL_PIN(28, "GPIO_28" ), |
145 | PINCTRL_PIN(29, "GPIO_29" ), |
146 | PINCTRL_PIN(30, "GPIO_30" ), |
147 | PINCTRL_PIN(31, "GPIO_31" ), |
148 | PINCTRL_PIN(32, "GPIO_32" ), |
149 | PINCTRL_PIN(33, "GPIO_33" ), |
150 | PINCTRL_PIN(34, "GPIO_34" ), |
151 | PINCTRL_PIN(35, "GPIO_35" ), |
152 | PINCTRL_PIN(36, "GPIO_36" ), |
153 | PINCTRL_PIN(37, "GPIO_37" ), |
154 | PINCTRL_PIN(38, "GPIO_38" ), |
155 | PINCTRL_PIN(39, "GPIO_39" ), |
156 | PINCTRL_PIN(40, "GPIO_40" ), |
157 | PINCTRL_PIN(41, "GPIO_41" ), |
158 | PINCTRL_PIN(42, "GPIO_42" ), |
159 | PINCTRL_PIN(43, "GPIO_43" ), |
160 | PINCTRL_PIN(44, "GPIO_44" ), |
161 | PINCTRL_PIN(45, "GPIO_45" ), |
162 | PINCTRL_PIN(46, "GPIO_46" ), |
163 | PINCTRL_PIN(47, "GPIO_47" ), |
164 | PINCTRL_PIN(48, "GPIO_48" ), |
165 | PINCTRL_PIN(49, "GPIO_49" ), |
166 | PINCTRL_PIN(50, "GPIO_50" ), |
167 | PINCTRL_PIN(51, "GPIO_51" ), |
168 | PINCTRL_PIN(52, "GPIO_52" ), |
169 | PINCTRL_PIN(53, "GPIO_53" ), |
170 | PINCTRL_PIN(54, "GPIO_54" ), |
171 | PINCTRL_PIN(55, "GPIO_55" ), |
172 | PINCTRL_PIN(56, "GPIO_56" ), |
173 | PINCTRL_PIN(57, "GPIO_57" ), |
174 | PINCTRL_PIN(58, "GPIO_58" ), |
175 | PINCTRL_PIN(59, "GPIO_59" ), |
176 | PINCTRL_PIN(60, "GPIO_60" ), |
177 | PINCTRL_PIN(61, "GPIO_61" ), |
178 | PINCTRL_PIN(62, "GPIO_62" ), |
179 | PINCTRL_PIN(63, "GPIO_63" ), |
180 | PINCTRL_PIN(64, "GPIO_64" ), |
181 | PINCTRL_PIN(65, "GPIO_65" ), |
182 | PINCTRL_PIN(66, "GPIO_66" ), |
183 | PINCTRL_PIN(67, "GPIO_67" ), |
184 | PINCTRL_PIN(68, "GPIO_68" ), |
185 | PINCTRL_PIN(69, "GPIO_69" ), |
186 | PINCTRL_PIN(70, "GPIO_70" ), |
187 | PINCTRL_PIN(71, "GPIO_71" ), |
188 | PINCTRL_PIN(72, "GPIO_72" ), |
189 | PINCTRL_PIN(73, "GPIO_73" ), |
190 | PINCTRL_PIN(74, "GPIO_74" ), |
191 | PINCTRL_PIN(75, "GPIO_75" ), |
192 | PINCTRL_PIN(76, "GPIO_76" ), |
193 | PINCTRL_PIN(77, "GPIO_77" ), |
194 | PINCTRL_PIN(78, "GPIO_78" ), |
195 | PINCTRL_PIN(79, "GPIO_79" ), |
196 | PINCTRL_PIN(80, "GPIO_80" ), |
197 | PINCTRL_PIN(81, "GPIO_81" ), |
198 | PINCTRL_PIN(82, "GPIO_82" ), |
199 | PINCTRL_PIN(83, "GPIO_83" ), |
200 | PINCTRL_PIN(84, "GPIO_84" ), |
201 | PINCTRL_PIN(85, "GPIO_85" ), |
202 | PINCTRL_PIN(86, "GPIO_86" ), |
203 | PINCTRL_PIN(87, "GPIO_87" ), |
204 | PINCTRL_PIN(88, "GPIO_88" ), |
205 | PINCTRL_PIN(89, "GPIO_89" ), |
206 | PINCTRL_PIN(90, "GPIO_90" ), |
207 | PINCTRL_PIN(91, "GPIO_91" ), |
208 | PINCTRL_PIN(92, "GPIO_92" ), |
209 | PINCTRL_PIN(93, "GPIO_93" ), |
210 | PINCTRL_PIN(94, "GPIO_94" ), |
211 | PINCTRL_PIN(95, "GPIO_95" ), |
212 | PINCTRL_PIN(96, "GPIO_96" ), |
213 | PINCTRL_PIN(97, "GPIO_97" ), |
214 | PINCTRL_PIN(98, "GPIO_98" ), |
215 | PINCTRL_PIN(99, "GPIO_99" ), |
216 | PINCTRL_PIN(100, "GPIO_100" ), |
217 | PINCTRL_PIN(101, "GPIO_101" ), |
218 | PINCTRL_PIN(102, "GPIO_102" ), |
219 | PINCTRL_PIN(103, "GPIO_103" ), |
220 | PINCTRL_PIN(104, "GPIO_104" ), |
221 | PINCTRL_PIN(105, "GPIO_105" ), |
222 | PINCTRL_PIN(106, "GPIO_106" ), |
223 | PINCTRL_PIN(107, "GPIO_107" ), |
224 | PINCTRL_PIN(108, "GPIO_108" ), |
225 | PINCTRL_PIN(109, "GPIO_109" ), |
226 | PINCTRL_PIN(110, "GPIO_110" ), |
227 | PINCTRL_PIN(111, "GPIO_111" ), |
228 | PINCTRL_PIN(112, "GPIO_112" ), |
229 | PINCTRL_PIN(113, "UFS_RESET" ), |
230 | PINCTRL_PIN(114, "SDC1_RCLK" ), |
231 | PINCTRL_PIN(115, "SDC1_CLK" ), |
232 | PINCTRL_PIN(116, "SDC1_CMD" ), |
233 | PINCTRL_PIN(117, "SDC1_DATA" ), |
234 | PINCTRL_PIN(118, "SDC2_CLK" ), |
235 | PINCTRL_PIN(119, "SDC2_CMD" ), |
236 | PINCTRL_PIN(120, "SDC2_DATA" ), |
237 | }; |
238 | |
239 | #define DECLARE_MSM_GPIO_PINS(pin) \ |
240 | static const unsigned int gpio##pin##_pins[] = { pin } |
241 | DECLARE_MSM_GPIO_PINS(0); |
242 | DECLARE_MSM_GPIO_PINS(1); |
243 | DECLARE_MSM_GPIO_PINS(2); |
244 | DECLARE_MSM_GPIO_PINS(3); |
245 | DECLARE_MSM_GPIO_PINS(4); |
246 | DECLARE_MSM_GPIO_PINS(5); |
247 | DECLARE_MSM_GPIO_PINS(6); |
248 | DECLARE_MSM_GPIO_PINS(7); |
249 | DECLARE_MSM_GPIO_PINS(8); |
250 | DECLARE_MSM_GPIO_PINS(9); |
251 | DECLARE_MSM_GPIO_PINS(10); |
252 | DECLARE_MSM_GPIO_PINS(11); |
253 | DECLARE_MSM_GPIO_PINS(12); |
254 | DECLARE_MSM_GPIO_PINS(13); |
255 | DECLARE_MSM_GPIO_PINS(14); |
256 | DECLARE_MSM_GPIO_PINS(15); |
257 | DECLARE_MSM_GPIO_PINS(16); |
258 | DECLARE_MSM_GPIO_PINS(17); |
259 | DECLARE_MSM_GPIO_PINS(18); |
260 | DECLARE_MSM_GPIO_PINS(19); |
261 | DECLARE_MSM_GPIO_PINS(20); |
262 | DECLARE_MSM_GPIO_PINS(21); |
263 | DECLARE_MSM_GPIO_PINS(22); |
264 | DECLARE_MSM_GPIO_PINS(23); |
265 | DECLARE_MSM_GPIO_PINS(24); |
266 | DECLARE_MSM_GPIO_PINS(25); |
267 | DECLARE_MSM_GPIO_PINS(26); |
268 | DECLARE_MSM_GPIO_PINS(27); |
269 | DECLARE_MSM_GPIO_PINS(28); |
270 | DECLARE_MSM_GPIO_PINS(29); |
271 | DECLARE_MSM_GPIO_PINS(30); |
272 | DECLARE_MSM_GPIO_PINS(31); |
273 | DECLARE_MSM_GPIO_PINS(32); |
274 | DECLARE_MSM_GPIO_PINS(33); |
275 | DECLARE_MSM_GPIO_PINS(34); |
276 | DECLARE_MSM_GPIO_PINS(35); |
277 | DECLARE_MSM_GPIO_PINS(36); |
278 | DECLARE_MSM_GPIO_PINS(37); |
279 | DECLARE_MSM_GPIO_PINS(38); |
280 | DECLARE_MSM_GPIO_PINS(39); |
281 | DECLARE_MSM_GPIO_PINS(40); |
282 | DECLARE_MSM_GPIO_PINS(41); |
283 | DECLARE_MSM_GPIO_PINS(42); |
284 | DECLARE_MSM_GPIO_PINS(43); |
285 | DECLARE_MSM_GPIO_PINS(44); |
286 | DECLARE_MSM_GPIO_PINS(45); |
287 | DECLARE_MSM_GPIO_PINS(46); |
288 | DECLARE_MSM_GPIO_PINS(47); |
289 | DECLARE_MSM_GPIO_PINS(48); |
290 | DECLARE_MSM_GPIO_PINS(49); |
291 | DECLARE_MSM_GPIO_PINS(50); |
292 | DECLARE_MSM_GPIO_PINS(51); |
293 | DECLARE_MSM_GPIO_PINS(52); |
294 | DECLARE_MSM_GPIO_PINS(53); |
295 | DECLARE_MSM_GPIO_PINS(54); |
296 | DECLARE_MSM_GPIO_PINS(55); |
297 | DECLARE_MSM_GPIO_PINS(56); |
298 | DECLARE_MSM_GPIO_PINS(57); |
299 | DECLARE_MSM_GPIO_PINS(58); |
300 | DECLARE_MSM_GPIO_PINS(59); |
301 | DECLARE_MSM_GPIO_PINS(60); |
302 | DECLARE_MSM_GPIO_PINS(61); |
303 | DECLARE_MSM_GPIO_PINS(62); |
304 | DECLARE_MSM_GPIO_PINS(63); |
305 | DECLARE_MSM_GPIO_PINS(64); |
306 | DECLARE_MSM_GPIO_PINS(65); |
307 | DECLARE_MSM_GPIO_PINS(66); |
308 | DECLARE_MSM_GPIO_PINS(67); |
309 | DECLARE_MSM_GPIO_PINS(68); |
310 | DECLARE_MSM_GPIO_PINS(69); |
311 | DECLARE_MSM_GPIO_PINS(70); |
312 | DECLARE_MSM_GPIO_PINS(71); |
313 | DECLARE_MSM_GPIO_PINS(72); |
314 | DECLARE_MSM_GPIO_PINS(73); |
315 | DECLARE_MSM_GPIO_PINS(74); |
316 | DECLARE_MSM_GPIO_PINS(75); |
317 | DECLARE_MSM_GPIO_PINS(76); |
318 | DECLARE_MSM_GPIO_PINS(77); |
319 | DECLARE_MSM_GPIO_PINS(78); |
320 | DECLARE_MSM_GPIO_PINS(79); |
321 | DECLARE_MSM_GPIO_PINS(80); |
322 | DECLARE_MSM_GPIO_PINS(81); |
323 | DECLARE_MSM_GPIO_PINS(82); |
324 | DECLARE_MSM_GPIO_PINS(83); |
325 | DECLARE_MSM_GPIO_PINS(84); |
326 | DECLARE_MSM_GPIO_PINS(85); |
327 | DECLARE_MSM_GPIO_PINS(86); |
328 | DECLARE_MSM_GPIO_PINS(87); |
329 | DECLARE_MSM_GPIO_PINS(88); |
330 | DECLARE_MSM_GPIO_PINS(89); |
331 | DECLARE_MSM_GPIO_PINS(90); |
332 | DECLARE_MSM_GPIO_PINS(91); |
333 | DECLARE_MSM_GPIO_PINS(92); |
334 | DECLARE_MSM_GPIO_PINS(93); |
335 | DECLARE_MSM_GPIO_PINS(94); |
336 | DECLARE_MSM_GPIO_PINS(95); |
337 | DECLARE_MSM_GPIO_PINS(96); |
338 | DECLARE_MSM_GPIO_PINS(97); |
339 | DECLARE_MSM_GPIO_PINS(98); |
340 | DECLARE_MSM_GPIO_PINS(99); |
341 | DECLARE_MSM_GPIO_PINS(100); |
342 | DECLARE_MSM_GPIO_PINS(101); |
343 | DECLARE_MSM_GPIO_PINS(102); |
344 | DECLARE_MSM_GPIO_PINS(103); |
345 | DECLARE_MSM_GPIO_PINS(104); |
346 | DECLARE_MSM_GPIO_PINS(105); |
347 | DECLARE_MSM_GPIO_PINS(106); |
348 | DECLARE_MSM_GPIO_PINS(107); |
349 | DECLARE_MSM_GPIO_PINS(108); |
350 | DECLARE_MSM_GPIO_PINS(109); |
351 | DECLARE_MSM_GPIO_PINS(110); |
352 | DECLARE_MSM_GPIO_PINS(111); |
353 | DECLARE_MSM_GPIO_PINS(112); |
354 | |
355 | static const unsigned int ufs_reset_pins[] = { 113 }; |
356 | static const unsigned int sdc1_rclk_pins[] = { 114 }; |
357 | static const unsigned int sdc1_clk_pins[] = { 115 }; |
358 | static const unsigned int sdc1_cmd_pins[] = { 116 }; |
359 | static const unsigned int sdc1_data_pins[] = { 117 }; |
360 | static const unsigned int sdc2_clk_pins[] = { 118 }; |
361 | static const unsigned int sdc2_cmd_pins[] = { 119 }; |
362 | static const unsigned int sdc2_data_pins[] = { 120 }; |
363 | |
364 | enum sm6115_functions { |
365 | msm_mux_adsp_ext, |
366 | msm_mux_agera_pll, |
367 | msm_mux_atest, |
368 | msm_mux_cam_mclk, |
369 | msm_mux_cci_async, |
370 | msm_mux_cci_i2c, |
371 | msm_mux_cci_timer, |
372 | msm_mux_cri_trng, |
373 | msm_mux_dac_calib, |
374 | msm_mux_dbg_out, |
375 | msm_mux_ddr_bist, |
376 | msm_mux_ddr_pxi0, |
377 | msm_mux_ddr_pxi1, |
378 | msm_mux_ddr_pxi2, |
379 | msm_mux_ddr_pxi3, |
380 | msm_mux_gcc_gp1, |
381 | msm_mux_gcc_gp2, |
382 | msm_mux_gcc_gp3, |
383 | msm_mux_gpio, |
384 | msm_mux_gp_pdm0, |
385 | msm_mux_gp_pdm1, |
386 | msm_mux_gp_pdm2, |
387 | msm_mux_gsm0_tx, |
388 | msm_mux_gsm1_tx, |
389 | msm_mux_jitter_bist, |
390 | msm_mux_mdp_vsync, |
391 | msm_mux_mdp_vsync_out_0, |
392 | msm_mux_mdp_vsync_out_1, |
393 | msm_mux_mpm_pwr, |
394 | msm_mux_mss_lte, |
395 | msm_mux_m_voc, |
396 | msm_mux_nav_gpio, |
397 | msm_mux_pa_indicator, |
398 | msm_mux_pbs, |
399 | msm_mux_pbs_out, |
400 | msm_mux_phase_flag, |
401 | msm_mux_pll_bist, |
402 | msm_mux_pll_bypassnl, |
403 | msm_mux_pll_reset, |
404 | msm_mux_prng_rosc, |
405 | msm_mux_qdss_cti, |
406 | msm_mux_qdss_gpio, |
407 | msm_mux_qup0, |
408 | msm_mux_qup1, |
409 | msm_mux_qup2, |
410 | msm_mux_qup3, |
411 | msm_mux_qup4, |
412 | msm_mux_qup5, |
413 | msm_mux_sdc1_tb, |
414 | msm_mux_sdc2_tb, |
415 | msm_mux_sd_write, |
416 | msm_mux_ssbi_wtr1, |
417 | msm_mux_tgu, |
418 | msm_mux_tsense_pwm, |
419 | msm_mux_uim1_clk, |
420 | msm_mux_uim1_data, |
421 | msm_mux_uim1_present, |
422 | msm_mux_uim1_reset, |
423 | msm_mux_uim2_clk, |
424 | msm_mux_uim2_data, |
425 | msm_mux_uim2_present, |
426 | msm_mux_uim2_reset, |
427 | msm_mux_usb_phy, |
428 | msm_mux_vfr_1, |
429 | msm_mux_vsense_trigger, |
430 | msm_mux_wlan1_adc0, |
431 | msm_mux_wlan1_adc1, |
432 | msm_mux__, |
433 | }; |
434 | |
435 | static const char * const qup0_groups[] = { |
436 | "gpio0" , "gpio1" , "gpio2" , "gpio3" , "gpio82" , "gpio86" , |
437 | }; |
438 | static const char * const gpio_groups[] = { |
439 | "gpio0" , "gpio1" , "gpio2" , "gpio3" , "gpio4" , "gpio5" , "gpio6" , "gpio7" , |
440 | "gpio8" , "gpio9" , "gpio10" , "gpio11" , "gpio12" , "gpio13" , "gpio14" , |
441 | "gpio15" , "gpio16" , "gpio17" , "gpio18" , "gpio19" , "gpio20" , "gpio21" , |
442 | "gpio22" , "gpio23" , "gpio24" , "gpio25" , "gpio26" , "gpio27" , "gpio28" , |
443 | "gpio29" , "gpio30" , "gpio31" , "gpio32" , "gpio33" , "gpio34" , "gpio35" , |
444 | "gpio36" , "gpio37" , "gpio38" , "gpio39" , "gpio40" , "gpio41" , "gpio42" , |
445 | "gpio43" , "gpio44" , "gpio45" , "gpio46" , "gpio47" , "gpio48" , "gpio49" , |
446 | "gpio50" , "gpio51" , "gpio52" , "gpio53" , "gpio54" , "gpio55" , "gpio56" , |
447 | "gpio57" , "gpio58" , "gpio59" , "gpio60" , "gpio61" , "gpio62" , "gpio63" , |
448 | "gpio64" , "gpio65" , "gpio66" , "gpio67" , "gpio68" , "gpio69" , "gpio70" , |
449 | "gpio71" , "gpio72" , "gpio73" , "gpio74" , "gpio75" , "gpio76" , "gpio77" , |
450 | "gpio78" , "gpio79" , "gpio80" , "gpio81" , "gpio82" , "gpio83" , "gpio84" , |
451 | "gpio85" , "gpio86" , "gpio87" , "gpio88" , "gpio89" , "gpio90" , "gpio91" , |
452 | "gpio92" , "gpio93" , "gpio94" , "gpio95" , "gpio96" , "gpio97" , "gpio98" , |
453 | "gpio99" , "gpio100" , "gpio101" , "gpio102" , "gpio103" , "gpio104" , |
454 | "gpio105" , "gpio106" , "gpio107" , "gpio108" , "gpio109" , "gpio110" , |
455 | "gpio111" , "gpio112" , |
456 | }; |
457 | static const char * const ddr_bist_groups[] = { |
458 | "gpio0" , "gpio1" , "gpio2" , "gpio3" , |
459 | }; |
460 | static const char * const phase_flag_groups[] = { |
461 | "gpio0" , "gpio1" , "gpio2" , "gpio3" , "gpio4" , "gpio5" , "gpio6" , |
462 | "gpio14" , "gpio15" , "gpio16" , "gpio17" , "gpio22" , "gpio23" , "gpio24" , |
463 | "gpio25" , "gpio26" , "gpio29" , "gpio30" , "gpio31" , "gpio32" , "gpio33" , |
464 | "gpio35" , "gpio36" , "gpio43" , "gpio44" , "gpio45" , "gpio63" , "gpio64" , |
465 | "gpio102" , "gpio103" , "gpio104" , "gpio105" , |
466 | }; |
467 | static const char * const qdss_gpio_groups[] = { |
468 | "gpio0" , "gpio1" , "gpio2" , "gpio3" , "gpio8" , "gpio9" , "gpio10" , |
469 | "gpio11" , "gpio14" , "gpio15" , "gpio16" , "gpio17" , "gpio18" , "gpio19" , |
470 | "gpio20" , "gpio21" , "gpio22" , "gpio23" , "gpio24" , "gpio25" , "gpio26" , |
471 | "gpio47" , "gpio48" , "gpio69" , "gpio70" , "gpio87" , "gpio90" , "gpio91" , |
472 | "gpio94" , "gpio95" , "gpio104" , "gpio105" , "gpio106" , "gpio107" , |
473 | "gpio109" , "gpio110" , |
474 | }; |
475 | static const char * const atest_groups[] = { |
476 | "gpio0" , "gpio1" , "gpio2" , "gpio3" , "gpio4" , "gpio5" , "gpio6" , |
477 | "gpio22" , "gpio23" , "gpio24" , "gpio25" , "gpio26" , "gpio29" , "gpio30" , |
478 | "gpio31" , "gpio32" , "gpio33" , "gpio86" , "gpio87" , "gpio88" , "gpio89" , |
479 | "gpio100" , "gpio101" , |
480 | }; |
481 | static const char * const mpm_pwr_groups[] = { |
482 | "gpio1" , |
483 | }; |
484 | static const char * const m_voc_groups[] = { |
485 | "gpio0" , |
486 | }; |
487 | static const char * const dac_calib_groups[] = { |
488 | "gpio2" , "gpio3" , "gpio4" , "gpio5" , "gpio6" , "gpio14" , "gpio15" , |
489 | "gpio16" , "gpio17" , "gpio22" , "gpio23" , "gpio24" , "gpio25" , "gpio26" , |
490 | "gpio29" , "gpio30" , "gpio31" , "gpio32" , "gpio33" , "gpio80" , "gpio81" , |
491 | "gpio82" , "gpio102" , "gpio103" , "gpio104" , "gpio105" |
492 | }; |
493 | static const char * const qup1_groups[] = { |
494 | "gpio4" , "gpio5" , "gpio69" , "gpio70" , |
495 | }; |
496 | static const char * const cri_trng_groups[] = { |
497 | "gpio4" , "gpio5" , "gpio18" , |
498 | }; |
499 | static const char * const qup2_groups[] = { |
500 | "gpio6" , "gpio7" , "gpio71" , "gpio80" , |
501 | }; |
502 | static const char * const qup3_groups[] = { |
503 | "gpio8" , "gpio9" , "gpio10" , "gpio11" , |
504 | }; |
505 | static const char * const pbs_out_groups[] = { |
506 | "gpio8" , "gpio9" , "gpio52" , |
507 | }; |
508 | static const char * const pll_bist_groups[] = { |
509 | "gpio8" , "gpio9" , |
510 | }; |
511 | static const char * const tsense_pwm_groups[] = { |
512 | "gpio8" , |
513 | }; |
514 | static const char * const agera_pll_groups[] = { |
515 | "gpio10" , "gpio11" , |
516 | }; |
517 | static const char * const pbs_groups[] = { |
518 | "gpio10" , "gpio11" , "gpio18" , "gpio19" , "gpio20" , "gpio21" , "gpio22" , |
519 | "gpio23" , "gpio24" , "gpio25" , "gpio26" , "gpio47" , "gpio48" , "gpio87" , |
520 | "gpio90" , "gpio91" , |
521 | }; |
522 | static const char * const qup4_groups[] = { |
523 | "gpio12" , "gpio13" , "gpio96" , "gpio97" , |
524 | }; |
525 | static const char * const tgu_groups[] = { |
526 | "gpio12" , "gpio13" , "gpio14" , "gpio15" , |
527 | }; |
528 | static const char * const qup5_groups[] = { |
529 | "gpio14" , "gpio15" , "gpio16" , "gpio17" , |
530 | }; |
531 | static const char * const sdc2_tb_groups[] = { |
532 | "gpio18" , |
533 | }; |
534 | static const char * const sdc1_tb_groups[] = { |
535 | "gpio19" , |
536 | }; |
537 | static const char * const cam_mclk_groups[] = { |
538 | "gpio20" , "gpio21" , "gpio27" , "gpio28" , |
539 | }; |
540 | static const char * const adsp_ext_groups[] = { |
541 | "gpio21" , |
542 | }; |
543 | static const char * const cci_i2c_groups[] = { |
544 | "gpio22" , "gpio23" , "gpio29" , "gpio30" , |
545 | }; |
546 | static const char * const prng_rosc_groups[] = { |
547 | "gpio22" , "gpio23" , |
548 | }; |
549 | static const char * const cci_timer_groups[] = { |
550 | "gpio24" , "gpio25" , "gpio28" , "gpio32" , |
551 | }; |
552 | static const char * const gcc_gp1_groups[] = { |
553 | "gpio24" , "gpio86" , |
554 | }; |
555 | static const char * const cci_async_groups[] = { |
556 | "gpio25" , |
557 | }; |
558 | static const char * const vsense_trigger_groups[] = { |
559 | "gpio26" , |
560 | }; |
561 | static const char * const qdss_cti_groups[] = { |
562 | "gpio27" , "gpio28" , "gpio72" , "gpio73" , "gpio96" , "gpio97" , |
563 | }; |
564 | static const char * const gp_pdm0_groups[] = { |
565 | "gpio31" , "gpio95" , |
566 | }; |
567 | static const char * const gp_pdm1_groups[] = { |
568 | "gpio32" , "gpio96" , |
569 | }; |
570 | static const char * const gp_pdm2_groups[] = { |
571 | "gpio33" , "gpio97" , |
572 | }; |
573 | static const char * const nav_gpio_groups[] = { |
574 | "gpio42" , "gpio47" , "gpio52" , "gpio95" , "gpio96" , "gpio97" , "gpio106" , |
575 | "gpio107" , "gpio108" , |
576 | }; |
577 | static const char * const vfr_1_groups[] = { |
578 | "gpio48" , |
579 | }; |
580 | static const char * const pa_indicator_groups[] = { |
581 | "gpio49" , |
582 | }; |
583 | static const char * const gsm1_tx_groups[] = { |
584 | "gpio53" , |
585 | }; |
586 | static const char * const ssbi_wtr1_groups[] = { |
587 | "gpio59" , "gpio60" , |
588 | }; |
589 | static const char * const pll_bypassnl_groups[] = { |
590 | "gpio62" , |
591 | }; |
592 | static const char * const pll_reset_groups[] = { |
593 | "gpio63" , |
594 | }; |
595 | static const char * const ddr_pxi0_groups[] = { |
596 | "gpio63" , "gpio64" , |
597 | }; |
598 | static const char * const gsm0_tx_groups[] = { |
599 | "gpio64" , |
600 | }; |
601 | static const char * const gcc_gp2_groups[] = { |
602 | "gpio69" , "gpio107" , |
603 | }; |
604 | static const char * const ddr_pxi1_groups[] = { |
605 | "gpio69" , "gpio70" , |
606 | }; |
607 | static const char * const gcc_gp3_groups[] = { |
608 | "gpio70" , "gpio106" , |
609 | }; |
610 | static const char * const dbg_out_groups[] = { |
611 | "gpio71" , |
612 | }; |
613 | static const char * const uim2_data_groups[] = { |
614 | "gpio72" , |
615 | }; |
616 | static const char * const uim2_clk_groups[] = { |
617 | "gpio73" , |
618 | }; |
619 | static const char * const uim2_reset_groups[] = { |
620 | "gpio74" , |
621 | }; |
622 | static const char * const uim2_present_groups[] = { |
623 | "gpio75" , |
624 | }; |
625 | static const char * const uim1_data_groups[] = { |
626 | "gpio76" , |
627 | }; |
628 | static const char * const uim1_clk_groups[] = { |
629 | "gpio77" , |
630 | }; |
631 | static const char * const uim1_reset_groups[] = { |
632 | "gpio78" , |
633 | }; |
634 | static const char * const uim1_present_groups[] = { |
635 | "gpio79" , |
636 | }; |
637 | static const char * const mdp_vsync_groups[] = { |
638 | "gpio81" , "gpio96" , "gpio97" , |
639 | }; |
640 | static const char * const mdp_vsync_out_0_groups[] = { |
641 | "gpio81" , |
642 | }; |
643 | static const char * const mdp_vsync_out_1_groups[] = { |
644 | "gpio81" , |
645 | }; |
646 | static const char * const usb_phy_groups[] = { |
647 | "gpio89" , |
648 | }; |
649 | static const char * const mss_lte_groups[] = { |
650 | "gpio90" , "gpio91" , |
651 | }; |
652 | static const char * const wlan1_adc0_groups[] = { |
653 | "gpio94" , |
654 | }; |
655 | static const char * const wlan1_adc1_groups[] = { |
656 | "gpio95" , |
657 | }; |
658 | static const char * const sd_write_groups[] = { |
659 | "gpio96" , |
660 | }; |
661 | static const char * const jitter_bist_groups[] = { |
662 | "gpio96" , "gpio97" , |
663 | }; |
664 | static const char * const ddr_pxi2_groups[] = { |
665 | "gpio102" , "gpio103" , |
666 | }; |
667 | static const char * const ddr_pxi3_groups[] = { |
668 | "gpio104" , "gpio105" , |
669 | }; |
670 | |
671 | static const struct pinfunction sm6115_functions[] = { |
672 | MSM_PIN_FUNCTION(adsp_ext), |
673 | MSM_PIN_FUNCTION(agera_pll), |
674 | MSM_PIN_FUNCTION(atest), |
675 | MSM_PIN_FUNCTION(cam_mclk), |
676 | MSM_PIN_FUNCTION(cci_async), |
677 | MSM_PIN_FUNCTION(cci_i2c), |
678 | MSM_PIN_FUNCTION(cci_timer), |
679 | MSM_PIN_FUNCTION(cri_trng), |
680 | MSM_PIN_FUNCTION(dac_calib), |
681 | MSM_PIN_FUNCTION(dbg_out), |
682 | MSM_PIN_FUNCTION(ddr_bist), |
683 | MSM_PIN_FUNCTION(ddr_pxi0), |
684 | MSM_PIN_FUNCTION(ddr_pxi1), |
685 | MSM_PIN_FUNCTION(ddr_pxi2), |
686 | MSM_PIN_FUNCTION(ddr_pxi3), |
687 | MSM_PIN_FUNCTION(gcc_gp1), |
688 | MSM_PIN_FUNCTION(gcc_gp2), |
689 | MSM_PIN_FUNCTION(gcc_gp3), |
690 | MSM_PIN_FUNCTION(gpio), |
691 | MSM_PIN_FUNCTION(gp_pdm0), |
692 | MSM_PIN_FUNCTION(gp_pdm1), |
693 | MSM_PIN_FUNCTION(gp_pdm2), |
694 | MSM_PIN_FUNCTION(gsm0_tx), |
695 | MSM_PIN_FUNCTION(gsm1_tx), |
696 | MSM_PIN_FUNCTION(jitter_bist), |
697 | MSM_PIN_FUNCTION(mdp_vsync), |
698 | MSM_PIN_FUNCTION(mdp_vsync_out_0), |
699 | MSM_PIN_FUNCTION(mdp_vsync_out_1), |
700 | MSM_PIN_FUNCTION(mpm_pwr), |
701 | MSM_PIN_FUNCTION(mss_lte), |
702 | MSM_PIN_FUNCTION(m_voc), |
703 | MSM_PIN_FUNCTION(nav_gpio), |
704 | MSM_PIN_FUNCTION(pa_indicator), |
705 | MSM_PIN_FUNCTION(pbs), |
706 | MSM_PIN_FUNCTION(pbs_out), |
707 | MSM_PIN_FUNCTION(phase_flag), |
708 | MSM_PIN_FUNCTION(pll_bist), |
709 | MSM_PIN_FUNCTION(pll_bypassnl), |
710 | MSM_PIN_FUNCTION(pll_reset), |
711 | MSM_PIN_FUNCTION(prng_rosc), |
712 | MSM_PIN_FUNCTION(qdss_cti), |
713 | MSM_PIN_FUNCTION(qdss_gpio), |
714 | MSM_PIN_FUNCTION(qup0), |
715 | MSM_PIN_FUNCTION(qup1), |
716 | MSM_PIN_FUNCTION(qup2), |
717 | MSM_PIN_FUNCTION(qup3), |
718 | MSM_PIN_FUNCTION(qup4), |
719 | MSM_PIN_FUNCTION(qup5), |
720 | MSM_PIN_FUNCTION(sdc1_tb), |
721 | MSM_PIN_FUNCTION(sdc2_tb), |
722 | MSM_PIN_FUNCTION(sd_write), |
723 | MSM_PIN_FUNCTION(ssbi_wtr1), |
724 | MSM_PIN_FUNCTION(tgu), |
725 | MSM_PIN_FUNCTION(tsense_pwm), |
726 | MSM_PIN_FUNCTION(uim1_clk), |
727 | MSM_PIN_FUNCTION(uim1_data), |
728 | MSM_PIN_FUNCTION(uim1_present), |
729 | MSM_PIN_FUNCTION(uim1_reset), |
730 | MSM_PIN_FUNCTION(uim2_clk), |
731 | MSM_PIN_FUNCTION(uim2_data), |
732 | MSM_PIN_FUNCTION(uim2_present), |
733 | MSM_PIN_FUNCTION(uim2_reset), |
734 | MSM_PIN_FUNCTION(usb_phy), |
735 | MSM_PIN_FUNCTION(vfr_1), |
736 | MSM_PIN_FUNCTION(vsense_trigger), |
737 | MSM_PIN_FUNCTION(wlan1_adc0), |
738 | MSM_PIN_FUNCTION(wlan1_adc1), |
739 | }; |
740 | |
741 | /* Every pin is maintained as a single group, and missing or non-existing pin |
742 | * would be maintained as dummy group to synchronize pin group index with |
743 | * pin descriptor registered with pinctrl core. |
744 | * Clients would not be able to request these dummy pin groups. |
745 | */ |
746 | static const struct msm_pingroup sm6115_groups[] = { |
747 | [0] = PINGROUP(0, WEST, qup0, m_voc, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _), |
748 | [1] = PINGROUP(1, WEST, qup0, mpm_pwr, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _), |
749 | [2] = PINGROUP(2, WEST, qup0, ddr_bist, _, phase_flag, qdss_gpio, dac_calib, atest, _, _), |
750 | [3] = PINGROUP(3, WEST, qup0, ddr_bist, _, phase_flag, qdss_gpio, dac_calib, atest, _, _), |
751 | [4] = PINGROUP(4, WEST, qup1, cri_trng, _, phase_flag, dac_calib, atest, _, _, _), |
752 | [5] = PINGROUP(5, WEST, qup1, cri_trng, _, phase_flag, dac_calib, atest, _, _, _), |
753 | [6] = PINGROUP(6, WEST, qup2, _, phase_flag, dac_calib, atest, _, _, _, _), |
754 | [7] = PINGROUP(7, WEST, qup2, _, _, _, _, _, _, _, _), |
755 | [8] = PINGROUP(8, EAST, qup3, pbs_out, pll_bist, _, qdss_gpio, _, tsense_pwm, _, _), |
756 | [9] = PINGROUP(9, EAST, qup3, pbs_out, pll_bist, _, qdss_gpio, _, _, _, _), |
757 | [10] = PINGROUP(10, EAST, qup3, agera_pll, _, pbs, qdss_gpio, _, _, _, _), |
758 | [11] = PINGROUP(11, EAST, qup3, agera_pll, _, pbs, qdss_gpio, _, _, _, _), |
759 | [12] = PINGROUP(12, WEST, qup4, tgu, _, _, _, _, _, _, _), |
760 | [13] = PINGROUP(13, WEST, qup4, tgu, _, _, _, _, _, _, _), |
761 | [14] = PINGROUP(14, WEST, qup5, tgu, _, phase_flag, qdss_gpio, dac_calib, _, _, _), |
762 | [15] = PINGROUP(15, WEST, qup5, tgu, _, phase_flag, qdss_gpio, dac_calib, _, _, _), |
763 | [16] = PINGROUP(16, WEST, qup5, _, phase_flag, qdss_gpio, dac_calib, _, _, _, _), |
764 | [17] = PINGROUP(17, WEST, qup5, _, phase_flag, qdss_gpio, dac_calib, _, _, _, _), |
765 | [18] = PINGROUP(18, EAST, sdc2_tb, cri_trng, pbs, qdss_gpio, _, _, _, _, _), |
766 | [19] = PINGROUP(19, EAST, sdc1_tb, pbs, qdss_gpio, _, _, _, _, _, _), |
767 | [20] = PINGROUP(20, EAST, cam_mclk, pbs, qdss_gpio, _, _, _, _, _, _), |
768 | [21] = PINGROUP(21, EAST, cam_mclk, adsp_ext, pbs, qdss_gpio, _, _, _, _, _), |
769 | [22] = PINGROUP(22, EAST, cci_i2c, prng_rosc, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _), |
770 | [23] = PINGROUP(23, EAST, cci_i2c, prng_rosc, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _), |
771 | [24] = PINGROUP(24, EAST, cci_timer, gcc_gp1, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _), |
772 | [25] = PINGROUP(25, EAST, cci_async, cci_timer, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _), |
773 | [26] = PINGROUP(26, EAST, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, vsense_trigger, _, _), |
774 | [27] = PINGROUP(27, EAST, cam_mclk, qdss_cti, _, _, _, _, _, _, _), |
775 | [28] = PINGROUP(28, EAST, cam_mclk, cci_timer, qdss_cti, _, _, _, _, _, _), |
776 | [29] = PINGROUP(29, EAST, cci_i2c, _, phase_flag, dac_calib, atest, _, _, _, _), |
777 | [30] = PINGROUP(30, EAST, cci_i2c, _, phase_flag, dac_calib, atest, _, _, _, _), |
778 | [31] = PINGROUP(31, EAST, gp_pdm0, _, phase_flag, dac_calib, atest, _, _, _, _), |
779 | [32] = PINGROUP(32, EAST, cci_timer, gp_pdm1, _, phase_flag, dac_calib, atest, _, _, _), |
780 | [33] = PINGROUP(33, EAST, gp_pdm2, _, phase_flag, dac_calib, atest, _, _, _, _), |
781 | [34] = PINGROUP(34, EAST, _, _, _, _, _, _, _, _, _), |
782 | [35] = PINGROUP(35, EAST, _, phase_flag, _, _, _, _, _, _, _), |
783 | [36] = PINGROUP(36, EAST, _, phase_flag, _, _, _, _, _, _, _), |
784 | [37] = PINGROUP(37, EAST, _, _, _, _, _, _, _, _, _), |
785 | [38] = PINGROUP(38, EAST, _, _, _, _, _, _, _, _, _), |
786 | [39] = PINGROUP(39, EAST, _, _, _, _, _, _, _, _, _), |
787 | [40] = PINGROUP(40, EAST, _, _, _, _, _, _, _, _, _), |
788 | [41] = PINGROUP(41, EAST, _, _, _, _, _, _, _, _, _), |
789 | [42] = PINGROUP(42, EAST, _, nav_gpio, _, _, _, _, _, _, _), |
790 | [43] = PINGROUP(43, EAST, _, _, phase_flag, _, _, _, _, _, _), |
791 | [44] = PINGROUP(44, EAST, _, _, phase_flag, _, _, _, _, _, _), |
792 | [45] = PINGROUP(45, EAST, _, _, phase_flag, _, _, _, _, _, _), |
793 | [46] = PINGROUP(46, EAST, _, _, _, _, _, _, _, _, _), |
794 | [47] = PINGROUP(47, EAST, _, nav_gpio, pbs, qdss_gpio, _, _, _, _, _), |
795 | [48] = PINGROUP(48, EAST, _, vfr_1, _, pbs, qdss_gpio, _, _, _, _), |
796 | [49] = PINGROUP(49, EAST, _, pa_indicator, _, _, _, _, _, _, _), |
797 | [50] = PINGROUP(50, EAST, _, _, _, _, _, _, _, _, _), |
798 | [51] = PINGROUP(51, EAST, _, _, _, _, _, _, _, _, _), |
799 | [52] = PINGROUP(52, EAST, _, nav_gpio, pbs_out, _, _, _, _, _, _), |
800 | [53] = PINGROUP(53, EAST, _, gsm1_tx, _, _, _, _, _, _, _), |
801 | [54] = PINGROUP(54, EAST, _, _, _, _, _, _, _, _, _), |
802 | [55] = PINGROUP(55, EAST, _, _, _, _, _, _, _, _, _), |
803 | [56] = PINGROUP(56, EAST, _, _, _, _, _, _, _, _, _), |
804 | [57] = PINGROUP(57, EAST, _, _, _, _, _, _, _, _, _), |
805 | [58] = PINGROUP(58, EAST, _, _, _, _, _, _, _, _, _), |
806 | [59] = PINGROUP(59, EAST, _, ssbi_wtr1, _, _, _, _, _, _, _), |
807 | [60] = PINGROUP(60, EAST, _, ssbi_wtr1, _, _, _, _, _, _, _), |
808 | [61] = PINGROUP(61, EAST, _, _, _, _, _, _, _, _, _), |
809 | [62] = PINGROUP(62, EAST, _, pll_bypassnl, _, _, _, _, _, _, _), |
810 | [63] = PINGROUP(63, EAST, pll_reset, _, phase_flag, ddr_pxi0, _, _, _, _, _), |
811 | [64] = PINGROUP(64, EAST, gsm0_tx, _, phase_flag, ddr_pxi0, _, _, _, _, _), |
812 | [65] = PINGROUP(65, WEST, _, _, _, _, _, _, _, _, _), |
813 | [66] = PINGROUP(66, WEST, _, _, _, _, _, _, _, _, _), |
814 | [67] = PINGROUP(67, WEST, _, _, _, _, _, _, _, _, _), |
815 | [68] = PINGROUP(68, WEST, _, _, _, _, _, _, _, _, _), |
816 | [69] = PINGROUP(69, WEST, qup1, gcc_gp2, qdss_gpio, ddr_pxi1, _, _, _, _, _), |
817 | [70] = PINGROUP(70, WEST, qup1, gcc_gp3, qdss_gpio, ddr_pxi1, _, _, _, _, _), |
818 | [71] = PINGROUP(71, WEST, qup2, dbg_out, _, _, _, _, _, _, _), |
819 | [72] = PINGROUP(72, SOUTH, uim2_data, qdss_cti, _, _, _, _, _, _, _), |
820 | [73] = PINGROUP(73, SOUTH, uim2_clk, _, qdss_cti, _, _, _, _, _, _), |
821 | [74] = PINGROUP(74, SOUTH, uim2_reset, _, _, _, _, _, _, _, _), |
822 | [75] = PINGROUP(75, SOUTH, uim2_present, _, _, _, _, _, _, _, _), |
823 | [76] = PINGROUP(76, SOUTH, uim1_data, _, _, _, _, _, _, _, _), |
824 | [77] = PINGROUP(77, SOUTH, uim1_clk, _, _, _, _, _, _, _, _), |
825 | [78] = PINGROUP(78, SOUTH, uim1_reset, _, _, _, _, _, _, _, _), |
826 | [79] = PINGROUP(79, SOUTH, uim1_present, _, _, _, _, _, _, _, _), |
827 | [80] = PINGROUP(80, WEST, qup2, dac_calib, _, _, _, _, _, _, _), |
828 | [81] = PINGROUP(81, WEST, mdp_vsync_out_0, mdp_vsync_out_1, mdp_vsync, dac_calib, _, _, _, _, _), |
829 | [82] = PINGROUP(82, WEST, qup0, dac_calib, _, _, _, _, _, _, _), |
830 | [83] = PINGROUP(83, WEST, _, _, _, _, _, _, _, _, _), |
831 | [84] = PINGROUP(84, WEST, _, _, _, _, _, _, _, _, _), |
832 | [85] = PINGROUP(85, WEST, _, _, _, _, _, _, _, _, _), |
833 | [86] = PINGROUP(86, WEST, qup0, gcc_gp1, atest, _, _, _, _, _, _), |
834 | [87] = PINGROUP(87, EAST, pbs, qdss_gpio, _, _, _, _, _, _, _), |
835 | [88] = PINGROUP(88, EAST, _, _, _, _, _, _, _, _, _), |
836 | [89] = PINGROUP(89, WEST, usb_phy, atest, _, _, _, _, _, _, _), |
837 | [90] = PINGROUP(90, EAST, mss_lte, pbs, qdss_gpio, _, _, _, _, _, _), |
838 | [91] = PINGROUP(91, EAST, mss_lte, pbs, qdss_gpio, _, _, _, _, _, _), |
839 | [92] = PINGROUP(92, WEST, _, _, _, _, _, _, _, _, _), |
840 | [93] = PINGROUP(93, WEST, _, _, _, _, _, _, _, _, _), |
841 | [94] = PINGROUP(94, WEST, _, qdss_gpio, wlan1_adc0, _, _, _, _, _, _), |
842 | [95] = PINGROUP(95, WEST, nav_gpio, gp_pdm0, qdss_gpio, wlan1_adc1, _, _, _, _, _), |
843 | [96] = PINGROUP(96, WEST, qup4, nav_gpio, mdp_vsync, gp_pdm1, sd_write, jitter_bist, qdss_cti, qdss_cti, _), |
844 | [97] = PINGROUP(97, WEST, qup4, nav_gpio, mdp_vsync, gp_pdm2, jitter_bist, qdss_cti, qdss_cti, _, _), |
845 | [98] = PINGROUP(98, SOUTH, _, _, _, _, _, _, _, _, _), |
846 | [99] = PINGROUP(99, SOUTH, _, _, _, _, _, _, _, _, _), |
847 | [100] = PINGROUP(100, SOUTH, atest, _, _, _, _, _, _, _, _), |
848 | [101] = PINGROUP(101, SOUTH, atest, _, _, _, _, _, _, _, _), |
849 | [102] = PINGROUP(102, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _), |
850 | [103] = PINGROUP(103, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _), |
851 | [104] = PINGROUP(104, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, _), |
852 | [105] = PINGROUP(105, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, _), |
853 | [106] = PINGROUP(106, SOUTH, nav_gpio, gcc_gp3, qdss_gpio, _, _, _, _, _, _), |
854 | [107] = PINGROUP(107, SOUTH, nav_gpio, gcc_gp2, qdss_gpio, _, _, _, _, _, _), |
855 | [108] = PINGROUP(108, SOUTH, nav_gpio, _, _, _, _, _, _, _, _), |
856 | [109] = PINGROUP(109, SOUTH, _, qdss_gpio, _, _, _, _, _, _, _), |
857 | [110] = PINGROUP(110, SOUTH, _, qdss_gpio, _, _, _, _, _, _, _), |
858 | [111] = PINGROUP(111, SOUTH, _, _, _, _, _, _, _, _, _), |
859 | [112] = PINGROUP(112, SOUTH, _, _, _, _, _, _, _, _, _), |
860 | [113] = UFS_RESET(ufs_reset, 0x78000), |
861 | [114] = SDC_QDSD_PINGROUP(sdc1_rclk, WEST, 0x75000, 15, 0), |
862 | [115] = SDC_QDSD_PINGROUP(sdc1_clk, WEST, 0x75000, 13, 6), |
863 | [116] = SDC_QDSD_PINGROUP(sdc1_cmd, WEST, 0x75000, 11, 3), |
864 | [117] = SDC_QDSD_PINGROUP(sdc1_data, WEST, 0x75000, 9, 0), |
865 | [118] = SDC_QDSD_PINGROUP(sdc2_clk, SOUTH, 0x73000, 14, 6), |
866 | [119] = SDC_QDSD_PINGROUP(sdc2_cmd, SOUTH, 0x73000, 11, 3), |
867 | [120] = SDC_QDSD_PINGROUP(sdc2_data, SOUTH, 0x73000, 9, 0), |
868 | }; |
869 | |
870 | static const struct msm_gpio_wakeirq_map sm6115_mpm_map[] = { |
871 | { 0, 84 }, { 3, 75 }, { 4, 16 }, { 6, 59 }, { 8, 63 }, { 11, 17 }, { 13, 18 }, |
872 | { 14, 51 }, { 17, 20 }, { 18, 52 }, { 19, 53 }, { 24, 6 }, { 25, 71 }, { 27, 73 }, |
873 | { 28, 41 }, { 31, 27 }, { 32, 54 }, { 33, 55 }, { 34, 56 }, { 35, 57 }, { 36, 58 }, |
874 | { 39, 28 }, { 46, 29 }, { 62, 60 }, { 63, 61 }, { 64, 62 }, { 65, 30 }, { 66, 31 }, |
875 | { 67, 32 }, { 69, 33 }, { 70, 34 }, { 72, 72 }, { 75, 35 }, { 79, 36 }, { 80, 21 }, |
876 | { 81, 38 }, { 83, 9 }, { 84, 39 }, { 85, 40 }, { 86, 19 }, { 87, 42 }, { 88, 43 }, |
877 | { 89, 45 }, { 91, 74 }, { 93, 46 }, { 94, 47 }, { 95, 48 }, { 96, 49 }, { 97, 50 }, |
878 | }; |
879 | |
880 | static const struct msm_pinctrl_soc_data sm6115_tlmm = { |
881 | .pins = sm6115_pins, |
882 | .npins = ARRAY_SIZE(sm6115_pins), |
883 | .functions = sm6115_functions, |
884 | .nfunctions = ARRAY_SIZE(sm6115_functions), |
885 | .groups = sm6115_groups, |
886 | .ngroups = ARRAY_SIZE(sm6115_groups), |
887 | .ngpios = 114, |
888 | .tiles = sm6115_tiles, |
889 | .ntiles = ARRAY_SIZE(sm6115_tiles), |
890 | .wakeirq_map = sm6115_mpm_map, |
891 | .nwakeirq_map = ARRAY_SIZE(sm6115_mpm_map), |
892 | }; |
893 | |
894 | static int sm6115_tlmm_probe(struct platform_device *pdev) |
895 | { |
896 | return msm_pinctrl_probe(pdev, soc_data: &sm6115_tlmm); |
897 | } |
898 | |
899 | static const struct of_device_id sm6115_tlmm_of_match[] = { |
900 | { .compatible = "qcom,sm6115-tlmm" , }, |
901 | { } |
902 | }; |
903 | |
904 | static struct platform_driver sm6115_tlmm_driver = { |
905 | .driver = { |
906 | .name = "sm6115-tlmm" , |
907 | .of_match_table = sm6115_tlmm_of_match, |
908 | }, |
909 | .probe = sm6115_tlmm_probe, |
910 | .remove_new = msm_pinctrl_remove, |
911 | }; |
912 | |
913 | static int __init sm6115_tlmm_init(void) |
914 | { |
915 | return platform_driver_register(&sm6115_tlmm_driver); |
916 | } |
917 | arch_initcall(sm6115_tlmm_init); |
918 | |
919 | static void __exit sm6115_tlmm_exit(void) |
920 | { |
921 | platform_driver_unregister(&sm6115_tlmm_driver); |
922 | } |
923 | module_exit(sm6115_tlmm_exit); |
924 | |
925 | MODULE_DESCRIPTION("QTI sm6115 tlmm driver" ); |
926 | MODULE_LICENSE("GPL v2" ); |
927 | MODULE_DEVICE_TABLE(of, sm6115_tlmm_of_match); |
928 | |