1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * Copyright (c) 2023 Realtek Semiconductor Corp. |
4 | */ |
5 | |
6 | #define NA 0xffffffff |
7 | #define PADDRI_4_8 1 |
8 | #define PADDRI_2_4 0 |
9 | |
10 | struct rtd_pin_group_desc { |
11 | const char *name; |
12 | const unsigned int *pins; |
13 | unsigned int num_pins; |
14 | }; |
15 | |
16 | struct rtd_pin_func_desc { |
17 | const char *name; |
18 | const char * const *groups; |
19 | unsigned int num_groups; |
20 | }; |
21 | |
22 | struct rtd_pin_mux_desc { |
23 | const char *name; |
24 | u32 mux_value; |
25 | }; |
26 | |
27 | struct rtd_pin_config_desc { |
28 | const char *name; |
29 | unsigned int reg_offset; |
30 | unsigned int base_bit; |
31 | unsigned int pud_en_offset; |
32 | unsigned int pud_sel_offset; |
33 | unsigned int curr_offset; |
34 | unsigned int smt_offset; |
35 | unsigned int power_offset; |
36 | unsigned int curr_type; |
37 | }; |
38 | |
39 | struct rtd_pin_sconfig_desc { |
40 | const char *name; |
41 | unsigned int reg_offset; |
42 | unsigned int dcycle_offset; |
43 | unsigned int dcycle_maskbits; |
44 | unsigned int ndrive_offset; |
45 | unsigned int ndrive_maskbits; |
46 | unsigned int pdrive_offset; |
47 | unsigned int pdrive_maskbits; |
48 | }; |
49 | |
50 | struct rtd_pin_desc { |
51 | const char *name; |
52 | unsigned int mux_offset; |
53 | u32 mux_mask; |
54 | const struct rtd_pin_mux_desc *functions; |
55 | }; |
56 | |
57 | struct rtd_pin_reg_list { |
58 | unsigned int reg_offset; |
59 | unsigned int val; |
60 | }; |
61 | |
62 | #define SHIFT_LEFT(_val, _shift) ((_val) << (_shift)) |
63 | |
64 | #define RTK_PIN_MUX(_name, _mux_off, _mux_mask, ...) \ |
65 | { \ |
66 | .name = # _name, \ |
67 | .mux_offset = _mux_off, \ |
68 | .mux_mask = _mux_mask, \ |
69 | .functions = (const struct rtd_pin_mux_desc []) { \ |
70 | __VA_ARGS__, { } \ |
71 | }, \ |
72 | } |
73 | |
74 | #define RTK_PIN_CONFIG(_name, _reg_off, _base_bit, _pud_en_off, \ |
75 | _pud_sel_off, _curr_off, _smt_off, _pow_off, _curr_type) \ |
76 | { \ |
77 | .name = # _name, \ |
78 | .reg_offset = _reg_off, \ |
79 | .base_bit = _base_bit, \ |
80 | .pud_en_offset = _pud_en_off, \ |
81 | .pud_sel_offset = _pud_sel_off, \ |
82 | .curr_offset = _curr_off, \ |
83 | .smt_offset = _smt_off, \ |
84 | .power_offset = _pow_off, \ |
85 | .curr_type = _curr_type, \ |
86 | } |
87 | |
88 | #define RTK_PIN_SCONFIG(_name, _reg_off, _d_offset, _d_mask, \ |
89 | _n_offset, _n_mask, _p_offset, _p_mask) \ |
90 | { \ |
91 | .name = # _name, \ |
92 | .reg_offset = _reg_off, \ |
93 | .dcycle_offset = _d_offset, \ |
94 | .dcycle_maskbits = _d_mask, \ |
95 | .ndrive_offset = _n_offset, \ |
96 | .ndrive_maskbits = _n_mask, \ |
97 | .pdrive_offset = _p_offset, \ |
98 | .pdrive_maskbits = _p_mask, \ |
99 | } |
100 | |
101 | #define RTK_PIN_FUNC(_mux_val, _name) \ |
102 | { \ |
103 | .name = _name, \ |
104 | .mux_value = _mux_val, \ |
105 | } |
106 | |
107 | struct rtd_pinctrl_desc { |
108 | const struct pinctrl_pin_desc *pins; |
109 | unsigned int num_pins; |
110 | const struct rtd_pin_group_desc *groups; |
111 | unsigned int num_groups; |
112 | const struct rtd_pin_func_desc *functions; |
113 | unsigned int num_functions; |
114 | const struct rtd_pin_desc *muxes; |
115 | unsigned int num_muxes; |
116 | const struct rtd_pin_config_desc *configs; |
117 | unsigned int num_configs; |
118 | const struct rtd_pin_sconfig_desc *sconfigs; |
119 | unsigned int num_sconfigs; |
120 | struct rtd_pin_reg_list *lists; |
121 | unsigned int num_regs; |
122 | }; |
123 | |
124 | int rtd_pinctrl_probe(struct platform_device *pdev, const struct rtd_pinctrl_desc *desc); |
125 | |