1	// SPDX-License-Identifier: GPL-2.0
2	/*
3	* R8A7740 processor support
4	*
5	* Copyright (C) 2011 Renesas Solutions Corp.
6	* Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
7	*/
8	#include <linux/io.h>
9	#include <linux/kernel.h>
10	#include <linux/pinctrl/pinconf-generic.h>
11
12	#include "sh_pfc.h"
13
14	#define CPU_ALL_PORT(fn, pfx, sfx) \
15	PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
16	PORT_10(100, fn, pfx##10, sfx), PORT_90(100, fn, pfx##1, sfx), \
17	PORT_10(200, fn, pfx##20, sfx), \
18	PORT_1(210, fn, pfx##210, sfx), PORT_1(211, fn, pfx##211, sfx)
19
20	#define IRQC_PIN_MUX(irq, pin) \
21	static const unsigned int intc_irq##irq##_pins[] = { \
22	pin, \
23	}; \
24	static const unsigned int intc_irq##irq##_mux[] = { \
25	IRQ##irq##_MARK, \
26	}
27
28	#define IRQC_PINS_MUX(irq, idx, pin) \
29	static const unsigned int intc_irq##irq##_##idx##_pins[] = { \
30	pin, \
31	}; \
32	static const unsigned int intc_irq##irq##_##idx##_mux[] = { \
33	IRQ##irq##_PORT##pin##_MARK, \
34	}
35
36	enum {
37	PINMUX_RESERVED = 0,
38
39	/* PORT0_DATA -> PORT211_DATA */
40	PINMUX_DATA_BEGIN,
41	PORT_ALL(DATA),
42	PINMUX_DATA_END,
43
44	/* PORT0_IN -> PORT211_IN */
45	PINMUX_INPUT_BEGIN,
46	PORT_ALL(IN),
47	PINMUX_INPUT_END,
48
49	/* PORT0_OUT -> PORT211_OUT */
50	PINMUX_OUTPUT_BEGIN,
51	PORT_ALL(OUT),
52	PINMUX_OUTPUT_END,
53
54	PINMUX_FUNCTION_BEGIN,
55	PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */
56	PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */
57	PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */
58	PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */
59	PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */
60	PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */
61	PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */
62	PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */
63	PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */
64	PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */
65
66	MSEL1CR_31_0, MSEL1CR_31_1,
67	MSEL1CR_30_0, MSEL1CR_30_1,
68	MSEL1CR_29_0, MSEL1CR_29_1,
69	MSEL1CR_28_0, MSEL1CR_28_1,
70	MSEL1CR_27_0, MSEL1CR_27_1,
71	MSEL1CR_26_0, MSEL1CR_26_1,
72	MSEL1CR_16_0, MSEL1CR_16_1,
73	MSEL1CR_15_0, MSEL1CR_15_1,
74	MSEL1CR_14_0, MSEL1CR_14_1,
75	MSEL1CR_13_0, MSEL1CR_13_1,
76	MSEL1CR_12_0, MSEL1CR_12_1,
77	MSEL1CR_9_0, MSEL1CR_9_1,
78	MSEL1CR_7_0, MSEL1CR_7_1,
79	MSEL1CR_6_0, MSEL1CR_6_1,
80	MSEL1CR_5_0, MSEL1CR_5_1,
81	MSEL1CR_4_0, MSEL1CR_4_1,
82	MSEL1CR_3_0, MSEL1CR_3_1,
83	MSEL1CR_2_0, MSEL1CR_2_1,
84	MSEL1CR_0_0, MSEL1CR_0_1,
85
86	MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */
87	MSEL3CR_6_0, MSEL3CR_6_1,
88
89	MSEL4CR_19_0, MSEL4CR_19_1,
90	MSEL4CR_18_0, MSEL4CR_18_1,
91	MSEL4CR_15_0, MSEL4CR_15_1,
92	MSEL4CR_10_0, MSEL4CR_10_1,
93	MSEL4CR_6_0, MSEL4CR_6_1,
94	MSEL4CR_4_0, MSEL4CR_4_1,
95	MSEL4CR_1_0, MSEL4CR_1_1,
96
97	MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */
98	MSEL5CR_30_0, MSEL5CR_30_1,
99	MSEL5CR_29_0, MSEL5CR_29_1,
100	MSEL5CR_27_0, MSEL5CR_27_1,
101	MSEL5CR_25_0, MSEL5CR_25_1,
102	MSEL5CR_23_0, MSEL5CR_23_1,
103	MSEL5CR_21_0, MSEL5CR_21_1,
104	MSEL5CR_19_0, MSEL5CR_19_1,
105	MSEL5CR_17_0, MSEL5CR_17_1,
106	MSEL5CR_15_0, MSEL5CR_15_1,
107	MSEL5CR_14_0, MSEL5CR_14_1,
108	MSEL5CR_13_0, MSEL5CR_13_1,
109	MSEL5CR_12_0, MSEL5CR_12_1,
110	MSEL5CR_11_0, MSEL5CR_11_1,
111	MSEL5CR_10_0, MSEL5CR_10_1,
112	MSEL5CR_8_0, MSEL5CR_8_1,
113	MSEL5CR_7_0, MSEL5CR_7_1,
114	MSEL5CR_6_0, MSEL5CR_6_1,
115	MSEL5CR_5_0, MSEL5CR_5_1,
116	MSEL5CR_4_0, MSEL5CR_4_1,
117	MSEL5CR_3_0, MSEL5CR_3_1,
118	MSEL5CR_2_0, MSEL5CR_2_1,
119	MSEL5CR_0_0, MSEL5CR_0_1,
120	PINMUX_FUNCTION_END,
121
122	PINMUX_MARK_BEGIN,
123
124	/* IRQ */
125	IRQ0_PORT2_MARK, IRQ0_PORT13_MARK,
126	IRQ1_MARK,
127	IRQ2_PORT11_MARK, IRQ2_PORT12_MARK,
128	IRQ3_PORT10_MARK, IRQ3_PORT14_MARK,
129	IRQ4_PORT15_MARK, IRQ4_PORT172_MARK,
130	IRQ5_PORT0_MARK, IRQ5_PORT1_MARK,
131	IRQ6_PORT121_MARK, IRQ6_PORT173_MARK,
132	IRQ7_PORT120_MARK, IRQ7_PORT209_MARK,
133	IRQ8_MARK,
134	IRQ9_PORT118_MARK, IRQ9_PORT210_MARK,
135	IRQ10_MARK,
136	IRQ11_MARK,
137	IRQ12_PORT42_MARK, IRQ12_PORT97_MARK,
138	IRQ13_PORT64_MARK, IRQ13_PORT98_MARK,
139	IRQ14_PORT63_MARK, IRQ14_PORT99_MARK,
140	IRQ15_PORT62_MARK, IRQ15_PORT100_MARK,
141	IRQ16_PORT68_MARK, IRQ16_PORT211_MARK,
142	IRQ17_MARK,
143	IRQ18_MARK,
144	IRQ19_MARK,
145	IRQ20_MARK,
146	IRQ21_MARK,
147	IRQ22_MARK,
148	IRQ23_MARK,
149	IRQ24_MARK,
150	IRQ25_MARK,
151	IRQ26_PORT58_MARK, IRQ26_PORT81_MARK,
152	IRQ27_PORT57_MARK, IRQ27_PORT168_MARK,
153	IRQ28_PORT56_MARK, IRQ28_PORT169_MARK,
154	IRQ29_PORT50_MARK, IRQ29_PORT170_MARK,
155	IRQ30_PORT49_MARK, IRQ30_PORT171_MARK,
156	IRQ31_PORT41_MARK, IRQ31_PORT167_MARK,
157
158	/* Function */
159
160	/* DBGT */
161	DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK,
162	DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK,
163	DBGMD21_MARK,
164
165	/* FSI-A */
166	FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */
167	FSIAISLD_PORT5_MARK,
168	FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */
169	FSIASPDIF_PORT18_MARK,
170	FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK,
171	FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK,
172	FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK,
173
174	/* FSI-B */
175	FSIBCK_MARK,
176
177	/* FMSI */
178	FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
179	FMSISLD_PORT6_MARK,
180	FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK,
181	FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK,
182	FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK,
183
184	/* SCIFA0 */
185	SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK,
186	SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
187
188	/* SCIFA1 */
189	SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK,
190	SCIFA1_TXD_MARK, SCIFA1_RTS_MARK,
191
192	/* SCIFA2 */
193	SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
194	SCIFA2_SCK_PORT199_MARK,
195	SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
196	SCIFA2_CTS_MARK, SCIFA2_RTS_MARK,
197
198	/* SCIFA3 */
199	SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
200	SCIFA3_SCK_PORT116_MARK,
201	SCIFA3_CTS_PORT117_MARK,
202	SCIFA3_RXD_PORT174_MARK,
203	SCIFA3_TXD_PORT175_MARK,
204
205	SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
206	SCIFA3_SCK_PORT158_MARK,
207	SCIFA3_CTS_PORT162_MARK,
208	SCIFA3_RXD_PORT159_MARK,
209	SCIFA3_TXD_PORT160_MARK,
210
211	/* SCIFA4 */
212	SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
213	SCIFA4_TXD_PORT13_MARK,
214
215	SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
216	SCIFA4_TXD_PORT203_MARK,
217
218	SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
219	SCIFA4_TXD_PORT93_MARK,
220
221	SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
222	SCIFA4_SCK_PORT205_MARK,
223
224	/* SCIFA5 */
225	SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
226	SCIFA5_RXD_PORT10_MARK,
227
228	SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
229	SCIFA5_TXD_PORT208_MARK,
230
231	SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
232	SCIFA5_RXD_PORT92_MARK,
233
234	SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
235	SCIFA5_SCK_PORT206_MARK,
236
237	/* SCIFA6 */
238	SCIFA6_SCK_MARK, SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
239
240	/* SCIFA7 */
241	SCIFA7_TXD_MARK, SCIFA7_RXD_MARK,
242
243	/* SCIFB */
244	SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
245	SCIFB_RXD_PORT191_MARK,
246	SCIFB_TXD_PORT192_MARK,
247	SCIFB_RTS_PORT186_MARK,
248	SCIFB_CTS_PORT187_MARK,
249
250	SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
251	SCIFB_RXD_PORT3_MARK,
252	SCIFB_TXD_PORT4_MARK,
253	SCIFB_RTS_PORT172_MARK,
254	SCIFB_CTS_PORT173_MARK,
255
256	/* LCD0 */
257	LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
258	LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
259	LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
260	LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
261	LCD0_D16_MARK, LCD0_D17_MARK,
262	LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
263	LCD0_DCK_MARK, LCD0_VSYN_MARK, /* for RGB */
264	LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */
265	LCD0_WR_MARK, LCD0_RD_MARK, /* for SYS */
266	LCD0_CS_MARK, LCD0_RS_MARK, /* for SYS */
267
268	LCD0_D21_PORT158_MARK, LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
269	LCD0_D22_PORT160_MARK, LCD0_D20_PORT161_MARK,
270	LCD0_D19_PORT162_MARK, LCD0_D18_PORT163_MARK,
271	LCD0_LCLK_PORT165_MARK,
272
273	LCD0_D18_PORT40_MARK, LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
274	LCD0_D23_PORT1_MARK, LCD0_D21_PORT2_MARK,
275	LCD0_D20_PORT3_MARK, LCD0_D19_PORT4_MARK,
276	LCD0_LCLK_PORT102_MARK,
277
278	/* LCD1 */
279	LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
280	LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
281	LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
282	LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
283	LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
284	LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
285	LCD1_DON_MARK, LCD1_VCPWC_MARK,
286	LCD1_LCLK_MARK, LCD1_VEPWC_MARK,
287
288	LCD1_DCK_MARK, LCD1_VSYN_MARK, /* for RGB */
289	LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */
290	LCD1_RS_MARK, LCD1_CS_MARK, /* for SYS */
291	LCD1_RD_MARK, LCD1_WR_MARK, /* for SYS */
292
293	/* RSPI */
294	RSPI_SSL0_A_MARK, RSPI_SSL1_A_MARK, RSPI_SSL2_A_MARK,
295	RSPI_SSL3_A_MARK, RSPI_CK_A_MARK, RSPI_MOSI_A_MARK,
296	RSPI_MISO_A_MARK,
297
298	/* VIO CKO */
299	VIO_CKO1_MARK, /* needs fixup */
300	VIO_CKO2_MARK,
301	VIO_CKO_1_MARK,
302	VIO_CKO_MARK,
303
304	/* VIO0 */
305	VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
306	VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
307	VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
308	VIO0_D12_MARK, VIO0_VD_MARK, VIO0_HD_MARK, VIO0_CLK_MARK,
309	VIO0_FIELD_MARK,
310
311	VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
312	VIO0_D14_PORT25_MARK,
313	VIO0_D15_PORT24_MARK,
314
315	VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
316	VIO0_D14_PORT95_MARK,
317	VIO0_D15_PORT96_MARK,
318
319	/* VIO1 */
320	VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
321	VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
322	VIO1_VD_MARK, VIO1_HD_MARK, VIO1_CLK_MARK, VIO1_FIELD_MARK,
323
324	/* TPU0 */
325	TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO3_MARK,
326	TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
327	TPU0TO2_PORT202_MARK,
328
329	/* SSP1 0 */
330	STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK,
331	STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK,
332	STP0_IPEN_MARK, STP0_IPCLK_MARK, STP0_IPSYNC_MARK,
333
334	/* SSP1 1 */
335	STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK,
336	STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK,
337	STP1_IPSYNC_MARK,
338
339	STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
340	STP1_IPEN_PORT187_MARK,
341
342	STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
343	STP1_IPEN_PORT193_MARK,
344
345	/* SIM */
346	SIM_RST_MARK, SIM_CLK_MARK,
347	SIM_D_PORT22_MARK, /* SIM_D Port 22/199 */
348	SIM_D_PORT199_MARK,
349
350	/* SDHI0 */
351	SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
352	SDHI0_CD_MARK, SDHI0_WP_MARK, SDHI0_CMD_MARK, SDHI0_CLK_MARK,
353
354	/* SDHI1 */
355	SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
356	SDHI1_CD_MARK, SDHI1_WP_MARK, SDHI1_CMD_MARK, SDHI1_CLK_MARK,
357
358	/* SDHI2 */
359	SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
360	SDHI2_CLK_MARK, SDHI2_CMD_MARK,
361
362	SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
363	SDHI2_WP_PORT25_MARK,
364
365	SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
366	SDHI2_CD_PORT202_MARK,
367
368	/* MSIOF2 */
369	MSIOF2_TXD_MARK, MSIOF2_RXD_MARK, MSIOF2_TSCK_MARK,
370	MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_SS1_MARK,
371	MSIOF2_MCK1_MARK, MSIOF2_MCK0_MARK, MSIOF2_RSYNC_MARK,
372	MSIOF2_RSCK_MARK,
373
374	/* KEYSC */
375	KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
376	KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
377	KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
378
379	KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
380	KEYIN1_PORT44_MARK,
381	KEYIN2_PORT45_MARK,
382	KEYIN3_PORT46_MARK,
383
384	KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
385	KEYIN1_PORT57_MARK,
386	KEYIN2_PORT56_MARK,
387	KEYIN3_PORT55_MARK,
388
389	/* VOU */
390	DV_D0_MARK, DV_D1_MARK, DV_D2_MARK, DV_D3_MARK,
391	DV_D4_MARK, DV_D5_MARK, DV_D6_MARK, DV_D7_MARK,
392	DV_D8_MARK, DV_D9_MARK, DV_D10_MARK, DV_D11_MARK,
393	DV_D12_MARK, DV_D13_MARK, DV_D14_MARK, DV_D15_MARK,
394	DV_CLK_MARK, DV_VSYNC_MARK, DV_HSYNC_MARK,
395
396	/* MEMC */
397	MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK,
398	MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK,
399	MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK,
400	MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK,
401	MEMC_CS0_MARK, MEMC_INT_MARK, MEMC_NWE_MARK, MEMC_NOE_MARK,
402
403	MEMC_CS1_MARK, /* MSEL4CR_6_0 */
404	MEMC_ADV_MARK,
405	MEMC_WAIT_MARK,
406	MEMC_BUSCLK_MARK,
407
408	MEMC_A1_MARK, /* MSEL4CR_6_1 */
409	MEMC_DREQ0_MARK,
410	MEMC_DREQ1_MARK,
411	MEMC_A0_MARK,
412
413	/* MMC */
414	MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK,
415	MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK,
416	MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, MMC0_CLK_PORT66_MARK,
417	MMC0_CMD_PORT67_MARK, /* MSEL4CR_15_0 */
418
419	MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK,
420	MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK,
421	MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, MMC1_CLK_PORT103_MARK,
422	MMC1_CMD_PORT104_MARK, /* MSEL4CR_15_1 */
423
424	/* MSIOF0 */
425	MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_RXD_MARK,
426	MSIOF0_TXD_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK,
427	MSIOF0_RSYNC_MARK, MSIOF0_RSCK_MARK, MSIOF0_TSCK_MARK,
428	MSIOF0_TSYNC_MARK,
429
430	/* MSIOF1 */
431	MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK,
432	MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
433
434	MSIOF1_SS2_PORT116_MARK, MSIOF1_SS1_PORT117_MARK,
435	MSIOF1_RXD_PORT118_MARK, MSIOF1_TXD_PORT119_MARK,
436	MSIOF1_TSYNC_PORT120_MARK,
437	MSIOF1_TSCK_PORT121_MARK, /* MSEL4CR_10_0 */
438
439	MSIOF1_SS1_PORT67_MARK, MSIOF1_TSCK_PORT72_MARK,
440	MSIOF1_TSYNC_PORT73_MARK, MSIOF1_TXD_PORT74_MARK,
441	MSIOF1_RXD_PORT75_MARK,
442	MSIOF1_SS2_PORT202_MARK, /* MSEL4CR_10_1 */
443
444	/* GPIO */
445	GPO0_MARK, GPI0_MARK, GPO1_MARK, GPI1_MARK,
446
447	/* USB0 */
448	USB0_OCI_MARK, USB0_PPON_MARK, VBUS_MARK,
449
450	/* USB1 */
451	USB1_OCI_MARK, USB1_PPON_MARK,
452
453	/* BBIF1 */
454	BBIF1_RXD_MARK, BBIF1_TXD_MARK, BBIF1_TSYNC_MARK,
455	BBIF1_TSCK_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
456	BBIF1_FLOW_MARK, BBIF1_RX_FLOW_N_MARK,
457
458	/* BBIF2 */
459	BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
460	BBIF2_RXD2_PORT60_MARK,
461	BBIF2_TSYNC2_PORT6_MARK,
462	BBIF2_TSCK2_PORT59_MARK,
463
464	BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
465	BBIF2_TXD2_PORT183_MARK,
466	BBIF2_TSCK2_PORT89_MARK,
467	BBIF2_TSYNC2_PORT184_MARK,
468
469	/* BSC / FLCTL / PCMCIA */
470	CS0_MARK, CS2_MARK, CS4_MARK,
471	CS5B_MARK, CS6A_MARK,
472	CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
473	CS5A_PORT19_MARK,
474	IOIS16_MARK, /* ? */
475
476	A0_MARK, A1_MARK, A2_MARK, A3_MARK,
477	A4_FOE_MARK, /* share with FLCTL */
478	A5_FCDE_MARK, /* share with FLCTL */
479	A6_MARK, A7_MARK, A8_MARK, A9_MARK,
480	A10_MARK, A11_MARK, A12_MARK, A13_MARK,
481	A14_MARK, A15_MARK, A16_MARK, A17_MARK,
482	A18_MARK, A19_MARK, A20_MARK, A21_MARK,
483	A22_MARK, A23_MARK, A24_MARK, A25_MARK,
484	A26_MARK,
485
486	D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, /* share with FLCTL */
487	D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, /* share with FLCTL */
488	D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, /* share with FLCTL */
489	D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */
490	D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */
491	D15_NAF15_MARK, /* share with FLCTL */
492	D16_MARK, D17_MARK, D18_MARK, D19_MARK,
493	D20_MARK, D21_MARK, D22_MARK, D23_MARK,
494	D24_MARK, D25_MARK, D26_MARK, D27_MARK,
495	D28_MARK, D29_MARK, D30_MARK, D31_MARK,
496
497	WE0_FWE_MARK, /* share with FLCTL */
498	WE1_MARK,
499	WE2_ICIORD_MARK, /* share with PCMCIA */
500	WE3_ICIOWR_MARK, /* share with PCMCIA */
501	CKO_MARK, BS_MARK, RDWR_MARK,
502	RD_FSC_MARK, /* share with FLCTL */
503	WAIT_PORT177_MARK, /* WAIT Port 90/177 */
504	WAIT_PORT90_MARK,
505
506	FCE0_MARK, FCE1_MARK, FRB_MARK, /* FLCTL */
507
508	/* IRDA */
509	IRDA_FIRSEL_MARK, IRDA_IN_MARK, IRDA_OUT_MARK,
510
511	/* ATAPI */
512	IDE_D0_MARK, IDE_D1_MARK, IDE_D2_MARK, IDE_D3_MARK,
513	IDE_D4_MARK, IDE_D5_MARK, IDE_D6_MARK, IDE_D7_MARK,
514	IDE_D8_MARK, IDE_D9_MARK, IDE_D10_MARK, IDE_D11_MARK,
515	IDE_D12_MARK, IDE_D13_MARK, IDE_D14_MARK, IDE_D15_MARK,
516	IDE_A0_MARK, IDE_A1_MARK, IDE_A2_MARK, IDE_CS0_MARK,
517	IDE_CS1_MARK, IDE_IOWR_MARK, IDE_IORD_MARK, IDE_IORDY_MARK,
518	IDE_INT_MARK, IDE_RST_MARK, IDE_DIRECTION_MARK,
519	IDE_EXBUF_ENB_MARK, IDE_IODACK_MARK, IDE_IODREQ_MARK,
520
521	/* RMII */
522	RMII_CRS_DV_MARK, RMII_RX_ER_MARK, RMII_RXD0_MARK,
523	RMII_RXD1_MARK, RMII_TX_EN_MARK, RMII_TXD0_MARK,
524	RMII_MDC_MARK, RMII_TXD1_MARK, RMII_MDIO_MARK,
525	RMII_REF50CK_MARK, /* for RMII */
526	RMII_REF125CK_MARK, /* for GMII */
527
528	/* GEther */
529	ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_ETXD0_MARK, ET_ETXD1_MARK,
530	ET_ETXD2_MARK, ET_ETXD3_MARK,
531	ET_ETXD4_MARK, ET_ETXD5_MARK, /* for GEther */
532	ET_ETXD6_MARK, ET_ETXD7_MARK, /* for GEther */
533	ET_COL_MARK, ET_TX_ER_MARK, ET_RX_CLK_MARK, ET_RX_DV_MARK,
534	ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
535	ET_ERXD4_MARK, ET_ERXD5_MARK, /* for GEther */
536	ET_ERXD6_MARK, ET_ERXD7_MARK, /* for GEther */
537	ET_RX_ER_MARK, ET_CRS_MARK, ET_MDC_MARK, ET_MDIO_MARK,
538	ET_LINK_MARK, ET_PHY_INT_MARK, ET_WOL_MARK, ET_GTX_CLK_MARK,
539
540	/* DMA0 */
541	DREQ0_MARK, DACK0_MARK,
542
543	/* DMA1 */
544	DREQ1_MARK, DACK1_MARK,
545
546	/* SYSC */
547	RESETOUTS_MARK, RESETP_PULLUP_MARK, RESETP_PLAIN_MARK,
548
549	/* IRREM */
550	IROUT_MARK,
551
552	/* SDENC */
553	SDENC_CPG_MARK, SDENC_DV_CLKI_MARK,
554
555	/* HDMI */
556	HDMI_HPD_MARK, HDMI_CEC_MARK,
557
558	/* DEBUG */
559	EDEBGREQ_PULLUP_MARK, /* for JTAG */
560	EDEBGREQ_PULLDOWN_MARK,
561
562	TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */
563	TRACEAUD_FROM_LCDC0_MARK,
564	TRACEAUD_FROM_MEMC_MARK,
565
566	PINMUX_MARK_END,
567	};
568
569	static const u16 pinmux_data[] = {
570	PINMUX_DATA_ALL(),
571
572	/* Port0 */
573	PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
574	PINMUX_DATA(FSIAISLD_PORT0_MARK, PORT0_FN2, MSEL5CR_3_0),
575	PINMUX_DATA(FSIAOSLD1_MARK, PORT0_FN3),
576	PINMUX_DATA(LCD0_D22_PORT0_MARK, PORT0_FN4, MSEL5CR_6_0),
577	PINMUX_DATA(SCIFA7_RXD_MARK, PORT0_FN6),
578	PINMUX_DATA(LCD1_D4_MARK, PORT0_FN7),
579	PINMUX_DATA(IRQ5_PORT0_MARK, PORT0_FN0, MSEL1CR_5_0),
580
581	/* Port1 */
582	PINMUX_DATA(DBGMDT1_MARK, PORT1_FN1),
583	PINMUX_DATA(FMSISLD_PORT1_MARK, PORT1_FN2, MSEL5CR_5_0),
584	PINMUX_DATA(FSIAOSLD2_MARK, PORT1_FN3),
585	PINMUX_DATA(LCD0_D23_PORT1_MARK, PORT1_FN4, MSEL5CR_6_0),
586	PINMUX_DATA(SCIFA7_TXD_MARK, PORT1_FN6),
587	PINMUX_DATA(LCD1_D3_MARK, PORT1_FN7),
588	PINMUX_DATA(IRQ5_PORT1_MARK, PORT1_FN0, MSEL1CR_5_1),
589
590	/* Port2 */
591	PINMUX_DATA(DBGMDT0_MARK, PORT2_FN1),
592	PINMUX_DATA(SCIFB_SCK_PORT2_MARK, PORT2_FN2, MSEL5CR_17_1),
593	PINMUX_DATA(LCD0_D21_PORT2_MARK, PORT2_FN4, MSEL5CR_6_0),
594	PINMUX_DATA(LCD1_D2_MARK, PORT2_FN7),
595	PINMUX_DATA(IRQ0_PORT2_MARK, PORT2_FN0, MSEL1CR_0_1),
596
597	/* Port3 */
598	PINMUX_DATA(DBGMD21_MARK, PORT3_FN1),
599	PINMUX_DATA(SCIFB_RXD_PORT3_MARK, PORT3_FN2, MSEL5CR_17_1),
600	PINMUX_DATA(LCD0_D20_PORT3_MARK, PORT3_FN4, MSEL5CR_6_0),
601	PINMUX_DATA(LCD1_D1_MARK, PORT3_FN7),
602
603	/* Port4 */
604	PINMUX_DATA(DBGMD20_MARK, PORT4_FN1),
605	PINMUX_DATA(SCIFB_TXD_PORT4_MARK, PORT4_FN2, MSEL5CR_17_1),
606	PINMUX_DATA(LCD0_D19_PORT4_MARK, PORT4_FN4, MSEL5CR_6_0),
607	PINMUX_DATA(LCD1_D0_MARK, PORT4_FN7),
608
609	/* Port5 */
610	PINMUX_DATA(DBGMD11_MARK, PORT5_FN1),
611	PINMUX_DATA(BBIF2_TXD2_PORT5_MARK, PORT5_FN2, MSEL5CR_0_0),
612	PINMUX_DATA(FSIAISLD_PORT5_MARK, PORT5_FN4, MSEL5CR_3_1),
613	PINMUX_DATA(RSPI_SSL0_A_MARK, PORT5_FN6),
614	PINMUX_DATA(LCD1_VCPWC_MARK, PORT5_FN7),
615
616	/* Port6 */
617	PINMUX_DATA(DBGMD10_MARK, PORT6_FN1),
618	PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK, PORT6_FN2, MSEL5CR_0_0),
619	PINMUX_DATA(FMSISLD_PORT6_MARK, PORT6_FN4, MSEL5CR_5_1),
620	PINMUX_DATA(RSPI_SSL1_A_MARK, PORT6_FN6),
621	PINMUX_DATA(LCD1_VEPWC_MARK, PORT6_FN7),
622
623	/* Port7 */
624	PINMUX_DATA(FSIAOLR_MARK, PORT7_FN1),
625
626	/* Port8 */
627	PINMUX_DATA(FSIAOBT_MARK, PORT8_FN1),
628
629	/* Port9 */
630	PINMUX_DATA(FSIAOSLD_MARK, PORT9_FN1),
631	PINMUX_DATA(FSIASPDIF_PORT9_MARK, PORT9_FN2, MSEL5CR_4_0),
632
633	/* Port10 */
634	PINMUX_DATA(FSIAOMC_MARK, PORT10_FN1),
635	PINMUX_DATA(SCIFA5_RXD_PORT10_MARK, PORT10_FN3, MSEL5CR_14_0, MSEL5CR_15_0),
636	PINMUX_DATA(IRQ3_PORT10_MARK, PORT10_FN0, MSEL1CR_3_0),
637
638	/* Port11 */
639	PINMUX_DATA(FSIACK_MARK, PORT11_FN1),
640	PINMUX_DATA(FSIBCK_MARK, PORT11_FN2),
641	PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0),
642
643	/* Port12 */
644	PINMUX_DATA(FSIAILR_MARK, PORT12_FN1),
645	PINMUX_DATA(SCIFA4_RXD_PORT12_MARK, PORT12_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
646	PINMUX_DATA(LCD1_RS_MARK, PORT12_FN6),
647	PINMUX_DATA(LCD1_DISP_MARK, PORT12_FN7),
648	PINMUX_DATA(IRQ2_PORT12_MARK, PORT12_FN0, MSEL1CR_2_1),
649
650	/* Port13 */
651	PINMUX_DATA(FSIAIBT_MARK, PORT13_FN1),
652	PINMUX_DATA(SCIFA4_TXD_PORT13_MARK, PORT13_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
653	PINMUX_DATA(LCD1_RD_MARK, PORT13_FN7),
654	PINMUX_DATA(IRQ0_PORT13_MARK, PORT13_FN0, MSEL1CR_0_0),
655
656	/* Port14 */
657	PINMUX_DATA(FMSOILR_MARK, PORT14_FN1),
658	PINMUX_DATA(FMSIILR_MARK, PORT14_FN2),
659	PINMUX_DATA(VIO_CKO1_MARK, PORT14_FN3),
660	PINMUX_DATA(LCD1_D23_MARK, PORT14_FN7),
661	PINMUX_DATA(IRQ3_PORT14_MARK, PORT14_FN0, MSEL1CR_3_1),
662
663	/* Port15 */
664	PINMUX_DATA(FMSOIBT_MARK, PORT15_FN1),
665	PINMUX_DATA(FMSIIBT_MARK, PORT15_FN2),
666	PINMUX_DATA(VIO_CKO2_MARK, PORT15_FN3),
667	PINMUX_DATA(LCD1_D22_MARK, PORT15_FN7),
668	PINMUX_DATA(IRQ4_PORT15_MARK, PORT15_FN0, MSEL1CR_4_0),
669
670	/* Port16 */
671	PINMUX_DATA(FMSOOLR_MARK, PORT16_FN1),
672	PINMUX_DATA(FMSIOLR_MARK, PORT16_FN2),
673
674	/* Port17 */
675	PINMUX_DATA(FMSOOBT_MARK, PORT17_FN1),
676	PINMUX_DATA(FMSIOBT_MARK, PORT17_FN2),
677
678	/* Port18 */
679	PINMUX_DATA(FMSOSLD_MARK, PORT18_FN1),
680	PINMUX_DATA(FSIASPDIF_PORT18_MARK, PORT18_FN2, MSEL5CR_4_1),
681
682	/* Port19 */
683	PINMUX_DATA(FMSICK_MARK, PORT19_FN1),
684	PINMUX_DATA(CS5A_PORT19_MARK, PORT19_FN7, MSEL5CR_2_1),
685	PINMUX_DATA(IRQ10_MARK, PORT19_FN0),
686
687	/* Port20 */
688	PINMUX_DATA(FMSOCK_MARK, PORT20_FN1),
689	PINMUX_DATA(SCIFA5_TXD_PORT20_MARK, PORT20_FN3, MSEL5CR_15_0, MSEL5CR_14_0),
690	PINMUX_DATA(IRQ1_MARK, PORT20_FN0),
691
692	/* Port21 */
693	PINMUX_DATA(SCIFA1_CTS_MARK, PORT21_FN1),
694	PINMUX_DATA(SCIFA4_SCK_PORT21_MARK, PORT21_FN2, MSEL5CR_10_0),
695	PINMUX_DATA(TPU0TO1_MARK, PORT21_FN4),
696	PINMUX_DATA(VIO1_FIELD_MARK, PORT21_FN5),
697	PINMUX_DATA(STP0_IPD5_MARK, PORT21_FN6),
698	PINMUX_DATA(LCD1_D10_MARK, PORT21_FN7),
699
700	/* Port22 */
701	PINMUX_DATA(SCIFA2_SCK_PORT22_MARK, PORT22_FN1, MSEL5CR_7_0),
702	PINMUX_DATA(SIM_D_PORT22_MARK, PORT22_FN4, MSEL5CR_21_0),
703	PINMUX_DATA(VIO0_D13_PORT22_MARK, PORT22_FN7, MSEL5CR_27_1),
704
705	/* Port23 */
706	PINMUX_DATA(SCIFA1_RTS_MARK, PORT23_FN1),
707	PINMUX_DATA(SCIFA5_SCK_PORT23_MARK, PORT23_FN3, MSEL5CR_13_0),
708	PINMUX_DATA(TPU0TO0_MARK, PORT23_FN4),
709	PINMUX_DATA(VIO_CKO_1_MARK, PORT23_FN5),
710	PINMUX_DATA(STP0_IPD2_MARK, PORT23_FN6),
711	PINMUX_DATA(LCD1_D7_MARK, PORT23_FN7),
712
713	/* Port24 */
714	PINMUX_DATA(VIO0_D15_PORT24_MARK, PORT24_FN1, MSEL5CR_27_0),
715	PINMUX_DATA(VIO1_D7_MARK, PORT24_FN5),
716	PINMUX_DATA(SCIFA6_SCK_MARK, PORT24_FN6),
717	PINMUX_DATA(SDHI2_CD_PORT24_MARK, PORT24_FN7, MSEL5CR_19_0),
718
719	/* Port25 */
720	PINMUX_DATA(VIO0_D14_PORT25_MARK, PORT25_FN1, MSEL5CR_27_0),
721	PINMUX_DATA(VIO1_D6_MARK, PORT25_FN5),
722	PINMUX_DATA(SCIFA6_RXD_MARK, PORT25_FN6),
723	PINMUX_DATA(SDHI2_WP_PORT25_MARK, PORT25_FN7, MSEL5CR_19_0),
724
725	/* Port26 */
726	PINMUX_DATA(VIO0_D13_PORT26_MARK, PORT26_FN1, MSEL5CR_27_0),
727	PINMUX_DATA(VIO1_D5_MARK, PORT26_FN5),
728	PINMUX_DATA(SCIFA6_TXD_MARK, PORT26_FN6),
729
730	/* Port27 - Port39 Function */
731	PINMUX_DATA(VIO0_D7_MARK, PORT27_FN1),
732	PINMUX_DATA(VIO0_D6_MARK, PORT28_FN1),
733	PINMUX_DATA(VIO0_D5_MARK, PORT29_FN1),
734	PINMUX_DATA(VIO0_D4_MARK, PORT30_FN1),
735	PINMUX_DATA(VIO0_D3_MARK, PORT31_FN1),
736	PINMUX_DATA(VIO0_D2_MARK, PORT32_FN1),
737	PINMUX_DATA(VIO0_D1_MARK, PORT33_FN1),
738	PINMUX_DATA(VIO0_D0_MARK, PORT34_FN1),
739	PINMUX_DATA(VIO0_CLK_MARK, PORT35_FN1),
740	PINMUX_DATA(VIO_CKO_MARK, PORT36_FN1),
741	PINMUX_DATA(VIO0_HD_MARK, PORT37_FN1),
742	PINMUX_DATA(VIO0_FIELD_MARK, PORT38_FN1),
743	PINMUX_DATA(VIO0_VD_MARK, PORT39_FN1),
744
745	/* Port38 IRQ */
746	PINMUX_DATA(IRQ25_MARK, PORT38_FN0),
747
748	/* Port40 */
749	PINMUX_DATA(LCD0_D18_PORT40_MARK, PORT40_FN4, MSEL5CR_6_0),
750	PINMUX_DATA(RSPI_CK_A_MARK, PORT40_FN6),
751	PINMUX_DATA(LCD1_LCLK_MARK, PORT40_FN7),
752
753	/* Port41 */
754	PINMUX_DATA(LCD0_D17_MARK, PORT41_FN1),
755	PINMUX_DATA(MSIOF2_SS1_MARK, PORT41_FN2),
756	PINMUX_DATA(IRQ31_PORT41_MARK, PORT41_FN0, MSEL1CR_31_1),
757
758	/* Port42 */
759	PINMUX_DATA(LCD0_D16_MARK, PORT42_FN1),
760	PINMUX_DATA(MSIOF2_MCK1_MARK, PORT42_FN2),
761	PINMUX_DATA(IRQ12_PORT42_MARK, PORT42_FN0, MSEL1CR_12_1),
762
763	/* Port43 */
764	PINMUX_DATA(LCD0_D15_MARK, PORT43_FN1),
765	PINMUX_DATA(MSIOF2_MCK0_MARK, PORT43_FN2),
766	PINMUX_DATA(KEYIN0_PORT43_MARK, PORT43_FN3, MSEL4CR_18_0),
767	PINMUX_DATA(DV_D15_MARK, PORT43_FN6),
768
769	/* Port44 */
770	PINMUX_DATA(LCD0_D14_MARK, PORT44_FN1),
771	PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT44_FN2),
772	PINMUX_DATA(KEYIN1_PORT44_MARK, PORT44_FN3, MSEL4CR_18_0),
773	PINMUX_DATA(DV_D14_MARK, PORT44_FN6),
774
775	/* Port45 */
776	PINMUX_DATA(LCD0_D13_MARK, PORT45_FN1),
777	PINMUX_DATA(MSIOF2_RSCK_MARK, PORT45_FN2),
778	PINMUX_DATA(KEYIN2_PORT45_MARK, PORT45_FN3, MSEL4CR_18_0),
779	PINMUX_DATA(DV_D13_MARK, PORT45_FN6),
780
781	/* Port46 */
782	PINMUX_DATA(LCD0_D12_MARK, PORT46_FN1),
783	PINMUX_DATA(KEYIN3_PORT46_MARK, PORT46_FN3, MSEL4CR_18_0),
784	PINMUX_DATA(DV_D12_MARK, PORT46_FN6),
785
786	/* Port47 */
787	PINMUX_DATA(LCD0_D11_MARK, PORT47_FN1),
788	PINMUX_DATA(KEYIN4_MARK, PORT47_FN3),
789	PINMUX_DATA(DV_D11_MARK, PORT47_FN6),
790
791	/* Port48 */
792	PINMUX_DATA(LCD0_D10_MARK, PORT48_FN1),
793	PINMUX_DATA(KEYIN5_MARK, PORT48_FN3),
794	PINMUX_DATA(DV_D10_MARK, PORT48_FN6),
795
796	/* Port49 */
797	PINMUX_DATA(LCD0_D9_MARK, PORT49_FN1),
798	PINMUX_DATA(KEYIN6_MARK, PORT49_FN3),
799	PINMUX_DATA(DV_D9_MARK, PORT49_FN6),
800	PINMUX_DATA(IRQ30_PORT49_MARK, PORT49_FN0, MSEL1CR_30_1),
801
802	/* Port50 */
803	PINMUX_DATA(LCD0_D8_MARK, PORT50_FN1),
804	PINMUX_DATA(KEYIN7_MARK, PORT50_FN3),
805	PINMUX_DATA(DV_D8_MARK, PORT50_FN6),
806	PINMUX_DATA(IRQ29_PORT50_MARK, PORT50_FN0, MSEL1CR_29_1),
807
808	/* Port51 */
809	PINMUX_DATA(LCD0_D7_MARK, PORT51_FN1),
810	PINMUX_DATA(KEYOUT0_MARK, PORT51_FN3),
811	PINMUX_DATA(DV_D7_MARK, PORT51_FN6),
812
813	/* Port52 */
814	PINMUX_DATA(LCD0_D6_MARK, PORT52_FN1),
815	PINMUX_DATA(KEYOUT1_MARK, PORT52_FN3),
816	PINMUX_DATA(DV_D6_MARK, PORT52_FN6),
817
818	/* Port53 */
819	PINMUX_DATA(LCD0_D5_MARK, PORT53_FN1),
820	PINMUX_DATA(KEYOUT2_MARK, PORT53_FN3),
821	PINMUX_DATA(DV_D5_MARK, PORT53_FN6),
822
823	/* Port54 */
824	PINMUX_DATA(LCD0_D4_MARK, PORT54_FN1),
825	PINMUX_DATA(KEYOUT3_MARK, PORT54_FN3),
826	PINMUX_DATA(DV_D4_MARK, PORT54_FN6),
827
828	/* Port55 */
829	PINMUX_DATA(LCD0_D3_MARK, PORT55_FN1),
830	PINMUX_DATA(KEYOUT4_MARK, PORT55_FN3),
831	PINMUX_DATA(KEYIN3_PORT55_MARK, PORT55_FN4, MSEL4CR_18_1),
832	PINMUX_DATA(DV_D3_MARK, PORT55_FN6),
833
834	/* Port56 */
835	PINMUX_DATA(LCD0_D2_MARK, PORT56_FN1),
836	PINMUX_DATA(KEYOUT5_MARK, PORT56_FN3),
837	PINMUX_DATA(KEYIN2_PORT56_MARK, PORT56_FN4, MSEL4CR_18_1),
838	PINMUX_DATA(DV_D2_MARK, PORT56_FN6),
839	PINMUX_DATA(IRQ28_PORT56_MARK, PORT56_FN0, MSEL1CR_28_1),
840
841	/* Port57 */
842	PINMUX_DATA(LCD0_D1_MARK, PORT57_FN1),
843	PINMUX_DATA(KEYOUT6_MARK, PORT57_FN3),
844	PINMUX_DATA(KEYIN1_PORT57_MARK, PORT57_FN4, MSEL4CR_18_1),
845	PINMUX_DATA(DV_D1_MARK, PORT57_FN6),
846	PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1),
847
848	/* Port58 */
849	PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1, MSEL3CR_6_0),
850	PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3),
851	PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1),
852	PINMUX_DATA(DV_D0_MARK, PORT58_FN6),
853	PINMUX_DATA(IRQ26_PORT58_MARK, PORT58_FN0, MSEL1CR_26_1),
854
855	/* Port59 */
856	PINMUX_DATA(LCD0_VCPWC_MARK, PORT59_FN1),
857	PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK, PORT59_FN2, MSEL5CR_0_0),
858	PINMUX_DATA(RSPI_MOSI_A_MARK, PORT59_FN6),
859
860	/* Port60 */
861	PINMUX_DATA(LCD0_VEPWC_MARK, PORT60_FN1),
862	PINMUX_DATA(BBIF2_RXD2_PORT60_MARK, PORT60_FN2, MSEL5CR_0_0),
863	PINMUX_DATA(RSPI_MISO_A_MARK, PORT60_FN6),
864
865	/* Port61 */
866	PINMUX_DATA(LCD0_DON_MARK, PORT61_FN1),
867	PINMUX_DATA(MSIOF2_TXD_MARK, PORT61_FN2),
868
869	/* Port62 */
870	PINMUX_DATA(LCD0_DCK_MARK, PORT62_FN1),
871	PINMUX_DATA(LCD0_WR_MARK, PORT62_FN4),
872	PINMUX_DATA(DV_CLK_MARK, PORT62_FN6),
873	PINMUX_DATA(IRQ15_PORT62_MARK, PORT62_FN0, MSEL1CR_15_1),
874
875	/* Port63 */
876	PINMUX_DATA(LCD0_VSYN_MARK, PORT63_FN1),
877	PINMUX_DATA(DV_VSYNC_MARK, PORT63_FN6),
878	PINMUX_DATA(IRQ14_PORT63_MARK, PORT63_FN0, MSEL1CR_14_1),
879
880	/* Port64 */
881	PINMUX_DATA(LCD0_HSYN_MARK, PORT64_FN1),
882	PINMUX_DATA(LCD0_CS_MARK, PORT64_FN4),
883	PINMUX_DATA(DV_HSYNC_MARK, PORT64_FN6),
884	PINMUX_DATA(IRQ13_PORT64_MARK, PORT64_FN0, MSEL1CR_13_1),
885
886	/* Port65 */
887	PINMUX_DATA(LCD0_DISP_MARK, PORT65_FN1),
888	PINMUX_DATA(MSIOF2_TSCK_MARK, PORT65_FN2),
889	PINMUX_DATA(LCD0_RS_MARK, PORT65_FN4),
890
891	/* Port66 */
892	PINMUX_DATA(MEMC_INT_MARK, PORT66_FN1),
893	PINMUX_DATA(TPU0TO2_PORT66_MARK, PORT66_FN3, MSEL5CR_25_0),
894	PINMUX_DATA(MMC0_CLK_PORT66_MARK, PORT66_FN4, MSEL4CR_15_0),
895	PINMUX_DATA(SDHI1_CLK_MARK, PORT66_FN6),
896
897	/* Port67 - Port73 Function1 */
898	PINMUX_DATA(MEMC_CS0_MARK, PORT67_FN1),
899	PINMUX_DATA(MEMC_AD8_MARK, PORT68_FN1),
900	PINMUX_DATA(MEMC_AD9_MARK, PORT69_FN1),
901	PINMUX_DATA(MEMC_AD10_MARK, PORT70_FN1),
902	PINMUX_DATA(MEMC_AD11_MARK, PORT71_FN1),
903	PINMUX_DATA(MEMC_AD12_MARK, PORT72_FN1),
904	PINMUX_DATA(MEMC_AD13_MARK, PORT73_FN1),
905
906	/* Port67 - Port73 Function2 */
907	PINMUX_DATA(MSIOF1_SS1_PORT67_MARK, PORT67_FN2, MSEL4CR_10_1),
908	PINMUX_DATA(MSIOF1_RSCK_MARK, PORT68_FN2),
909	PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT69_FN2),
910	PINMUX_DATA(MSIOF1_MCK0_MARK, PORT70_FN2),
911	PINMUX_DATA(MSIOF1_MCK1_MARK, PORT71_FN2),
912	PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK, PORT72_FN2, MSEL4CR_10_1),
913	PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK, PORT73_FN2, MSEL4CR_10_1),
914
915	/* Port67 - Port73 Function4 */
916	PINMUX_DATA(MMC0_CMD_PORT67_MARK, PORT67_FN4, MSEL4CR_15_0),
917	PINMUX_DATA(MMC0_D0_PORT68_MARK, PORT68_FN4, MSEL4CR_15_0),
918	PINMUX_DATA(MMC0_D1_PORT69_MARK, PORT69_FN4, MSEL4CR_15_0),
919	PINMUX_DATA(MMC0_D2_PORT70_MARK, PORT70_FN4, MSEL4CR_15_0),
920	PINMUX_DATA(MMC0_D3_PORT71_MARK, PORT71_FN4, MSEL4CR_15_0),
921	PINMUX_DATA(MMC0_D4_PORT72_MARK, PORT72_FN4, MSEL4CR_15_0),
922	PINMUX_DATA(MMC0_D5_PORT73_MARK, PORT73_FN4, MSEL4CR_15_0),
923
924	/* Port67 - Port73 Function6 */
925	PINMUX_DATA(SDHI1_CMD_MARK, PORT67_FN6),
926	PINMUX_DATA(SDHI1_D0_MARK, PORT68_FN6),
927	PINMUX_DATA(SDHI1_D1_MARK, PORT69_FN6),
928	PINMUX_DATA(SDHI1_D2_MARK, PORT70_FN6),
929	PINMUX_DATA(SDHI1_D3_MARK, PORT71_FN6),
930	PINMUX_DATA(SDHI1_CD_MARK, PORT72_FN6),
931	PINMUX_DATA(SDHI1_WP_MARK, PORT73_FN6),
932
933	/* Port67 - Port71 IRQ */
934	PINMUX_DATA(IRQ20_MARK, PORT67_FN0),
935	PINMUX_DATA(IRQ16_PORT68_MARK, PORT68_FN0, MSEL1CR_16_0),
936	PINMUX_DATA(IRQ17_MARK, PORT69_FN0),
937	PINMUX_DATA(IRQ18_MARK, PORT70_FN0),
938	PINMUX_DATA(IRQ19_MARK, PORT71_FN0),
939
940	/* Port74 */
941	PINMUX_DATA(MEMC_AD14_MARK, PORT74_FN1),
942	PINMUX_DATA(MSIOF1_TXD_PORT74_MARK, PORT74_FN2, MSEL4CR_10_1),
943	PINMUX_DATA(MMC0_D6_PORT74_MARK, PORT74_FN4, MSEL4CR_15_0),
944	PINMUX_DATA(STP1_IPD7_MARK, PORT74_FN6),
945	PINMUX_DATA(LCD1_D21_MARK, PORT74_FN7),
946
947	/* Port75 */
948	PINMUX_DATA(MEMC_AD15_MARK, PORT75_FN1),
949	PINMUX_DATA(MSIOF1_RXD_PORT75_MARK, PORT75_FN2, MSEL4CR_10_1),
950	PINMUX_DATA(MMC0_D7_PORT75_MARK, PORT75_FN4, MSEL4CR_15_0),
951	PINMUX_DATA(STP1_IPD6_MARK, PORT75_FN6),
952	PINMUX_DATA(LCD1_D20_MARK, PORT75_FN7),
953
954	/* Port76 - Port80 Function */
955	PINMUX_DATA(SDHI0_CMD_MARK, PORT76_FN1),
956	PINMUX_DATA(SDHI0_D0_MARK, PORT77_FN1),
957	PINMUX_DATA(SDHI0_D1_MARK, PORT78_FN1),
958	PINMUX_DATA(SDHI0_D2_MARK, PORT79_FN1),
959	PINMUX_DATA(SDHI0_D3_MARK, PORT80_FN1),
960
961	/* Port81 */
962	PINMUX_DATA(SDHI0_CD_MARK, PORT81_FN1),
963	PINMUX_DATA(IRQ26_PORT81_MARK, PORT81_FN0, MSEL1CR_26_0),
964
965	/* Port82 - Port88 Function */
966	PINMUX_DATA(SDHI0_CLK_MARK, PORT82_FN1),
967	PINMUX_DATA(SDHI0_WP_MARK, PORT83_FN1),
968	PINMUX_DATA(RESETOUTS_MARK, PORT84_FN1),
969	PINMUX_DATA(USB0_PPON_MARK, PORT85_FN1),
970	PINMUX_DATA(USB0_OCI_MARK, PORT86_FN1),
971	PINMUX_DATA(USB1_PPON_MARK, PORT87_FN1),
972	PINMUX_DATA(USB1_OCI_MARK, PORT88_FN1),
973
974	/* Port89 */
975	PINMUX_DATA(DREQ0_MARK, PORT89_FN1),
976	PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK, PORT89_FN2, MSEL5CR_0_1),
977	PINMUX_DATA(RSPI_SSL3_A_MARK, PORT89_FN6),
978
979	/* Port90 */
980	PINMUX_DATA(DACK0_MARK, PORT90_FN1),
981	PINMUX_DATA(BBIF2_RXD2_PORT90_MARK, PORT90_FN2, MSEL5CR_0_1),
982	PINMUX_DATA(RSPI_SSL2_A_MARK, PORT90_FN6),
983	PINMUX_DATA(WAIT_PORT90_MARK, PORT90_FN7, MSEL5CR_2_1),
984
985	/* Port91 */
986	PINMUX_DATA(MEMC_AD0_MARK, PORT91_FN1),
987	PINMUX_DATA(BBIF1_RXD_MARK, PORT91_FN2),
988	PINMUX_DATA(SCIFA5_TXD_PORT91_MARK, PORT91_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
989	PINMUX_DATA(LCD1_D5_MARK, PORT91_FN7),
990
991	/* Port92 */
992	PINMUX_DATA(MEMC_AD1_MARK, PORT92_FN1),
993	PINMUX_DATA(BBIF1_TSYNC_MARK, PORT92_FN2),
994	PINMUX_DATA(SCIFA5_RXD_PORT92_MARK, PORT92_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
995	PINMUX_DATA(STP0_IPD1_MARK, PORT92_FN6),
996	PINMUX_DATA(LCD1_D6_MARK, PORT92_FN7),
997
998	/* Port93 */
999	PINMUX_DATA(MEMC_AD2_MARK, PORT93_FN1),
1000	PINMUX_DATA(BBIF1_TSCK_MARK, PORT93_FN2),
1001	PINMUX_DATA(SCIFA4_TXD_PORT93_MARK, PORT93_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1002	PINMUX_DATA(STP0_IPD3_MARK, PORT93_FN6),
1003	PINMUX_DATA(LCD1_D8_MARK, PORT93_FN7),
1004
1005	/* Port94 */
1006	PINMUX_DATA(MEMC_AD3_MARK, PORT94_FN1),
1007	PINMUX_DATA(BBIF1_TXD_MARK, PORT94_FN2),
1008	PINMUX_DATA(SCIFA4_RXD_PORT94_MARK, PORT94_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1009	PINMUX_DATA(STP0_IPD4_MARK, PORT94_FN6),
1010	PINMUX_DATA(LCD1_D9_MARK, PORT94_FN7),
1011
1012	/* Port95 */
1013	PINMUX_DATA(MEMC_CS1_MARK, PORT95_FN1, MSEL4CR_6_0),
1014	PINMUX_DATA(MEMC_A1_MARK, PORT95_FN1, MSEL4CR_6_1),
1015
1016	PINMUX_DATA(SCIFA2_CTS_MARK, PORT95_FN2),
1017	PINMUX_DATA(SIM_RST_MARK, PORT95_FN4),
1018	PINMUX_DATA(VIO0_D14_PORT95_MARK, PORT95_FN7, MSEL5CR_27_1),
1019	PINMUX_DATA(IRQ22_MARK, PORT95_FN0),
1020
1021	/* Port96 */
1022	PINMUX_DATA(MEMC_ADV_MARK, PORT96_FN1, MSEL4CR_6_0),
1023	PINMUX_DATA(MEMC_DREQ0_MARK, PORT96_FN1, MSEL4CR_6_1),
1024
1025	PINMUX_DATA(SCIFA2_RTS_MARK, PORT96_FN2),
1026	PINMUX_DATA(SIM_CLK_MARK, PORT96_FN4),
1027	PINMUX_DATA(VIO0_D15_PORT96_MARK, PORT96_FN7, MSEL5CR_27_1),
1028	PINMUX_DATA(IRQ23_MARK, PORT96_FN0),
1029
1030	/* Port97 */
1031	PINMUX_DATA(MEMC_AD4_MARK, PORT97_FN1),
1032	PINMUX_DATA(BBIF1_RSCK_MARK, PORT97_FN2),
1033	PINMUX_DATA(LCD1_CS_MARK, PORT97_FN6),
1034	PINMUX_DATA(LCD1_HSYN_MARK, PORT97_FN7),
1035	PINMUX_DATA(IRQ12_PORT97_MARK, PORT97_FN0, MSEL1CR_12_0),
1036
1037	/* Port98 */
1038	PINMUX_DATA(MEMC_AD5_MARK, PORT98_FN1),
1039	PINMUX_DATA(BBIF1_RSYNC_MARK, PORT98_FN2),
1040	PINMUX_DATA(LCD1_VSYN_MARK, PORT98_FN7),
1041	PINMUX_DATA(IRQ13_PORT98_MARK, PORT98_FN0, MSEL1CR_13_0),
1042
1043	/* Port99 */
1044	PINMUX_DATA(MEMC_AD6_MARK, PORT99_FN1),
1045	PINMUX_DATA(BBIF1_FLOW_MARK, PORT99_FN2),
1046	PINMUX_DATA(LCD1_WR_MARK, PORT99_FN6),
1047	PINMUX_DATA(LCD1_DCK_MARK, PORT99_FN7),
1048	PINMUX_DATA(IRQ14_PORT99_MARK, PORT99_FN0, MSEL1CR_14_0),
1049
1050	/* Port100 */
1051	PINMUX_DATA(MEMC_AD7_MARK, PORT100_FN1),
1052	PINMUX_DATA(BBIF1_RX_FLOW_N_MARK, PORT100_FN2),
1053	PINMUX_DATA(LCD1_DON_MARK, PORT100_FN7),
1054	PINMUX_DATA(IRQ15_PORT100_MARK, PORT100_FN0, MSEL1CR_15_0),
1055
1056	/* Port101 */
1057	PINMUX_DATA(FCE0_MARK, PORT101_FN1),
1058
1059	/* Port102 */
1060	PINMUX_DATA(FRB_MARK, PORT102_FN1),
1061	PINMUX_DATA(LCD0_LCLK_PORT102_MARK, PORT102_FN4, MSEL5CR_6_0),
1062
1063	/* Port103 */
1064	PINMUX_DATA(CS5B_MARK, PORT103_FN1),
1065	PINMUX_DATA(FCE1_MARK, PORT103_FN2),
1066	PINMUX_DATA(MMC1_CLK_PORT103_MARK, PORT103_FN3, MSEL4CR_15_1),
1067
1068	/* Port104 */
1069	PINMUX_DATA(CS6A_MARK, PORT104_FN1),
1070	PINMUX_DATA(MMC1_CMD_PORT104_MARK, PORT104_FN3, MSEL4CR_15_1),
1071	PINMUX_DATA(IRQ11_MARK, PORT104_FN0),
1072
1073	/* Port105 */
1074	PINMUX_DATA(CS5A_PORT105_MARK, PORT105_FN1, MSEL5CR_2_0),
1075	PINMUX_DATA(SCIFA3_RTS_PORT105_MARK, PORT105_FN4, MSEL5CR_8_0),
1076
1077	/* Port106 */
1078	PINMUX_DATA(IOIS16_MARK, PORT106_FN1),
1079	PINMUX_DATA(IDE_EXBUF_ENB_MARK, PORT106_FN6),
1080
1081	/* Port107 - Port115 Function */
1082	PINMUX_DATA(WE3_ICIOWR_MARK, PORT107_FN1),
1083	PINMUX_DATA(WE2_ICIORD_MARK, PORT108_FN1),
1084	PINMUX_DATA(CS0_MARK, PORT109_FN1),
1085	PINMUX_DATA(CS2_MARK, PORT110_FN1),
1086	PINMUX_DATA(CS4_MARK, PORT111_FN1),
1087	PINMUX_DATA(WE1_MARK, PORT112_FN1),
1088	PINMUX_DATA(WE0_FWE_MARK, PORT113_FN1),
1089	PINMUX_DATA(RDWR_MARK, PORT114_FN1),
1090	PINMUX_DATA(RD_FSC_MARK, PORT115_FN1),
1091
1092	/* Port116 */
1093	PINMUX_DATA(A25_MARK, PORT116_FN1),
1094	PINMUX_DATA(MSIOF0_SS2_MARK, PORT116_FN2),
1095	PINMUX_DATA(MSIOF1_SS2_PORT116_MARK, PORT116_FN3, MSEL4CR_10_0),
1096	PINMUX_DATA(SCIFA3_SCK_PORT116_MARK, PORT116_FN4, MSEL5CR_8_0),
1097	PINMUX_DATA(GPO1_MARK, PORT116_FN5),
1098
1099	/* Port117 */
1100	PINMUX_DATA(A24_MARK, PORT117_FN1),
1101	PINMUX_DATA(MSIOF0_SS1_MARK, PORT117_FN2),
1102	PINMUX_DATA(MSIOF1_SS1_PORT117_MARK, PORT117_FN3, MSEL4CR_10_0),
1103	PINMUX_DATA(SCIFA3_CTS_PORT117_MARK, PORT117_FN4, MSEL5CR_8_0),
1104	PINMUX_DATA(GPO0_MARK, PORT117_FN5),
1105
1106	/* Port118 */
1107	PINMUX_DATA(A23_MARK, PORT118_FN1),
1108	PINMUX_DATA(MSIOF0_MCK1_MARK, PORT118_FN2),
1109	PINMUX_DATA(MSIOF1_RXD_PORT118_MARK, PORT118_FN3, MSEL4CR_10_0),
1110	PINMUX_DATA(GPI1_MARK, PORT118_FN5),
1111	PINMUX_DATA(IRQ9_PORT118_MARK, PORT118_FN0, MSEL1CR_9_0),
1112
1113	/* Port119 */
1114	PINMUX_DATA(A22_MARK, PORT119_FN1),
1115	PINMUX_DATA(MSIOF0_MCK0_MARK, PORT119_FN2),
1116	PINMUX_DATA(MSIOF1_TXD_PORT119_MARK, PORT119_FN3, MSEL4CR_10_0),
1117	PINMUX_DATA(GPI0_MARK, PORT119_FN5),
1118	PINMUX_DATA(IRQ8_MARK, PORT119_FN0),
1119
1120	/* Port120 */
1121	PINMUX_DATA(A21_MARK, PORT120_FN1),
1122	PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2),
1123	PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0),
1124	PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_1),
1125
1126	/* Port121 */
1127	PINMUX_DATA(A20_MARK, PORT121_FN1),
1128	PINMUX_DATA(MSIOF0_RSCK_MARK, PORT121_FN2),
1129	PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK, PORT121_FN3, MSEL4CR_10_0),
1130	PINMUX_DATA(IRQ6_PORT121_MARK, PORT121_FN0, MSEL1CR_6_0),
1131
1132	/* Port122 */
1133	PINMUX_DATA(A19_MARK, PORT122_FN1),
1134	PINMUX_DATA(MSIOF0_RXD_MARK, PORT122_FN2),
1135
1136	/* Port123 */
1137	PINMUX_DATA(A18_MARK, PORT123_FN1),
1138	PINMUX_DATA(MSIOF0_TSCK_MARK, PORT123_FN2),
1139
1140	/* Port124 */
1141	PINMUX_DATA(A17_MARK, PORT124_FN1),
1142	PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT124_FN2),
1143
1144	/* Port125 - Port141 Function */
1145	PINMUX_DATA(A16_MARK, PORT125_FN1),
1146	PINMUX_DATA(A15_MARK, PORT126_FN1),
1147	PINMUX_DATA(A14_MARK, PORT127_FN1),
1148	PINMUX_DATA(A13_MARK, PORT128_FN1),
1149	PINMUX_DATA(A12_MARK, PORT129_FN1),
1150	PINMUX_DATA(A11_MARK, PORT130_FN1),
1151	PINMUX_DATA(A10_MARK, PORT131_FN1),
1152	PINMUX_DATA(A9_MARK, PORT132_FN1),
1153	PINMUX_DATA(A8_MARK, PORT133_FN1),
1154	PINMUX_DATA(A7_MARK, PORT134_FN1),
1155	PINMUX_DATA(A6_MARK, PORT135_FN1),
1156	PINMUX_DATA(A5_FCDE_MARK, PORT136_FN1),
1157	PINMUX_DATA(A4_FOE_MARK, PORT137_FN1),
1158	PINMUX_DATA(A3_MARK, PORT138_FN1),
1159	PINMUX_DATA(A2_MARK, PORT139_FN1),
1160	PINMUX_DATA(A1_MARK, PORT140_FN1),
1161	PINMUX_DATA(CKO_MARK, PORT141_FN1),
1162
1163	/* Port142 - Port157 Function1 */
1164	PINMUX_DATA(D15_NAF15_MARK, PORT142_FN1),
1165	PINMUX_DATA(D14_NAF14_MARK, PORT143_FN1),
1166	PINMUX_DATA(D13_NAF13_MARK, PORT144_FN1),
1167	PINMUX_DATA(D12_NAF12_MARK, PORT145_FN1),
1168	PINMUX_DATA(D11_NAF11_MARK, PORT146_FN1),
1169	PINMUX_DATA(D10_NAF10_MARK, PORT147_FN1),
1170	PINMUX_DATA(D9_NAF9_MARK, PORT148_FN1),
1171	PINMUX_DATA(D8_NAF8_MARK, PORT149_FN1),
1172	PINMUX_DATA(D7_NAF7_MARK, PORT150_FN1),
1173	PINMUX_DATA(D6_NAF6_MARK, PORT151_FN1),
1174	PINMUX_DATA(D5_NAF5_MARK, PORT152_FN1),
1175	PINMUX_DATA(D4_NAF4_MARK, PORT153_FN1),
1176	PINMUX_DATA(D3_NAF3_MARK, PORT154_FN1),
1177	PINMUX_DATA(D2_NAF2_MARK, PORT155_FN1),
1178	PINMUX_DATA(D1_NAF1_MARK, PORT156_FN1),
1179	PINMUX_DATA(D0_NAF0_MARK, PORT157_FN1),
1180
1181	/* Port142 - Port149 Function3 */
1182	PINMUX_DATA(MMC1_D7_PORT142_MARK, PORT142_FN3, MSEL4CR_15_1),
1183	PINMUX_DATA(MMC1_D6_PORT143_MARK, PORT143_FN3, MSEL4CR_15_1),
1184	PINMUX_DATA(MMC1_D5_PORT144_MARK, PORT144_FN3, MSEL4CR_15_1),
1185	PINMUX_DATA(MMC1_D4_PORT145_MARK, PORT145_FN3, MSEL4CR_15_1),
1186	PINMUX_DATA(MMC1_D3_PORT146_MARK, PORT146_FN3, MSEL4CR_15_1),
1187	PINMUX_DATA(MMC1_D2_PORT147_MARK, PORT147_FN3, MSEL4CR_15_1),
1188	PINMUX_DATA(MMC1_D1_PORT148_MARK, PORT148_FN3, MSEL4CR_15_1),
1189	PINMUX_DATA(MMC1_D0_PORT149_MARK, PORT149_FN3, MSEL4CR_15_1),
1190
1191	/* Port158 */
1192	PINMUX_DATA(D31_MARK, PORT158_FN1),
1193	PINMUX_DATA(SCIFA3_SCK_PORT158_MARK, PORT158_FN2, MSEL5CR_8_1),
1194	PINMUX_DATA(RMII_REF125CK_MARK, PORT158_FN3),
1195	PINMUX_DATA(LCD0_D21_PORT158_MARK, PORT158_FN4, MSEL5CR_6_1),
1196	PINMUX_DATA(IRDA_FIRSEL_MARK, PORT158_FN5),
1197	PINMUX_DATA(IDE_D15_MARK, PORT158_FN6),
1198
1199	/* Port159 */
1200	PINMUX_DATA(D30_MARK, PORT159_FN1),
1201	PINMUX_DATA(SCIFA3_RXD_PORT159_MARK, PORT159_FN2, MSEL5CR_8_1),
1202	PINMUX_DATA(RMII_REF50CK_MARK, PORT159_FN3),
1203	PINMUX_DATA(LCD0_D23_PORT159_MARK, PORT159_FN4, MSEL5CR_6_1),
1204	PINMUX_DATA(IDE_D14_MARK, PORT159_FN6),
1205
1206	/* Port160 */
1207	PINMUX_DATA(D29_MARK, PORT160_FN1),
1208	PINMUX_DATA(SCIFA3_TXD_PORT160_MARK, PORT160_FN2, MSEL5CR_8_1),
1209	PINMUX_DATA(LCD0_D22_PORT160_MARK, PORT160_FN4, MSEL5CR_6_1),
1210	PINMUX_DATA(VIO1_HD_MARK, PORT160_FN5),
1211	PINMUX_DATA(IDE_D13_MARK, PORT160_FN6),
1212
1213	/* Port161 */
1214	PINMUX_DATA(D28_MARK, PORT161_FN1),
1215	PINMUX_DATA(SCIFA3_RTS_PORT161_MARK, PORT161_FN2, MSEL5CR_8_1),
1216	PINMUX_DATA(ET_RX_DV_MARK, PORT161_FN3),
1217	PINMUX_DATA(LCD0_D20_PORT161_MARK, PORT161_FN4, MSEL5CR_6_1),
1218	PINMUX_DATA(IRDA_IN_MARK, PORT161_FN5),
1219	PINMUX_DATA(IDE_D12_MARK, PORT161_FN6),
1220
1221	/* Port162 */
1222	PINMUX_DATA(D27_MARK, PORT162_FN1),
1223	PINMUX_DATA(SCIFA3_CTS_PORT162_MARK, PORT162_FN2, MSEL5CR_8_1),
1224	PINMUX_DATA(LCD0_D19_PORT162_MARK, PORT162_FN4, MSEL5CR_6_1),
1225	PINMUX_DATA(IRDA_OUT_MARK, PORT162_FN5),
1226	PINMUX_DATA(IDE_D11_MARK, PORT162_FN6),
1227
1228	/* Port163 */
1229	PINMUX_DATA(D26_MARK, PORT163_FN1),
1230	PINMUX_DATA(MSIOF2_SS2_MARK, PORT163_FN2),
1231	PINMUX_DATA(ET_COL_MARK, PORT163_FN3),
1232	PINMUX_DATA(LCD0_D18_PORT163_MARK, PORT163_FN4, MSEL5CR_6_1),
1233	PINMUX_DATA(IROUT_MARK, PORT163_FN5),
1234	PINMUX_DATA(IDE_D10_MARK, PORT163_FN6),
1235
1236	/* Port164 */
1237	PINMUX_DATA(D25_MARK, PORT164_FN1),
1238	PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT164_FN2),
1239	PINMUX_DATA(ET_PHY_INT_MARK, PORT164_FN3),
1240	PINMUX_DATA(LCD0_RD_MARK, PORT164_FN4),
1241	PINMUX_DATA(IDE_D9_MARK, PORT164_FN6),
1242
1243	/* Port165 */
1244	PINMUX_DATA(D24_MARK, PORT165_FN1),
1245	PINMUX_DATA(MSIOF2_RXD_MARK, PORT165_FN2),
1246	PINMUX_DATA(LCD0_LCLK_PORT165_MARK, PORT165_FN4, MSEL5CR_6_1),
1247	PINMUX_DATA(IDE_D8_MARK, PORT165_FN6),
1248
1249	/* Port166 - Port171 Function1 */
1250	PINMUX_DATA(D21_MARK, PORT166_FN1),
1251	PINMUX_DATA(D20_MARK, PORT167_FN1),
1252	PINMUX_DATA(D19_MARK, PORT168_FN1),
1253	PINMUX_DATA(D18_MARK, PORT169_FN1),
1254	PINMUX_DATA(D17_MARK, PORT170_FN1),
1255	PINMUX_DATA(D16_MARK, PORT171_FN1),
1256
1257	/* Port166 - Port171 Function3 */
1258	PINMUX_DATA(ET_ETXD5_MARK, PORT166_FN3),
1259	PINMUX_DATA(ET_ETXD4_MARK, PORT167_FN3),
1260	PINMUX_DATA(ET_ETXD3_MARK, PORT168_FN3),
1261	PINMUX_DATA(ET_ETXD2_MARK, PORT169_FN3),
1262	PINMUX_DATA(ET_ETXD1_MARK, PORT170_FN3),
1263	PINMUX_DATA(ET_ETXD0_MARK, PORT171_FN3),
1264
1265	/* Port166 - Port171 Function6 */
1266	PINMUX_DATA(IDE_D5_MARK, PORT166_FN6),
1267	PINMUX_DATA(IDE_D4_MARK, PORT167_FN6),
1268	PINMUX_DATA(IDE_D3_MARK, PORT168_FN6),
1269	PINMUX_DATA(IDE_D2_MARK, PORT169_FN6),
1270	PINMUX_DATA(IDE_D1_MARK, PORT170_FN6),
1271	PINMUX_DATA(IDE_D0_MARK, PORT171_FN6),
1272
1273	/* Port167 - Port171 IRQ */
1274	PINMUX_DATA(IRQ31_PORT167_MARK, PORT167_FN0, MSEL1CR_31_0),
1275	PINMUX_DATA(IRQ27_PORT168_MARK, PORT168_FN0, MSEL1CR_27_0),
1276	PINMUX_DATA(IRQ28_PORT169_MARK, PORT169_FN0, MSEL1CR_28_0),
1277	PINMUX_DATA(IRQ29_PORT170_MARK, PORT170_FN0, MSEL1CR_29_0),
1278	PINMUX_DATA(IRQ30_PORT171_MARK, PORT171_FN0, MSEL1CR_30_0),
1279
1280	/* Port172 */
1281	PINMUX_DATA(D23_MARK, PORT172_FN1),
1282	PINMUX_DATA(SCIFB_RTS_PORT172_MARK, PORT172_FN2, MSEL5CR_17_1),
1283	PINMUX_DATA(ET_ETXD7_MARK, PORT172_FN3),
1284	PINMUX_DATA(IDE_D7_MARK, PORT172_FN6),
1285	PINMUX_DATA(IRQ4_PORT172_MARK, PORT172_FN0, MSEL1CR_4_1),
1286
1287	/* Port173 */
1288	PINMUX_DATA(D22_MARK, PORT173_FN1),
1289	PINMUX_DATA(SCIFB_CTS_PORT173_MARK, PORT173_FN2, MSEL5CR_17_1),
1290	PINMUX_DATA(ET_ETXD6_MARK, PORT173_FN3),
1291	PINMUX_DATA(IDE_D6_MARK, PORT173_FN6),
1292	PINMUX_DATA(IRQ6_PORT173_MARK, PORT173_FN0, MSEL1CR_6_1),
1293
1294	/* Port174 */
1295	PINMUX_DATA(A26_MARK, PORT174_FN1),
1296	PINMUX_DATA(MSIOF0_TXD_MARK, PORT174_FN2),
1297	PINMUX_DATA(ET_RX_CLK_MARK, PORT174_FN3),
1298	PINMUX_DATA(SCIFA3_RXD_PORT174_MARK, PORT174_FN4, MSEL5CR_8_0),
1299
1300	/* Port175 */
1301	PINMUX_DATA(A0_MARK, PORT175_FN1),
1302	PINMUX_DATA(BS_MARK, PORT175_FN2),
1303	PINMUX_DATA(ET_WOL_MARK, PORT175_FN3),
1304	PINMUX_DATA(SCIFA3_TXD_PORT175_MARK, PORT175_FN4, MSEL5CR_8_0),
1305
1306	/* Port176 */
1307	PINMUX_DATA(ET_GTX_CLK_MARK, PORT176_FN3),
1308
1309	/* Port177 */
1310	PINMUX_DATA(WAIT_PORT177_MARK, PORT177_FN1, MSEL5CR_2_0),
1311	PINMUX_DATA(ET_LINK_MARK, PORT177_FN3),
1312	PINMUX_DATA(IDE_IOWR_MARK, PORT177_FN6),
1313	PINMUX_DATA(SDHI2_WP_PORT177_MARK, PORT177_FN7, MSEL5CR_19_1),
1314
1315	/* Port178 */
1316	PINMUX_DATA(VIO0_D12_MARK, PORT178_FN1),
1317	PINMUX_DATA(VIO1_D4_MARK, PORT178_FN5),
1318	PINMUX_DATA(IDE_IORD_MARK, PORT178_FN6),
1319
1320	/* Port179 */
1321	PINMUX_DATA(VIO0_D11_MARK, PORT179_FN1),
1322	PINMUX_DATA(VIO1_D3_MARK, PORT179_FN5),
1323	PINMUX_DATA(IDE_IORDY_MARK, PORT179_FN6),
1324
1325	/* Port180 */
1326	PINMUX_DATA(VIO0_D10_MARK, PORT180_FN1),
1327	PINMUX_DATA(TPU0TO3_MARK, PORT180_FN4),
1328	PINMUX_DATA(VIO1_D2_MARK, PORT180_FN5),
1329	PINMUX_DATA(IDE_INT_MARK, PORT180_FN6),
1330	PINMUX_DATA(IRQ24_MARK, PORT180_FN0),
1331
1332	/* Port181 */
1333	PINMUX_DATA(VIO0_D9_MARK, PORT181_FN1),
1334	PINMUX_DATA(VIO1_D1_MARK, PORT181_FN5),
1335	PINMUX_DATA(IDE_RST_MARK, PORT181_FN6),
1336
1337	/* Port182 */
1338	PINMUX_DATA(VIO0_D8_MARK, PORT182_FN1),
1339	PINMUX_DATA(VIO1_D0_MARK, PORT182_FN5),
1340	PINMUX_DATA(IDE_DIRECTION_MARK, PORT182_FN6),
1341
1342	/* Port183 */
1343	PINMUX_DATA(DREQ1_MARK, PORT183_FN1),
1344	PINMUX_DATA(BBIF2_TXD2_PORT183_MARK, PORT183_FN2, MSEL5CR_0_1),
1345	PINMUX_DATA(ET_TX_EN_MARK, PORT183_FN3),
1346
1347	/* Port184 */
1348	PINMUX_DATA(DACK1_MARK, PORT184_FN1),
1349	PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK, PORT184_FN2, MSEL5CR_0_1),
1350	PINMUX_DATA(ET_TX_CLK_MARK, PORT184_FN3),
1351
1352	/* Port185 - Port192 Function1 */
1353	PINMUX_DATA(SCIFA1_SCK_MARK, PORT185_FN1),
1354	PINMUX_DATA(SCIFB_RTS_PORT186_MARK, PORT186_FN1, MSEL5CR_17_0),
1355	PINMUX_DATA(SCIFB_CTS_PORT187_MARK, PORT187_FN1, MSEL5CR_17_0),
1356	PINMUX_DATA(SCIFA0_SCK_MARK, PORT188_FN1),
1357	PINMUX_DATA(SCIFB_SCK_PORT190_MARK, PORT190_FN1, MSEL5CR_17_0),
1358	PINMUX_DATA(SCIFB_RXD_PORT191_MARK, PORT191_FN1, MSEL5CR_17_0),
1359	PINMUX_DATA(SCIFB_TXD_PORT192_MARK, PORT192_FN1, MSEL5CR_17_0),
1360
1361	/* Port185 - Port192 Function3 */
1362	PINMUX_DATA(ET_ERXD0_MARK, PORT185_FN3),
1363	PINMUX_DATA(ET_ERXD1_MARK, PORT186_FN3),
1364	PINMUX_DATA(ET_ERXD2_MARK, PORT187_FN3),
1365	PINMUX_DATA(ET_ERXD3_MARK, PORT188_FN3),
1366	PINMUX_DATA(ET_ERXD4_MARK, PORT189_FN3),
1367	PINMUX_DATA(ET_ERXD5_MARK, PORT190_FN3),
1368	PINMUX_DATA(ET_ERXD6_MARK, PORT191_FN3),
1369	PINMUX_DATA(ET_ERXD7_MARK, PORT192_FN3),
1370
1371	/* Port185 - Port192 Function6 */
1372	PINMUX_DATA(STP1_IPCLK_MARK, PORT185_FN6),
1373	PINMUX_DATA(STP1_IPD0_PORT186_MARK, PORT186_FN6, MSEL5CR_23_0),
1374	PINMUX_DATA(STP1_IPEN_PORT187_MARK, PORT187_FN6, MSEL5CR_23_0),
1375	PINMUX_DATA(STP1_IPSYNC_MARK, PORT188_FN6),
1376	PINMUX_DATA(STP0_IPCLK_MARK, PORT189_FN6),
1377	PINMUX_DATA(STP0_IPD0_MARK, PORT190_FN6),
1378	PINMUX_DATA(STP0_IPEN_MARK, PORT191_FN6),
1379	PINMUX_DATA(STP0_IPSYNC_MARK, PORT192_FN6),
1380
1381	/* Port193 */
1382	PINMUX_DATA(SCIFA0_CTS_MARK, PORT193_FN1),
1383	PINMUX_DATA(RMII_CRS_DV_MARK, PORT193_FN3),
1384	PINMUX_DATA(STP1_IPEN_PORT193_MARK, PORT193_FN6, MSEL5CR_23_1), /* ? */
1385	PINMUX_DATA(LCD1_D17_MARK, PORT193_FN7),
1386
1387	/* Port194 */
1388	PINMUX_DATA(SCIFA0_RTS_MARK, PORT194_FN1),
1389	PINMUX_DATA(RMII_RX_ER_MARK, PORT194_FN3),
1390	PINMUX_DATA(STP1_IPD0_PORT194_MARK, PORT194_FN6, MSEL5CR_23_1), /* ? */
1391	PINMUX_DATA(LCD1_D16_MARK, PORT194_FN7),
1392
1393	/* Port195 */
1394	PINMUX_DATA(SCIFA1_RXD_MARK, PORT195_FN1),
1395	PINMUX_DATA(RMII_RXD0_MARK, PORT195_FN3),
1396	PINMUX_DATA(STP1_IPD3_MARK, PORT195_FN6),
1397	PINMUX_DATA(LCD1_D15_MARK, PORT195_FN7),
1398
1399	/* Port196 */
1400	PINMUX_DATA(SCIFA1_TXD_MARK, PORT196_FN1),
1401	PINMUX_DATA(RMII_RXD1_MARK, PORT196_FN3),
1402	PINMUX_DATA(STP1_IPD2_MARK, PORT196_FN6),
1403	PINMUX_DATA(LCD1_D14_MARK, PORT196_FN7),
1404
1405	/* Port197 */
1406	PINMUX_DATA(SCIFA0_RXD_MARK, PORT197_FN1),
1407	PINMUX_DATA(VIO1_CLK_MARK, PORT197_FN5),
1408	PINMUX_DATA(STP1_IPD5_MARK, PORT197_FN6),
1409	PINMUX_DATA(LCD1_D19_MARK, PORT197_FN7),
1410
1411	/* Port198 */
1412	PINMUX_DATA(SCIFA0_TXD_MARK, PORT198_FN1),
1413	PINMUX_DATA(VIO1_VD_MARK, PORT198_FN5),
1414	PINMUX_DATA(STP1_IPD4_MARK, PORT198_FN6),
1415	PINMUX_DATA(LCD1_D18_MARK, PORT198_FN7),
1416
1417	/* Port199 */
1418	PINMUX_DATA(MEMC_NWE_MARK, PORT199_FN1),
1419	PINMUX_DATA(SCIFA2_SCK_PORT199_MARK, PORT199_FN2, MSEL5CR_7_1),
1420	PINMUX_DATA(RMII_TX_EN_MARK, PORT199_FN3),
1421	PINMUX_DATA(SIM_D_PORT199_MARK, PORT199_FN4, MSEL5CR_21_1),
1422	PINMUX_DATA(STP1_IPD1_MARK, PORT199_FN6),
1423	PINMUX_DATA(LCD1_D13_MARK, PORT199_FN7),
1424
1425	/* Port200 */
1426	PINMUX_DATA(MEMC_NOE_MARK, PORT200_FN1),
1427	PINMUX_DATA(SCIFA2_RXD_MARK, PORT200_FN2),
1428	PINMUX_DATA(RMII_TXD0_MARK, PORT200_FN3),
1429	PINMUX_DATA(STP0_IPD7_MARK, PORT200_FN6),
1430	PINMUX_DATA(LCD1_D12_MARK, PORT200_FN7),
1431
1432	/* Port201 */
1433	PINMUX_DATA(MEMC_WAIT_MARK, PORT201_FN1, MSEL4CR_6_0),
1434	PINMUX_DATA(MEMC_DREQ1_MARK, PORT201_FN1, MSEL4CR_6_1),
1435
1436	PINMUX_DATA(SCIFA2_TXD_MARK, PORT201_FN2),
1437	PINMUX_DATA(RMII_TXD1_MARK, PORT201_FN3),
1438	PINMUX_DATA(STP0_IPD6_MARK, PORT201_FN6),
1439	PINMUX_DATA(LCD1_D11_MARK, PORT201_FN7),
1440
1441	/* Port202 */
1442	PINMUX_DATA(MEMC_BUSCLK_MARK, PORT202_FN1, MSEL4CR_6_0),
1443	PINMUX_DATA(MEMC_A0_MARK, PORT202_FN1, MSEL4CR_6_1),
1444
1445	PINMUX_DATA(MSIOF1_SS2_PORT202_MARK, PORT202_FN2, MSEL4CR_10_1),
1446	PINMUX_DATA(RMII_MDC_MARK, PORT202_FN3),
1447	PINMUX_DATA(TPU0TO2_PORT202_MARK, PORT202_FN4, MSEL5CR_25_1),
1448	PINMUX_DATA(IDE_CS0_MARK, PORT202_FN6),
1449	PINMUX_DATA(SDHI2_CD_PORT202_MARK, PORT202_FN7, MSEL5CR_19_1),
1450	PINMUX_DATA(IRQ21_MARK, PORT202_FN0),
1451
1452	/* Port203 - Port208 Function1 */
1453	PINMUX_DATA(SDHI2_CLK_MARK, PORT203_FN1),
1454	PINMUX_DATA(SDHI2_CMD_MARK, PORT204_FN1),
1455	PINMUX_DATA(SDHI2_D0_MARK, PORT205_FN1),
1456	PINMUX_DATA(SDHI2_D1_MARK, PORT206_FN1),
1457	PINMUX_DATA(SDHI2_D2_MARK, PORT207_FN1),
1458	PINMUX_DATA(SDHI2_D3_MARK, PORT208_FN1),
1459
1460	/* Port203 - Port208 Function3 */
1461	PINMUX_DATA(ET_TX_ER_MARK, PORT203_FN3),
1462	PINMUX_DATA(ET_RX_ER_MARK, PORT204_FN3),
1463	PINMUX_DATA(ET_CRS_MARK, PORT205_FN3),
1464	PINMUX_DATA(ET_MDC_MARK, PORT206_FN3),
1465	PINMUX_DATA(ET_MDIO_MARK, PORT207_FN3),
1466	PINMUX_DATA(RMII_MDIO_MARK, PORT208_FN3),
1467
1468	/* Port203 - Port208 Function6 */
1469	PINMUX_DATA(IDE_A2_MARK, PORT203_FN6),
1470	PINMUX_DATA(IDE_A1_MARK, PORT204_FN6),
1471	PINMUX_DATA(IDE_A0_MARK, PORT205_FN6),
1472	PINMUX_DATA(IDE_IODACK_MARK, PORT206_FN6),
1473	PINMUX_DATA(IDE_IODREQ_MARK, PORT207_FN6),
1474	PINMUX_DATA(IDE_CS1_MARK, PORT208_FN6),
1475
1476	/* Port203 - Port208 Function7 */
1477	PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1478	PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1479	PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1),
1480	PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1),
1481	PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1482	PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1483
1484	/* Port209 */
1485	PINMUX_DATA(VBUS_MARK, PORT209_FN1),
1486	PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_0),
1487
1488	/* Port210 */
1489	PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1),
1490	PINMUX_DATA(HDMI_HPD_MARK, PORT210_FN1),
1491
1492	/* Port211 */
1493	PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1),
1494	PINMUX_DATA(HDMI_CEC_MARK, PORT211_FN1),
1495
1496	/* SDENC */
1497	PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
1498	PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
1499
1500	/* SYSC */
1501	PINMUX_DATA(RESETP_PULLUP_MARK, MSEL4CR_4_0),
1502	PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1),
1503
1504	/* DEBUG */
1505	PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0),
1506	PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1),
1507
1508	PINMUX_DATA(TRACEAUD_FROM_VIO_MARK, MSEL5CR_30_0, MSEL5CR_29_0),
1509	PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1),
1510	PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
1511	};
1512
1513	#define __I (SH_PFC_PIN_CFG_INPUT)
1514	#define __O (SH_PFC_PIN_CFG_OUTPUT)
1515	#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1516	#define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
1517	#define __PU (SH_PFC_PIN_CFG_PULL_UP)
1518	#define __PUD (SH_PFC_PIN_CFG_PULL_UP_DOWN)
1519
1520	#define R8A7740_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD)
1521	#define R8A7740_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU)
1522	#define R8A7740_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD)
1523	#define R8A7740_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO)
1524	#define R8A7740_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD)
1525	#define R8A7740_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU)
1526	#define R8A7740_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
1527	#define R8A7740_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
1528	#define R8A7740_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD)
1529
1530	static const struct sh_pfc_pin pinmux_pins[] = {
1531	/* Table 56-1 (I/O and Pull U/D) */
1532	R8A7740_PIN_IO_PD(0), R8A7740_PIN_IO_PD(1),
1533	R8A7740_PIN_IO_PD(2), R8A7740_PIN_IO_PD(3),
1534	R8A7740_PIN_IO_PD(4), R8A7740_PIN_IO_PD(5),
1535	R8A7740_PIN_IO_PD(6), R8A7740_PIN_IO(7),
1536	R8A7740_PIN_IO(8), R8A7740_PIN_IO(9),
1537	R8A7740_PIN_IO_PD(10), R8A7740_PIN_IO_PD(11),
1538	R8A7740_PIN_IO_PD(12), R8A7740_PIN_IO_PU_PD(13),
1539	R8A7740_PIN_IO_PD(14), R8A7740_PIN_IO_PD(15),
1540	R8A7740_PIN_IO_PD(16), R8A7740_PIN_IO_PD(17),
1541	R8A7740_PIN_IO(18), R8A7740_PIN_IO_PU(19),
1542	R8A7740_PIN_IO_PU_PD(20), R8A7740_PIN_IO_PD(21),
1543	R8A7740_PIN_IO_PU_PD(22), R8A7740_PIN_IO(23),
1544	R8A7740_PIN_IO_PU(24), R8A7740_PIN_IO_PU(25),
1545	R8A7740_PIN_IO_PU(26), R8A7740_PIN_IO_PU(27),
1546	R8A7740_PIN_IO_PU(28), R8A7740_PIN_IO_PU(29),
1547	R8A7740_PIN_IO_PU(30), R8A7740_PIN_IO_PD(31),
1548	R8A7740_PIN_IO_PD(32), R8A7740_PIN_IO_PD(33),
1549	R8A7740_PIN_IO_PD(34), R8A7740_PIN_IO_PU(35),
1550	R8A7740_PIN_IO_PU(36), R8A7740_PIN_IO_PD(37),
1551	R8A7740_PIN_IO_PU(38), R8A7740_PIN_IO_PD(39),
1552	R8A7740_PIN_IO_PU_PD(40), R8A7740_PIN_IO_PD(41),
1553	R8A7740_PIN_IO_PD(42), R8A7740_PIN_IO_PU_PD(43),
1554	R8A7740_PIN_IO_PU_PD(44), R8A7740_PIN_IO_PU_PD(45),
1555	R8A7740_PIN_IO_PU_PD(46), R8A7740_PIN_IO_PU_PD(47),
1556	R8A7740_PIN_IO_PU_PD(48), R8A7740_PIN_IO_PU_PD(49),
1557	R8A7740_PIN_IO_PU_PD(50), R8A7740_PIN_IO_PD(51),
1558	R8A7740_PIN_IO_PD(52), R8A7740_PIN_IO_PD(53),
1559	R8A7740_PIN_IO_PD(54), R8A7740_PIN_IO_PU_PD(55),
1560	R8A7740_PIN_IO_PU_PD(56), R8A7740_PIN_IO_PU_PD(57),
1561	R8A7740_PIN_IO_PU_PD(58), R8A7740_PIN_IO_PU_PD(59),
1562	R8A7740_PIN_IO_PU_PD(60), R8A7740_PIN_IO_PD(61),
1563	R8A7740_PIN_IO_PD(62), R8A7740_PIN_IO_PD(63),
1564	R8A7740_PIN_IO_PD(64), R8A7740_PIN_IO_PD(65),
1565	R8A7740_PIN_IO_PU_PD(66), R8A7740_PIN_IO_PU_PD(67),
1566	R8A7740_PIN_IO_PU_PD(68), R8A7740_PIN_IO_PU_PD(69),
1567	R8A7740_PIN_IO_PU_PD(70), R8A7740_PIN_IO_PU_PD(71),
1568	R8A7740_PIN_IO_PU_PD(72), R8A7740_PIN_IO_PU_PD(73),
1569	R8A7740_PIN_IO_PU_PD(74), R8A7740_PIN_IO_PU_PD(75),
1570	R8A7740_PIN_IO_PU_PD(76), R8A7740_PIN_IO_PU_PD(77),
1571	R8A7740_PIN_IO_PU_PD(78), R8A7740_PIN_IO_PU_PD(79),
1572	R8A7740_PIN_IO_PU_PD(80), R8A7740_PIN_IO_PU_PD(81),
1573	R8A7740_PIN_IO(82), R8A7740_PIN_IO_PU_PD(83),
1574	R8A7740_PIN_IO(84), R8A7740_PIN_IO_PD(85),
1575	R8A7740_PIN_IO_PD(86), R8A7740_PIN_IO_PD(87),
1576	R8A7740_PIN_IO_PD(88), R8A7740_PIN_IO_PD(89),
1577	R8A7740_PIN_IO_PD(90), R8A7740_PIN_IO_PU_PD(91),
1578	R8A7740_PIN_IO_PU_PD(92), R8A7740_PIN_IO_PU_PD(93),
1579	R8A7740_PIN_IO_PU_PD(94), R8A7740_PIN_IO_PU_PD(95),
1580	R8A7740_PIN_IO_PU_PD(96), R8A7740_PIN_IO_PU_PD(97),
1581	R8A7740_PIN_IO_PU_PD(98), R8A7740_PIN_IO_PU_PD(99),
1582	R8A7740_PIN_IO_PU_PD(100), R8A7740_PIN_IO(101),
1583	R8A7740_PIN_IO_PU(102), R8A7740_PIN_IO_PU_PD(103),
1584	R8A7740_PIN_IO_PU(104), R8A7740_PIN_IO_PU(105),
1585	R8A7740_PIN_IO_PU_PD(106), R8A7740_PIN_IO(107),
1586	R8A7740_PIN_IO(108), R8A7740_PIN_IO(109),
1587	R8A7740_PIN_IO(110), R8A7740_PIN_IO(111),
1588	R8A7740_PIN_IO(112), R8A7740_PIN_IO(113),
1589	R8A7740_PIN_IO_PU_PD(114), R8A7740_PIN_IO(115),
1590	R8A7740_PIN_IO_PD(116), R8A7740_PIN_IO_PD(117),
1591	R8A7740_PIN_IO_PD(118), R8A7740_PIN_IO_PD(119),
1592	R8A7740_PIN_IO_PD(120), R8A7740_PIN_IO_PD(121),
1593	R8A7740_PIN_IO_PD(122), R8A7740_PIN_IO_PD(123),
1594	R8A7740_PIN_IO_PD(124), R8A7740_PIN_IO(125),
1595	R8A7740_PIN_IO(126), R8A7740_PIN_IO(127),
1596	R8A7740_PIN_IO(128), R8A7740_PIN_IO(129),
1597	R8A7740_PIN_IO(130), R8A7740_PIN_IO(131),
1598	R8A7740_PIN_IO(132), R8A7740_PIN_IO(133),
1599	R8A7740_PIN_IO(134), R8A7740_PIN_IO(135),
1600	R8A7740_PIN_IO(136), R8A7740_PIN_IO(137),
1601	R8A7740_PIN_IO(138), R8A7740_PIN_IO(139),
1602	R8A7740_PIN_IO(140), R8A7740_PIN_IO(141),
1603	R8A7740_PIN_IO_PU(142), R8A7740_PIN_IO_PU(143),
1604	R8A7740_PIN_IO_PU(144), R8A7740_PIN_IO_PU(145),
1605	R8A7740_PIN_IO_PU(146), R8A7740_PIN_IO_PU(147),
1606	R8A7740_PIN_IO_PU(148), R8A7740_PIN_IO_PU(149),
1607	R8A7740_PIN_IO_PU(150), R8A7740_PIN_IO_PU(151),
1608	R8A7740_PIN_IO_PU(152), R8A7740_PIN_IO_PU(153),
1609	R8A7740_PIN_IO_PU(154), R8A7740_PIN_IO_PU(155),
1610	R8A7740_PIN_IO_PU(156), R8A7740_PIN_IO_PU(157),
1611	R8A7740_PIN_IO_PD(158), R8A7740_PIN_IO_PD(159),
1612	R8A7740_PIN_IO_PU_PD(160), R8A7740_PIN_IO_PD(161),
1613	R8A7740_PIN_IO_PD(162), R8A7740_PIN_IO_PD(163),
1614	R8A7740_PIN_IO_PD(164), R8A7740_PIN_IO_PD(165),
1615	R8A7740_PIN_IO_PU(166), R8A7740_PIN_IO_PU(167),
1616	R8A7740_PIN_IO_PU(168), R8A7740_PIN_IO_PU(169),
1617	R8A7740_PIN_IO_PU(170), R8A7740_PIN_IO_PU(171),
1618	R8A7740_PIN_IO_PD(172), R8A7740_PIN_IO_PD(173),
1619	R8A7740_PIN_IO_PD(174), R8A7740_PIN_IO_PD(175),
1620	R8A7740_PIN_IO_PU(176), R8A7740_PIN_IO_PU_PD(177),
1621	R8A7740_PIN_IO_PU(178), R8A7740_PIN_IO_PD(179),
1622	R8A7740_PIN_IO_PD(180), R8A7740_PIN_IO_PU(181),
1623	R8A7740_PIN_IO_PU(182), R8A7740_PIN_IO(183),
1624	R8A7740_PIN_IO_PD(184), R8A7740_PIN_IO_PD(185),
1625	R8A7740_PIN_IO_PD(186), R8A7740_PIN_IO_PD(187),
1626	R8A7740_PIN_IO_PD(188), R8A7740_PIN_IO_PD(189),
1627	R8A7740_PIN_IO_PD(190), R8A7740_PIN_IO_PD(191),
1628	R8A7740_PIN_IO_PD(192), R8A7740_PIN_IO_PU_PD(193),
1629	R8A7740_PIN_IO_PU_PD(194), R8A7740_PIN_IO_PD(195),
1630	R8A7740_PIN_IO_PU_PD(196), R8A7740_PIN_IO_PD(197),
1631	R8A7740_PIN_IO_PU_PD(198), R8A7740_PIN_IO_PU_PD(199),
1632	R8A7740_PIN_IO_PU_PD(200), R8A7740_PIN_IO_PU(201),
1633	R8A7740_PIN_IO_PU_PD(202), R8A7740_PIN_IO(203),
1634	R8A7740_PIN_IO_PU_PD(204), R8A7740_PIN_IO_PU_PD(205),
1635	R8A7740_PIN_IO_PU_PD(206), R8A7740_PIN_IO_PU_PD(207),
1636	R8A7740_PIN_IO_PU_PD(208), R8A7740_PIN_IO_PD(209),
1637	R8A7740_PIN_IO_PD(210), R8A7740_PIN_IO_PD(211),
1638	};
1639
1640	/* - BSC -------------------------------------------------------------------- */
1641	static const unsigned int bsc_data_pins[] = {
1642	/* D[0:31] */
1643	157, 156, 155, 154, 153, 152, 151, 150,
1644	149, 148, 147, 146, 145, 144, 143, 142,
1645	171, 170, 169, 168, 167, 166, 173, 172,
1646	165, 164, 163, 162, 161, 160, 159, 158,
1647	};
1648	static const unsigned int bsc_data_mux[] = {
1649	D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1650	D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1651	D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1652	D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1653	D16_MARK, D17_MARK, D18_MARK, D19_MARK,
1654	D20_MARK, D21_MARK, D22_MARK, D23_MARK,
1655	D24_MARK, D25_MARK, D26_MARK, D27_MARK,
1656	D28_MARK, D29_MARK, D30_MARK, D31_MARK,
1657	};
1658	static const unsigned int bsc_cs0_pins[] = {
1659	/* CS */
1660	109,
1661	};
1662	static const unsigned int bsc_cs0_mux[] = {
1663	CS0_MARK,
1664	};
1665	static const unsigned int bsc_cs2_pins[] = {
1666	/* CS */
1667	110,
1668	};
1669	static const unsigned int bsc_cs2_mux[] = {
1670	CS2_MARK,
1671	};
1672	static const unsigned int bsc_cs4_pins[] = {
1673	/* CS */
1674	111,
1675	};
1676	static const unsigned int bsc_cs4_mux[] = {
1677	CS4_MARK,
1678	};
1679	static const unsigned int bsc_cs5a_0_pins[] = {
1680	/* CS */
1681	105,
1682	};
1683	static const unsigned int bsc_cs5a_0_mux[] = {
1684	CS5A_PORT105_MARK,
1685	};
1686	static const unsigned int bsc_cs5a_1_pins[] = {
1687	/* CS */
1688	19,
1689	};
1690	static const unsigned int bsc_cs5a_1_mux[] = {
1691	CS5A_PORT19_MARK,
1692	};
1693	static const unsigned int bsc_cs5b_pins[] = {
1694	/* CS */
1695	103,
1696	};
1697	static const unsigned int bsc_cs5b_mux[] = {
1698	CS5B_MARK,
1699	};
1700	static const unsigned int bsc_cs6a_pins[] = {
1701	/* CS */
1702	104,
1703	};
1704	static const unsigned int bsc_cs6a_mux[] = {
1705	CS6A_MARK,
1706	};
1707	static const unsigned int bsc_rd_we_pins[] = {
1708	/* RD, WE[0:3] */
1709	115, 113, 112, 108, 107,
1710	};
1711	static const unsigned int bsc_rd_we_mux[] = {
1712	RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
1713	};
1714	static const unsigned int bsc_bs_pins[] = {
1715	/* BS */
1716	175,
1717	};
1718	static const unsigned int bsc_bs_mux[] = {
1719	BS_MARK,
1720	};
1721	static const unsigned int bsc_rdwr_pins[] = {
1722	/* RDWR */
1723	114,
1724	};
1725	static const unsigned int bsc_rdwr_mux[] = {
1726	RDWR_MARK,
1727	};
1728	/* - CEU0 ------------------------------------------------------------------- */
1729	static const unsigned int ceu0_data_0_7_pins[] = {
1730	/* D[0:7] */
1731	34, 33, 32, 31, 30, 29, 28, 27,
1732	};
1733	static const unsigned int ceu0_data_0_7_mux[] = {
1734	VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
1735	VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
1736	};
1737	static const unsigned int ceu0_data_8_15_0_pins[] = {
1738	/* D[8:15] */
1739	182, 181, 180, 179, 178, 26, 25, 24,
1740	};
1741	static const unsigned int ceu0_data_8_15_0_mux[] = {
1742	VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
1743	VIO0_D12_MARK, VIO0_D13_PORT26_MARK, VIO0_D14_PORT25_MARK,
1744	VIO0_D15_PORT24_MARK,
1745	};
1746	static const unsigned int ceu0_data_8_15_1_pins[] = {
1747	/* D[8:15] */
1748	182, 181, 180, 179, 178, 22, 95, 96,
1749	};
1750	static const unsigned int ceu0_data_8_15_1_mux[] = {
1751	VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
1752	VIO0_D12_MARK, VIO0_D13_PORT22_MARK, VIO0_D14_PORT95_MARK,
1753	VIO0_D15_PORT96_MARK,
1754	};
1755	static const unsigned int ceu0_clk_0_pins[] = {
1756	/* CKO */
1757	36,
1758	};
1759	static const unsigned int ceu0_clk_0_mux[] = {
1760	VIO_CKO_MARK,
1761	};
1762	static const unsigned int ceu0_clk_1_pins[] = {
1763	/* CKO */
1764	14,
1765	};
1766	static const unsigned int ceu0_clk_1_mux[] = {
1767	VIO_CKO1_MARK,
1768	};
1769	static const unsigned int ceu0_clk_2_pins[] = {
1770	/* CKO */
1771	15,
1772	};
1773	static const unsigned int ceu0_clk_2_mux[] = {
1774	VIO_CKO2_MARK,
1775	};
1776	static const unsigned int ceu0_sync_pins[] = {
1777	/* CLK, VD, HD */
1778	35, 39, 37,
1779	};
1780	static const unsigned int ceu0_sync_mux[] = {
1781	VIO0_CLK_MARK, VIO0_VD_MARK, VIO0_HD_MARK,
1782	};
1783	static const unsigned int ceu0_field_pins[] = {
1784	/* FIELD */
1785	38,
1786	};
1787	static const unsigned int ceu0_field_mux[] = {
1788	VIO0_FIELD_MARK,
1789	};
1790	/* - CEU1 ------------------------------------------------------------------- */
1791	static const unsigned int ceu1_data_pins[] = {
1792	/* D[0:7] */
1793	182, 181, 180, 179, 178, 26, 25, 24,
1794	};
1795	static const unsigned int ceu1_data_mux[] = {
1796	VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
1797	VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
1798	};
1799	static const unsigned int ceu1_clk_pins[] = {
1800	/* CKO */
1801	23,
1802	};
1803	static const unsigned int ceu1_clk_mux[] = {
1804	VIO_CKO_1_MARK,
1805	};
1806	static const unsigned int ceu1_sync_pins[] = {
1807	/* CLK, VD, HD */
1808	197, 198, 160,
1809	};
1810	static const unsigned int ceu1_sync_mux[] = {
1811	VIO1_CLK_MARK, VIO1_VD_MARK, VIO1_HD_MARK,
1812	};
1813	static const unsigned int ceu1_field_pins[] = {
1814	/* FIELD */
1815	21,
1816	};
1817	static const unsigned int ceu1_field_mux[] = {
1818	VIO1_FIELD_MARK,
1819	};
1820	/* - FSIA ------------------------------------------------------------------- */
1821	static const unsigned int fsia_mclk_in_pins[] = {
1822	/* CK */
1823	11,
1824	};
1825	static const unsigned int fsia_mclk_in_mux[] = {
1826	FSIACK_MARK,
1827	};
1828	static const unsigned int fsia_mclk_out_pins[] = {
1829	/* OMC */
1830	10,
1831	};
1832	static const unsigned int fsia_mclk_out_mux[] = {
1833	FSIAOMC_MARK,
1834	};
1835	static const unsigned int fsia_sclk_in_pins[] = {
1836	/* ILR, IBT */
1837	12, 13,
1838	};
1839	static const unsigned int fsia_sclk_in_mux[] = {
1840	FSIAILR_MARK, FSIAIBT_MARK,
1841	};
1842	static const unsigned int fsia_sclk_out_pins[] = {
1843	/* OLR, OBT */
1844	7, 8,
1845	};
1846	static const unsigned int fsia_sclk_out_mux[] = {
1847	FSIAOLR_MARK, FSIAOBT_MARK,
1848	};
1849	static const unsigned int fsia_data_in_0_pins[] = {
1850	/* ISLD */
1851	0,
1852	};
1853	static const unsigned int fsia_data_in_0_mux[] = {
1854	FSIAISLD_PORT0_MARK,
1855	};
1856	static const unsigned int fsia_data_in_1_pins[] = {
1857	/* ISLD */
1858	5,
1859	};
1860	static const unsigned int fsia_data_in_1_mux[] = {
1861	FSIAISLD_PORT5_MARK,
1862	};
1863	static const unsigned int fsia_data_out_0_pins[] = {
1864	/* OSLD */
1865	9,
1866	};
1867	static const unsigned int fsia_data_out_0_mux[] = {
1868	FSIAOSLD_MARK,
1869	};
1870	static const unsigned int fsia_data_out_1_pins[] = {
1871	/* OSLD */
1872	0,
1873	};
1874	static const unsigned int fsia_data_out_1_mux[] = {
1875	FSIAOSLD1_MARK,
1876	};
1877	static const unsigned int fsia_data_out_2_pins[] = {
1878	/* OSLD */
1879	1,
1880	};
1881	static const unsigned int fsia_data_out_2_mux[] = {
1882	FSIAOSLD2_MARK,
1883	};
1884	static const unsigned int fsia_spdif_0_pins[] = {
1885	/* SPDIF */
1886	9,
1887	};
1888	static const unsigned int fsia_spdif_0_mux[] = {
1889	FSIASPDIF_PORT9_MARK,
1890	};
1891	static const unsigned int fsia_spdif_1_pins[] = {
1892	/* SPDIF */
1893	18,
1894	};
1895	static const unsigned int fsia_spdif_1_mux[] = {
1896	FSIASPDIF_PORT18_MARK,
1897	};
1898	/* - FSIB ------------------------------------------------------------------- */
1899	static const unsigned int fsib_mclk_in_pins[] = {
1900	/* CK */
1901	11,
1902	};
1903	static const unsigned int fsib_mclk_in_mux[] = {
1904	FSIBCK_MARK,
1905	};
1906	/* - GETHER ----------------------------------------------------------------- */
1907	static const unsigned int gether_rmii_pins[] = {
1908	/* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */
1909	195, 196, 194, 193, 200, 201, 199, 159, 202, 208,
1910	};
1911	static const unsigned int gether_rmii_mux[] = {
1912	RMII_RXD0_MARK, RMII_RXD1_MARK, RMII_RX_ER_MARK, RMII_CRS_DV_MARK,
1913	RMII_TXD0_MARK, RMII_TXD1_MARK, RMII_TX_EN_MARK, RMII_REF50CK_MARK,
1914	RMII_MDC_MARK, RMII_MDIO_MARK,
1915	};
1916	static const unsigned int gether_mii_pins[] = {
1917	/* RXD[0:3], RX_CLK, RX_DV, RX_ER
1918	* TXD[0:3], TX_CLK, TX_EN, TX_ER
1919	* CRS, COL, MDC, MDIO,
1920	*/
1921	185, 186, 187, 188, 174, 161, 204,
1922	171, 170, 169, 168, 184, 183, 203,
1923	205, 163, 206, 207,
1924	};
1925	static const unsigned int gether_mii_mux[] = {
1926	ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
1927	ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
1928	ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
1929	ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
1930	ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
1931	};
1932	static const unsigned int gether_gmii_pins[] = {
1933	/* RXD[0:7], RX_CLK, RX_DV, RX_ER
1934	* TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER
1935	* CRS, COL, MDC, MDIO, REF125CK_MARK,
1936	*/
1937	185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204,
1938	171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203,
1939	205, 163, 206, 207, 158,
1940	};
1941	static const unsigned int gether_gmii_mux[] = {
1942	ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
1943	ET_ERXD4_MARK, ET_ERXD5_MARK, ET_ERXD6_MARK, ET_ERXD7_MARK,
1944	ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
1945	ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
1946	ET_ETXD4_MARK, ET_ETXD5_MARK, ET_ETXD6_MARK, ET_ETXD7_MARK,
1947	ET_GTX_CLK_MARK, ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
1948	ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
1949	RMII_REF125CK_MARK,
1950	};
1951	static const unsigned int gether_int_pins[] = {
1952	/* PHY_INT */
1953	164,
1954	};
1955	static const unsigned int gether_int_mux[] = {
1956	ET_PHY_INT_MARK,
1957	};
1958	static const unsigned int gether_link_pins[] = {
1959	/* LINK */
1960	177,
1961	};
1962	static const unsigned int gether_link_mux[] = {
1963	ET_LINK_MARK,
1964	};
1965	static const unsigned int gether_wol_pins[] = {
1966	/* WOL */
1967	175,
1968	};
1969	static const unsigned int gether_wol_mux[] = {
1970	ET_WOL_MARK,
1971	};
1972	/* - HDMI ------------------------------------------------------------------- */
1973	static const unsigned int hdmi_pins[] = {
1974	/* HPD, CEC */
1975	210, 211,
1976	};
1977	static const unsigned int hdmi_mux[] = {
1978	HDMI_HPD_MARK, HDMI_CEC_MARK,
1979	};
1980	/* - INTC ------------------------------------------------------------------- */
1981	IRQC_PINS_MUX(0, 0, 2);
1982	IRQC_PINS_MUX(0, 1, 13);
1983	IRQC_PIN_MUX(1, 20);
1984	IRQC_PINS_MUX(2, 0, 11);
1985	IRQC_PINS_MUX(2, 1, 12);
1986	IRQC_PINS_MUX(3, 0, 10);
1987	IRQC_PINS_MUX(3, 1, 14);
1988	IRQC_PINS_MUX(4, 0, 15);
1989	IRQC_PINS_MUX(4, 1, 172);
1990	IRQC_PINS_MUX(5, 0, 0);
1991	IRQC_PINS_MUX(5, 1, 1);
1992	IRQC_PINS_MUX(6, 0, 121);
1993	IRQC_PINS_MUX(6, 1, 173);
1994	IRQC_PINS_MUX(7, 0, 120);
1995	IRQC_PINS_MUX(7, 1, 209);
1996	IRQC_PIN_MUX(8, 119);
1997	IRQC_PINS_MUX(9, 0, 118);
1998	IRQC_PINS_MUX(9, 1, 210);
1999	IRQC_PIN_MUX(10, 19);
2000	IRQC_PIN_MUX(11, 104);
2001	IRQC_PINS_MUX(12, 0, 42);
2002	IRQC_PINS_MUX(12, 1, 97);
2003	IRQC_PINS_MUX(13, 0, 64);
2004	IRQC_PINS_MUX(13, 1, 98);
2005	IRQC_PINS_MUX(14, 0, 63);
2006	IRQC_PINS_MUX(14, 1, 99);
2007	IRQC_PINS_MUX(15, 0, 62);
2008	IRQC_PINS_MUX(15, 1, 100);
2009	IRQC_PINS_MUX(16, 0, 68);
2010	IRQC_PINS_MUX(16, 1, 211);
2011	IRQC_PIN_MUX(17, 69);
2012	IRQC_PIN_MUX(18, 70);
2013	IRQC_PIN_MUX(19, 71);
2014	IRQC_PIN_MUX(20, 67);
2015	IRQC_PIN_MUX(21, 202);
2016	IRQC_PIN_MUX(22, 95);
2017	IRQC_PIN_MUX(23, 96);
2018	IRQC_PIN_MUX(24, 180);
2019	IRQC_PIN_MUX(25, 38);
2020	IRQC_PINS_MUX(26, 0, 58);
2021	IRQC_PINS_MUX(26, 1, 81);
2022	IRQC_PINS_MUX(27, 0, 57);
2023	IRQC_PINS_MUX(27, 1, 168);
2024	IRQC_PINS_MUX(28, 0, 56);
2025	IRQC_PINS_MUX(28, 1, 169);
2026	IRQC_PINS_MUX(29, 0, 50);
2027	IRQC_PINS_MUX(29, 1, 170);
2028	IRQC_PINS_MUX(30, 0, 49);
2029	IRQC_PINS_MUX(30, 1, 171);
2030	IRQC_PINS_MUX(31, 0, 41);
2031	IRQC_PINS_MUX(31, 1, 167);
2032
2033	/* - LCD0 ------------------------------------------------------------------- */
2034	static const unsigned int lcd0_data24_0_pins[] = {
2035	/* D[0:23] */
2036	58, 57, 56, 55, 54, 53, 52, 51,
2037	50, 49, 48, 47, 46, 45, 44, 43,
2038	42, 41, 40, 4, 3, 2, 0, 1,
2039	};
2040	static const unsigned int lcd0_data24_0_mux[] = {
2041	LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2042	LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2043	LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2044	LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2045	LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK,
2046	LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK,
2047	LCD0_D23_PORT1_MARK,
2048	};
2049	static const unsigned int lcd0_data24_1_pins[] = {
2050	/* D[0:23] */
2051	58, 57, 56, 55, 54, 53, 52, 51,
2052	50, 49, 48, 47, 46, 45, 44, 43,
2053	42, 41, 163, 162, 161, 158, 160, 159,
2054	};
2055	static const unsigned int lcd0_data24_1_mux[] = {
2056	LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2057	LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2058	LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2059	LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2060	LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK,
2061	LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK,
2062	LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK,
2063	};
2064	static const unsigned int lcd0_display_pins[] = {
2065	/* DON, VCPWC, VEPWC */
2066	61, 59, 60,
2067	};
2068	static const unsigned int lcd0_display_mux[] = {
2069	LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
2070	};
2071	static const unsigned int lcd0_lclk_0_pins[] = {
2072	/* LCLK */
2073	102,
2074	};
2075	static const unsigned int lcd0_lclk_0_mux[] = {
2076	LCD0_LCLK_PORT102_MARK,
2077	};
2078	static const unsigned int lcd0_lclk_1_pins[] = {
2079	/* LCLK */
2080	165,
2081	};
2082	static const unsigned int lcd0_lclk_1_mux[] = {
2083	LCD0_LCLK_PORT165_MARK,
2084	};
2085	static const unsigned int lcd0_sync_pins[] = {
2086	/* VSYN, HSYN, DCK, DISP */
2087	63, 64, 62, 65,
2088	};
2089	static const unsigned int lcd0_sync_mux[] = {
2090	LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK,
2091	};
2092	static const unsigned int lcd0_sys_pins[] = {
2093	/* CS, WR, RD, RS */
2094	64, 62, 164, 65,
2095	};
2096	static const unsigned int lcd0_sys_mux[] = {
2097	LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
2098	};
2099	/* - LCD1 ------------------------------------------------------------------- */
2100	static const unsigned int lcd1_data_pins[] = {
2101	/* D[0:23] */
2102	4, 3, 2, 1, 0, 91, 92, 23,
2103	93, 94, 21, 201, 200, 199, 196, 195,
2104	194, 193, 198, 197, 75, 74, 15, 14,
2105	};
2106	static const unsigned int lcd1_data_mux[] = {
2107	LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2108	LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2109	LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2110	LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2111	LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
2112	LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
2113	};
2114	static const unsigned int lcd1_display_pins[] = {
2115	/* DON, VCPWC, VEPWC */
2116	100, 5, 6,
2117	};
2118	static const unsigned int lcd1_display_mux[] = {
2119	LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK,
2120	};
2121	static const unsigned int lcd1_lclk_pins[] = {
2122	/* LCLK */
2123	40,
2124	};
2125	static const unsigned int lcd1_lclk_mux[] = {
2126	LCD1_LCLK_MARK,
2127	};
2128	static const unsigned int lcd1_sync_pins[] = {
2129	/* VSYN, HSYN, DCK, DISP */
2130	98, 97, 99, 12,
2131	};
2132	static const unsigned int lcd1_sync_mux[] = {
2133	LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK,
2134	};
2135	static const unsigned int lcd1_sys_pins[] = {
2136	/* CS, WR, RD, RS */
2137	97, 99, 13, 12,
2138	};
2139	static const unsigned int lcd1_sys_mux[] = {
2140	LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
2141	};
2142	/* - MMCIF ------------------------------------------------------------------ */
2143	static const unsigned int mmc0_data_0_pins[] = {
2144	/* D[0:7] */
2145	68, 69, 70, 71, 72, 73, 74, 75,
2146	};
2147	static const unsigned int mmc0_data_0_mux[] = {
2148	MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
2149	MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
2150	};
2151	static const unsigned int mmc0_ctrl_0_pins[] = {
2152	/* CMD, CLK */
2153	67, 66,
2154	};
2155	static const unsigned int mmc0_ctrl_0_mux[] = {
2156	MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
2157	};
2158
2159	static const unsigned int mmc0_data_1_pins[] = {
2160	/* D[0:7] */
2161	149, 148, 147, 146, 145, 144, 143, 142,
2162	};
2163	static const unsigned int mmc0_data_1_mux[] = {
2164	MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
2165	MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
2166	};
2167	static const unsigned int mmc0_ctrl_1_pins[] = {
2168	/* CMD, CLK */
2169	104, 103,
2170	};
2171	static const unsigned int mmc0_ctrl_1_mux[] = {
2172	MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
2173	};
2174	/* - SCIFA0 ----------------------------------------------------------------- */
2175	static const unsigned int scifa0_data_pins[] = {
2176	/* RXD, TXD */
2177	197, 198,
2178	};
2179	static const unsigned int scifa0_data_mux[] = {
2180	SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2181	};
2182	static const unsigned int scifa0_clk_pins[] = {
2183	/* SCK */
2184	188,
2185	};
2186	static const unsigned int scifa0_clk_mux[] = {
2187	SCIFA0_SCK_MARK,
2188	};
2189	static const unsigned int scifa0_ctrl_pins[] = {
2190	/* RTS, CTS */
2191	194, 193,
2192	};
2193	static const unsigned int scifa0_ctrl_mux[] = {
2194	SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
2195	};
2196	/* - SCIFA1 ----------------------------------------------------------------- */
2197	static const unsigned int scifa1_data_pins[] = {
2198	/* RXD, TXD */
2199	195, 196,
2200	};
2201	static const unsigned int scifa1_data_mux[] = {
2202	SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2203	};
2204	static const unsigned int scifa1_clk_pins[] = {
2205	/* SCK */
2206	185,
2207	};
2208	static const unsigned int scifa1_clk_mux[] = {
2209	SCIFA1_SCK_MARK,
2210	};
2211	static const unsigned int scifa1_ctrl_pins[] = {
2212	/* RTS, CTS */
2213	23, 21,
2214	};
2215	static const unsigned int scifa1_ctrl_mux[] = {
2216	SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
2217	};
2218	/* - SCIFA2 ----------------------------------------------------------------- */
2219	static const unsigned int scifa2_data_pins[] = {
2220	/* RXD, TXD */
2221	200, 201,
2222	};
2223	static const unsigned int scifa2_data_mux[] = {
2224	SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2225	};
2226	static const unsigned int scifa2_clk_0_pins[] = {
2227	/* SCK */
2228	22,
2229	};
2230	static const unsigned int scifa2_clk_0_mux[] = {
2231	SCIFA2_SCK_PORT22_MARK,
2232	};
2233	static const unsigned int scifa2_clk_1_pins[] = {
2234	/* SCK */
2235	199,
2236	};
2237	static const unsigned int scifa2_clk_1_mux[] = {
2238	SCIFA2_SCK_PORT199_MARK,
2239	};
2240	static const unsigned int scifa2_ctrl_pins[] = {
2241	/* RTS, CTS */
2242	96, 95,
2243	};
2244	static const unsigned int scifa2_ctrl_mux[] = {
2245	SCIFA2_RTS_MARK, SCIFA2_CTS_MARK,
2246	};
2247	/* - SCIFA3 ----------------------------------------------------------------- */
2248	static const unsigned int scifa3_data_0_pins[] = {
2249	/* RXD, TXD */
2250	174, 175,
2251	};
2252	static const unsigned int scifa3_data_0_mux[] = {
2253	SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK,
2254	};
2255	static const unsigned int scifa3_clk_0_pins[] = {
2256	/* SCK */
2257	116,
2258	};
2259	static const unsigned int scifa3_clk_0_mux[] = {
2260	SCIFA3_SCK_PORT116_MARK,
2261	};
2262	static const unsigned int scifa3_ctrl_0_pins[] = {
2263	/* RTS, CTS */
2264	105, 117,
2265	};
2266	static const unsigned int scifa3_ctrl_0_mux[] = {
2267	SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK,
2268	};
2269	static const unsigned int scifa3_data_1_pins[] = {
2270	/* RXD, TXD */
2271	159, 160,
2272	};
2273	static const unsigned int scifa3_data_1_mux[] = {
2274	SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK,
2275	};
2276	static const unsigned int scifa3_clk_1_pins[] = {
2277	/* SCK */
2278	158,
2279	};
2280	static const unsigned int scifa3_clk_1_mux[] = {
2281	SCIFA3_SCK_PORT158_MARK,
2282	};
2283	static const unsigned int scifa3_ctrl_1_pins[] = {
2284	/* RTS, CTS */
2285	161, 162,
2286	};
2287	static const unsigned int scifa3_ctrl_1_mux[] = {
2288	SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK,
2289	};
2290	/* - SCIFA4 ----------------------------------------------------------------- */
2291	static const unsigned int scifa4_data_0_pins[] = {
2292	/* RXD, TXD */
2293	12, 13,
2294	};
2295	static const unsigned int scifa4_data_0_mux[] = {
2296	SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK,
2297	};
2298	static const unsigned int scifa4_data_1_pins[] = {
2299	/* RXD, TXD */
2300	204, 203,
2301	};
2302	static const unsigned int scifa4_data_1_mux[] = {
2303	SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK,
2304	};
2305	static const unsigned int scifa4_data_2_pins[] = {
2306	/* RXD, TXD */
2307	94, 93,
2308	};
2309	static const unsigned int scifa4_data_2_mux[] = {
2310	SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK,
2311	};
2312	static const unsigned int scifa4_clk_0_pins[] = {
2313	/* SCK */
2314	21,
2315	};
2316	static const unsigned int scifa4_clk_0_mux[] = {
2317	SCIFA4_SCK_PORT21_MARK,
2318	};
2319	static const unsigned int scifa4_clk_1_pins[] = {
2320	/* SCK */
2321	205,
2322	};
2323	static const unsigned int scifa4_clk_1_mux[] = {
2324	SCIFA4_SCK_PORT205_MARK,
2325	};
2326	/* - SCIFA5 ----------------------------------------------------------------- */
2327	static const unsigned int scifa5_data_0_pins[] = {
2328	/* RXD, TXD */
2329	10, 20,
2330	};
2331	static const unsigned int scifa5_data_0_mux[] = {
2332	SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK,
2333	};
2334	static const unsigned int scifa5_data_1_pins[] = {
2335	/* RXD, TXD */
2336	207, 208,
2337	};
2338	static const unsigned int scifa5_data_1_mux[] = {
2339	SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK,
2340	};
2341	static const unsigned int scifa5_data_2_pins[] = {
2342	/* RXD, TXD */
2343	92, 91,
2344	};
2345	static const unsigned int scifa5_data_2_mux[] = {
2346	SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK,
2347	};
2348	static const unsigned int scifa5_clk_0_pins[] = {
2349	/* SCK */
2350	23,
2351	};
2352	static const unsigned int scifa5_clk_0_mux[] = {
2353	SCIFA5_SCK_PORT23_MARK,
2354	};
2355	static const unsigned int scifa5_clk_1_pins[] = {
2356	/* SCK */
2357	206,
2358	};
2359	static const unsigned int scifa5_clk_1_mux[] = {
2360	SCIFA5_SCK_PORT206_MARK,
2361	};
2362	/* - SCIFA6 ----------------------------------------------------------------- */
2363	static const unsigned int scifa6_data_pins[] = {
2364	/* RXD, TXD */
2365	25, 26,
2366	};
2367	static const unsigned int scifa6_data_mux[] = {
2368	SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
2369	};
2370	static const unsigned int scifa6_clk_pins[] = {
2371	/* SCK */
2372	24,
2373	};
2374	static const unsigned int scifa6_clk_mux[] = {
2375	SCIFA6_SCK_MARK,
2376	};
2377	/* - SCIFA7 ----------------------------------------------------------------- */
2378	static const unsigned int scifa7_data_pins[] = {
2379	/* RXD, TXD */
2380	0, 1,
2381	};
2382	static const unsigned int scifa7_data_mux[] = {
2383	SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2384	};
2385	/* - SCIFB ------------------------------------------------------------------ */
2386	static const unsigned int scifb_data_0_pins[] = {
2387	/* RXD, TXD */
2388	191, 192,
2389	};
2390	static const unsigned int scifb_data_0_mux[] = {
2391	SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK,
2392	};
2393	static const unsigned int scifb_clk_0_pins[] = {
2394	/* SCK */
2395	190,
2396	};
2397	static const unsigned int scifb_clk_0_mux[] = {
2398	SCIFB_SCK_PORT190_MARK,
2399	};
2400	static const unsigned int scifb_ctrl_0_pins[] = {
2401	/* RTS, CTS */
2402	186, 187,
2403	};
2404	static const unsigned int scifb_ctrl_0_mux[] = {
2405	SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK,
2406	};
2407	static const unsigned int scifb_data_1_pins[] = {
2408	/* RXD, TXD */
2409	3, 4,
2410	};
2411	static const unsigned int scifb_data_1_mux[] = {
2412	SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK,
2413	};
2414	static const unsigned int scifb_clk_1_pins[] = {
2415	/* SCK */
2416	2,
2417	};
2418	static const unsigned int scifb_clk_1_mux[] = {
2419	SCIFB_SCK_PORT2_MARK,
2420	};
2421	static const unsigned int scifb_ctrl_1_pins[] = {
2422	/* RTS, CTS */
2423	172, 173,
2424	};
2425	static const unsigned int scifb_ctrl_1_mux[] = {
2426	SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
2427	};
2428	/* - SDHI0 ------------------------------------------------------------------ */
2429	static const unsigned int sdhi0_data_pins[] = {
2430	/* D[0:3] */
2431	77, 78, 79, 80,
2432	};
2433	static const unsigned int sdhi0_data_mux[] = {
2434	SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
2435	};
2436	static const unsigned int sdhi0_ctrl_pins[] = {
2437	/* CMD, CLK */
2438	76, 82,
2439	};
2440	static const unsigned int sdhi0_ctrl_mux[] = {
2441	SDHI0_CMD_MARK, SDHI0_CLK_MARK,
2442	};
2443	static const unsigned int sdhi0_cd_pins[] = {
2444	/* CD */
2445	81,
2446	};
2447	static const unsigned int sdhi0_cd_mux[] = {
2448	SDHI0_CD_MARK,
2449	};
2450	static const unsigned int sdhi0_wp_pins[] = {
2451	/* WP */
2452	83,
2453	};
2454	static const unsigned int sdhi0_wp_mux[] = {
2455	SDHI0_WP_MARK,
2456	};
2457	/* - SDHI1 ------------------------------------------------------------------ */
2458	static const unsigned int sdhi1_data_pins[] = {
2459	/* D[0:3] */
2460	68, 69, 70, 71,
2461	};
2462	static const unsigned int sdhi1_data_mux[] = {
2463	SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
2464	};
2465	static const unsigned int sdhi1_ctrl_pins[] = {
2466	/* CMD, CLK */
2467	67, 66,
2468	};
2469	static const unsigned int sdhi1_ctrl_mux[] = {
2470	SDHI1_CMD_MARK, SDHI1_CLK_MARK,
2471	};
2472	static const unsigned int sdhi1_cd_pins[] = {
2473	/* CD */
2474	72,
2475	};
2476	static const unsigned int sdhi1_cd_mux[] = {
2477	SDHI1_CD_MARK,
2478	};
2479	static const unsigned int sdhi1_wp_pins[] = {
2480	/* WP */
2481	73,
2482	};
2483	static const unsigned int sdhi1_wp_mux[] = {
2484	SDHI1_WP_MARK,
2485	};
2486	/* - SDHI2 ------------------------------------------------------------------ */
2487	static const unsigned int sdhi2_data_pins[] = {
2488	/* D[0:3] */
2489	205, 206, 207, 208,
2490	};
2491	static const unsigned int sdhi2_data_mux[] = {
2492	SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
2493	};
2494	static const unsigned int sdhi2_ctrl_pins[] = {
2495	/* CMD, CLK */
2496	204, 203,
2497	};
2498	static const unsigned int sdhi2_ctrl_mux[] = {
2499	SDHI2_CMD_MARK, SDHI2_CLK_MARK,
2500	};
2501	static const unsigned int sdhi2_cd_0_pins[] = {
2502	/* CD */
2503	202,
2504	};
2505	static const unsigned int sdhi2_cd_0_mux[] = {
2506	SDHI2_CD_PORT202_MARK,
2507	};
2508	static const unsigned int sdhi2_wp_0_pins[] = {
2509	/* WP */
2510	177,
2511	};
2512	static const unsigned int sdhi2_wp_0_mux[] = {
2513	SDHI2_WP_PORT177_MARK,
2514	};
2515	static const unsigned int sdhi2_cd_1_pins[] = {
2516	/* CD */
2517	24,
2518	};
2519	static const unsigned int sdhi2_cd_1_mux[] = {
2520	SDHI2_CD_PORT24_MARK,
2521	};
2522	static const unsigned int sdhi2_wp_1_pins[] = {
2523	/* WP */
2524	25,
2525	};
2526	static const unsigned int sdhi2_wp_1_mux[] = {
2527	SDHI2_WP_PORT25_MARK,
2528	};
2529	/* - TPU0 ------------------------------------------------------------------- */
2530	static const unsigned int tpu0_to0_pins[] = {
2531	/* TO */
2532	23,
2533	};
2534	static const unsigned int tpu0_to0_mux[] = {
2535	TPU0TO0_MARK,
2536	};
2537	static const unsigned int tpu0_to1_pins[] = {
2538	/* TO */
2539	21,
2540	};
2541	static const unsigned int tpu0_to1_mux[] = {
2542	TPU0TO1_MARK,
2543	};
2544	static const unsigned int tpu0_to2_0_pins[] = {
2545	/* TO */
2546	66,
2547	};
2548	static const unsigned int tpu0_to2_0_mux[] = {
2549	TPU0TO2_PORT66_MARK,
2550	};
2551	static const unsigned int tpu0_to2_1_pins[] = {
2552	/* TO */
2553	202,
2554	};
2555	static const unsigned int tpu0_to2_1_mux[] = {
2556	TPU0TO2_PORT202_MARK,
2557	};
2558	static const unsigned int tpu0_to3_pins[] = {
2559	/* TO */
2560	180,
2561	};
2562	static const unsigned int tpu0_to3_mux[] = {
2563	TPU0TO3_MARK,
2564	};
2565
2566	static const struct sh_pfc_pin_group pinmux_groups[] = {
2567	BUS_DATA_PIN_GROUP(bsc_data, 8),
2568	BUS_DATA_PIN_GROUP(bsc_data, 16),
2569	BUS_DATA_PIN_GROUP(bsc_data, 32),
2570	SH_PFC_PIN_GROUP(bsc_cs0),
2571	SH_PFC_PIN_GROUP(bsc_cs2),
2572	SH_PFC_PIN_GROUP(bsc_cs4),
2573	SH_PFC_PIN_GROUP(bsc_cs5a_0),
2574	SH_PFC_PIN_GROUP(bsc_cs5a_1),
2575	SH_PFC_PIN_GROUP(bsc_cs5b),
2576	SH_PFC_PIN_GROUP(bsc_cs6a),
2577	SH_PFC_PIN_GROUP_SUBSET(bsc_rd_we8, bsc_rd_we, 0, 2),
2578	SH_PFC_PIN_GROUP_SUBSET(bsc_rd_we16, bsc_rd_we, 0, 3),
2579	SH_PFC_PIN_GROUP_SUBSET(bsc_rd_we32, bsc_rd_we, 0, 5),
2580	SH_PFC_PIN_GROUP(bsc_bs),
2581	SH_PFC_PIN_GROUP(bsc_rdwr),
2582	SH_PFC_PIN_GROUP(ceu0_data_0_7),
2583	SH_PFC_PIN_GROUP(ceu0_data_8_15_0),
2584	SH_PFC_PIN_GROUP(ceu0_data_8_15_1),
2585	SH_PFC_PIN_GROUP(ceu0_clk_0),
2586	SH_PFC_PIN_GROUP(ceu0_clk_1),
2587	SH_PFC_PIN_GROUP(ceu0_clk_2),
2588	SH_PFC_PIN_GROUP(ceu0_sync),
2589	SH_PFC_PIN_GROUP(ceu0_field),
2590	SH_PFC_PIN_GROUP(ceu1_data),
2591	SH_PFC_PIN_GROUP(ceu1_clk),
2592	SH_PFC_PIN_GROUP(ceu1_sync),
2593	SH_PFC_PIN_GROUP(ceu1_field),
2594	SH_PFC_PIN_GROUP(fsia_mclk_in),
2595	SH_PFC_PIN_GROUP(fsia_mclk_out),
2596	SH_PFC_PIN_GROUP(fsia_sclk_in),
2597	SH_PFC_PIN_GROUP(fsia_sclk_out),
2598	SH_PFC_PIN_GROUP(fsia_data_in_0),
2599	SH_PFC_PIN_GROUP(fsia_data_in_1),
2600	SH_PFC_PIN_GROUP(fsia_data_out_0),
2601	SH_PFC_PIN_GROUP(fsia_data_out_1),
2602	SH_PFC_PIN_GROUP(fsia_data_out_2),
2603	SH_PFC_PIN_GROUP(fsia_spdif_0),
2604	SH_PFC_PIN_GROUP(fsia_spdif_1),
2605	SH_PFC_PIN_GROUP(fsib_mclk_in),
2606	SH_PFC_PIN_GROUP(gether_rmii),
2607	SH_PFC_PIN_GROUP(gether_mii),
2608	SH_PFC_PIN_GROUP(gether_gmii),
2609	SH_PFC_PIN_GROUP(gether_int),
2610	SH_PFC_PIN_GROUP(gether_link),
2611	SH_PFC_PIN_GROUP(gether_wol),
2612	SH_PFC_PIN_GROUP(hdmi),
2613	SH_PFC_PIN_GROUP(intc_irq0_0),
2614	SH_PFC_PIN_GROUP(intc_irq0_1),
2615	SH_PFC_PIN_GROUP(intc_irq1),
2616	SH_PFC_PIN_GROUP(intc_irq2_0),
2617	SH_PFC_PIN_GROUP(intc_irq2_1),
2618	SH_PFC_PIN_GROUP(intc_irq3_0),
2619	SH_PFC_PIN_GROUP(intc_irq3_1),
2620	SH_PFC_PIN_GROUP(intc_irq4_0),
2621	SH_PFC_PIN_GROUP(intc_irq4_1),
2622	SH_PFC_PIN_GROUP(intc_irq5_0),
2623	SH_PFC_PIN_GROUP(intc_irq5_1),
2624	SH_PFC_PIN_GROUP(intc_irq6_0),
2625	SH_PFC_PIN_GROUP(intc_irq6_1),
2626	SH_PFC_PIN_GROUP(intc_irq7_0),
2627	SH_PFC_PIN_GROUP(intc_irq7_1),
2628	SH_PFC_PIN_GROUP(intc_irq8),
2629	SH_PFC_PIN_GROUP(intc_irq9_0),
2630	SH_PFC_PIN_GROUP(intc_irq9_1),
2631	SH_PFC_PIN_GROUP(intc_irq10),
2632	SH_PFC_PIN_GROUP(intc_irq11),
2633	SH_PFC_PIN_GROUP(intc_irq12_0),
2634	SH_PFC_PIN_GROUP(intc_irq12_1),
2635	SH_PFC_PIN_GROUP(intc_irq13_0),
2636	SH_PFC_PIN_GROUP(intc_irq13_1),
2637	SH_PFC_PIN_GROUP(intc_irq14_0),
2638	SH_PFC_PIN_GROUP(intc_irq14_1),
2639	SH_PFC_PIN_GROUP(intc_irq15_0),
2640	SH_PFC_PIN_GROUP(intc_irq15_1),
2641	SH_PFC_PIN_GROUP(intc_irq16_0),
2642	SH_PFC_PIN_GROUP(intc_irq16_1),
2643	SH_PFC_PIN_GROUP(intc_irq17),
2644	SH_PFC_PIN_GROUP(intc_irq18),
2645	SH_PFC_PIN_GROUP(intc_irq19),
2646	SH_PFC_PIN_GROUP(intc_irq20),
2647	SH_PFC_PIN_GROUP(intc_irq21),
2648	SH_PFC_PIN_GROUP(intc_irq22),
2649	SH_PFC_PIN_GROUP(intc_irq23),
2650	SH_PFC_PIN_GROUP(intc_irq24),
2651	SH_PFC_PIN_GROUP(intc_irq25),
2652	SH_PFC_PIN_GROUP(intc_irq26_0),
2653	SH_PFC_PIN_GROUP(intc_irq26_1),
2654	SH_PFC_PIN_GROUP(intc_irq27_0),
2655	SH_PFC_PIN_GROUP(intc_irq27_1),
2656	SH_PFC_PIN_GROUP(intc_irq28_0),
2657	SH_PFC_PIN_GROUP(intc_irq28_1),
2658	SH_PFC_PIN_GROUP(intc_irq29_0),
2659	SH_PFC_PIN_GROUP(intc_irq29_1),
2660	SH_PFC_PIN_GROUP(intc_irq30_0),
2661	SH_PFC_PIN_GROUP(intc_irq30_1),
2662	SH_PFC_PIN_GROUP(intc_irq31_0),
2663	SH_PFC_PIN_GROUP(intc_irq31_1),
2664	SH_PFC_PIN_GROUP_SUBSET(lcd0_data8, lcd0_data24_0, 0, 8),
2665	SH_PFC_PIN_GROUP_SUBSET(lcd0_data9, lcd0_data24_0, 0, 9),
2666	SH_PFC_PIN_GROUP_SUBSET(lcd0_data12, lcd0_data24_0, 0, 12),
2667	SH_PFC_PIN_GROUP_SUBSET(lcd0_data16, lcd0_data24_0, 0, 16),
2668	SH_PFC_PIN_GROUP_SUBSET(lcd0_data18, lcd0_data24_0, 0, 18),
2669	SH_PFC_PIN_GROUP(lcd0_data24_0),
2670	SH_PFC_PIN_GROUP(lcd0_data24_1),
2671	SH_PFC_PIN_GROUP(lcd0_display),
2672	SH_PFC_PIN_GROUP(lcd0_lclk_0),
2673	SH_PFC_PIN_GROUP(lcd0_lclk_1),
2674	SH_PFC_PIN_GROUP(lcd0_sync),
2675	SH_PFC_PIN_GROUP(lcd0_sys),
2676	BUS_DATA_PIN_GROUP(lcd1_data, 8),
2677	BUS_DATA_PIN_GROUP(lcd1_data, 9),
2678	BUS_DATA_PIN_GROUP(lcd1_data, 12),
2679	BUS_DATA_PIN_GROUP(lcd1_data, 16),
2680	BUS_DATA_PIN_GROUP(lcd1_data, 18),
2681	BUS_DATA_PIN_GROUP(lcd1_data, 24),
2682	SH_PFC_PIN_GROUP(lcd1_display),
2683	SH_PFC_PIN_GROUP(lcd1_lclk),
2684	SH_PFC_PIN_GROUP(lcd1_sync),
2685	SH_PFC_PIN_GROUP(lcd1_sys),
2686	BUS_DATA_PIN_GROUP(mmc0_data, 1, _0),
2687	BUS_DATA_PIN_GROUP(mmc0_data, 4, _0),
2688	BUS_DATA_PIN_GROUP(mmc0_data, 8, _0),
2689	SH_PFC_PIN_GROUP(mmc0_ctrl_0),
2690	BUS_DATA_PIN_GROUP(mmc0_data, 1, _1),
2691	BUS_DATA_PIN_GROUP(mmc0_data, 4, _1),
2692	BUS_DATA_PIN_GROUP(mmc0_data, 8, _1),
2693	SH_PFC_PIN_GROUP(mmc0_ctrl_1),
2694	SH_PFC_PIN_GROUP(scifa0_data),
2695	SH_PFC_PIN_GROUP(scifa0_clk),
2696	SH_PFC_PIN_GROUP(scifa0_ctrl),
2697	SH_PFC_PIN_GROUP(scifa1_data),
2698	SH_PFC_PIN_GROUP(scifa1_clk),
2699	SH_PFC_PIN_GROUP(scifa1_ctrl),
2700	SH_PFC_PIN_GROUP(scifa2_data),
2701	SH_PFC_PIN_GROUP(scifa2_clk_0),
2702	SH_PFC_PIN_GROUP(scifa2_clk_1),
2703	SH_PFC_PIN_GROUP(scifa2_ctrl),
2704	SH_PFC_PIN_GROUP(scifa3_data_0),
2705	SH_PFC_PIN_GROUP(scifa3_clk_0),
2706	SH_PFC_PIN_GROUP(scifa3_ctrl_0),
2707	SH_PFC_PIN_GROUP(scifa3_data_1),
2708	SH_PFC_PIN_GROUP(scifa3_clk_1),
2709	SH_PFC_PIN_GROUP(scifa3_ctrl_1),
2710	SH_PFC_PIN_GROUP(scifa4_data_0),
2711	SH_PFC_PIN_GROUP(scifa4_data_1),
2712	SH_PFC_PIN_GROUP(scifa4_data_2),
2713	SH_PFC_PIN_GROUP(scifa4_clk_0),
2714	SH_PFC_PIN_GROUP(scifa4_clk_1),
2715	SH_PFC_PIN_GROUP(scifa5_data_0),
2716	SH_PFC_PIN_GROUP(scifa5_data_1),
2717	SH_PFC_PIN_GROUP(scifa5_data_2),
2718	SH_PFC_PIN_GROUP(scifa5_clk_0),
2719	SH_PFC_PIN_GROUP(scifa5_clk_1),
2720	SH_PFC_PIN_GROUP(scifa6_data),
2721	SH_PFC_PIN_GROUP(scifa6_clk),
2722	SH_PFC_PIN_GROUP(scifa7_data),
2723	SH_PFC_PIN_GROUP(scifb_data_0),
2724	SH_PFC_PIN_GROUP(scifb_clk_0),
2725	SH_PFC_PIN_GROUP(scifb_ctrl_0),
2726	SH_PFC_PIN_GROUP(scifb_data_1),
2727	SH_PFC_PIN_GROUP(scifb_clk_1),
2728	SH_PFC_PIN_GROUP(scifb_ctrl_1),
2729	BUS_DATA_PIN_GROUP(sdhi0_data, 1),
2730	BUS_DATA_PIN_GROUP(sdhi0_data, 4),
2731	SH_PFC_PIN_GROUP(sdhi0_ctrl),
2732	SH_PFC_PIN_GROUP(sdhi0_cd),
2733	SH_PFC_PIN_GROUP(sdhi0_wp),
2734	BUS_DATA_PIN_GROUP(sdhi1_data, 1),
2735	BUS_DATA_PIN_GROUP(sdhi1_data, 4),
2736	SH_PFC_PIN_GROUP(sdhi1_ctrl),
2737	SH_PFC_PIN_GROUP(sdhi1_cd),
2738	SH_PFC_PIN_GROUP(sdhi1_wp),
2739	BUS_DATA_PIN_GROUP(sdhi2_data, 1),
2740	BUS_DATA_PIN_GROUP(sdhi2_data, 4),
2741	SH_PFC_PIN_GROUP(sdhi2_ctrl),
2742	SH_PFC_PIN_GROUP(sdhi2_cd_0),
2743	SH_PFC_PIN_GROUP(sdhi2_wp_0),
2744	SH_PFC_PIN_GROUP(sdhi2_cd_1),
2745	SH_PFC_PIN_GROUP(sdhi2_wp_1),
2746	SH_PFC_PIN_GROUP(tpu0_to0),
2747	SH_PFC_PIN_GROUP(tpu0_to1),
2748	SH_PFC_PIN_GROUP(tpu0_to2_0),
2749	SH_PFC_PIN_GROUP(tpu0_to2_1),
2750	SH_PFC_PIN_GROUP(tpu0_to3),
2751	};
2752
2753	static const char * const bsc_groups[] = {
2754	"bsc_data8",
2755	"bsc_data16",
2756	"bsc_data32",
2757	"bsc_cs0",
2758	"bsc_cs2",
2759	"bsc_cs4",
2760	"bsc_cs5a_0",
2761	"bsc_cs5a_1",
2762	"bsc_cs5b",
2763	"bsc_cs6a",
2764	"bsc_rd_we8",
2765	"bsc_rd_we16",
2766	"bsc_rd_we32",
2767	"bsc_bs",
2768	"bsc_rdwr",
2769	};
2770
2771	static const char * const ceu0_groups[] = {
2772	"ceu0_data_0_7",
2773	"ceu0_data_8_15_0",
2774	"ceu0_data_8_15_1",
2775	"ceu0_clk_0",
2776	"ceu0_clk_1",
2777	"ceu0_clk_2",
2778	"ceu0_sync",
2779	"ceu0_field",
2780	};
2781
2782	static const char * const ceu1_groups[] = {
2783	"ceu1_data",
2784	"ceu1_clk",
2785	"ceu1_sync",
2786	"ceu1_field",
2787	};
2788
2789	static const char * const fsia_groups[] = {
2790	"fsia_mclk_in",
2791	"fsia_mclk_out",
2792	"fsia_sclk_in",
2793	"fsia_sclk_out",
2794	"fsia_data_in_0",
2795	"fsia_data_in_1",
2796	"fsia_data_out_0",
2797	"fsia_data_out_1",
2798	"fsia_data_out_2",
2799	"fsia_spdif_0",
2800	"fsia_spdif_1",
2801	};
2802
2803	static const char * const fsib_groups[] = {
2804	"fsib_mclk_in",
2805	};
2806
2807	static const char * const gether_groups[] = {
2808	"gether_rmii",
2809	"gether_mii",
2810	"gether_gmii",
2811	"gether_int",
2812	"gether_link",
2813	"gether_wol",
2814	};
2815
2816	static const char * const hdmi_groups[] = {
2817	"hdmi",
2818	};
2819
2820	static const char * const intc_groups[] = {
2821	"intc_irq0_0",
2822	"intc_irq0_1",
2823	"intc_irq1",
2824	"intc_irq2_0",
2825	"intc_irq2_1",
2826	"intc_irq3_0",
2827	"intc_irq3_1",
2828	"intc_irq4_0",
2829	"intc_irq4_1",
2830	"intc_irq5_0",
2831	"intc_irq5_1",
2832	"intc_irq6_0",
2833	"intc_irq6_1",
2834	"intc_irq7_0",
2835	"intc_irq7_1",
2836	"intc_irq8",
2837	"intc_irq9_0",
2838	"intc_irq9_1",
2839	"intc_irq10",
2840	"intc_irq11",
2841	"intc_irq12_0",
2842	"intc_irq12_1",
2843	"intc_irq13_0",
2844	"intc_irq13_1",
2845	"intc_irq14_0",
2846	"intc_irq14_1",
2847	"intc_irq15_0",
2848	"intc_irq15_1",
2849	"intc_irq16_0",
2850	"intc_irq16_1",
2851	"intc_irq17",
2852	"intc_irq18",
2853	"intc_irq19",
2854	"intc_irq20",
2855	"intc_irq21",
2856	"intc_irq22",
2857	"intc_irq23",
2858	"intc_irq24",
2859	"intc_irq25",
2860	"intc_irq26_0",
2861	"intc_irq26_1",
2862	"intc_irq27_0",
2863	"intc_irq27_1",
2864	"intc_irq28_0",
2865	"intc_irq28_1",
2866	"intc_irq29_0",
2867	"intc_irq29_1",
2868	"intc_irq30_0",
2869	"intc_irq30_1",
2870	"intc_irq31_0",
2871	"intc_irq31_1",
2872	};
2873
2874	static const char * const lcd0_groups[] = {
2875	"lcd0_data8",
2876	"lcd0_data9",
2877	"lcd0_data12",
2878	"lcd0_data16",
2879	"lcd0_data18",
2880	"lcd0_data24_0",
2881	"lcd0_data24_1",
2882	"lcd0_display",
2883	"lcd0_lclk_0",
2884	"lcd0_lclk_1",
2885	"lcd0_sync",
2886	"lcd0_sys",
2887	};
2888
2889	static const char * const lcd1_groups[] = {
2890	"lcd1_data8",
2891	"lcd1_data9",
2892	"lcd1_data12",
2893	"lcd1_data16",
2894	"lcd1_data18",
2895	"lcd1_data24",
2896	"lcd1_display",
2897	"lcd1_lclk",
2898	"lcd1_sync",
2899	"lcd1_sys",
2900	};
2901
2902	static const char * const mmc0_groups[] = {
2903	"mmc0_data1_0",
2904	"mmc0_data4_0",
2905	"mmc0_data8_0",
2906	"mmc0_ctrl_0",
2907	"mmc0_data1_1",
2908	"mmc0_data4_1",
2909	"mmc0_data8_1",
2910	"mmc0_ctrl_1",
2911	};
2912
2913	static const char * const scifa0_groups[] = {
2914	"scifa0_data",
2915	"scifa0_clk",
2916	"scifa0_ctrl",
2917	};
2918
2919	static const char * const scifa1_groups[] = {
2920	"scifa1_data",
2921	"scifa1_clk",
2922	"scifa1_ctrl",
2923	};
2924
2925	static const char * const scifa2_groups[] = {
2926	"scifa2_data",
2927	"scifa2_clk_0",
2928	"scifa2_clk_1",
2929	"scifa2_ctrl",
2930	};
2931
2932	static const char * const scifa3_groups[] = {
2933	"scifa3_data_0",
2934	"scifa3_clk_0",
2935	"scifa3_ctrl_0",
2936	"scifa3_data_1",
2937	"scifa3_clk_1",
2938	"scifa3_ctrl_1",
2939	};
2940
2941	static const char * const scifa4_groups[] = {
2942	"scifa4_data_0",
2943	"scifa4_data_1",
2944	"scifa4_data_2",
2945	"scifa4_clk_0",
2946	"scifa4_clk_1",
2947	};
2948
2949	static const char * const scifa5_groups[] = {
2950	"scifa5_data_0",
2951	"scifa5_data_1",
2952	"scifa5_data_2",
2953	"scifa5_clk_0",
2954	"scifa5_clk_1",
2955	};
2956
2957	static const char * const scifa6_groups[] = {
2958	"scifa6_data",
2959	"scifa6_clk",
2960	};
2961
2962	static const char * const scifa7_groups[] = {
2963	"scifa7_data",
2964	};
2965
2966	static const char * const scifb_groups[] = {
2967	"scifb_data_0",
2968	"scifb_clk_0",
2969	"scifb_ctrl_0",
2970	"scifb_data_1",
2971	"scifb_clk_1",
2972	"scifb_ctrl_1",
2973	};
2974
2975	static const char * const sdhi0_groups[] = {
2976	"sdhi0_data1",
2977	"sdhi0_data4",
2978	"sdhi0_ctrl",
2979	"sdhi0_cd",
2980	"sdhi0_wp",
2981	};
2982
2983	static const char * const sdhi1_groups[] = {
2984	"sdhi1_data1",
2985	"sdhi1_data4",
2986	"sdhi1_ctrl",
2987	"sdhi1_cd",
2988	"sdhi1_wp",
2989	};
2990
2991	static const char * const sdhi2_groups[] = {
2992	"sdhi2_data1",
2993	"sdhi2_data4",
2994	"sdhi2_ctrl",
2995	"sdhi2_cd_0",
2996	"sdhi2_wp_0",
2997	"sdhi2_cd_1",
2998	"sdhi2_wp_1",
2999	};
3000
3001	static const char * const tpu0_groups[] = {
3002	"tpu0_to0",
3003	"tpu0_to1",
3004	"tpu0_to2_0",
3005	"tpu0_to2_1",
3006	"tpu0_to3",
3007	};
3008
3009	static const struct sh_pfc_function pinmux_functions[] = {
3010	SH_PFC_FUNCTION(bsc),
3011	SH_PFC_FUNCTION(ceu0),
3012	SH_PFC_FUNCTION(ceu1),
3013	SH_PFC_FUNCTION(fsia),
3014	SH_PFC_FUNCTION(fsib),
3015	SH_PFC_FUNCTION(gether),
3016	SH_PFC_FUNCTION(hdmi),
3017	SH_PFC_FUNCTION(intc),
3018	SH_PFC_FUNCTION(lcd0),
3019	SH_PFC_FUNCTION(lcd1),
3020	SH_PFC_FUNCTION(mmc0),
3021	SH_PFC_FUNCTION(scifa0),
3022	SH_PFC_FUNCTION(scifa1),
3023	SH_PFC_FUNCTION(scifa2),
3024	SH_PFC_FUNCTION(scifa3),
3025	SH_PFC_FUNCTION(scifa4),
3026	SH_PFC_FUNCTION(scifa5),
3027	SH_PFC_FUNCTION(scifa6),
3028	SH_PFC_FUNCTION(scifa7),
3029	SH_PFC_FUNCTION(scifb),
3030	SH_PFC_FUNCTION(sdhi0),
3031	SH_PFC_FUNCTION(sdhi1),
3032	SH_PFC_FUNCTION(sdhi2),
3033	SH_PFC_FUNCTION(tpu0),
3034	};
3035
3036	static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3037	PORTCR(0, 0xe6050000), /* PORT0CR */
3038	PORTCR(1, 0xe6050001), /* PORT1CR */
3039	PORTCR(2, 0xe6050002), /* PORT2CR */
3040	PORTCR(3, 0xe6050003), /* PORT3CR */
3041	PORTCR(4, 0xe6050004), /* PORT4CR */
3042	PORTCR(5, 0xe6050005), /* PORT5CR */
3043	PORTCR(6, 0xe6050006), /* PORT6CR */
3044	PORTCR(7, 0xe6050007), /* PORT7CR */
3045	PORTCR(8, 0xe6050008), /* PORT8CR */
3046	PORTCR(9, 0xe6050009), /* PORT9CR */
3047	PORTCR(10, 0xe605000a), /* PORT10CR */
3048	PORTCR(11, 0xe605000b), /* PORT11CR */
3049	PORTCR(12, 0xe605000c), /* PORT12CR */
3050	PORTCR(13, 0xe605000d), /* PORT13CR */
3051	PORTCR(14, 0xe605000e), /* PORT14CR */
3052	PORTCR(15, 0xe605000f), /* PORT15CR */
3053	PORTCR(16, 0xe6050010), /* PORT16CR */
3054	PORTCR(17, 0xe6050011), /* PORT17CR */
3055	PORTCR(18, 0xe6050012), /* PORT18CR */
3056	PORTCR(19, 0xe6050013), /* PORT19CR */
3057	PORTCR(20, 0xe6050014), /* PORT20CR */
3058	PORTCR(21, 0xe6050015), /* PORT21CR */
3059	PORTCR(22, 0xe6050016), /* PORT22CR */
3060	PORTCR(23, 0xe6050017), /* PORT23CR */
3061	PORTCR(24, 0xe6050018), /* PORT24CR */
3062	PORTCR(25, 0xe6050019), /* PORT25CR */
3063	PORTCR(26, 0xe605001a), /* PORT26CR */
3064	PORTCR(27, 0xe605001b), /* PORT27CR */
3065	PORTCR(28, 0xe605001c), /* PORT28CR */
3066	PORTCR(29, 0xe605001d), /* PORT29CR */
3067	PORTCR(30, 0xe605001e), /* PORT30CR */
3068	PORTCR(31, 0xe605001f), /* PORT31CR */
3069	PORTCR(32, 0xe6050020), /* PORT32CR */
3070	PORTCR(33, 0xe6050021), /* PORT33CR */
3071	PORTCR(34, 0xe6050022), /* PORT34CR */
3072	PORTCR(35, 0xe6050023), /* PORT35CR */
3073	PORTCR(36, 0xe6050024), /* PORT36CR */
3074	PORTCR(37, 0xe6050025), /* PORT37CR */
3075	PORTCR(38, 0xe6050026), /* PORT38CR */
3076	PORTCR(39, 0xe6050027), /* PORT39CR */
3077	PORTCR(40, 0xe6050028), /* PORT40CR */
3078	PORTCR(41, 0xe6050029), /* PORT41CR */
3079	PORTCR(42, 0xe605002a), /* PORT42CR */
3080	PORTCR(43, 0xe605002b), /* PORT43CR */
3081	PORTCR(44, 0xe605002c), /* PORT44CR */
3082	PORTCR(45, 0xe605002d), /* PORT45CR */
3083	PORTCR(46, 0xe605002e), /* PORT46CR */
3084	PORTCR(47, 0xe605002f), /* PORT47CR */
3085	PORTCR(48, 0xe6050030), /* PORT48CR */
3086	PORTCR(49, 0xe6050031), /* PORT49CR */
3087	PORTCR(50, 0xe6050032), /* PORT50CR */
3088	PORTCR(51, 0xe6050033), /* PORT51CR */
3089	PORTCR(52, 0xe6050034), /* PORT52CR */
3090	PORTCR(53, 0xe6050035), /* PORT53CR */
3091	PORTCR(54, 0xe6050036), /* PORT54CR */
3092	PORTCR(55, 0xe6050037), /* PORT55CR */
3093	PORTCR(56, 0xe6050038), /* PORT56CR */
3094	PORTCR(57, 0xe6050039), /* PORT57CR */
3095	PORTCR(58, 0xe605003a), /* PORT58CR */
3096	PORTCR(59, 0xe605003b), /* PORT59CR */
3097	PORTCR(60, 0xe605003c), /* PORT60CR */
3098	PORTCR(61, 0xe605003d), /* PORT61CR */
3099	PORTCR(62, 0xe605003e), /* PORT62CR */
3100	PORTCR(63, 0xe605003f), /* PORT63CR */
3101	PORTCR(64, 0xe6050040), /* PORT64CR */
3102	PORTCR(65, 0xe6050041), /* PORT65CR */
3103	PORTCR(66, 0xe6050042), /* PORT66CR */
3104	PORTCR(67, 0xe6050043), /* PORT67CR */
3105	PORTCR(68, 0xe6050044), /* PORT68CR */
3106	PORTCR(69, 0xe6050045), /* PORT69CR */
3107	PORTCR(70, 0xe6050046), /* PORT70CR */
3108	PORTCR(71, 0xe6050047), /* PORT71CR */
3109	PORTCR(72, 0xe6050048), /* PORT72CR */
3110	PORTCR(73, 0xe6050049), /* PORT73CR */
3111	PORTCR(74, 0xe605004a), /* PORT74CR */
3112	PORTCR(75, 0xe605004b), /* PORT75CR */
3113	PORTCR(76, 0xe605004c), /* PORT76CR */
3114	PORTCR(77, 0xe605004d), /* PORT77CR */
3115	PORTCR(78, 0xe605004e), /* PORT78CR */
3116	PORTCR(79, 0xe605004f), /* PORT79CR */
3117	PORTCR(80, 0xe6050050), /* PORT80CR */
3118	PORTCR(81, 0xe6050051), /* PORT81CR */
3119	PORTCR(82, 0xe6050052), /* PORT82CR */
3120	PORTCR(83, 0xe6050053), /* PORT83CR */
3121
3122	PORTCR(84, 0xe6051054), /* PORT84CR */
3123	PORTCR(85, 0xe6051055), /* PORT85CR */
3124	PORTCR(86, 0xe6051056), /* PORT86CR */
3125	PORTCR(87, 0xe6051057), /* PORT87CR */
3126	PORTCR(88, 0xe6051058), /* PORT88CR */
3127	PORTCR(89, 0xe6051059), /* PORT89CR */
3128	PORTCR(90, 0xe605105a), /* PORT90CR */
3129	PORTCR(91, 0xe605105b), /* PORT91CR */
3130	PORTCR(92, 0xe605105c), /* PORT92CR */
3131	PORTCR(93, 0xe605105d), /* PORT93CR */
3132	PORTCR(94, 0xe605105e), /* PORT94CR */
3133	PORTCR(95, 0xe605105f), /* PORT95CR */
3134	PORTCR(96, 0xe6051060), /* PORT96CR */
3135	PORTCR(97, 0xe6051061), /* PORT97CR */
3136	PORTCR(98, 0xe6051062), /* PORT98CR */
3137	PORTCR(99, 0xe6051063), /* PORT99CR */
3138	PORTCR(100, 0xe6051064), /* PORT100CR */
3139	PORTCR(101, 0xe6051065), /* PORT101CR */
3140	PORTCR(102, 0xe6051066), /* PORT102CR */
3141	PORTCR(103, 0xe6051067), /* PORT103CR */
3142	PORTCR(104, 0xe6051068), /* PORT104CR */
3143	PORTCR(105, 0xe6051069), /* PORT105CR */
3144	PORTCR(106, 0xe605106a), /* PORT106CR */
3145	PORTCR(107, 0xe605106b), /* PORT107CR */
3146	PORTCR(108, 0xe605106c), /* PORT108CR */
3147	PORTCR(109, 0xe605106d), /* PORT109CR */
3148	PORTCR(110, 0xe605106e), /* PORT110CR */
3149	PORTCR(111, 0xe605106f), /* PORT111CR */
3150	PORTCR(112, 0xe6051070), /* PORT112CR */
3151	PORTCR(113, 0xe6051071), /* PORT113CR */
3152	PORTCR(114, 0xe6051072), /* PORT114CR */
3153
3154	PORTCR(115, 0xe6052073), /* PORT115CR */
3155	PORTCR(116, 0xe6052074), /* PORT116CR */
3156	PORTCR(117, 0xe6052075), /* PORT117CR */
3157	PORTCR(118, 0xe6052076), /* PORT118CR */
3158	PORTCR(119, 0xe6052077), /* PORT119CR */
3159	PORTCR(120, 0xe6052078), /* PORT120CR */
3160	PORTCR(121, 0xe6052079), /* PORT121CR */
3161	PORTCR(122, 0xe605207a), /* PORT122CR */
3162	PORTCR(123, 0xe605207b), /* PORT123CR */
3163	PORTCR(124, 0xe605207c), /* PORT124CR */
3164	PORTCR(125, 0xe605207d), /* PORT125CR */
3165	PORTCR(126, 0xe605207e), /* PORT126CR */
3166	PORTCR(127, 0xe605207f), /* PORT127CR */
3167	PORTCR(128, 0xe6052080), /* PORT128CR */
3168	PORTCR(129, 0xe6052081), /* PORT129CR */
3169	PORTCR(130, 0xe6052082), /* PORT130CR */
3170	PORTCR(131, 0xe6052083), /* PORT131CR */
3171	PORTCR(132, 0xe6052084), /* PORT132CR */
3172	PORTCR(133, 0xe6052085), /* PORT133CR */
3173	PORTCR(134, 0xe6052086), /* PORT134CR */
3174	PORTCR(135, 0xe6052087), /* PORT135CR */
3175	PORTCR(136, 0xe6052088), /* PORT136CR */
3176	PORTCR(137, 0xe6052089), /* PORT137CR */
3177	PORTCR(138, 0xe605208a), /* PORT138CR */
3178	PORTCR(139, 0xe605208b), /* PORT139CR */
3179	PORTCR(140, 0xe605208c), /* PORT140CR */
3180	PORTCR(141, 0xe605208d), /* PORT141CR */
3181	PORTCR(142, 0xe605208e), /* PORT142CR */
3182	PORTCR(143, 0xe605208f), /* PORT143CR */
3183	PORTCR(144, 0xe6052090), /* PORT144CR */
3184	PORTCR(145, 0xe6052091), /* PORT145CR */
3185	PORTCR(146, 0xe6052092), /* PORT146CR */
3186	PORTCR(147, 0xe6052093), /* PORT147CR */
3187	PORTCR(148, 0xe6052094), /* PORT148CR */
3188	PORTCR(149, 0xe6052095), /* PORT149CR */
3189	PORTCR(150, 0xe6052096), /* PORT150CR */
3190	PORTCR(151, 0xe6052097), /* PORT151CR */
3191	PORTCR(152, 0xe6052098), /* PORT152CR */
3192	PORTCR(153, 0xe6052099), /* PORT153CR */
3193	PORTCR(154, 0xe605209a), /* PORT154CR */
3194	PORTCR(155, 0xe605209b), /* PORT155CR */
3195	PORTCR(156, 0xe605209c), /* PORT156CR */
3196	PORTCR(157, 0xe605209d), /* PORT157CR */
3197	PORTCR(158, 0xe605209e), /* PORT158CR */
3198	PORTCR(159, 0xe605209f), /* PORT159CR */
3199	PORTCR(160, 0xe60520a0), /* PORT160CR */
3200	PORTCR(161, 0xe60520a1), /* PORT161CR */
3201	PORTCR(162, 0xe60520a2), /* PORT162CR */
3202	PORTCR(163, 0xe60520a3), /* PORT163CR */
3203	PORTCR(164, 0xe60520a4), /* PORT164CR */
3204	PORTCR(165, 0xe60520a5), /* PORT165CR */
3205	PORTCR(166, 0xe60520a6), /* PORT166CR */
3206	PORTCR(167, 0xe60520a7), /* PORT167CR */
3207	PORTCR(168, 0xe60520a8), /* PORT168CR */
3208	PORTCR(169, 0xe60520a9), /* PORT169CR */
3209	PORTCR(170, 0xe60520aa), /* PORT170CR */
3210	PORTCR(171, 0xe60520ab), /* PORT171CR */
3211	PORTCR(172, 0xe60520ac), /* PORT172CR */
3212	PORTCR(173, 0xe60520ad), /* PORT173CR */
3213	PORTCR(174, 0xe60520ae), /* PORT174CR */
3214	PORTCR(175, 0xe60520af), /* PORT175CR */
3215	PORTCR(176, 0xe60520b0), /* PORT176CR */
3216	PORTCR(177, 0xe60520b1), /* PORT177CR */
3217	PORTCR(178, 0xe60520b2), /* PORT178CR */
3218	PORTCR(179, 0xe60520b3), /* PORT179CR */
3219	PORTCR(180, 0xe60520b4), /* PORT180CR */
3220	PORTCR(181, 0xe60520b5), /* PORT181CR */
3221	PORTCR(182, 0xe60520b6), /* PORT182CR */
3222	PORTCR(183, 0xe60520b7), /* PORT183CR */
3223	PORTCR(184, 0xe60520b8), /* PORT184CR */
3224	PORTCR(185, 0xe60520b9), /* PORT185CR */
3225	PORTCR(186, 0xe60520ba), /* PORT186CR */
3226	PORTCR(187, 0xe60520bb), /* PORT187CR */
3227	PORTCR(188, 0xe60520bc), /* PORT188CR */
3228	PORTCR(189, 0xe60520bd), /* PORT189CR */
3229	PORTCR(190, 0xe60520be), /* PORT190CR */
3230	PORTCR(191, 0xe60520bf), /* PORT191CR */
3231	PORTCR(192, 0xe60520c0), /* PORT192CR */
3232	PORTCR(193, 0xe60520c1), /* PORT193CR */
3233	PORTCR(194, 0xe60520c2), /* PORT194CR */
3234	PORTCR(195, 0xe60520c3), /* PORT195CR */
3235	PORTCR(196, 0xe60520c4), /* PORT196CR */
3236	PORTCR(197, 0xe60520c5), /* PORT197CR */
3237	PORTCR(198, 0xe60520c6), /* PORT198CR */
3238	PORTCR(199, 0xe60520c7), /* PORT199CR */
3239	PORTCR(200, 0xe60520c8), /* PORT200CR */
3240	PORTCR(201, 0xe60520c9), /* PORT201CR */
3241	PORTCR(202, 0xe60520ca), /* PORT202CR */
3242	PORTCR(203, 0xe60520cb), /* PORT203CR */
3243	PORTCR(204, 0xe60520cc), /* PORT204CR */
3244	PORTCR(205, 0xe60520cd), /* PORT205CR */
3245	PORTCR(206, 0xe60520ce), /* PORT206CR */
3246	PORTCR(207, 0xe60520cf), /* PORT207CR */
3247	PORTCR(208, 0xe60520d0), /* PORT208CR */
3248	PORTCR(209, 0xe60520d1), /* PORT209CR */
3249
3250	PORTCR(210, 0xe60530d2), /* PORT210CR */
3251	PORTCR(211, 0xe60530d3), /* PORT211CR */
3252
3253	{ PINMUX_CFG_REG_VAR("MSEL1CR", 0xe605800c, 32,
3254	GROUP(1, 1, 1, 1, 1, 1, -9, 1, 1, 1, 1, 1,
3255	-2, 1, -1, 1, 1, 1, 1, 1, 1, -1, 1),
3256	GROUP(
3257	MSEL1CR_31_0, MSEL1CR_31_1,
3258	MSEL1CR_30_0, MSEL1CR_30_1,
3259	MSEL1CR_29_0, MSEL1CR_29_1,
3260	MSEL1CR_28_0, MSEL1CR_28_1,
3261	MSEL1CR_27_0, MSEL1CR_27_1,
3262	MSEL1CR_26_0, MSEL1CR_26_1,
3263	/* RESERVED [9] */
3264	MSEL1CR_16_0, MSEL1CR_16_1,
3265	MSEL1CR_15_0, MSEL1CR_15_1,
3266	MSEL1CR_14_0, MSEL1CR_14_1,
3267	MSEL1CR_13_0, MSEL1CR_13_1,
3268	MSEL1CR_12_0, MSEL1CR_12_1,
3269	/* RESERVED [2] */
3270	MSEL1CR_9_0, MSEL1CR_9_1,
3271	/* RESERVED [1] */
3272	MSEL1CR_7_0, MSEL1CR_7_1,
3273	MSEL1CR_6_0, MSEL1CR_6_1,
3274	MSEL1CR_5_0, MSEL1CR_5_1,
3275	MSEL1CR_4_0, MSEL1CR_4_1,
3276	MSEL1CR_3_0, MSEL1CR_3_1,
3277	MSEL1CR_2_0, MSEL1CR_2_1,
3278	/* RESERVED [1] */
3279	MSEL1CR_0_0, MSEL1CR_0_1,
3280	))
3281	},
3282	{ PINMUX_CFG_REG_VAR("MSEL3CR", 0xE6058020, 32,
3283	GROUP(-16, 1, -8, 1, -6),
3284	GROUP(
3285	/* RESERVED [16] */
3286	MSEL3CR_15_0, MSEL3CR_15_1,
3287	/* RESERVED [8] */
3288	MSEL3CR_6_0, MSEL3CR_6_1,
3289	/* RESERVED [6] */
3290	))
3291	},
3292	{ PINMUX_CFG_REG_VAR("MSEL4CR", 0xE6058024, 32,
3293	GROUP(-12, 1, 1, -2, 1, -4, 1, -3, 1, -1, 1, -2,
3294	1, -1),
3295	GROUP(
3296	/* RESERVED [12] */
3297	MSEL4CR_19_0, MSEL4CR_19_1,
3298	MSEL4CR_18_0, MSEL4CR_18_1,
3299	/* RESERVED [2] */
3300	MSEL4CR_15_0, MSEL4CR_15_1,
3301	/* RESERVED [4] */
3302	MSEL4CR_10_0, MSEL4CR_10_1,
3303	/* RESERVED [3] */
3304	MSEL4CR_6_0, MSEL4CR_6_1,
3305	/* RESERVED [1] */
3306	MSEL4CR_4_0, MSEL4CR_4_1,
3307	/* RESERVED [2] */
3308	MSEL4CR_1_0, MSEL4CR_1_1,
3309	/* RESERVED [1] */
3310	))
3311	},
3312	{ PINMUX_CFG_REG_VAR("MSEL5CR", 0xE6058028, 32,
3313	GROUP(1, 1, 1, -1, 1, -1, 1, -1, 1, -1, 1,
3314	-1, 1, -1, 1, -1, 1, 1, 1, 1, 1, 1,
3315	-1, 1, 1, 1, 1, 1, 1, 1, -1, 1),
3316	GROUP(
3317	MSEL5CR_31_0, MSEL5CR_31_1,
3318	MSEL5CR_30_0, MSEL5CR_30_1,
3319	MSEL5CR_29_0, MSEL5CR_29_1,
3320	/* RESERVED [1] */
3321	MSEL5CR_27_0, MSEL5CR_27_1,
3322	/* RESERVED [1] */
3323	MSEL5CR_25_0, MSEL5CR_25_1,
3324	/* RESERVED [1] */
3325	MSEL5CR_23_0, MSEL5CR_23_1,
3326	/* RESERVED [1] */
3327	MSEL5CR_21_0, MSEL5CR_21_1,
3328	/* RESERVED [1] */
3329	MSEL5CR_19_0, MSEL5CR_19_1,
3330	/* RESERVED [1] */
3331	MSEL5CR_17_0, MSEL5CR_17_1,
3332	/* RESERVED [1] */
3333	MSEL5CR_15_0, MSEL5CR_15_1,
3334	MSEL5CR_14_0, MSEL5CR_14_1,
3335	MSEL5CR_13_0, MSEL5CR_13_1,
3336	MSEL5CR_12_0, MSEL5CR_12_1,
3337	MSEL5CR_11_0, MSEL5CR_11_1,
3338	MSEL5CR_10_0, MSEL5CR_10_1,
3339	/* RESERVED [1] */
3340	MSEL5CR_8_0, MSEL5CR_8_1,
3341	MSEL5CR_7_0, MSEL5CR_7_1,
3342	MSEL5CR_6_0, MSEL5CR_6_1,
3343	MSEL5CR_5_0, MSEL5CR_5_1,
3344	MSEL5CR_4_0, MSEL5CR_4_1,
3345	MSEL5CR_3_0, MSEL5CR_3_1,
3346	MSEL5CR_2_0, MSEL5CR_2_1,
3347	/* RESERVED [1] */
3348	MSEL5CR_0_0, MSEL5CR_0_1,
3349	))
3350	},
3351	{ /* sentinel */ }
3352	};
3353
3354	static const struct pinmux_data_reg pinmux_data_regs[] = {
3355	{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32, GROUP(
3356	PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
3357	PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
3358	PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
3359	PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
3360	PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
3361	PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
3362	PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
3363	PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA ))
3364	},
3365	{ PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32, GROUP(
3366	PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
3367	PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
3368	PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
3369	PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
3370	PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
3371	PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
3372	PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
3373	PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA ))
3374	},
3375	{ PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32, GROUP(
3376	0, 0, 0, 0,
3377	0, 0, 0, 0,
3378	0, 0, 0, 0,
3379	PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
3380	PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
3381	PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
3382	PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
3383	PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA ))
3384	},
3385	{ PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32, GROUP(
3386	PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
3387	PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
3388	PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
3389	0, 0, 0, 0,
3390	0, 0, 0, 0,
3391	0, 0, 0, 0,
3392	0, 0, 0, 0,
3393	0, 0, 0, 0 ))
3394	},
3395	{ PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32, GROUP(
3396	0, 0, 0, 0,
3397	0, 0, 0, 0,
3398	0, 0, 0, 0,
3399	0, PORT114_DATA, PORT113_DATA, PORT112_DATA,
3400	PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
3401	PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
3402	PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
3403	PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA ))
3404	},
3405	{ PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32, GROUP(
3406	PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
3407	PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
3408	PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
3409	PORT115_DATA, 0, 0, 0,
3410	0, 0, 0, 0,
3411	0, 0, 0, 0,
3412	0, 0, 0, 0,
3413	0, 0, 0, 0 ))
3414	},
3415	{ PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32, GROUP(
3416	PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
3417	PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
3418	PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
3419	PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
3420	PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
3421	PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
3422	PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
3423	PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA ))
3424	},
3425	{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32, GROUP(
3426	PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
3427	PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
3428	PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
3429	PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
3430	PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
3431	PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
3432	PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
3433	PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA ))
3434	},
3435	{ PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32, GROUP(
3436	0, 0, 0, 0,
3437	0, 0, 0, 0,
3438	0, 0, 0, 0,
3439	0, 0, PORT209_DATA, PORT208_DATA,
3440	PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
3441	PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
3442	PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
3443	PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA ))
3444	},
3445	{ PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32, GROUP(
3446	0, 0, 0, 0,
3447	0, 0, 0, 0,
3448	0, 0, 0, 0,
3449	PORT211_DATA, PORT210_DATA, 0, 0,
3450	0, 0, 0, 0,
3451	0, 0, 0, 0,
3452	0, 0, 0, 0,
3453	0, 0, 0, 0 ))
3454	},
3455	{ /* sentinel */ }
3456	};
3457
3458	static const struct pinmux_irq pinmux_irqs[] = {
3459	PINMUX_IRQ(2, 13), /* IRQ0A */
3460	PINMUX_IRQ(20), /* IRQ1A */
3461	PINMUX_IRQ(11, 12), /* IRQ2A */
3462	PINMUX_IRQ(10, 14), /* IRQ3A */
3463	PINMUX_IRQ(15, 172), /* IRQ4A */
3464	PINMUX_IRQ(0, 1), /* IRQ5A */
3465	PINMUX_IRQ(121, 173), /* IRQ6A */
3466	PINMUX_IRQ(120, 209), /* IRQ7A */
3467	PINMUX_IRQ(119), /* IRQ8A */
3468	PINMUX_IRQ(118, 210), /* IRQ9A */
3469	PINMUX_IRQ(19), /* IRQ10A */
3470	PINMUX_IRQ(104), /* IRQ11A */
3471	PINMUX_IRQ(42, 97), /* IRQ12A */
3472	PINMUX_IRQ(64, 98), /* IRQ13A */
3473	PINMUX_IRQ(63, 99), /* IRQ14A */
3474	PINMUX_IRQ(62, 100), /* IRQ15A */
3475	PINMUX_IRQ(68, 211), /* IRQ16A */
3476	PINMUX_IRQ(69), /* IRQ17A */
3477	PINMUX_IRQ(70), /* IRQ18A */
3478	PINMUX_IRQ(71), /* IRQ19A */
3479	PINMUX_IRQ(67), /* IRQ20A */
3480	PINMUX_IRQ(202), /* IRQ21A */
3481	PINMUX_IRQ(95), /* IRQ22A */
3482	PINMUX_IRQ(96), /* IRQ23A */
3483	PINMUX_IRQ(180), /* IRQ24A */
3484	PINMUX_IRQ(38), /* IRQ25A */
3485	PINMUX_IRQ(58, 81), /* IRQ26A */
3486	PINMUX_IRQ(57, 168), /* IRQ27A */
3487	PINMUX_IRQ(56, 169), /* IRQ28A */
3488	PINMUX_IRQ(50, 170), /* IRQ29A */
3489	PINMUX_IRQ(49, 171), /* IRQ30A */
3490	PINMUX_IRQ(41, 167), /* IRQ31A */
3491	};
3492
3493	struct r8a7740_portcr_group {
3494	unsigned int end_pin;
3495	unsigned int offset;
3496	};
3497
3498	static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = {
3499	{ .end_pin: 83, .offset: 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
3500	};
3501
3502	static int r8a7740_pin_to_portcr(unsigned int pin)
3503	{
3504	unsigned int i;
3505
3506	for (i = 0; i < ARRAY_SIZE(r8a7740_portcr_offsets); ++i) {
3507	const struct r8a7740_portcr_group *group =
3508	&r8a7740_portcr_offsets[i];
3509
3510	if (pin <= group->end_pin)
3511	return group->offset + pin;
3512	}
3513
3514	return -1;
3515	}
3516
3517	static const struct sh_pfc_soc_operations r8a7740_pfc_ops = {
3518	.get_bias = rmobile_pinmux_get_bias,
3519	.set_bias = rmobile_pinmux_set_bias,
3520	.pin_to_portcr = r8a7740_pin_to_portcr,
3521	};
3522
3523	const struct sh_pfc_soc_info r8a7740_pinmux_info = {
3524	.name = "r8a7740_pfc",
3525	.ops = &r8a7740_pfc_ops,
3526
3527	.input = { PINMUX_INPUT_BEGIN,
3528	PINMUX_INPUT_END },
3529	.output = { PINMUX_OUTPUT_BEGIN,
3530	PINMUX_OUTPUT_END },
3531	.function = { PINMUX_FUNCTION_BEGIN,
3532	PINMUX_FUNCTION_END },
3533
3534	.pins = pinmux_pins,
3535	.nr_pins = ARRAY_SIZE(pinmux_pins),
3536	.groups = pinmux_groups,
3537	.nr_groups = ARRAY_SIZE(pinmux_groups),
3538	.functions = pinmux_functions,
3539	.nr_functions = ARRAY_SIZE(pinmux_functions),
3540
3541	.cfg_regs = pinmux_config_regs,
3542	.data_regs = pinmux_data_regs,
3543
3544	.pinmux_data = pinmux_data,
3545	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
3546
3547	.gpio_irq = pinmux_irqs,
3548	.gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
3549	};
3550