1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * R8A779A0 processor support - PFC hardware block. |
4 | * |
5 | * Copyright (C) 2020 Renesas Electronics Corp. |
6 | * |
7 | * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c |
8 | */ |
9 | |
10 | #include <linux/errno.h> |
11 | #include <linux/io.h> |
12 | #include <linux/kernel.h> |
13 | |
14 | #include "sh_pfc.h" |
15 | |
16 | #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) |
17 | |
18 | #define CPU_ALL_GP(fn, sfx) \ |
19 | PORT_GP_CFG_15(0, fn, sfx, CFG_FLAGS), \ |
20 | PORT_GP_CFG_1(0, 15, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
21 | PORT_GP_CFG_1(0, 16, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
22 | PORT_GP_CFG_1(0, 17, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
23 | PORT_GP_CFG_1(0, 18, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
24 | PORT_GP_CFG_1(0, 19, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
25 | PORT_GP_CFG_1(0, 20, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
26 | PORT_GP_CFG_1(0, 21, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
27 | PORT_GP_CFG_1(0, 22, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
28 | PORT_GP_CFG_1(0, 23, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
29 | PORT_GP_CFG_1(0, 24, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
30 | PORT_GP_CFG_1(0, 25, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
31 | PORT_GP_CFG_1(0, 26, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
32 | PORT_GP_CFG_1(0, 27, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
33 | PORT_GP_CFG_31(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
34 | PORT_GP_CFG_2(2, fn, sfx, CFG_FLAGS), \ |
35 | PORT_GP_CFG_1(2, 2, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
36 | PORT_GP_CFG_1(2, 3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
37 | PORT_GP_CFG_1(2, 4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
38 | PORT_GP_CFG_1(2, 5, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
39 | PORT_GP_CFG_1(2, 6, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
40 | PORT_GP_CFG_1(2, 7, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
41 | PORT_GP_CFG_1(2, 8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
42 | PORT_GP_CFG_1(2, 9, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
43 | PORT_GP_CFG_1(2, 10, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
44 | PORT_GP_CFG_1(2, 11, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
45 | PORT_GP_CFG_1(2, 12, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
46 | PORT_GP_CFG_1(2, 13, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
47 | PORT_GP_CFG_1(2, 14, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
48 | PORT_GP_CFG_1(2, 15, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
49 | PORT_GP_CFG_1(2, 16, fn, sfx, CFG_FLAGS), \ |
50 | PORT_GP_CFG_1(2, 17, fn, sfx, CFG_FLAGS), \ |
51 | PORT_GP_CFG_1(2, 18, fn, sfx, CFG_FLAGS), \ |
52 | PORT_GP_CFG_1(2, 19, fn, sfx, CFG_FLAGS), \ |
53 | PORT_GP_CFG_1(2, 20, fn, sfx, CFG_FLAGS), \ |
54 | PORT_GP_CFG_1(2, 21, fn, sfx, CFG_FLAGS), \ |
55 | PORT_GP_CFG_1(2, 22, fn, sfx, CFG_FLAGS), \ |
56 | PORT_GP_CFG_1(2, 23, fn, sfx, CFG_FLAGS), \ |
57 | PORT_GP_CFG_1(2, 24, fn, sfx, CFG_FLAGS), \ |
58 | PORT_GP_CFG_17(3, fn, sfx, CFG_FLAGS), \ |
59 | PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\ |
60 | PORT_GP_CFG_1(4, 18, fn, sfx, CFG_FLAGS), \ |
61 | PORT_GP_CFG_1(4, 19, fn, sfx, CFG_FLAGS), \ |
62 | PORT_GP_CFG_1(4, 20, fn, sfx, CFG_FLAGS), \ |
63 | PORT_GP_CFG_1(4, 21, fn, sfx, CFG_FLAGS), \ |
64 | PORT_GP_CFG_1(4, 22, fn, sfx, CFG_FLAGS), \ |
65 | PORT_GP_CFG_1(4, 23, fn, sfx, CFG_FLAGS), \ |
66 | PORT_GP_CFG_1(4, 24, fn, sfx, CFG_FLAGS), \ |
67 | PORT_GP_CFG_1(4, 25, fn, sfx, CFG_FLAGS), \ |
68 | PORT_GP_CFG_1(4, 26, fn, sfx, CFG_FLAGS), \ |
69 | PORT_GP_CFG_18(5, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\ |
70 | PORT_GP_CFG_1(5, 18, fn, sfx, CFG_FLAGS), \ |
71 | PORT_GP_CFG_1(5, 19, fn, sfx, CFG_FLAGS), \ |
72 | PORT_GP_CFG_1(5, 20, fn, sfx, CFG_FLAGS), \ |
73 | PORT_GP_CFG_18(6, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\ |
74 | PORT_GP_CFG_1(6, 18, fn, sfx, CFG_FLAGS), \ |
75 | PORT_GP_CFG_1(6, 19, fn, sfx, CFG_FLAGS), \ |
76 | PORT_GP_CFG_1(6, 20, fn, sfx, CFG_FLAGS), \ |
77 | PORT_GP_CFG_18(7, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\ |
78 | PORT_GP_CFG_1(7, 18, fn, sfx, CFG_FLAGS), \ |
79 | PORT_GP_CFG_1(7, 19, fn, sfx, CFG_FLAGS), \ |
80 | PORT_GP_CFG_1(7, 20, fn, sfx, CFG_FLAGS), \ |
81 | PORT_GP_CFG_18(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\ |
82 | PORT_GP_CFG_1(8, 18, fn, sfx, CFG_FLAGS), \ |
83 | PORT_GP_CFG_1(8, 19, fn, sfx, CFG_FLAGS), \ |
84 | PORT_GP_CFG_1(8, 20, fn, sfx, CFG_FLAGS), \ |
85 | PORT_GP_CFG_18(9, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\ |
86 | PORT_GP_CFG_1(9, 18, fn, sfx, CFG_FLAGS), \ |
87 | PORT_GP_CFG_1(9, 19, fn, sfx, CFG_FLAGS), \ |
88 | PORT_GP_CFG_1(9, 20, fn, sfx, CFG_FLAGS) |
89 | |
90 | #define CPU_ALL_NOGP(fn) \ |
91 | PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ |
92 | PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ |
93 | PIN_NOGP_CFG(DCUTRST_N_LPDRST_N, "DCUTRST#_LPDRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ |
94 | PIN_NOGP_CFG(DCUTCK_LPDCLK, "DCUTCK_LPDCLK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ |
95 | PIN_NOGP_CFG(DCUTMS, "DCUTMS", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ |
96 | PIN_NOGP_CFG(DCUTDI_LPDI, "DCUTDI_LPDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) |
97 | |
98 | /* |
99 | * F_() : just information |
100 | * FM() : macro for FN_xxx / xxx_MARK |
101 | */ |
102 | |
103 | /* GPSR0 */ |
104 | #define GPSR0_27 FM(MMC_D7) |
105 | #define GPSR0_26 FM(MMC_D6) |
106 | #define GPSR0_25 FM(MMC_D5) |
107 | #define GPSR0_24 FM(MMC_D4) |
108 | #define GPSR0_23 FM(MMC_SD_CLK) |
109 | #define GPSR0_22 FM(MMC_SD_D3) |
110 | #define GPSR0_21 FM(MMC_SD_D2) |
111 | #define GPSR0_20 FM(MMC_SD_D1) |
112 | #define GPSR0_19 FM(MMC_SD_D0) |
113 | #define GPSR0_18 FM(MMC_SD_CMD) |
114 | #define GPSR0_17 FM(MMC_DS) |
115 | #define GPSR0_16 FM(SD_CD) |
116 | #define GPSR0_15 FM(SD_WP) |
117 | #define GPSR0_14 FM(RPC_INT_N) |
118 | #define GPSR0_13 FM(RPC_WP_N) |
119 | #define GPSR0_12 FM(RPC_RESET_N) |
120 | #define GPSR0_11 FM(QSPI1_SSL) |
121 | #define GPSR0_10 FM(QSPI1_IO3) |
122 | #define GPSR0_9 FM(QSPI1_IO2) |
123 | #define GPSR0_8 FM(QSPI1_MISO_IO1) |
124 | #define GPSR0_7 FM(QSPI1_MOSI_IO0) |
125 | #define GPSR0_6 FM(QSPI1_SPCLK) |
126 | #define GPSR0_5 FM(QSPI0_SSL) |
127 | #define GPSR0_4 FM(QSPI0_IO3) |
128 | #define GPSR0_3 FM(QSPI0_IO2) |
129 | #define GPSR0_2 FM(QSPI0_MISO_IO1) |
130 | #define GPSR0_1 FM(QSPI0_MOSI_IO0) |
131 | #define GPSR0_0 FM(QSPI0_SPCLK) |
132 | |
133 | /* GPSR1 */ |
134 | #define GPSR1_30 F_(GP1_30, IP3SR1_27_24) |
135 | #define GPSR1_29 F_(GP1_29, IP3SR1_23_20) |
136 | #define GPSR1_28 F_(GP1_28, IP3SR1_19_16) |
137 | #define GPSR1_27 F_(IRQ3, IP3SR1_15_12) |
138 | #define GPSR1_26 F_(IRQ2, IP3SR1_11_8) |
139 | #define GPSR1_25 F_(IRQ1, IP3SR1_7_4) |
140 | #define GPSR1_24 F_(IRQ0, IP3SR1_3_0) |
141 | #define GPSR1_23 F_(MSIOF2_SS2, IP2SR1_31_28) |
142 | #define GPSR1_22 F_(MSIOF2_SS1, IP2SR1_27_24) |
143 | #define GPSR1_21 F_(MSIOF2_SYNC, IP2SR1_23_20) |
144 | #define GPSR1_20 F_(MSIOF2_SCK, IP2SR1_19_16) |
145 | #define GPSR1_19 F_(MSIOF2_TXD, IP2SR1_15_12) |
146 | #define GPSR1_18 F_(MSIOF2_RXD, IP2SR1_11_8) |
147 | #define GPSR1_17 F_(MSIOF1_SS2, IP2SR1_7_4) |
148 | #define GPSR1_16 F_(MSIOF1_SS1, IP2SR1_3_0) |
149 | #define GPSR1_15 F_(MSIOF1_SYNC, IP1SR1_31_28) |
150 | #define GPSR1_14 F_(MSIOF1_SCK, IP1SR1_27_24) |
151 | #define GPSR1_13 F_(MSIOF1_TXD, IP1SR1_23_20) |
152 | #define GPSR1_12 F_(MSIOF1_RXD, IP1SR1_19_16) |
153 | #define GPSR1_11 F_(MSIOF0_SS2, IP1SR1_15_12) |
154 | #define GPSR1_10 F_(MSIOF0_SS1, IP1SR1_11_8) |
155 | #define GPSR1_9 F_(MSIOF0_SYNC, IP1SR1_7_4) |
156 | #define GPSR1_8 F_(MSIOF0_SCK, IP1SR1_3_0) |
157 | #define GPSR1_7 F_(MSIOF0_TXD, IP0SR1_31_28) |
158 | #define GPSR1_6 F_(MSIOF0_RXD, IP0SR1_27_24) |
159 | #define GPSR1_5 F_(HTX0, IP0SR1_23_20) |
160 | #define GPSR1_4 F_(HCTS0_N, IP0SR1_19_16) |
161 | #define GPSR1_3 F_(HRTS0_N, IP0SR1_15_12) |
162 | #define GPSR1_2 F_(HSCK0, IP0SR1_11_8) |
163 | #define GPSR1_1 F_(HRX0, IP0SR1_7_4) |
164 | #define GPSR1_0 F_(SCIF_CLK, IP0SR1_3_0) |
165 | |
166 | /* GPSR2 */ |
167 | #define GPSR2_24 FM(TCLK2_A) |
168 | #define GPSR2_23 F_(TCLK1_A, IP2SR2_31_28) |
169 | #define GPSR2_22 F_(TPU0TO1, IP2SR2_27_24) |
170 | #define GPSR2_21 F_(TPU0TO0, IP2SR2_23_20) |
171 | #define GPSR2_20 F_(CLK_EXTFXR, IP2SR2_19_16) |
172 | #define GPSR2_19 F_(RXDB_EXTFXR, IP2SR2_15_12) |
173 | #define GPSR2_18 F_(FXR_TXDB, IP2SR2_11_8) |
174 | #define GPSR2_17 F_(RXDA_EXTFXR_A, IP2SR2_7_4) |
175 | #define GPSR2_16 F_(FXR_TXDA_A, IP2SR2_3_0) |
176 | #define GPSR2_15 F_(GP2_15, IP1SR2_31_28) |
177 | #define GPSR2_14 F_(GP2_14, IP1SR2_27_24) |
178 | #define GPSR2_13 F_(GP2_13, IP1SR2_23_20) |
179 | #define GPSR2_12 F_(GP2_12, IP1SR2_19_16) |
180 | #define GPSR2_11 F_(GP2_11, IP1SR2_15_12) |
181 | #define GPSR2_10 F_(GP2_10, IP1SR2_11_8) |
182 | #define GPSR2_9 F_(GP2_09, IP1SR2_7_4) |
183 | #define GPSR2_8 F_(GP2_08, IP1SR2_3_0) |
184 | #define GPSR2_7 F_(GP2_07, IP0SR2_31_28) |
185 | #define GPSR2_6 F_(GP2_06, IP0SR2_27_24) |
186 | #define GPSR2_5 F_(GP2_05, IP0SR2_23_20) |
187 | #define GPSR2_4 F_(GP2_04, IP0SR2_19_16) |
188 | #define GPSR2_3 F_(GP2_03, IP0SR2_15_12) |
189 | #define GPSR2_2 F_(GP2_02, IP0SR2_11_8) |
190 | #define GPSR2_1 F_(IPC_CLKOUT, IP0SR2_7_4) |
191 | #define GPSR2_0 F_(IPC_CLKIN, IP0SR2_3_0) |
192 | |
193 | /* GPSR3 */ |
194 | #define GPSR3_16 FM(CANFD7_RX) |
195 | #define GPSR3_15 FM(CANFD7_TX) |
196 | #define GPSR3_14 FM(CANFD6_RX) |
197 | #define GPSR3_13 F_(CANFD6_TX, IP1SR3_23_20) |
198 | #define GPSR3_12 F_(CANFD5_RX, IP1SR3_19_16) |
199 | #define GPSR3_11 F_(CANFD5_TX, IP1SR3_15_12) |
200 | #define GPSR3_10 F_(CANFD4_RX, IP1SR3_11_8) |
201 | #define GPSR3_9 F_(CANFD4_TX, IP1SR3_7_4) |
202 | #define GPSR3_8 F_(CANFD3_RX, IP1SR3_3_0) |
203 | #define GPSR3_7 F_(CANFD3_TX, IP0SR3_31_28) |
204 | #define GPSR3_6 F_(CANFD2_RX, IP0SR3_27_24) |
205 | #define GPSR3_5 F_(CANFD2_TX, IP0SR3_23_20) |
206 | #define GPSR3_4 FM(CANFD1_RX) |
207 | #define GPSR3_3 FM(CANFD1_TX) |
208 | #define GPSR3_2 F_(CANFD0_RX, IP0SR3_11_8) |
209 | #define GPSR3_1 F_(CANFD0_TX, IP0SR3_7_4) |
210 | #define GPSR3_0 FM(CAN_CLK) |
211 | |
212 | /* GPSR4 */ |
213 | #define GPSR4_26 FM(AVS1) |
214 | #define GPSR4_25 FM(AVS0) |
215 | #define GPSR4_24 FM(PCIE3_CLKREQ_N) |
216 | #define GPSR4_23 FM(PCIE2_CLKREQ_N) |
217 | #define GPSR4_22 FM(PCIE1_CLKREQ_N) |
218 | #define GPSR4_21 FM(PCIE0_CLKREQ_N) |
219 | #define GPSR4_20 F_(AVB0_AVTP_PPS, IP2SR4_19_16) |
220 | #define GPSR4_19 F_(AVB0_AVTP_CAPTURE, IP2SR4_15_12) |
221 | #define GPSR4_18 F_(AVB0_AVTP_MATCH, IP2SR4_11_8) |
222 | #define GPSR4_17 F_(AVB0_LINK, IP2SR4_7_4) |
223 | #define GPSR4_16 FM(AVB0_PHY_INT) |
224 | #define GPSR4_15 F_(AVB0_MAGIC, IP1SR4_31_28) |
225 | #define GPSR4_14 F_(AVB0_MDC, IP1SR4_27_24) |
226 | #define GPSR4_13 F_(AVB0_MDIO, IP1SR4_23_20) |
227 | #define GPSR4_12 F_(AVB0_TXCREFCLK, IP1SR4_19_16) |
228 | #define GPSR4_11 F_(AVB0_TD3, IP1SR4_15_12) |
229 | #define GPSR4_10 F_(AVB0_TD2, IP1SR4_11_8) |
230 | #define GPSR4_9 F_(AVB0_TD1, IP1SR4_7_4) |
231 | #define GPSR4_8 F_(AVB0_TD0, IP1SR4_3_0) |
232 | #define GPSR4_7 F_(AVB0_TXC, IP0SR4_31_28) |
233 | #define GPSR4_6 F_(AVB0_TX_CTL, IP0SR4_27_24) |
234 | #define GPSR4_5 F_(AVB0_RD3, IP0SR4_23_20) |
235 | #define GPSR4_4 F_(AVB0_RD2, IP0SR4_19_16) |
236 | #define GPSR4_3 F_(AVB0_RD1, IP0SR4_15_12) |
237 | #define GPSR4_2 F_(AVB0_RD0, IP0SR4_11_8) |
238 | #define GPSR4_1 F_(AVB0_RXC, IP0SR4_7_4) |
239 | #define GPSR4_0 F_(AVB0_RX_CTL, IP0SR4_3_0) |
240 | |
241 | /* GPSR5 */ |
242 | #define GPSR5_20 F_(AVB1_AVTP_PPS, IP2SR5_19_16) |
243 | #define GPSR5_19 F_(AVB1_AVTP_CAPTURE, IP2SR5_15_12) |
244 | #define GPSR5_18 F_(AVB1_AVTP_MATCH, IP2SR5_11_8) |
245 | #define GPSR5_17 F_(AVB1_LINK, IP2SR5_7_4) |
246 | #define GPSR5_16 FM(AVB1_PHY_INT) |
247 | #define GPSR5_15 F_(AVB1_MAGIC, IP1SR5_31_28) |
248 | #define GPSR5_14 F_(AVB1_MDC, IP1SR5_27_24) |
249 | #define GPSR5_13 F_(AVB1_MDIO, IP1SR5_23_20) |
250 | #define GPSR5_12 F_(AVB1_TXCREFCLK, IP1SR5_19_16) |
251 | #define GPSR5_11 F_(AVB1_TD3, IP1SR5_15_12) |
252 | #define GPSR5_10 F_(AVB1_TD2, IP1SR5_11_8) |
253 | #define GPSR5_9 F_(AVB1_TD1, IP1SR5_7_4) |
254 | #define GPSR5_8 F_(AVB1_TD0, IP1SR5_3_0) |
255 | #define GPSR5_7 F_(AVB1_TXC, IP0SR5_31_28) |
256 | #define GPSR5_6 F_(AVB1_TX_CTL, IP0SR5_27_24) |
257 | #define GPSR5_5 F_(AVB1_RD3, IP0SR5_23_20) |
258 | #define GPSR5_4 F_(AVB1_RD2, IP0SR5_19_16) |
259 | #define GPSR5_3 F_(AVB1_RD1, IP0SR5_15_12) |
260 | #define GPSR5_2 F_(AVB1_RD0, IP0SR5_11_8) |
261 | #define GPSR5_1 F_(AVB1_RXC, IP0SR5_7_4) |
262 | #define GPSR5_0 F_(AVB1_RX_CTL, IP0SR5_3_0) |
263 | |
264 | /* GPSR6 */ |
265 | #define GPSR6_20 FM(AVB2_AVTP_PPS) |
266 | #define GPSR6_19 FM(AVB2_AVTP_CAPTURE) |
267 | #define GPSR6_18 FM(AVB2_AVTP_MATCH) |
268 | #define GPSR6_17 FM(AVB2_LINK) |
269 | #define GPSR6_16 FM(AVB2_PHY_INT) |
270 | #define GPSR6_15 FM(AVB2_MAGIC) |
271 | #define GPSR6_14 FM(AVB2_MDC) |
272 | #define GPSR6_13 FM(AVB2_MDIO) |
273 | #define GPSR6_12 FM(AVB2_TXCREFCLK) |
274 | #define GPSR6_11 FM(AVB2_TD3) |
275 | #define GPSR6_10 FM(AVB2_TD2) |
276 | #define GPSR6_9 FM(AVB2_TD1) |
277 | #define GPSR6_8 FM(AVB2_TD0) |
278 | #define GPSR6_7 FM(AVB2_TXC) |
279 | #define GPSR6_6 FM(AVB2_TX_CTL) |
280 | #define GPSR6_5 FM(AVB2_RD3) |
281 | #define GPSR6_4 FM(AVB2_RD2) |
282 | #define GPSR6_3 FM(AVB2_RD1) |
283 | #define GPSR6_2 FM(AVB2_RD0) |
284 | #define GPSR6_1 FM(AVB2_RXC) |
285 | #define GPSR6_0 FM(AVB2_RX_CTL) |
286 | |
287 | /* GPSR7 */ |
288 | #define GPSR7_20 FM(AVB3_AVTP_PPS) |
289 | #define GPSR7_19 FM(AVB3_AVTP_CAPTURE) |
290 | #define GPSR7_18 FM(AVB3_AVTP_MATCH) |
291 | #define GPSR7_17 FM(AVB3_LINK) |
292 | #define GPSR7_16 FM(AVB3_PHY_INT) |
293 | #define GPSR7_15 FM(AVB3_MAGIC) |
294 | #define GPSR7_14 FM(AVB3_MDC) |
295 | #define GPSR7_13 FM(AVB3_MDIO) |
296 | #define GPSR7_12 FM(AVB3_TXCREFCLK) |
297 | #define GPSR7_11 FM(AVB3_TD3) |
298 | #define GPSR7_10 FM(AVB3_TD2) |
299 | #define GPSR7_9 FM(AVB3_TD1) |
300 | #define GPSR7_8 FM(AVB3_TD0) |
301 | #define GPSR7_7 FM(AVB3_TXC) |
302 | #define GPSR7_6 FM(AVB3_TX_CTL) |
303 | #define GPSR7_5 FM(AVB3_RD3) |
304 | #define GPSR7_4 FM(AVB3_RD2) |
305 | #define GPSR7_3 FM(AVB3_RD1) |
306 | #define GPSR7_2 FM(AVB3_RD0) |
307 | #define GPSR7_1 FM(AVB3_RXC) |
308 | #define GPSR7_0 FM(AVB3_RX_CTL) |
309 | |
310 | /* GPSR8 */ |
311 | #define GPSR8_20 FM(AVB4_AVTP_PPS) |
312 | #define GPSR8_19 FM(AVB4_AVTP_CAPTURE) |
313 | #define GPSR8_18 FM(AVB4_AVTP_MATCH) |
314 | #define GPSR8_17 FM(AVB4_LINK) |
315 | #define GPSR8_16 FM(AVB4_PHY_INT) |
316 | #define GPSR8_15 FM(AVB4_MAGIC) |
317 | #define GPSR8_14 FM(AVB4_MDC) |
318 | #define GPSR8_13 FM(AVB4_MDIO) |
319 | #define GPSR8_12 FM(AVB4_TXCREFCLK) |
320 | #define GPSR8_11 FM(AVB4_TD3) |
321 | #define GPSR8_10 FM(AVB4_TD2) |
322 | #define GPSR8_9 FM(AVB4_TD1) |
323 | #define GPSR8_8 FM(AVB4_TD0) |
324 | #define GPSR8_7 FM(AVB4_TXC) |
325 | #define GPSR8_6 FM(AVB4_TX_CTL) |
326 | #define GPSR8_5 FM(AVB4_RD3) |
327 | #define GPSR8_4 FM(AVB4_RD2) |
328 | #define GPSR8_3 FM(AVB4_RD1) |
329 | #define GPSR8_2 FM(AVB4_RD0) |
330 | #define GPSR8_1 FM(AVB4_RXC) |
331 | #define GPSR8_0 FM(AVB4_RX_CTL) |
332 | |
333 | /* GPSR9 */ |
334 | #define GPSR9_20 FM(AVB5_AVTP_PPS) |
335 | #define GPSR9_19 FM(AVB5_AVTP_CAPTURE) |
336 | #define GPSR9_18 FM(AVB5_AVTP_MATCH) |
337 | #define GPSR9_17 FM(AVB5_LINK) |
338 | #define GPSR9_16 FM(AVB5_PHY_INT) |
339 | #define GPSR9_15 FM(AVB5_MAGIC) |
340 | #define GPSR9_14 FM(AVB5_MDC) |
341 | #define GPSR9_13 FM(AVB5_MDIO) |
342 | #define GPSR9_12 FM(AVB5_TXCREFCLK) |
343 | #define GPSR9_11 FM(AVB5_TD3) |
344 | #define GPSR9_10 FM(AVB5_TD2) |
345 | #define GPSR9_9 FM(AVB5_TD1) |
346 | #define GPSR9_8 FM(AVB5_TD0) |
347 | #define GPSR9_7 FM(AVB5_TXC) |
348 | #define GPSR9_6 FM(AVB5_TX_CTL) |
349 | #define GPSR9_5 FM(AVB5_RD3) |
350 | #define GPSR9_4 FM(AVB5_RD2) |
351 | #define GPSR9_3 FM(AVB5_RD1) |
352 | #define GPSR9_2 FM(AVB5_RD0) |
353 | #define GPSR9_1 FM(AVB5_RXC) |
354 | #define GPSR9_0 FM(AVB5_RX_CTL) |
355 | |
356 | /* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ |
357 | #define IP0SR1_3_0 FM(SCIF_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
358 | #define IP0SR1_7_4 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
359 | #define IP0SR1_11_8 FM(HSCK0) FM(SCK0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
360 | #define IP0SR1_15_12 FM(HRTS0_N) FM(RTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
361 | #define IP0SR1_19_16 FM(HCTS0_N) FM(CTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
362 | #define IP0SR1_23_20 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
363 | #define IP0SR1_27_24 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
364 | #define IP0SR1_31_28 FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR3) FM(A7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
365 | /* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ |
366 | #define IP1SR1_3_0 FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR4) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
367 | #define IP1SR1_7_4 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
368 | #define IP1SR1_11_8 FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
369 | #define IP1SR1_15_12 FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR7) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
370 | #define IP1SR1_19_16 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DG2) FM(A12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
371 | #define IP1SR1_23_20 FM(MSIOF1_TXD) FM(HRX3) FM(SCK3) F_(0, 0) FM(DU_DG3) FM(A13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
372 | #define IP1SR1_27_24 FM(MSIOF1_SCK) FM(HSCK3) FM(CTS3_N) F_(0, 0) FM(DU_DG4) FM(A14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
373 | #define IP1SR1_31_28 FM(MSIOF1_SYNC) FM(HRTS3_N) FM(RTS3_N) F_(0, 0) FM(DU_DG5) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
374 | /* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ |
375 | #define IP2SR1_3_0 FM(MSIOF1_SS1) FM(HCTS3_N) FM(RX3) F_(0, 0) FM(DU_DG6) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
376 | #define IP2SR1_7_4 FM(MSIOF1_SS2) FM(HTX3) FM(TX3) F_(0, 0) FM(DU_DG7) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
377 | #define IP2SR1_11_8 FM(MSIOF2_RXD) FM(HSCK1) FM(SCK1) F_(0, 0) FM(DU_DB2) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
378 | #define IP2SR1_15_12 FM(MSIOF2_TXD) FM(HCTS1_N) FM(CTS1_N) F_(0, 0) FM(DU_DB3) FM(A19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
379 | #define IP2SR1_19_16 FM(MSIOF2_SCK) FM(HRTS1_N) FM(RTS1_N) F_(0, 0) FM(DU_DB4) FM(A20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
380 | #define IP2SR1_23_20 FM(MSIOF2_SYNC) FM(HRX1) FM(RX1_A) F_(0, 0) FM(DU_DB5) FM(A21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
381 | #define IP2SR1_27_24 FM(MSIOF2_SS1) FM(HTX1) FM(TX1_A) F_(0, 0) FM(DU_DB6) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
382 | #define IP2SR1_31_28 FM(MSIOF2_SS2) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(DU_DB7) FM(A23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
383 | |
384 | /* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ |
385 | #define IP3SR1_3_0 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKOUT) FM(A24) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
386 | #define IP3SR1_7_4 FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_HSYNC) FM(A25) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
387 | #define IP3SR1_11_8 FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_VSYNC) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
388 | #define IP3SR1_15_12 FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_ODDF_DISP_CDE) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
389 | #define IP3SR1_19_16 FM(GP1_28) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
390 | #define IP3SR1_23_20 FM(GP1_29) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
391 | #define IP3SR1_27_24 FM(GP1_30) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
392 | |
393 | /* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ |
394 | #define IP0SR2_3_0 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
395 | #define IP0SR2_7_4 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
396 | #define IP0SR2_11_8 FM(GP2_02) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
397 | #define IP0SR2_15_12 FM(GP2_03) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
398 | #define IP0SR2_19_16 FM(GP2_04) F_(0, 0) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) FM(D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
399 | #define IP0SR2_23_20 FM(GP2_05) FM(HSCK2) FM(MSIOF4_TXD) FM(SCK4) F_(0, 0) FM(D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
400 | #define IP0SR2_27_24 FM(GP2_06) FM(HCTS2_N) FM(MSIOF4_SCK) FM(CTS4_N) F_(0, 0) FM(D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
401 | #define IP0SR2_31_28 FM(GP2_07) FM(HRTS2_N) FM(MSIOF4_SYNC) FM(RTS4_N) F_(0, 0) FM(D8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
402 | /* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ |
403 | #define IP1SR2_3_0 FM(GP2_08) FM(HRX2) FM(MSIOF4_SS1) FM(RX4) F_(0, 0) FM(D9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
404 | #define IP1SR2_7_4 FM(GP2_09) FM(HTX2) FM(MSIOF4_SS2) FM(TX4) F_(0, 0) FM(D10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
405 | #define IP1SR2_11_8 FM(GP2_10) FM(TCLK2_B) FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) FM(D11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
406 | #define IP1SR2_15_12 FM(GP2_11) FM(TCLK3) FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) FM(D12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
407 | #define IP1SR2_19_16 FM(GP2_12) FM(TCLK4) FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) FM(D13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
408 | #define IP1SR2_23_20 FM(GP2_13) F_(0, 0) FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
409 | #define IP1SR2_27_24 FM(GP2_14) FM(IRQ4) FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
410 | #define IP1SR2_31_28 FM(GP2_15) FM(IRQ5) FM(MSIOF5_SS2) FM(CPG_CPCKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
411 | /* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ |
412 | #define IP2SR2_3_0 FM(FXR_TXDA_A) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
413 | #define IP2SR2_7_4 FM(RXDA_EXTFXR_A) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) FM(BS_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
414 | #define IP2SR2_11_8 FM(FXR_TXDB) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(RD_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
415 | #define IP2SR2_15_12 FM(RXDB_EXTFXR) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(WE0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
416 | #define IP2SR2_19_16 FM(CLK_EXTFXR) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
417 | #define IP2SR2_23_20 FM(TPU0TO0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(RD_WR_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
418 | #define IP2SR2_27_24 FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
419 | #define IP2SR2_31_28 FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(EX_WAIT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
420 | |
421 | /* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ |
422 | #define IP0SR3_7_4 FM(CANFD0_TX) FM(FXR_TXDA_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
423 | #define IP0SR3_11_8 FM(CANFD0_RX) FM(RXDA_EXTFXR_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
424 | #define IP0SR3_23_20 FM(CANFD2_TX) FM(TPU0TO2) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
425 | #define IP0SR3_27_24 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
426 | #define IP0SR3_31_28 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
427 | /* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ |
428 | #define IP1SR3_3_0 FM(CANFD3_RX) F_(0, 0) FM(PWM3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
429 | #define IP1SR3_7_4 FM(CANFD4_TX) F_(0, 0) FM(PWM4) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
430 | #define IP1SR3_11_8 FM(CANFD4_RX) F_(0, 0) F_(0, 0) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
431 | #define IP1SR3_15_12 FM(CANFD5_TX) F_(0, 0) F_(0, 0) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
432 | #define IP1SR3_19_16 FM(CANFD5_RX) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
433 | #define IP1SR3_23_20 FM(CANFD6_TX) F_(0, 0) F_(0, 0) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
434 | |
435 | /* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ |
436 | #define IP0SR4_3_0 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
437 | #define IP0SR4_7_4 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
438 | #define IP0SR4_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
439 | #define IP0SR4_15_12 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
440 | #define IP0SR4_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
441 | #define IP0SR4_23_20 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
442 | #define IP0SR4_27_24 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
443 | #define IP0SR4_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
444 | /* IP1SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ |
445 | #define IP1SR4_3_0 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
446 | #define IP1SR4_7_4 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
447 | #define IP1SR4_11_8 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
448 | #define IP1SR4_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
449 | #define IP1SR4_19_16 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
450 | #define IP1SR4_23_20 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
451 | #define IP1SR4_27_24 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
452 | #define IP1SR4_31_28 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
453 | /* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ |
454 | #define IP2SR4_7_4 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
455 | #define IP2SR4_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
456 | #define IP2SR4_15_12 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
457 | #define IP2SR4_19_16 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
458 | |
459 | /* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ |
460 | #define IP0SR5_3_0 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
461 | #define IP0SR5_7_4 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
462 | #define IP0SR5_11_8 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
463 | #define IP0SR5_15_12 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
464 | #define IP0SR5_19_16 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
465 | #define IP0SR5_23_20 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
466 | #define IP0SR5_27_24 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
467 | #define IP0SR5_31_28 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
468 | /* IP1SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ |
469 | #define IP1SR5_3_0 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
470 | #define IP1SR5_7_4 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
471 | #define IP1SR5_11_8 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
472 | #define IP1SR5_15_12 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
473 | #define IP1SR5_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
474 | #define IP1SR5_23_20 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
475 | #define IP1SR5_27_24 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
476 | #define IP1SR5_31_28 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
477 | /* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ |
478 | #define IP2SR5_7_4 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
479 | #define IP2SR5_11_8 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
480 | #define IP2SR5_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
481 | #define IP2SR5_19_16 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
482 | |
483 | #define PINMUX_GPSR \ |
484 | \ |
485 | GPSR1_30 \ |
486 | GPSR1_29 \ |
487 | GPSR1_28 \ |
488 | GPSR0_27 GPSR1_27 \ |
489 | GPSR0_26 GPSR1_26 GPSR4_26 \ |
490 | GPSR0_25 GPSR1_25 GPSR4_25 \ |
491 | GPSR0_24 GPSR1_24 GPSR2_24 GPSR4_24 \ |
492 | GPSR0_23 GPSR1_23 GPSR2_23 GPSR4_23 \ |
493 | GPSR0_22 GPSR1_22 GPSR2_22 GPSR4_22 \ |
494 | GPSR0_21 GPSR1_21 GPSR2_21 GPSR4_21 \ |
495 | GPSR0_20 GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 GPSR6_20 GPSR7_20 GPSR8_20 GPSR9_20 \ |
496 | GPSR0_19 GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 GPSR6_19 GPSR7_19 GPSR8_19 GPSR9_19 \ |
497 | GPSR0_18 GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 GPSR6_18 GPSR7_18 GPSR8_18 GPSR9_18 \ |
498 | GPSR0_17 GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 GPSR6_17 GPSR7_17 GPSR8_17 GPSR9_17 \ |
499 | GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 GPSR5_16 GPSR6_16 GPSR7_16 GPSR8_16 GPSR9_16 \ |
500 | GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 GPSR7_15 GPSR8_15 GPSR9_15 \ |
501 | GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 GPSR7_14 GPSR8_14 GPSR9_14 \ |
502 | GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 GPSR7_13 GPSR8_13 GPSR9_13 \ |
503 | GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 GPSR7_12 GPSR8_12 GPSR9_12 \ |
504 | GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 GPSR7_11 GPSR8_11 GPSR9_11 \ |
505 | GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 GPSR7_10 GPSR8_10 GPSR9_10 \ |
506 | GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 GPSR7_9 GPSR8_9 GPSR9_9 \ |
507 | GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 GPSR7_8 GPSR8_8 GPSR9_8 \ |
508 | GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 GPSR7_7 GPSR8_7 GPSR9_7 \ |
509 | GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 GPSR7_6 GPSR8_6 GPSR9_6 \ |
510 | GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 GPSR7_5 GPSR8_5 GPSR9_5 \ |
511 | GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 GPSR7_4 GPSR8_4 GPSR9_4 \ |
512 | GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 GPSR8_3 GPSR9_3 \ |
513 | GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 GPSR8_2 GPSR9_2 \ |
514 | GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 GPSR8_1 GPSR9_1 \ |
515 | GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 GPSR8_0 GPSR9_0 |
516 | |
517 | #define PINMUX_IPSR \ |
518 | \ |
519 | FM(IP0SR1_3_0) IP0SR1_3_0 FM(IP1SR1_3_0) IP1SR1_3_0 FM(IP2SR1_3_0) IP2SR1_3_0 FM(IP3SR1_3_0) IP3SR1_3_0 \ |
520 | FM(IP0SR1_7_4) IP0SR1_7_4 FM(IP1SR1_7_4) IP1SR1_7_4 FM(IP2SR1_7_4) IP2SR1_7_4 FM(IP3SR1_7_4) IP3SR1_7_4 \ |
521 | FM(IP0SR1_11_8) IP0SR1_11_8 FM(IP1SR1_11_8) IP1SR1_11_8 FM(IP2SR1_11_8) IP2SR1_11_8 FM(IP3SR1_11_8) IP3SR1_11_8 \ |
522 | FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \ |
523 | FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \ |
524 | FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 FM(IP3SR1_23_20) IP3SR1_23_20 \ |
525 | FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 FM(IP3SR1_27_24) IP3SR1_27_24 \ |
526 | FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 \ |
527 | \ |
528 | FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 FM(IP2SR2_3_0) IP2SR2_3_0 \ |
529 | FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \ |
530 | FM(IP0SR2_11_8) IP0SR2_11_8 FM(IP1SR2_11_8) IP1SR2_11_8 FM(IP2SR2_11_8) IP2SR2_11_8 \ |
531 | FM(IP0SR2_15_12) IP0SR2_15_12 FM(IP1SR2_15_12) IP1SR2_15_12 FM(IP2SR2_15_12) IP2SR2_15_12 \ |
532 | FM(IP0SR2_19_16) IP0SR2_19_16 FM(IP1SR2_19_16) IP1SR2_19_16 FM(IP2SR2_19_16) IP2SR2_19_16 \ |
533 | FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 FM(IP2SR2_23_20) IP2SR2_23_20 \ |
534 | FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 FM(IP2SR2_27_24) IP2SR2_27_24 \ |
535 | FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 FM(IP2SR2_31_28) IP2SR2_31_28 \ |
536 | \ |
537 | FM(IP1SR3_3_0) IP1SR3_3_0 \ |
538 | FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 \ |
539 | FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 \ |
540 | FM(IP1SR3_15_12) IP1SR3_15_12 \ |
541 | FM(IP1SR3_19_16) IP1SR3_19_16 \ |
542 | FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 \ |
543 | FM(IP0SR3_27_24) IP0SR3_27_24 \ |
544 | FM(IP0SR3_31_28) IP0SR3_31_28 \ |
545 | \ |
546 | FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 \ |
547 | FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 FM(IP2SR4_7_4) IP2SR4_7_4 \ |
548 | FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 FM(IP2SR4_11_8) IP2SR4_11_8 \ |
549 | FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 FM(IP2SR4_15_12) IP2SR4_15_12 \ |
550 | FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 FM(IP2SR4_19_16) IP2SR4_19_16 \ |
551 | FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 \ |
552 | FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 \ |
553 | FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 \ |
554 | \ |
555 | FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 \ |
556 | FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \ |
557 | FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \ |
558 | FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \ |
559 | FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \ |
560 | FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 \ |
561 | FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 \ |
562 | FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 |
563 | |
564 | /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ |
565 | #define MOD_SEL2_15_14 FM(SEL_I2C6_0) F_(0, 0) F_(0, 0) FM(SEL_I2C6_3) |
566 | #define MOD_SEL2_13_12 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3) |
567 | #define MOD_SEL2_11_10 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3) |
568 | #define MOD_SEL2_9_8 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3) |
569 | #define MOD_SEL2_7_6 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3) |
570 | #define MOD_SEL2_5_4 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3) |
571 | #define MOD_SEL2_3_2 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3) |
572 | |
573 | #define PINMUX_MOD_SELS \ |
574 | \ |
575 | MOD_SEL2_15_14 \ |
576 | MOD_SEL2_13_12 \ |
577 | MOD_SEL2_11_10 \ |
578 | MOD_SEL2_9_8 \ |
579 | MOD_SEL2_7_6 \ |
580 | MOD_SEL2_5_4 \ |
581 | MOD_SEL2_3_2 |
582 | |
583 | #define PINMUX_PHYS \ |
584 | FM(SCL0) FM(SDA0) FM(SCL1) FM(SDA1) FM(SCL2) FM(SDA2) FM(SCL3) FM(SDA3) \ |
585 | FM(SCL4) FM(SDA4) FM(SCL5) FM(SDA5) FM(SCL6) FM(SDA6) |
586 | |
587 | enum { |
588 | PINMUX_RESERVED = 0, |
589 | |
590 | PINMUX_DATA_BEGIN, |
591 | GP_ALL(DATA), |
592 | PINMUX_DATA_END, |
593 | |
594 | #define F_(x, y) |
595 | #define FM(x) FN_##x, |
596 | PINMUX_FUNCTION_BEGIN, |
597 | GP_ALL(FN), |
598 | PINMUX_GPSR |
599 | PINMUX_IPSR |
600 | PINMUX_MOD_SELS |
601 | PINMUX_FUNCTION_END, |
602 | #undef F_ |
603 | #undef FM |
604 | |
605 | #define F_(x, y) |
606 | #define FM(x) x##_MARK, |
607 | PINMUX_MARK_BEGIN, |
608 | PINMUX_GPSR |
609 | PINMUX_IPSR |
610 | PINMUX_MOD_SELS |
611 | PINMUX_PHYS |
612 | PINMUX_MARK_END, |
613 | #undef F_ |
614 | #undef FM |
615 | }; |
616 | |
617 | static const u16 pinmux_data[] = { |
618 | /* Using GP_2_[2-15] requires disabling I2C in MOD_SEL2 */ |
619 | #define GP_2_2_FN GP_2_2_FN, FN_SEL_I2C0_0 |
620 | #define GP_2_3_FN GP_2_3_FN, FN_SEL_I2C0_0 |
621 | #define GP_2_4_FN GP_2_4_FN, FN_SEL_I2C1_0 |
622 | #define GP_2_5_FN GP_2_5_FN, FN_SEL_I2C1_0 |
623 | #define GP_2_6_FN GP_2_6_FN, FN_SEL_I2C2_0 |
624 | #define GP_2_7_FN GP_2_7_FN, FN_SEL_I2C2_0 |
625 | #define GP_2_8_FN GP_2_8_FN, FN_SEL_I2C3_0 |
626 | #define GP_2_9_FN GP_2_9_FN, FN_SEL_I2C3_0 |
627 | #define GP_2_10_FN GP_2_10_FN, FN_SEL_I2C4_0 |
628 | #define GP_2_11_FN GP_2_11_FN, FN_SEL_I2C4_0 |
629 | #define GP_2_12_FN GP_2_12_FN, FN_SEL_I2C5_0 |
630 | #define GP_2_13_FN GP_2_13_FN, FN_SEL_I2C5_0 |
631 | #define GP_2_14_FN GP_2_14_FN, FN_SEL_I2C6_0 |
632 | #define GP_2_15_FN GP_2_15_FN, FN_SEL_I2C6_0 |
633 | PINMUX_DATA_GP_ALL(), |
634 | #undef GP_2_2_FN |
635 | #undef GP_2_3_FN |
636 | #undef GP_2_4_FN |
637 | #undef GP_2_5_FN |
638 | #undef GP_2_6_FN |
639 | #undef GP_2_7_FN |
640 | #undef GP_2_8_FN |
641 | #undef GP_2_9_FN |
642 | #undef GP_2_10_FN |
643 | #undef GP_2_11_FN |
644 | #undef GP_2_12_FN |
645 | #undef GP_2_13_FN |
646 | #undef GP_2_14_FN |
647 | #undef GP_2_15_FN |
648 | |
649 | PINMUX_SINGLE(MMC_D7), |
650 | PINMUX_SINGLE(MMC_D6), |
651 | PINMUX_SINGLE(MMC_D5), |
652 | PINMUX_SINGLE(MMC_D4), |
653 | PINMUX_SINGLE(MMC_SD_CLK), |
654 | PINMUX_SINGLE(MMC_SD_D3), |
655 | PINMUX_SINGLE(MMC_SD_D2), |
656 | PINMUX_SINGLE(MMC_SD_D1), |
657 | PINMUX_SINGLE(MMC_SD_D0), |
658 | PINMUX_SINGLE(MMC_SD_CMD), |
659 | PINMUX_SINGLE(MMC_DS), |
660 | |
661 | PINMUX_SINGLE(SD_CD), |
662 | PINMUX_SINGLE(SD_WP), |
663 | |
664 | PINMUX_SINGLE(RPC_INT_N), |
665 | PINMUX_SINGLE(RPC_WP_N), |
666 | PINMUX_SINGLE(RPC_RESET_N), |
667 | |
668 | PINMUX_SINGLE(QSPI1_SSL), |
669 | PINMUX_SINGLE(QSPI1_IO3), |
670 | PINMUX_SINGLE(QSPI1_IO2), |
671 | PINMUX_SINGLE(QSPI1_MISO_IO1), |
672 | PINMUX_SINGLE(QSPI1_MOSI_IO0), |
673 | PINMUX_SINGLE(QSPI1_SPCLK), |
674 | PINMUX_SINGLE(QSPI0_SSL), |
675 | PINMUX_SINGLE(QSPI0_IO3), |
676 | PINMUX_SINGLE(QSPI0_IO2), |
677 | PINMUX_SINGLE(QSPI0_MISO_IO1), |
678 | PINMUX_SINGLE(QSPI0_MOSI_IO0), |
679 | PINMUX_SINGLE(QSPI0_SPCLK), |
680 | |
681 | PINMUX_SINGLE(TCLK2_A), |
682 | |
683 | PINMUX_SINGLE(CANFD7_RX), |
684 | PINMUX_SINGLE(CANFD7_TX), |
685 | PINMUX_SINGLE(CANFD6_RX), |
686 | PINMUX_SINGLE(CANFD1_RX), |
687 | PINMUX_SINGLE(CANFD1_TX), |
688 | PINMUX_SINGLE(CAN_CLK), |
689 | |
690 | PINMUX_SINGLE(AVS1), |
691 | PINMUX_SINGLE(AVS0), |
692 | |
693 | PINMUX_SINGLE(PCIE3_CLKREQ_N), |
694 | PINMUX_SINGLE(PCIE2_CLKREQ_N), |
695 | PINMUX_SINGLE(PCIE1_CLKREQ_N), |
696 | PINMUX_SINGLE(PCIE0_CLKREQ_N), |
697 | |
698 | PINMUX_SINGLE(AVB0_PHY_INT), |
699 | |
700 | PINMUX_SINGLE(AVB1_PHY_INT), |
701 | |
702 | PINMUX_SINGLE(AVB2_AVTP_PPS), |
703 | PINMUX_SINGLE(AVB2_AVTP_CAPTURE), |
704 | PINMUX_SINGLE(AVB2_AVTP_MATCH), |
705 | PINMUX_SINGLE(AVB2_LINK), |
706 | PINMUX_SINGLE(AVB2_PHY_INT), |
707 | PINMUX_SINGLE(AVB2_MAGIC), |
708 | PINMUX_SINGLE(AVB2_MDC), |
709 | PINMUX_SINGLE(AVB2_MDIO), |
710 | PINMUX_SINGLE(AVB2_TXCREFCLK), |
711 | PINMUX_SINGLE(AVB2_TD3), |
712 | PINMUX_SINGLE(AVB2_TD2), |
713 | PINMUX_SINGLE(AVB2_TD1), |
714 | PINMUX_SINGLE(AVB2_TD0), |
715 | PINMUX_SINGLE(AVB2_TXC), |
716 | PINMUX_SINGLE(AVB2_TX_CTL), |
717 | PINMUX_SINGLE(AVB2_RD3), |
718 | PINMUX_SINGLE(AVB2_RD2), |
719 | PINMUX_SINGLE(AVB2_RD1), |
720 | PINMUX_SINGLE(AVB2_RD0), |
721 | PINMUX_SINGLE(AVB2_RXC), |
722 | PINMUX_SINGLE(AVB2_RX_CTL), |
723 | |
724 | PINMUX_SINGLE(AVB3_AVTP_PPS), |
725 | PINMUX_SINGLE(AVB3_AVTP_CAPTURE), |
726 | PINMUX_SINGLE(AVB3_AVTP_MATCH), |
727 | PINMUX_SINGLE(AVB3_LINK), |
728 | PINMUX_SINGLE(AVB3_PHY_INT), |
729 | PINMUX_SINGLE(AVB3_MAGIC), |
730 | PINMUX_SINGLE(AVB3_MDC), |
731 | PINMUX_SINGLE(AVB3_MDIO), |
732 | PINMUX_SINGLE(AVB3_TXCREFCLK), |
733 | PINMUX_SINGLE(AVB3_TD3), |
734 | PINMUX_SINGLE(AVB3_TD2), |
735 | PINMUX_SINGLE(AVB3_TD1), |
736 | PINMUX_SINGLE(AVB3_TD0), |
737 | PINMUX_SINGLE(AVB3_TXC), |
738 | PINMUX_SINGLE(AVB3_TX_CTL), |
739 | PINMUX_SINGLE(AVB3_RD3), |
740 | PINMUX_SINGLE(AVB3_RD2), |
741 | PINMUX_SINGLE(AVB3_RD1), |
742 | PINMUX_SINGLE(AVB3_RD0), |
743 | PINMUX_SINGLE(AVB3_RXC), |
744 | PINMUX_SINGLE(AVB3_RX_CTL), |
745 | |
746 | PINMUX_SINGLE(AVB4_AVTP_PPS), |
747 | PINMUX_SINGLE(AVB4_AVTP_CAPTURE), |
748 | PINMUX_SINGLE(AVB4_AVTP_MATCH), |
749 | PINMUX_SINGLE(AVB4_LINK), |
750 | PINMUX_SINGLE(AVB4_PHY_INT), |
751 | PINMUX_SINGLE(AVB4_MAGIC), |
752 | PINMUX_SINGLE(AVB4_MDC), |
753 | PINMUX_SINGLE(AVB4_MDIO), |
754 | PINMUX_SINGLE(AVB4_TXCREFCLK), |
755 | PINMUX_SINGLE(AVB4_TD3), |
756 | PINMUX_SINGLE(AVB4_TD2), |
757 | PINMUX_SINGLE(AVB4_TD1), |
758 | PINMUX_SINGLE(AVB4_TD0), |
759 | PINMUX_SINGLE(AVB4_TXC), |
760 | PINMUX_SINGLE(AVB4_TX_CTL), |
761 | PINMUX_SINGLE(AVB4_RD3), |
762 | PINMUX_SINGLE(AVB4_RD2), |
763 | PINMUX_SINGLE(AVB4_RD1), |
764 | PINMUX_SINGLE(AVB4_RD0), |
765 | PINMUX_SINGLE(AVB4_RXC), |
766 | PINMUX_SINGLE(AVB4_RX_CTL), |
767 | |
768 | PINMUX_SINGLE(AVB5_AVTP_PPS), |
769 | PINMUX_SINGLE(AVB5_AVTP_CAPTURE), |
770 | PINMUX_SINGLE(AVB5_AVTP_MATCH), |
771 | PINMUX_SINGLE(AVB5_LINK), |
772 | PINMUX_SINGLE(AVB5_PHY_INT), |
773 | PINMUX_SINGLE(AVB5_MAGIC), |
774 | PINMUX_SINGLE(AVB5_MDC), |
775 | PINMUX_SINGLE(AVB5_MDIO), |
776 | PINMUX_SINGLE(AVB5_TXCREFCLK), |
777 | PINMUX_SINGLE(AVB5_TD3), |
778 | PINMUX_SINGLE(AVB5_TD2), |
779 | PINMUX_SINGLE(AVB5_TD1), |
780 | PINMUX_SINGLE(AVB5_TD0), |
781 | PINMUX_SINGLE(AVB5_TXC), |
782 | PINMUX_SINGLE(AVB5_TX_CTL), |
783 | PINMUX_SINGLE(AVB5_RD3), |
784 | PINMUX_SINGLE(AVB5_RD2), |
785 | PINMUX_SINGLE(AVB5_RD1), |
786 | PINMUX_SINGLE(AVB5_RD0), |
787 | PINMUX_SINGLE(AVB5_RXC), |
788 | PINMUX_SINGLE(AVB5_RX_CTL), |
789 | |
790 | /* IP0SR1 */ |
791 | PINMUX_IPSR_GPSR(IP0SR1_3_0, SCIF_CLK), |
792 | PINMUX_IPSR_GPSR(IP0SR1_3_0, A0), |
793 | |
794 | PINMUX_IPSR_GPSR(IP0SR1_7_4, HRX0), |
795 | PINMUX_IPSR_GPSR(IP0SR1_7_4, RX0), |
796 | PINMUX_IPSR_GPSR(IP0SR1_7_4, A1), |
797 | |
798 | PINMUX_IPSR_GPSR(IP0SR1_11_8, HSCK0), |
799 | PINMUX_IPSR_GPSR(IP0SR1_11_8, SCK0), |
800 | PINMUX_IPSR_GPSR(IP0SR1_11_8, A2), |
801 | |
802 | PINMUX_IPSR_GPSR(IP0SR1_15_12, HRTS0_N), |
803 | PINMUX_IPSR_GPSR(IP0SR1_15_12, RTS0_N), |
804 | PINMUX_IPSR_GPSR(IP0SR1_15_12, A3), |
805 | |
806 | PINMUX_IPSR_GPSR(IP0SR1_19_16, HCTS0_N), |
807 | PINMUX_IPSR_GPSR(IP0SR1_19_16, CTS0_N), |
808 | PINMUX_IPSR_GPSR(IP0SR1_19_16, A4), |
809 | |
810 | PINMUX_IPSR_GPSR(IP0SR1_23_20, HTX0), |
811 | PINMUX_IPSR_GPSR(IP0SR1_23_20, TX0), |
812 | PINMUX_IPSR_GPSR(IP0SR1_23_20, A5), |
813 | |
814 | PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_RXD), |
815 | PINMUX_IPSR_GPSR(IP0SR1_27_24, DU_DR2), |
816 | PINMUX_IPSR_GPSR(IP0SR1_27_24, A6), |
817 | |
818 | PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_TXD), |
819 | PINMUX_IPSR_GPSR(IP0SR1_31_28, DU_DR3), |
820 | PINMUX_IPSR_GPSR(IP0SR1_31_28, A7), |
821 | |
822 | /* IP1SR1 */ |
823 | PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SCK), |
824 | PINMUX_IPSR_GPSR(IP1SR1_3_0, DU_DR4), |
825 | PINMUX_IPSR_GPSR(IP1SR1_3_0, A8), |
826 | |
827 | PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_SYNC), |
828 | PINMUX_IPSR_GPSR(IP1SR1_7_4, DU_DR5), |
829 | PINMUX_IPSR_GPSR(IP1SR1_7_4, A9), |
830 | |
831 | PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SS1), |
832 | PINMUX_IPSR_GPSR(IP1SR1_11_8, DU_DR6), |
833 | PINMUX_IPSR_GPSR(IP1SR1_11_8, A10), |
834 | |
835 | PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_SS2), |
836 | PINMUX_IPSR_GPSR(IP1SR1_15_12, DU_DR7), |
837 | PINMUX_IPSR_GPSR(IP1SR1_15_12, A11), |
838 | |
839 | PINMUX_IPSR_GPSR(IP1SR1_19_16, MSIOF1_RXD), |
840 | PINMUX_IPSR_GPSR(IP1SR1_19_16, DU_DG2), |
841 | PINMUX_IPSR_GPSR(IP1SR1_19_16, A12), |
842 | |
843 | PINMUX_IPSR_GPSR(IP1SR1_23_20, MSIOF1_TXD), |
844 | PINMUX_IPSR_GPSR(IP1SR1_23_20, HRX3), |
845 | PINMUX_IPSR_GPSR(IP1SR1_23_20, SCK3), |
846 | PINMUX_IPSR_GPSR(IP1SR1_23_20, DU_DG3), |
847 | PINMUX_IPSR_GPSR(IP1SR1_23_20, A13), |
848 | |
849 | PINMUX_IPSR_GPSR(IP1SR1_27_24, MSIOF1_SCK), |
850 | PINMUX_IPSR_GPSR(IP1SR1_27_24, HSCK3), |
851 | PINMUX_IPSR_GPSR(IP1SR1_27_24, CTS3_N), |
852 | PINMUX_IPSR_GPSR(IP1SR1_27_24, DU_DG4), |
853 | PINMUX_IPSR_GPSR(IP1SR1_27_24, A14), |
854 | |
855 | PINMUX_IPSR_GPSR(IP1SR1_31_28, MSIOF1_SYNC), |
856 | PINMUX_IPSR_GPSR(IP1SR1_31_28, HRTS3_N), |
857 | PINMUX_IPSR_GPSR(IP1SR1_31_28, RTS3_N), |
858 | PINMUX_IPSR_GPSR(IP1SR1_31_28, DU_DG5), |
859 | PINMUX_IPSR_GPSR(IP1SR1_31_28, A15), |
860 | |
861 | /* IP2SR1 */ |
862 | PINMUX_IPSR_GPSR(IP2SR1_3_0, MSIOF1_SS1), |
863 | PINMUX_IPSR_GPSR(IP2SR1_3_0, HCTS3_N), |
864 | PINMUX_IPSR_GPSR(IP2SR1_3_0, RX3), |
865 | PINMUX_IPSR_GPSR(IP2SR1_3_0, DU_DG6), |
866 | PINMUX_IPSR_GPSR(IP2SR1_3_0, A16), |
867 | |
868 | PINMUX_IPSR_GPSR(IP2SR1_7_4, MSIOF1_SS2), |
869 | PINMUX_IPSR_GPSR(IP2SR1_7_4, HTX3), |
870 | PINMUX_IPSR_GPSR(IP2SR1_7_4, TX3), |
871 | PINMUX_IPSR_GPSR(IP2SR1_7_4, DU_DG7), |
872 | PINMUX_IPSR_GPSR(IP2SR1_7_4, A17), |
873 | |
874 | PINMUX_IPSR_GPSR(IP2SR1_11_8, MSIOF2_RXD), |
875 | PINMUX_IPSR_GPSR(IP2SR1_11_8, HSCK1), |
876 | PINMUX_IPSR_GPSR(IP2SR1_11_8, SCK1), |
877 | PINMUX_IPSR_GPSR(IP2SR1_11_8, DU_DB2), |
878 | PINMUX_IPSR_GPSR(IP2SR1_11_8, A18), |
879 | |
880 | PINMUX_IPSR_GPSR(IP2SR1_15_12, MSIOF2_TXD), |
881 | PINMUX_IPSR_GPSR(IP2SR1_15_12, HCTS1_N), |
882 | PINMUX_IPSR_GPSR(IP2SR1_15_12, CTS1_N), |
883 | PINMUX_IPSR_GPSR(IP2SR1_15_12, DU_DB3), |
884 | PINMUX_IPSR_GPSR(IP2SR1_15_12, A19), |
885 | |
886 | PINMUX_IPSR_GPSR(IP2SR1_19_16, MSIOF2_SCK), |
887 | PINMUX_IPSR_GPSR(IP2SR1_19_16, HRTS1_N), |
888 | PINMUX_IPSR_GPSR(IP2SR1_19_16, RTS1_N), |
889 | PINMUX_IPSR_GPSR(IP2SR1_19_16, DU_DB4), |
890 | PINMUX_IPSR_GPSR(IP2SR1_19_16, A20), |
891 | |
892 | PINMUX_IPSR_GPSR(IP2SR1_23_20, MSIOF2_SYNC), |
893 | PINMUX_IPSR_GPSR(IP2SR1_23_20, HRX1), |
894 | PINMUX_IPSR_GPSR(IP2SR1_23_20, RX1_A), |
895 | PINMUX_IPSR_GPSR(IP2SR1_23_20, DU_DB5), |
896 | PINMUX_IPSR_GPSR(IP2SR1_23_20, A21), |
897 | |
898 | PINMUX_IPSR_GPSR(IP2SR1_27_24, MSIOF2_SS1), |
899 | PINMUX_IPSR_GPSR(IP2SR1_27_24, HTX1), |
900 | PINMUX_IPSR_GPSR(IP2SR1_27_24, TX1_A), |
901 | PINMUX_IPSR_GPSR(IP2SR1_27_24, DU_DB6), |
902 | PINMUX_IPSR_GPSR(IP2SR1_27_24, A22), |
903 | |
904 | PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF2_SS2), |
905 | PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK1_B), |
906 | PINMUX_IPSR_GPSR(IP2SR1_31_28, DU_DB7), |
907 | PINMUX_IPSR_GPSR(IP2SR1_31_28, A23), |
908 | |
909 | /* IP3SR1 */ |
910 | PINMUX_IPSR_GPSR(IP3SR1_3_0, IRQ0), |
911 | PINMUX_IPSR_GPSR(IP3SR1_3_0, DU_DOTCLKOUT), |
912 | PINMUX_IPSR_GPSR(IP3SR1_3_0, A24), |
913 | |
914 | PINMUX_IPSR_GPSR(IP3SR1_7_4, IRQ1), |
915 | PINMUX_IPSR_GPSR(IP3SR1_7_4, DU_HSYNC), |
916 | PINMUX_IPSR_GPSR(IP3SR1_7_4, A25), |
917 | |
918 | PINMUX_IPSR_GPSR(IP3SR1_11_8, IRQ2), |
919 | PINMUX_IPSR_GPSR(IP3SR1_11_8, DU_VSYNC), |
920 | PINMUX_IPSR_GPSR(IP3SR1_11_8, CS1_N_A26), |
921 | |
922 | PINMUX_IPSR_GPSR(IP3SR1_15_12, IRQ3), |
923 | PINMUX_IPSR_GPSR(IP3SR1_15_12, DU_ODDF_DISP_CDE), |
924 | PINMUX_IPSR_GPSR(IP3SR1_15_12, CS0_N), |
925 | |
926 | PINMUX_IPSR_GPSR(IP3SR1_19_16, GP1_28), |
927 | PINMUX_IPSR_GPSR(IP3SR1_19_16, D0), |
928 | |
929 | PINMUX_IPSR_GPSR(IP3SR1_23_20, GP1_29), |
930 | PINMUX_IPSR_GPSR(IP3SR1_23_20, D1), |
931 | |
932 | PINMUX_IPSR_GPSR(IP3SR1_27_24, GP1_30), |
933 | PINMUX_IPSR_GPSR(IP3SR1_27_24, D2), |
934 | |
935 | /* IP0SR2 */ |
936 | PINMUX_IPSR_GPSR(IP0SR2_3_0, IPC_CLKIN), |
937 | PINMUX_IPSR_GPSR(IP0SR2_3_0, IPC_CLKEN_IN), |
938 | PINMUX_IPSR_GPSR(IP0SR2_3_0, DU_DOTCLKIN), |
939 | |
940 | PINMUX_IPSR_GPSR(IP0SR2_7_4, IPC_CLKOUT), |
941 | PINMUX_IPSR_GPSR(IP0SR2_7_4, IPC_CLKEN_OUT), |
942 | |
943 | /* GP2_02 = SCL0 */ |
944 | PINMUX_IPSR_MSEL(IP0SR2_11_8, GP2_02, SEL_I2C0_0), |
945 | PINMUX_IPSR_MSEL(IP0SR2_11_8, D3, SEL_I2C0_0), |
946 | PINMUX_IPSR_PHYS(IP0SR2_11_8, SCL0, SEL_I2C0_3), |
947 | |
948 | /* GP2_03 = SDA0 */ |
949 | PINMUX_IPSR_MSEL(IP0SR2_15_12, GP2_03, SEL_I2C0_0), |
950 | PINMUX_IPSR_MSEL(IP0SR2_15_12, D4, SEL_I2C0_0), |
951 | PINMUX_IPSR_PHYS(IP0SR2_15_12, SDA0, SEL_I2C0_3), |
952 | |
953 | /* GP2_04 = SCL1 */ |
954 | PINMUX_IPSR_MSEL(IP0SR2_19_16, GP2_04, SEL_I2C1_0), |
955 | PINMUX_IPSR_MSEL(IP0SR2_19_16, MSIOF4_RXD, SEL_I2C1_0), |
956 | PINMUX_IPSR_MSEL(IP0SR2_19_16, D5, SEL_I2C1_0), |
957 | PINMUX_IPSR_PHYS(IP0SR2_19_16, SCL1, SEL_I2C1_3), |
958 | |
959 | /* GP2_05 = SDA1 */ |
960 | PINMUX_IPSR_MSEL(IP0SR2_23_20, GP2_05, SEL_I2C1_0), |
961 | PINMUX_IPSR_MSEL(IP0SR2_23_20, HSCK2, SEL_I2C1_0), |
962 | PINMUX_IPSR_MSEL(IP0SR2_23_20, MSIOF4_TXD, SEL_I2C1_0), |
963 | PINMUX_IPSR_MSEL(IP0SR2_23_20, SCK4, SEL_I2C1_0), |
964 | PINMUX_IPSR_MSEL(IP0SR2_23_20, D6, SEL_I2C1_0), |
965 | PINMUX_IPSR_PHYS(IP0SR2_23_20, SDA1, SEL_I2C1_3), |
966 | |
967 | /* GP2_06 = SCL2 */ |
968 | PINMUX_IPSR_MSEL(IP0SR2_27_24, GP2_06, SEL_I2C2_0), |
969 | PINMUX_IPSR_MSEL(IP0SR2_27_24, HCTS2_N, SEL_I2C2_0), |
970 | PINMUX_IPSR_MSEL(IP0SR2_27_24, MSIOF4_SCK, SEL_I2C2_0), |
971 | PINMUX_IPSR_MSEL(IP0SR2_27_24, CTS4_N, SEL_I2C2_0), |
972 | PINMUX_IPSR_MSEL(IP0SR2_27_24, D7, SEL_I2C2_0), |
973 | PINMUX_IPSR_PHYS(IP0SR2_27_24, SCL2, SEL_I2C2_3), |
974 | |
975 | /* GP2_07 = SDA2 */ |
976 | PINMUX_IPSR_MSEL(IP0SR2_31_28, GP2_07, SEL_I2C2_0), |
977 | PINMUX_IPSR_MSEL(IP0SR2_31_28, HRTS2_N, SEL_I2C2_0), |
978 | PINMUX_IPSR_MSEL(IP0SR2_31_28, MSIOF4_SYNC, SEL_I2C2_0), |
979 | PINMUX_IPSR_MSEL(IP0SR2_31_28, RTS4_N, SEL_I2C2_0), |
980 | PINMUX_IPSR_MSEL(IP0SR2_31_28, D8, SEL_I2C2_0), |
981 | PINMUX_IPSR_PHYS(IP0SR2_31_28, SDA2, SEL_I2C2_3), |
982 | |
983 | /* GP2_08 = SCL3 */ |
984 | PINMUX_IPSR_MSEL(IP1SR2_3_0, GP2_08, SEL_I2C3_0), |
985 | PINMUX_IPSR_MSEL(IP1SR2_3_0, HRX2, SEL_I2C3_0), |
986 | PINMUX_IPSR_MSEL(IP1SR2_3_0, MSIOF4_SS1, SEL_I2C3_0), |
987 | PINMUX_IPSR_MSEL(IP1SR2_3_0, RX4, SEL_I2C3_0), |
988 | PINMUX_IPSR_MSEL(IP1SR2_3_0, D9, SEL_I2C3_0), |
989 | PINMUX_IPSR_PHYS(IP1SR2_3_0, SCL3, SEL_I2C3_3), |
990 | |
991 | /* GP2_09 = SDA3 */ |
992 | PINMUX_IPSR_MSEL(IP1SR2_7_4, GP2_09, SEL_I2C3_0), |
993 | PINMUX_IPSR_MSEL(IP1SR2_7_4, HTX2, SEL_I2C3_0), |
994 | PINMUX_IPSR_MSEL(IP1SR2_7_4, MSIOF4_SS2, SEL_I2C3_0), |
995 | PINMUX_IPSR_MSEL(IP1SR2_7_4, TX4, SEL_I2C3_0), |
996 | PINMUX_IPSR_MSEL(IP1SR2_7_4, D10, SEL_I2C3_0), |
997 | PINMUX_IPSR_PHYS(IP1SR2_7_4, SDA3, SEL_I2C3_3), |
998 | |
999 | /* GP2_10 = SCL4 */ |
1000 | PINMUX_IPSR_MSEL(IP1SR2_11_8, GP2_10, SEL_I2C4_0), |
1001 | PINMUX_IPSR_MSEL(IP1SR2_11_8, TCLK2_B, SEL_I2C4_0), |
1002 | PINMUX_IPSR_MSEL(IP1SR2_11_8, MSIOF5_RXD, SEL_I2C4_0), |
1003 | PINMUX_IPSR_MSEL(IP1SR2_11_8, D11, SEL_I2C4_0), |
1004 | PINMUX_IPSR_PHYS(IP1SR2_11_8, SCL4, SEL_I2C4_3), |
1005 | |
1006 | /* GP2_11 = SDA4 */ |
1007 | PINMUX_IPSR_MSEL(IP1SR2_15_12, GP2_11, SEL_I2C4_0), |
1008 | PINMUX_IPSR_MSEL(IP1SR2_15_12, TCLK3, SEL_I2C4_0), |
1009 | PINMUX_IPSR_MSEL(IP1SR2_15_12, MSIOF5_TXD, SEL_I2C4_0), |
1010 | PINMUX_IPSR_MSEL(IP1SR2_15_12, D12, SEL_I2C4_0), |
1011 | PINMUX_IPSR_PHYS(IP1SR2_15_12, SDA4, SEL_I2C4_3), |
1012 | |
1013 | /* GP2_12 = SCL5 */ |
1014 | PINMUX_IPSR_MSEL(IP1SR2_19_16, GP2_12, SEL_I2C5_0), |
1015 | PINMUX_IPSR_MSEL(IP1SR2_19_16, TCLK4, SEL_I2C5_0), |
1016 | PINMUX_IPSR_MSEL(IP1SR2_19_16, MSIOF5_SCK, SEL_I2C5_0), |
1017 | PINMUX_IPSR_MSEL(IP1SR2_19_16, D13, SEL_I2C5_0), |
1018 | PINMUX_IPSR_PHYS(IP1SR2_19_16, SCL5, SEL_I2C5_3), |
1019 | |
1020 | /* GP2_13 = SDA5 */ |
1021 | PINMUX_IPSR_MSEL(IP1SR2_23_20, GP2_13, SEL_I2C5_0), |
1022 | PINMUX_IPSR_MSEL(IP1SR2_23_20, MSIOF5_SYNC, SEL_I2C5_0), |
1023 | PINMUX_IPSR_MSEL(IP1SR2_23_20, D14, SEL_I2C5_0), |
1024 | PINMUX_IPSR_PHYS(IP1SR2_23_20, SDA5, SEL_I2C5_3), |
1025 | |
1026 | /* GP2_14 = SCL6 */ |
1027 | PINMUX_IPSR_MSEL(IP1SR2_27_24, GP2_14, SEL_I2C6_0), |
1028 | PINMUX_IPSR_MSEL(IP1SR2_27_24, IRQ4, SEL_I2C6_0), |
1029 | PINMUX_IPSR_MSEL(IP1SR2_27_24, MSIOF5_SS1, SEL_I2C6_0), |
1030 | PINMUX_IPSR_MSEL(IP1SR2_27_24, D15, SEL_I2C6_0), |
1031 | PINMUX_IPSR_PHYS(IP1SR2_27_24, SCL6, SEL_I2C6_3), |
1032 | |
1033 | /* GP2_15 = SDA6 */ |
1034 | PINMUX_IPSR_MSEL(IP1SR2_31_28, GP2_15, SEL_I2C6_0), |
1035 | PINMUX_IPSR_MSEL(IP1SR2_31_28, IRQ5, SEL_I2C6_0), |
1036 | PINMUX_IPSR_MSEL(IP1SR2_31_28, MSIOF5_SS2, SEL_I2C6_0), |
1037 | PINMUX_IPSR_MSEL(IP1SR2_31_28, CPG_CPCKOUT, SEL_I2C6_0), |
1038 | PINMUX_IPSR_PHYS(IP1SR2_31_28, SDA6, SEL_I2C6_3), |
1039 | |
1040 | /* IP2SR2 */ |
1041 | PINMUX_IPSR_GPSR(IP2SR2_3_0, FXR_TXDA_A), |
1042 | PINMUX_IPSR_GPSR(IP2SR2_3_0, MSIOF3_SS1), |
1043 | |
1044 | PINMUX_IPSR_GPSR(IP2SR2_7_4, RXDA_EXTFXR_A), |
1045 | PINMUX_IPSR_GPSR(IP2SR2_7_4, MSIOF3_SS2), |
1046 | PINMUX_IPSR_GPSR(IP2SR2_7_4, BS_N), |
1047 | |
1048 | PINMUX_IPSR_GPSR(IP2SR2_11_8, FXR_TXDB), |
1049 | PINMUX_IPSR_GPSR(IP2SR2_11_8, MSIOF3_RXD), |
1050 | PINMUX_IPSR_GPSR(IP2SR2_11_8, RD_N), |
1051 | |
1052 | PINMUX_IPSR_GPSR(IP2SR2_15_12, RXDB_EXTFXR), |
1053 | PINMUX_IPSR_GPSR(IP2SR2_15_12, MSIOF3_TXD), |
1054 | PINMUX_IPSR_GPSR(IP2SR2_15_12, WE0_N), |
1055 | |
1056 | PINMUX_IPSR_GPSR(IP2SR2_19_16, CLK_EXTFXR), |
1057 | PINMUX_IPSR_GPSR(IP2SR2_19_16, MSIOF3_SCK), |
1058 | PINMUX_IPSR_GPSR(IP2SR2_19_16, WE1_N), |
1059 | |
1060 | PINMUX_IPSR_GPSR(IP2SR2_23_20, TPU0TO0), |
1061 | PINMUX_IPSR_GPSR(IP2SR2_23_20, MSIOF3_SYNC), |
1062 | PINMUX_IPSR_GPSR(IP2SR2_23_20, RD_WR_N), |
1063 | |
1064 | PINMUX_IPSR_GPSR(IP2SR2_27_24, TPU0TO1), |
1065 | PINMUX_IPSR_GPSR(IP2SR2_27_24, CLKOUT), |
1066 | |
1067 | PINMUX_IPSR_GPSR(IP2SR2_31_28, TCLK1_A), |
1068 | PINMUX_IPSR_GPSR(IP2SR2_31_28, EX_WAIT0), |
1069 | |
1070 | /* IP0SR3 */ |
1071 | PINMUX_IPSR_GPSR(IP0SR3_7_4, CANFD0_TX), |
1072 | PINMUX_IPSR_GPSR(IP0SR3_7_4, FXR_TXDA_B), |
1073 | PINMUX_IPSR_GPSR(IP0SR3_7_4, TX1_B), |
1074 | |
1075 | PINMUX_IPSR_GPSR(IP0SR3_11_8, CANFD0_RX), |
1076 | PINMUX_IPSR_GPSR(IP0SR3_11_8, RXDA_EXTFXR_B), |
1077 | PINMUX_IPSR_GPSR(IP0SR3_11_8, RX1_B), |
1078 | |
1079 | PINMUX_IPSR_GPSR(IP0SR3_23_20, CANFD2_TX), |
1080 | PINMUX_IPSR_GPSR(IP0SR3_23_20, TPU0TO2), |
1081 | PINMUX_IPSR_GPSR(IP0SR3_23_20, PWM0), |
1082 | |
1083 | PINMUX_IPSR_GPSR(IP0SR3_27_24, CANFD2_RX), |
1084 | PINMUX_IPSR_GPSR(IP0SR3_27_24, TPU0TO3), |
1085 | PINMUX_IPSR_GPSR(IP0SR3_27_24, PWM1), |
1086 | |
1087 | PINMUX_IPSR_GPSR(IP0SR3_31_28, CANFD3_TX), |
1088 | PINMUX_IPSR_GPSR(IP0SR3_31_28, PWM2), |
1089 | |
1090 | /* IP1SR3 */ |
1091 | PINMUX_IPSR_GPSR(IP1SR3_3_0, CANFD3_RX), |
1092 | PINMUX_IPSR_GPSR(IP1SR3_3_0, PWM3), |
1093 | |
1094 | PINMUX_IPSR_GPSR(IP1SR3_7_4, CANFD4_TX), |
1095 | PINMUX_IPSR_GPSR(IP1SR3_7_4, PWM4), |
1096 | PINMUX_IPSR_GPSR(IP1SR3_7_4, FXR_CLKOUT1), |
1097 | |
1098 | PINMUX_IPSR_GPSR(IP1SR3_11_8, CANFD4_RX), |
1099 | PINMUX_IPSR_GPSR(IP1SR3_11_8, FXR_CLKOUT2), |
1100 | |
1101 | PINMUX_IPSR_GPSR(IP1SR3_15_12, CANFD5_TX), |
1102 | PINMUX_IPSR_GPSR(IP1SR3_15_12, FXR_TXENA_N), |
1103 | |
1104 | PINMUX_IPSR_GPSR(IP1SR3_19_16, CANFD5_RX), |
1105 | PINMUX_IPSR_GPSR(IP1SR3_19_16, FXR_TXENB_N), |
1106 | |
1107 | PINMUX_IPSR_GPSR(IP1SR3_23_20, CANFD6_TX), |
1108 | PINMUX_IPSR_GPSR(IP1SR3_23_20, STPWT_EXTFXR), |
1109 | |
1110 | /* IP0SR4 */ |
1111 | PINMUX_IPSR_GPSR(IP0SR4_3_0, AVB0_RX_CTL), |
1112 | PINMUX_IPSR_GPSR(IP0SR4_3_0, AVB0_MII_RX_DV), |
1113 | |
1114 | PINMUX_IPSR_GPSR(IP0SR4_7_4, AVB0_RXC), |
1115 | PINMUX_IPSR_GPSR(IP0SR4_7_4, AVB0_MII_RXC), |
1116 | |
1117 | PINMUX_IPSR_GPSR(IP0SR4_11_8, AVB0_RD0), |
1118 | PINMUX_IPSR_GPSR(IP0SR4_11_8, AVB0_MII_RD0), |
1119 | |
1120 | PINMUX_IPSR_GPSR(IP0SR4_15_12, AVB0_RD1), |
1121 | PINMUX_IPSR_GPSR(IP0SR4_15_12, AVB0_MII_RD1), |
1122 | |
1123 | PINMUX_IPSR_GPSR(IP0SR4_19_16, AVB0_RD2), |
1124 | PINMUX_IPSR_GPSR(IP0SR4_19_16, AVB0_MII_RD2), |
1125 | |
1126 | PINMUX_IPSR_GPSR(IP0SR4_23_20, AVB0_RD3), |
1127 | PINMUX_IPSR_GPSR(IP0SR4_23_20, AVB0_MII_RD3), |
1128 | |
1129 | PINMUX_IPSR_GPSR(IP0SR4_27_24, AVB0_TX_CTL), |
1130 | PINMUX_IPSR_GPSR(IP0SR4_27_24, AVB0_MII_TX_EN), |
1131 | |
1132 | PINMUX_IPSR_GPSR(IP0SR4_31_28, AVB0_TXC), |
1133 | PINMUX_IPSR_GPSR(IP0SR4_31_28, AVB0_MII_TXC), |
1134 | |
1135 | /* IP1SR4 */ |
1136 | PINMUX_IPSR_GPSR(IP1SR4_3_0, AVB0_TD0), |
1137 | PINMUX_IPSR_GPSR(IP1SR4_3_0, AVB0_MII_TD0), |
1138 | |
1139 | PINMUX_IPSR_GPSR(IP1SR4_7_4, AVB0_TD1), |
1140 | PINMUX_IPSR_GPSR(IP1SR4_7_4, AVB0_MII_TD1), |
1141 | |
1142 | PINMUX_IPSR_GPSR(IP1SR4_11_8, AVB0_TD2), |
1143 | PINMUX_IPSR_GPSR(IP1SR4_11_8, AVB0_MII_TD2), |
1144 | |
1145 | PINMUX_IPSR_GPSR(IP1SR4_15_12, AVB0_TD3), |
1146 | PINMUX_IPSR_GPSR(IP1SR4_15_12, AVB0_MII_TD3), |
1147 | |
1148 | PINMUX_IPSR_GPSR(IP1SR4_19_16, AVB0_TXCREFCLK), |
1149 | |
1150 | PINMUX_IPSR_GPSR(IP1SR4_23_20, AVB0_MDIO), |
1151 | |
1152 | PINMUX_IPSR_GPSR(IP1SR4_27_24, AVB0_MDC), |
1153 | |
1154 | PINMUX_IPSR_GPSR(IP1SR4_31_28, AVB0_MAGIC), |
1155 | |
1156 | /* IP2SR4 */ |
1157 | PINMUX_IPSR_GPSR(IP2SR4_7_4, AVB0_LINK), |
1158 | PINMUX_IPSR_GPSR(IP2SR4_7_4, AVB0_MII_TX_ER), |
1159 | |
1160 | PINMUX_IPSR_GPSR(IP2SR4_11_8, AVB0_AVTP_MATCH), |
1161 | PINMUX_IPSR_GPSR(IP2SR4_11_8, AVB0_MII_RX_ER), |
1162 | PINMUX_IPSR_GPSR(IP2SR4_11_8, CC5_OSCOUT), |
1163 | |
1164 | PINMUX_IPSR_GPSR(IP2SR4_15_12, AVB0_AVTP_CAPTURE), |
1165 | PINMUX_IPSR_GPSR(IP2SR4_15_12, AVB0_MII_CRS), |
1166 | |
1167 | PINMUX_IPSR_GPSR(IP2SR4_19_16, AVB0_AVTP_PPS), |
1168 | PINMUX_IPSR_GPSR(IP2SR4_19_16, AVB0_MII_COL), |
1169 | |
1170 | /* IP0SR5 */ |
1171 | PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB1_RX_CTL), |
1172 | PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB1_MII_RX_DV), |
1173 | |
1174 | PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB1_RXC), |
1175 | PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB1_MII_RXC), |
1176 | |
1177 | PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB1_RD0), |
1178 | PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB1_MII_RD0), |
1179 | |
1180 | PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB1_RD1), |
1181 | PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB1_MII_RD1), |
1182 | |
1183 | PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB1_RD2), |
1184 | PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB1_MII_RD2), |
1185 | |
1186 | PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB1_RD3), |
1187 | PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB1_MII_RD3), |
1188 | |
1189 | PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB1_TX_CTL), |
1190 | PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB1_MII_TX_EN), |
1191 | |
1192 | PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB1_TXC), |
1193 | PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB1_MII_TXC), |
1194 | |
1195 | /* IP1SR5 */ |
1196 | PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB1_TD0), |
1197 | PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB1_MII_TD0), |
1198 | |
1199 | PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB1_TD1), |
1200 | PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB1_MII_TD1), |
1201 | |
1202 | PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB1_TD2), |
1203 | PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB1_MII_TD2), |
1204 | |
1205 | PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB1_TD3), |
1206 | PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB1_MII_TD3), |
1207 | |
1208 | PINMUX_IPSR_GPSR(IP1SR5_19_16, AVB1_TXCREFCLK), |
1209 | |
1210 | PINMUX_IPSR_GPSR(IP1SR5_23_20, AVB1_MDIO), |
1211 | |
1212 | PINMUX_IPSR_GPSR(IP1SR5_27_24, AVB1_MDC), |
1213 | |
1214 | PINMUX_IPSR_GPSR(IP1SR5_31_28, AVB1_MAGIC), |
1215 | |
1216 | /* IP2SR5 */ |
1217 | PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB1_LINK), |
1218 | PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB1_MII_TX_ER), |
1219 | |
1220 | PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB1_AVTP_MATCH), |
1221 | PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB1_MII_RX_ER), |
1222 | |
1223 | PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB1_AVTP_CAPTURE), |
1224 | PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB1_MII_CRS), |
1225 | |
1226 | PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB1_AVTP_PPS), |
1227 | PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB1_MII_COL), |
1228 | }; |
1229 | |
1230 | /* |
1231 | * Pins not associated with a GPIO port. |
1232 | */ |
1233 | enum { |
1234 | GP_ASSIGN_LAST(), |
1235 | NOGP_ALL(), |
1236 | }; |
1237 | |
1238 | static const struct sh_pfc_pin pinmux_pins[] = { |
1239 | PINMUX_GPIO_GP_ALL(), |
1240 | }; |
1241 | |
1242 | /* - AVB0 ------------------------------------------------ */ |
1243 | static const unsigned int avb0_link_pins[] = { |
1244 | /* AVB0_LINK */ |
1245 | RCAR_GP_PIN(4, 17), |
1246 | }; |
1247 | static const unsigned int avb0_link_mux[] = { |
1248 | AVB0_LINK_MARK, |
1249 | }; |
1250 | static const unsigned int avb0_magic_pins[] = { |
1251 | /* AVB0_MAGIC */ |
1252 | RCAR_GP_PIN(4, 15), |
1253 | }; |
1254 | static const unsigned int avb0_magic_mux[] = { |
1255 | AVB0_MAGIC_MARK, |
1256 | }; |
1257 | static const unsigned int avb0_phy_int_pins[] = { |
1258 | /* AVB0_PHY_INT */ |
1259 | RCAR_GP_PIN(4, 16), |
1260 | }; |
1261 | static const unsigned int avb0_phy_int_mux[] = { |
1262 | AVB0_PHY_INT_MARK, |
1263 | }; |
1264 | static const unsigned int avb0_mdio_pins[] = { |
1265 | /* AVB0_MDC, AVB0_MDIO */ |
1266 | RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), |
1267 | }; |
1268 | static const unsigned int avb0_mdio_mux[] = { |
1269 | AVB0_MDC_MARK, AVB0_MDIO_MARK, |
1270 | }; |
1271 | static const unsigned int avb0_rgmii_pins[] = { |
1272 | /* |
1273 | * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3, |
1274 | * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3, |
1275 | */ |
1276 | RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), |
1277 | RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), |
1278 | RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), |
1279 | RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), |
1280 | RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), |
1281 | RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), |
1282 | }; |
1283 | static const unsigned int avb0_rgmii_mux[] = { |
1284 | AVB0_TX_CTL_MARK, AVB0_TXC_MARK, |
1285 | AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK, |
1286 | AVB0_RX_CTL_MARK, AVB0_RXC_MARK, |
1287 | AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK, |
1288 | }; |
1289 | static const unsigned int avb0_txcrefclk_pins[] = { |
1290 | /* AVB0_TXCREFCLK */ |
1291 | RCAR_GP_PIN(4, 12), |
1292 | }; |
1293 | static const unsigned int avb0_txcrefclk_mux[] = { |
1294 | AVB0_TXCREFCLK_MARK, |
1295 | }; |
1296 | static const unsigned int avb0_avtp_pps_pins[] = { |
1297 | /* AVB0_AVTP_PPS */ |
1298 | RCAR_GP_PIN(4, 20), |
1299 | }; |
1300 | static const unsigned int avb0_avtp_pps_mux[] = { |
1301 | AVB0_AVTP_PPS_MARK, |
1302 | }; |
1303 | static const unsigned int avb0_avtp_capture_pins[] = { |
1304 | /* AVB0_AVTP_CAPTURE */ |
1305 | RCAR_GP_PIN(4, 19), |
1306 | }; |
1307 | static const unsigned int avb0_avtp_capture_mux[] = { |
1308 | AVB0_AVTP_CAPTURE_MARK, |
1309 | }; |
1310 | static const unsigned int avb0_avtp_match_pins[] = { |
1311 | /* AVB0_AVTP_MATCH */ |
1312 | RCAR_GP_PIN(4, 18), |
1313 | }; |
1314 | static const unsigned int avb0_avtp_match_mux[] = { |
1315 | AVB0_AVTP_MATCH_MARK, |
1316 | }; |
1317 | |
1318 | /* - AVB1 ------------------------------------------------ */ |
1319 | static const unsigned int avb1_link_pins[] = { |
1320 | /* AVB1_LINK */ |
1321 | RCAR_GP_PIN(5, 17), |
1322 | }; |
1323 | static const unsigned int avb1_link_mux[] = { |
1324 | AVB1_LINK_MARK, |
1325 | }; |
1326 | static const unsigned int avb1_magic_pins[] = { |
1327 | /* AVB1_MAGIC */ |
1328 | RCAR_GP_PIN(5, 15), |
1329 | }; |
1330 | static const unsigned int avb1_magic_mux[] = { |
1331 | AVB1_MAGIC_MARK, |
1332 | }; |
1333 | static const unsigned int avb1_phy_int_pins[] = { |
1334 | /* AVB1_PHY_INT */ |
1335 | RCAR_GP_PIN(5, 16), |
1336 | }; |
1337 | static const unsigned int avb1_phy_int_mux[] = { |
1338 | AVB1_PHY_INT_MARK, |
1339 | }; |
1340 | static const unsigned int avb1_mdio_pins[] = { |
1341 | /* AVB1_MDC, AVB1_MDIO */ |
1342 | RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 13), |
1343 | }; |
1344 | static const unsigned int avb1_mdio_mux[] = { |
1345 | AVB1_MDC_MARK, AVB1_MDIO_MARK, |
1346 | }; |
1347 | static const unsigned int avb1_rgmii_pins[] = { |
1348 | /* |
1349 | * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3, |
1350 | * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3, |
1351 | */ |
1352 | RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), |
1353 | RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), |
1354 | RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), |
1355 | RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), |
1356 | RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3), |
1357 | RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), |
1358 | }; |
1359 | static const unsigned int avb1_rgmii_mux[] = { |
1360 | AVB1_TX_CTL_MARK, AVB1_TXC_MARK, |
1361 | AVB1_TD0_MARK, AVB1_TD1_MARK, AVB1_TD2_MARK, AVB1_TD3_MARK, |
1362 | AVB1_RX_CTL_MARK, AVB1_RXC_MARK, |
1363 | AVB1_RD0_MARK, AVB1_RD1_MARK, AVB1_RD2_MARK, AVB1_RD3_MARK, |
1364 | }; |
1365 | static const unsigned int avb1_txcrefclk_pins[] = { |
1366 | /* AVB1_TXCREFCLK */ |
1367 | RCAR_GP_PIN(5, 12), |
1368 | }; |
1369 | static const unsigned int avb1_txcrefclk_mux[] = { |
1370 | AVB1_TXCREFCLK_MARK, |
1371 | }; |
1372 | static const unsigned int avb1_avtp_pps_pins[] = { |
1373 | /* AVB1_AVTP_PPS */ |
1374 | RCAR_GP_PIN(5, 20), |
1375 | }; |
1376 | static const unsigned int avb1_avtp_pps_mux[] = { |
1377 | AVB1_AVTP_PPS_MARK, |
1378 | }; |
1379 | static const unsigned int avb1_avtp_capture_pins[] = { |
1380 | /* AVB1_AVTP_CAPTURE */ |
1381 | RCAR_GP_PIN(5, 19), |
1382 | }; |
1383 | static const unsigned int avb1_avtp_capture_mux[] = { |
1384 | AVB1_AVTP_CAPTURE_MARK, |
1385 | }; |
1386 | static const unsigned int avb1_avtp_match_pins[] = { |
1387 | /* AVB1_AVTP_MATCH */ |
1388 | RCAR_GP_PIN(5, 18), |
1389 | }; |
1390 | static const unsigned int avb1_avtp_match_mux[] = { |
1391 | AVB1_AVTP_MATCH_MARK, |
1392 | }; |
1393 | |
1394 | /* - AVB2 ------------------------------------------------ */ |
1395 | static const unsigned int avb2_link_pins[] = { |
1396 | /* AVB2_LINK */ |
1397 | RCAR_GP_PIN(6, 17), |
1398 | }; |
1399 | static const unsigned int avb2_link_mux[] = { |
1400 | AVB2_LINK_MARK, |
1401 | }; |
1402 | static const unsigned int avb2_magic_pins[] = { |
1403 | /* AVB2_MAGIC */ |
1404 | RCAR_GP_PIN(6, 15), |
1405 | }; |
1406 | static const unsigned int avb2_magic_mux[] = { |
1407 | AVB2_MAGIC_MARK, |
1408 | }; |
1409 | static const unsigned int avb2_phy_int_pins[] = { |
1410 | /* AVB2_PHY_INT */ |
1411 | RCAR_GP_PIN(6, 16), |
1412 | }; |
1413 | static const unsigned int avb2_phy_int_mux[] = { |
1414 | AVB2_PHY_INT_MARK, |
1415 | }; |
1416 | static const unsigned int avb2_mdio_pins[] = { |
1417 | /* AVB2_MDC, AVB2_MDIO */ |
1418 | RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 13), |
1419 | }; |
1420 | static const unsigned int avb2_mdio_mux[] = { |
1421 | AVB2_MDC_MARK, AVB2_MDIO_MARK, |
1422 | }; |
1423 | static const unsigned int avb2_rgmii_pins[] = { |
1424 | /* |
1425 | * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3, |
1426 | * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3, |
1427 | */ |
1428 | RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7), |
1429 | RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), |
1430 | RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), |
1431 | RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), |
1432 | RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), |
1433 | RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), |
1434 | }; |
1435 | static const unsigned int avb2_rgmii_mux[] = { |
1436 | AVB2_TX_CTL_MARK, AVB2_TXC_MARK, |
1437 | AVB2_TD0_MARK, AVB2_TD1_MARK, AVB2_TD2_MARK, AVB2_TD3_MARK, |
1438 | AVB2_RX_CTL_MARK, AVB2_RXC_MARK, |
1439 | AVB2_RD0_MARK, AVB2_RD1_MARK, AVB2_RD2_MARK, AVB2_RD3_MARK, |
1440 | }; |
1441 | static const unsigned int avb2_txcrefclk_pins[] = { |
1442 | /* AVB2_TXCREFCLK */ |
1443 | RCAR_GP_PIN(6, 12), |
1444 | }; |
1445 | static const unsigned int avb2_txcrefclk_mux[] = { |
1446 | AVB2_TXCREFCLK_MARK, |
1447 | }; |
1448 | static const unsigned int avb2_avtp_pps_pins[] = { |
1449 | /* AVB2_AVTP_PPS */ |
1450 | RCAR_GP_PIN(6, 20), |
1451 | }; |
1452 | static const unsigned int avb2_avtp_pps_mux[] = { |
1453 | AVB2_AVTP_PPS_MARK, |
1454 | }; |
1455 | static const unsigned int avb2_avtp_capture_pins[] = { |
1456 | /* AVB2_AVTP_CAPTURE */ |
1457 | RCAR_GP_PIN(6, 19), |
1458 | }; |
1459 | static const unsigned int avb2_avtp_capture_mux[] = { |
1460 | AVB2_AVTP_CAPTURE_MARK, |
1461 | }; |
1462 | static const unsigned int avb2_avtp_match_pins[] = { |
1463 | /* AVB2_AVTP_MATCH */ |
1464 | RCAR_GP_PIN(6, 18), |
1465 | }; |
1466 | static const unsigned int avb2_avtp_match_mux[] = { |
1467 | AVB2_AVTP_MATCH_MARK, |
1468 | }; |
1469 | |
1470 | /* - AVB3 ------------------------------------------------ */ |
1471 | static const unsigned int avb3_link_pins[] = { |
1472 | /* AVB3_LINK */ |
1473 | RCAR_GP_PIN(7, 17), |
1474 | }; |
1475 | static const unsigned int avb3_link_mux[] = { |
1476 | AVB3_LINK_MARK, |
1477 | }; |
1478 | static const unsigned int avb3_magic_pins[] = { |
1479 | /* AVB3_MAGIC */ |
1480 | RCAR_GP_PIN(7, 15), |
1481 | }; |
1482 | static const unsigned int avb3_magic_mux[] = { |
1483 | AVB3_MAGIC_MARK, |
1484 | }; |
1485 | static const unsigned int avb3_phy_int_pins[] = { |
1486 | /* AVB3_PHY_INT */ |
1487 | RCAR_GP_PIN(7, 16), |
1488 | }; |
1489 | static const unsigned int avb3_phy_int_mux[] = { |
1490 | AVB3_PHY_INT_MARK, |
1491 | }; |
1492 | static const unsigned int avb3_mdio_pins[] = { |
1493 | /* AVB3_MDC, AVB3_MDIO */ |
1494 | RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 13), |
1495 | }; |
1496 | static const unsigned int avb3_mdio_mux[] = { |
1497 | AVB3_MDC_MARK, AVB3_MDIO_MARK, |
1498 | }; |
1499 | static const unsigned int avb3_rgmii_pins[] = { |
1500 | /* |
1501 | * AVB3_TX_CTL, AVB3_TXC, AVB3_TD0, AVB3_TD1, AVB3_TD2, AVB3_TD3, |
1502 | * AVB3_RX_CTL, AVB3_RXC, AVB3_RD0, AVB3_RD1, AVB3_RD2, AVB3_RD3, |
1503 | */ |
1504 | RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7), |
1505 | RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), |
1506 | RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11), |
1507 | RCAR_GP_PIN(7, 0), RCAR_GP_PIN(7, 1), |
1508 | RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3), |
1509 | RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5), |
1510 | }; |
1511 | static const unsigned int avb3_rgmii_mux[] = { |
1512 | AVB3_TX_CTL_MARK, AVB3_TXC_MARK, |
1513 | AVB3_TD0_MARK, AVB3_TD1_MARK, AVB3_TD2_MARK, AVB3_TD3_MARK, |
1514 | AVB3_RX_CTL_MARK, AVB3_RXC_MARK, |
1515 | AVB3_RD0_MARK, AVB3_RD1_MARK, AVB3_RD2_MARK, AVB3_RD3_MARK, |
1516 | }; |
1517 | static const unsigned int avb3_txcrefclk_pins[] = { |
1518 | /* AVB3_TXCREFCLK */ |
1519 | RCAR_GP_PIN(7, 12), |
1520 | }; |
1521 | static const unsigned int avb3_txcrefclk_mux[] = { |
1522 | AVB3_TXCREFCLK_MARK, |
1523 | }; |
1524 | static const unsigned int avb3_avtp_pps_pins[] = { |
1525 | /* AVB3_AVTP_PPS */ |
1526 | RCAR_GP_PIN(7, 20), |
1527 | }; |
1528 | static const unsigned int avb3_avtp_pps_mux[] = { |
1529 | AVB3_AVTP_PPS_MARK, |
1530 | }; |
1531 | static const unsigned int avb3_avtp_capture_pins[] = { |
1532 | /* AVB3_AVTP_CAPTURE */ |
1533 | RCAR_GP_PIN(7, 19), |
1534 | }; |
1535 | static const unsigned int avb3_avtp_capture_mux[] = { |
1536 | AVB3_AVTP_CAPTURE_MARK, |
1537 | }; |
1538 | static const unsigned int avb3_avtp_match_pins[] = { |
1539 | /* AVB3_AVTP_MATCH */ |
1540 | RCAR_GP_PIN(7, 18), |
1541 | }; |
1542 | static const unsigned int avb3_avtp_match_mux[] = { |
1543 | AVB3_AVTP_MATCH_MARK, |
1544 | }; |
1545 | |
1546 | /* - AVB4 ------------------------------------------------ */ |
1547 | static const unsigned int avb4_link_pins[] = { |
1548 | /* AVB4_LINK */ |
1549 | RCAR_GP_PIN(8, 17), |
1550 | }; |
1551 | static const unsigned int avb4_link_mux[] = { |
1552 | AVB4_LINK_MARK, |
1553 | }; |
1554 | static const unsigned int avb4_magic_pins[] = { |
1555 | /* AVB4_MAGIC */ |
1556 | RCAR_GP_PIN(8, 15), |
1557 | }; |
1558 | static const unsigned int avb4_magic_mux[] = { |
1559 | AVB4_MAGIC_MARK, |
1560 | }; |
1561 | static const unsigned int avb4_phy_int_pins[] = { |
1562 | /* AVB4_PHY_INT */ |
1563 | RCAR_GP_PIN(8, 16), |
1564 | }; |
1565 | static const unsigned int avb4_phy_int_mux[] = { |
1566 | AVB4_PHY_INT_MARK, |
1567 | }; |
1568 | static const unsigned int avb4_mdio_pins[] = { |
1569 | /* AVB4_MDC, AVB4_MDIO */ |
1570 | RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 13), |
1571 | }; |
1572 | static const unsigned int avb4_mdio_mux[] = { |
1573 | AVB4_MDC_MARK, AVB4_MDIO_MARK, |
1574 | }; |
1575 | static const unsigned int avb4_rgmii_pins[] = { |
1576 | /* |
1577 | * AVB4_TX_CTL, AVB4_TXC, AVB4_TD0, AVB4_TD1, AVB4_TD2, AVB4_TD3, |
1578 | * AVB4_RX_CTL, AVB4_RXC, AVB4_RD0, AVB4_RD1, AVB4_RD2, AVB4_RD3, |
1579 | */ |
1580 | RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7), |
1581 | RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9), |
1582 | RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11), |
1583 | RCAR_GP_PIN(8, 0), RCAR_GP_PIN(8, 1), |
1584 | RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3), |
1585 | RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5), |
1586 | }; |
1587 | static const unsigned int avb4_rgmii_mux[] = { |
1588 | AVB4_TX_CTL_MARK, AVB4_TXC_MARK, |
1589 | AVB4_TD0_MARK, AVB4_TD1_MARK, AVB4_TD2_MARK, AVB4_TD3_MARK, |
1590 | AVB4_RX_CTL_MARK, AVB4_RXC_MARK, |
1591 | AVB4_RD0_MARK, AVB4_RD1_MARK, AVB4_RD2_MARK, AVB4_RD3_MARK, |
1592 | }; |
1593 | static const unsigned int avb4_txcrefclk_pins[] = { |
1594 | /* AVB4_TXCREFCLK */ |
1595 | RCAR_GP_PIN(8, 12), |
1596 | }; |
1597 | static const unsigned int avb4_txcrefclk_mux[] = { |
1598 | AVB4_TXCREFCLK_MARK, |
1599 | }; |
1600 | static const unsigned int avb4_avtp_pps_pins[] = { |
1601 | /* AVB4_AVTP_PPS */ |
1602 | RCAR_GP_PIN(8, 20), |
1603 | }; |
1604 | static const unsigned int avb4_avtp_pps_mux[] = { |
1605 | AVB4_AVTP_PPS_MARK, |
1606 | }; |
1607 | static const unsigned int avb4_avtp_capture_pins[] = { |
1608 | /* AVB4_AVTP_CAPTURE */ |
1609 | RCAR_GP_PIN(8, 19), |
1610 | }; |
1611 | static const unsigned int avb4_avtp_capture_mux[] = { |
1612 | AVB4_AVTP_CAPTURE_MARK, |
1613 | }; |
1614 | static const unsigned int avb4_avtp_match_pins[] = { |
1615 | /* AVB4_AVTP_MATCH */ |
1616 | RCAR_GP_PIN(8, 18), |
1617 | }; |
1618 | static const unsigned int avb4_avtp_match_mux[] = { |
1619 | AVB4_AVTP_MATCH_MARK, |
1620 | }; |
1621 | |
1622 | /* - AVB5 ------------------------------------------------ */ |
1623 | static const unsigned int avb5_link_pins[] = { |
1624 | /* AVB5_LINK */ |
1625 | RCAR_GP_PIN(9, 17), |
1626 | }; |
1627 | static const unsigned int avb5_link_mux[] = { |
1628 | AVB5_LINK_MARK, |
1629 | }; |
1630 | static const unsigned int avb5_magic_pins[] = { |
1631 | /* AVB5_MAGIC */ |
1632 | RCAR_GP_PIN(9, 15), |
1633 | }; |
1634 | static const unsigned int avb5_magic_mux[] = { |
1635 | AVB5_MAGIC_MARK, |
1636 | }; |
1637 | static const unsigned int avb5_phy_int_pins[] = { |
1638 | /* AVB5_PHY_INT */ |
1639 | RCAR_GP_PIN(9, 16), |
1640 | }; |
1641 | static const unsigned int avb5_phy_int_mux[] = { |
1642 | AVB5_PHY_INT_MARK, |
1643 | }; |
1644 | static const unsigned int avb5_mdio_pins[] = { |
1645 | /* AVB5_MDC, AVB5_MDIO */ |
1646 | RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 13), |
1647 | }; |
1648 | static const unsigned int avb5_mdio_mux[] = { |
1649 | AVB5_MDC_MARK, AVB5_MDIO_MARK, |
1650 | }; |
1651 | static const unsigned int avb5_rgmii_pins[] = { |
1652 | /* |
1653 | * AVB5_TX_CTL, AVB5_TXC, AVB5_TD0, AVB5_TD1, AVB5_TD2, AVB5_TD3, |
1654 | * AVB5_RX_CTL, AVB5_RXC, AVB5_RD0, AVB5_RD1, AVB5_RD2, AVB5_RD3, |
1655 | */ |
1656 | RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7), |
1657 | RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9), |
1658 | RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11), |
1659 | RCAR_GP_PIN(9, 0), RCAR_GP_PIN(9, 1), |
1660 | RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3), |
1661 | RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5), |
1662 | }; |
1663 | static const unsigned int avb5_rgmii_mux[] = { |
1664 | AVB5_TX_CTL_MARK, AVB5_TXC_MARK, |
1665 | AVB5_TD0_MARK, AVB5_TD1_MARK, AVB5_TD2_MARK, AVB5_TD3_MARK, |
1666 | AVB5_RX_CTL_MARK, AVB5_RXC_MARK, |
1667 | AVB5_RD0_MARK, AVB5_RD1_MARK, AVB5_RD2_MARK, AVB5_RD3_MARK, |
1668 | }; |
1669 | static const unsigned int avb5_txcrefclk_pins[] = { |
1670 | /* AVB5_TXCREFCLK */ |
1671 | RCAR_GP_PIN(9, 12), |
1672 | }; |
1673 | static const unsigned int avb5_txcrefclk_mux[] = { |
1674 | AVB5_TXCREFCLK_MARK, |
1675 | }; |
1676 | static const unsigned int avb5_avtp_pps_pins[] = { |
1677 | /* AVB5_AVTP_PPS */ |
1678 | RCAR_GP_PIN(9, 20), |
1679 | }; |
1680 | static const unsigned int avb5_avtp_pps_mux[] = { |
1681 | AVB5_AVTP_PPS_MARK, |
1682 | }; |
1683 | static const unsigned int avb5_avtp_capture_pins[] = { |
1684 | /* AVB5_AVTP_CAPTURE */ |
1685 | RCAR_GP_PIN(9, 19), |
1686 | }; |
1687 | static const unsigned int avb5_avtp_capture_mux[] = { |
1688 | AVB5_AVTP_CAPTURE_MARK, |
1689 | }; |
1690 | static const unsigned int avb5_avtp_match_pins[] = { |
1691 | /* AVB5_AVTP_MATCH */ |
1692 | RCAR_GP_PIN(9, 18), |
1693 | }; |
1694 | static const unsigned int avb5_avtp_match_mux[] = { |
1695 | AVB5_AVTP_MATCH_MARK, |
1696 | }; |
1697 | |
1698 | /* - CANFD0 ----------------------------------------------------------------- */ |
1699 | static const unsigned int canfd0_data_pins[] = { |
1700 | /* CANFD0_TX, CANFD0_RX */ |
1701 | RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), |
1702 | }; |
1703 | static const unsigned int canfd0_data_mux[] = { |
1704 | CANFD0_TX_MARK, CANFD0_RX_MARK, |
1705 | }; |
1706 | |
1707 | /* - CANFD1 ----------------------------------------------------------------- */ |
1708 | static const unsigned int canfd1_data_pins[] = { |
1709 | /* CANFD1_TX, CANFD1_RX */ |
1710 | RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), |
1711 | }; |
1712 | static const unsigned int canfd1_data_mux[] = { |
1713 | CANFD1_TX_MARK, CANFD1_RX_MARK, |
1714 | }; |
1715 | |
1716 | /* - CANFD2 ----------------------------------------------------------------- */ |
1717 | static const unsigned int canfd2_data_pins[] = { |
1718 | /* CANFD2_TX, CANFD2_RX */ |
1719 | RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), |
1720 | }; |
1721 | static const unsigned int canfd2_data_mux[] = { |
1722 | CANFD2_TX_MARK, CANFD2_RX_MARK, |
1723 | }; |
1724 | |
1725 | /* - CANFD3 ----------------------------------------------------------------- */ |
1726 | static const unsigned int canfd3_data_pins[] = { |
1727 | /* CANFD3_TX, CANFD3_RX */ |
1728 | RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), |
1729 | }; |
1730 | static const unsigned int canfd3_data_mux[] = { |
1731 | CANFD3_TX_MARK, CANFD3_RX_MARK, |
1732 | }; |
1733 | |
1734 | /* - CANFD4 ----------------------------------------------------------------- */ |
1735 | static const unsigned int canfd4_data_pins[] = { |
1736 | /* CANFD4_TX, CANFD4_RX */ |
1737 | RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), |
1738 | }; |
1739 | static const unsigned int canfd4_data_mux[] = { |
1740 | CANFD4_TX_MARK, CANFD4_RX_MARK, |
1741 | }; |
1742 | |
1743 | /* - CANFD5 ----------------------------------------------------------------- */ |
1744 | static const unsigned int canfd5_data_pins[] = { |
1745 | /* CANFD5_TX, CANFD5_RX */ |
1746 | RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), |
1747 | }; |
1748 | static const unsigned int canfd5_data_mux[] = { |
1749 | CANFD5_TX_MARK, CANFD5_RX_MARK, |
1750 | }; |
1751 | |
1752 | /* - CANFD6 ----------------------------------------------------------------- */ |
1753 | static const unsigned int canfd6_data_pins[] = { |
1754 | /* CANFD6_TX, CANFD6_RX */ |
1755 | RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), |
1756 | }; |
1757 | static const unsigned int canfd6_data_mux[] = { |
1758 | CANFD6_TX_MARK, CANFD6_RX_MARK, |
1759 | }; |
1760 | |
1761 | /* - CANFD7 ----------------------------------------------------------------- */ |
1762 | static const unsigned int canfd7_data_pins[] = { |
1763 | /* CANFD7_TX, CANFD7_RX */ |
1764 | RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), |
1765 | }; |
1766 | static const unsigned int canfd7_data_mux[] = { |
1767 | CANFD7_TX_MARK, CANFD7_RX_MARK, |
1768 | }; |
1769 | |
1770 | /* - CANFD Clock ------------------------------------------------------------ */ |
1771 | static const unsigned int can_clk_pins[] = { |
1772 | /* CAN_CLK */ |
1773 | RCAR_GP_PIN(3, 0), |
1774 | }; |
1775 | static const unsigned int can_clk_mux[] = { |
1776 | CAN_CLK_MARK, |
1777 | }; |
1778 | |
1779 | /* - DU --------------------------------------------------------------------- */ |
1780 | static const unsigned int du_rgb888_pins[] = { |
1781 | /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */ |
1782 | RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), |
1783 | RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), |
1784 | RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), |
1785 | RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), |
1786 | RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), |
1787 | RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), |
1788 | }; |
1789 | static const unsigned int du_rgb888_mux[] = { |
1790 | DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, |
1791 | DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK, |
1792 | DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, |
1793 | DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK, |
1794 | DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, |
1795 | DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK, |
1796 | }; |
1797 | static const unsigned int du_clk_out_pins[] = { |
1798 | /* DU_DOTCLKOUT */ |
1799 | RCAR_GP_PIN(1, 24), |
1800 | }; |
1801 | static const unsigned int du_clk_out_mux[] = { |
1802 | DU_DOTCLKOUT_MARK, |
1803 | }; |
1804 | static const unsigned int du_sync_pins[] = { |
1805 | /* DU_HSYNC, DU_VSYNC */ |
1806 | RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 26), |
1807 | }; |
1808 | static const unsigned int du_sync_mux[] = { |
1809 | DU_HSYNC_MARK, DU_VSYNC_MARK, |
1810 | }; |
1811 | static const unsigned int du_oddf_pins[] = { |
1812 | /* DU_EXODDF/DU_ODDF/DISP/CDE */ |
1813 | RCAR_GP_PIN(1, 27), |
1814 | }; |
1815 | static const unsigned int du_oddf_mux[] = { |
1816 | DU_ODDF_DISP_CDE_MARK, |
1817 | }; |
1818 | |
1819 | /* - HSCIF0 ----------------------------------------------------------------- */ |
1820 | static const unsigned int hscif0_data_pins[] = { |
1821 | /* HRX0, HTX0 */ |
1822 | RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 5), |
1823 | }; |
1824 | static const unsigned int hscif0_data_mux[] = { |
1825 | HRX0_MARK, HTX0_MARK, |
1826 | }; |
1827 | static const unsigned int hscif0_clk_pins[] = { |
1828 | /* HSCK0 */ |
1829 | RCAR_GP_PIN(1, 2), |
1830 | }; |
1831 | static const unsigned int hscif0_clk_mux[] = { |
1832 | HSCK0_MARK, |
1833 | }; |
1834 | static const unsigned int hscif0_ctrl_pins[] = { |
1835 | /* HRTS0#, HCTS0# */ |
1836 | RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4), |
1837 | }; |
1838 | static const unsigned int hscif0_ctrl_mux[] = { |
1839 | HRTS0_N_MARK, HCTS0_N_MARK, |
1840 | }; |
1841 | |
1842 | /* - HSCIF1 ----------------------------------------------------------------- */ |
1843 | static const unsigned int hscif1_data_pins[] = { |
1844 | /* HRX1, HTX1 */ |
1845 | RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), |
1846 | }; |
1847 | static const unsigned int hscif1_data_mux[] = { |
1848 | HRX1_MARK, HTX1_MARK, |
1849 | }; |
1850 | static const unsigned int hscif1_clk_pins[] = { |
1851 | /* HSCK1 */ |
1852 | RCAR_GP_PIN(1, 18), |
1853 | }; |
1854 | static const unsigned int hscif1_clk_mux[] = { |
1855 | HSCK1_MARK, |
1856 | }; |
1857 | static const unsigned int hscif1_ctrl_pins[] = { |
1858 | /* HRTS1#, HCTS1# */ |
1859 | RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), |
1860 | }; |
1861 | static const unsigned int hscif1_ctrl_mux[] = { |
1862 | HRTS1_N_MARK, HCTS1_N_MARK, |
1863 | }; |
1864 | |
1865 | /* - HSCIF2 ----------------------------------------------------------------- */ |
1866 | static const unsigned int hscif2_data_pins[] = { |
1867 | /* HRX2, HTX2 */ |
1868 | RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), |
1869 | }; |
1870 | static const unsigned int hscif2_data_mux[] = { |
1871 | HRX2_MARK, HTX2_MARK, |
1872 | }; |
1873 | static const unsigned int hscif2_clk_pins[] = { |
1874 | /* HSCK2 */ |
1875 | RCAR_GP_PIN(2, 5), |
1876 | }; |
1877 | static const unsigned int hscif2_clk_mux[] = { |
1878 | HSCK2_MARK, |
1879 | }; |
1880 | static const unsigned int hscif2_ctrl_pins[] = { |
1881 | /* HRTS2#, HCTS2# */ |
1882 | RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), |
1883 | }; |
1884 | static const unsigned int hscif2_ctrl_mux[] = { |
1885 | HRTS2_N_MARK, HCTS2_N_MARK, |
1886 | }; |
1887 | |
1888 | /* - HSCIF3 ----------------------------------------------------------------- */ |
1889 | static const unsigned int hscif3_data_pins[] = { |
1890 | /* HRX3, HTX3 */ |
1891 | RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 17), |
1892 | }; |
1893 | static const unsigned int hscif3_data_mux[] = { |
1894 | HRX3_MARK, HTX3_MARK, |
1895 | }; |
1896 | static const unsigned int hscif3_clk_pins[] = { |
1897 | /* HSCK3 */ |
1898 | RCAR_GP_PIN(1, 14), |
1899 | }; |
1900 | static const unsigned int hscif3_clk_mux[] = { |
1901 | HSCK3_MARK, |
1902 | }; |
1903 | static const unsigned int hscif3_ctrl_pins[] = { |
1904 | /* HRTS3#, HCTS3# */ |
1905 | RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), |
1906 | }; |
1907 | static const unsigned int hscif3_ctrl_mux[] = { |
1908 | HRTS3_N_MARK, HCTS3_N_MARK, |
1909 | }; |
1910 | |
1911 | /* - I2C0 ------------------------------------------------------------------- */ |
1912 | static const unsigned int i2c0_pins[] = { |
1913 | /* SDA0, SCL0 */ |
1914 | RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2), |
1915 | }; |
1916 | static const unsigned int i2c0_mux[] = { |
1917 | SDA0_MARK, SCL0_MARK, |
1918 | }; |
1919 | |
1920 | /* - I2C1 ------------------------------------------------------------------- */ |
1921 | static const unsigned int i2c1_pins[] = { |
1922 | /* SDA1, SCL1 */ |
1923 | RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), |
1924 | }; |
1925 | static const unsigned int i2c1_mux[] = { |
1926 | SDA1_MARK, SCL1_MARK, |
1927 | }; |
1928 | |
1929 | /* - I2C2 ------------------------------------------------------------------- */ |
1930 | static const unsigned int i2c2_pins[] = { |
1931 | /* SDA2, SCL2 */ |
1932 | RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), |
1933 | }; |
1934 | static const unsigned int i2c2_mux[] = { |
1935 | SDA2_MARK, SCL2_MARK, |
1936 | }; |
1937 | |
1938 | /* - I2C3 ------------------------------------------------------------------- */ |
1939 | static const unsigned int i2c3_pins[] = { |
1940 | /* SDA3, SCL3 */ |
1941 | RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8), |
1942 | }; |
1943 | static const unsigned int i2c3_mux[] = { |
1944 | SDA3_MARK, SCL3_MARK, |
1945 | }; |
1946 | |
1947 | /* - I2C4 ------------------------------------------------------------------- */ |
1948 | static const unsigned int i2c4_pins[] = { |
1949 | /* SDA4, SCL4 */ |
1950 | RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), |
1951 | }; |
1952 | static const unsigned int i2c4_mux[] = { |
1953 | SDA4_MARK, SCL4_MARK, |
1954 | }; |
1955 | |
1956 | /* - I2C5 ------------------------------------------------------------------- */ |
1957 | static const unsigned int i2c5_pins[] = { |
1958 | /* SDA5, SCL5 */ |
1959 | RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12), |
1960 | }; |
1961 | static const unsigned int i2c5_mux[] = { |
1962 | SDA5_MARK, SCL5_MARK, |
1963 | }; |
1964 | |
1965 | /* - I2C6 ------------------------------------------------------------------- */ |
1966 | static const unsigned int i2c6_pins[] = { |
1967 | /* SDA6, SCL6 */ |
1968 | RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), |
1969 | }; |
1970 | static const unsigned int i2c6_mux[] = { |
1971 | SDA6_MARK, SCL6_MARK, |
1972 | }; |
1973 | |
1974 | /* - INTC-EX ---------------------------------------------------------------- */ |
1975 | static const unsigned int intc_ex_irq0_pins[] = { |
1976 | /* IRQ0 */ |
1977 | RCAR_GP_PIN(1, 24), |
1978 | }; |
1979 | static const unsigned int intc_ex_irq0_mux[] = { |
1980 | IRQ0_MARK, |
1981 | }; |
1982 | static const unsigned int intc_ex_irq1_pins[] = { |
1983 | /* IRQ1 */ |
1984 | RCAR_GP_PIN(1, 25), |
1985 | }; |
1986 | static const unsigned int intc_ex_irq1_mux[] = { |
1987 | IRQ1_MARK, |
1988 | }; |
1989 | static const unsigned int intc_ex_irq2_pins[] = { |
1990 | /* IRQ2 */ |
1991 | RCAR_GP_PIN(1, 26), |
1992 | }; |
1993 | static const unsigned int intc_ex_irq2_mux[] = { |
1994 | IRQ2_MARK, |
1995 | }; |
1996 | static const unsigned int intc_ex_irq3_pins[] = { |
1997 | /* IRQ3 */ |
1998 | RCAR_GP_PIN(1, 27), |
1999 | }; |
2000 | static const unsigned int intc_ex_irq3_mux[] = { |
2001 | IRQ3_MARK, |
2002 | }; |
2003 | static const unsigned int intc_ex_irq4_pins[] = { |
2004 | /* IRQ4 */ |
2005 | RCAR_GP_PIN(2, 14), |
2006 | }; |
2007 | static const unsigned int intc_ex_irq4_mux[] = { |
2008 | IRQ4_MARK, |
2009 | }; |
2010 | static const unsigned int intc_ex_irq5_pins[] = { |
2011 | /* IRQ5 */ |
2012 | RCAR_GP_PIN(2, 15), |
2013 | }; |
2014 | static const unsigned int intc_ex_irq5_mux[] = { |
2015 | IRQ5_MARK, |
2016 | }; |
2017 | |
2018 | /* - MMC -------------------------------------------------------------------- */ |
2019 | static const unsigned int mmc_data_pins[] = { |
2020 | /* MMC_SD_D[0:3], MMC_D[4:7] */ |
2021 | RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), |
2022 | RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22), |
2023 | RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), |
2024 | RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 27), |
2025 | }; |
2026 | static const unsigned int mmc_data_mux[] = { |
2027 | MMC_SD_D0_MARK, MMC_SD_D1_MARK, |
2028 | MMC_SD_D2_MARK, MMC_SD_D3_MARK, |
2029 | MMC_D4_MARK, MMC_D5_MARK, |
2030 | MMC_D6_MARK, MMC_D7_MARK, |
2031 | }; |
2032 | static const unsigned int mmc_ctrl_pins[] = { |
2033 | /* MMC_SD_CLK, MMC_SD_CMD */ |
2034 | RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 18), |
2035 | }; |
2036 | static const unsigned int mmc_ctrl_mux[] = { |
2037 | MMC_SD_CLK_MARK, MMC_SD_CMD_MARK, |
2038 | }; |
2039 | static const unsigned int mmc_cd_pins[] = { |
2040 | /* SD_CD */ |
2041 | RCAR_GP_PIN(0, 16), |
2042 | }; |
2043 | static const unsigned int mmc_cd_mux[] = { |
2044 | SD_CD_MARK, |
2045 | }; |
2046 | static const unsigned int mmc_wp_pins[] = { |
2047 | /* SD_WP */ |
2048 | RCAR_GP_PIN(0, 15), |
2049 | }; |
2050 | static const unsigned int mmc_wp_mux[] = { |
2051 | SD_WP_MARK, |
2052 | }; |
2053 | static const unsigned int mmc_ds_pins[] = { |
2054 | /* MMC_DS */ |
2055 | RCAR_GP_PIN(0, 17), |
2056 | }; |
2057 | static const unsigned int mmc_ds_mux[] = { |
2058 | MMC_DS_MARK, |
2059 | }; |
2060 | |
2061 | /* - MSIOF0 ----------------------------------------------------------------- */ |
2062 | static const unsigned int msiof0_clk_pins[] = { |
2063 | /* MSIOF0_SCK */ |
2064 | RCAR_GP_PIN(1, 8), |
2065 | }; |
2066 | static const unsigned int msiof0_clk_mux[] = { |
2067 | MSIOF0_SCK_MARK, |
2068 | }; |
2069 | static const unsigned int msiof0_sync_pins[] = { |
2070 | /* MSIOF0_SYNC */ |
2071 | RCAR_GP_PIN(1, 9), |
2072 | }; |
2073 | static const unsigned int msiof0_sync_mux[] = { |
2074 | MSIOF0_SYNC_MARK, |
2075 | }; |
2076 | static const unsigned int msiof0_ss1_pins[] = { |
2077 | /* MSIOF0_SS1 */ |
2078 | RCAR_GP_PIN(1, 10), |
2079 | }; |
2080 | static const unsigned int msiof0_ss1_mux[] = { |
2081 | MSIOF0_SS1_MARK, |
2082 | }; |
2083 | static const unsigned int msiof0_ss2_pins[] = { |
2084 | /* MSIOF0_SS2 */ |
2085 | RCAR_GP_PIN(1, 11), |
2086 | }; |
2087 | static const unsigned int msiof0_ss2_mux[] = { |
2088 | MSIOF0_SS2_MARK, |
2089 | }; |
2090 | static const unsigned int msiof0_txd_pins[] = { |
2091 | /* MSIOF0_TXD */ |
2092 | RCAR_GP_PIN(1, 7), |
2093 | }; |
2094 | static const unsigned int msiof0_txd_mux[] = { |
2095 | MSIOF0_TXD_MARK, |
2096 | }; |
2097 | static const unsigned int msiof0_rxd_pins[] = { |
2098 | /* MSIOF0_RXD */ |
2099 | RCAR_GP_PIN(1, 6), |
2100 | }; |
2101 | static const unsigned int msiof0_rxd_mux[] = { |
2102 | MSIOF0_RXD_MARK, |
2103 | }; |
2104 | |
2105 | /* - MSIOF1 ----------------------------------------------------------------- */ |
2106 | static const unsigned int msiof1_clk_pins[] = { |
2107 | /* MSIOF1_SCK */ |
2108 | RCAR_GP_PIN(1, 14), |
2109 | }; |
2110 | static const unsigned int msiof1_clk_mux[] = { |
2111 | MSIOF1_SCK_MARK, |
2112 | }; |
2113 | static const unsigned int msiof1_sync_pins[] = { |
2114 | /* MSIOF1_SYNC */ |
2115 | RCAR_GP_PIN(1, 15), |
2116 | }; |
2117 | static const unsigned int msiof1_sync_mux[] = { |
2118 | MSIOF1_SYNC_MARK, |
2119 | }; |
2120 | static const unsigned int msiof1_ss1_pins[] = { |
2121 | /* MSIOF1_SS1 */ |
2122 | RCAR_GP_PIN(1, 16), |
2123 | }; |
2124 | static const unsigned int msiof1_ss1_mux[] = { |
2125 | MSIOF1_SS1_MARK, |
2126 | }; |
2127 | static const unsigned int msiof1_ss2_pins[] = { |
2128 | /* MSIOF1_SS2 */ |
2129 | RCAR_GP_PIN(1, 17), |
2130 | }; |
2131 | static const unsigned int msiof1_ss2_mux[] = { |
2132 | MSIOF1_SS2_MARK, |
2133 | }; |
2134 | static const unsigned int msiof1_txd_pins[] = { |
2135 | /* MSIOF1_TXD */ |
2136 | RCAR_GP_PIN(1, 13), |
2137 | }; |
2138 | static const unsigned int msiof1_txd_mux[] = { |
2139 | MSIOF1_TXD_MARK, |
2140 | }; |
2141 | static const unsigned int msiof1_rxd_pins[] = { |
2142 | /* MSIOF1_RXD */ |
2143 | RCAR_GP_PIN(1, 12), |
2144 | }; |
2145 | static const unsigned int msiof1_rxd_mux[] = { |
2146 | MSIOF1_RXD_MARK, |
2147 | }; |
2148 | |
2149 | /* - MSIOF2 ----------------------------------------------------------------- */ |
2150 | static const unsigned int msiof2_clk_pins[] = { |
2151 | /* MSIOF2_SCK */ |
2152 | RCAR_GP_PIN(1, 20), |
2153 | }; |
2154 | static const unsigned int msiof2_clk_mux[] = { |
2155 | MSIOF2_SCK_MARK, |
2156 | }; |
2157 | static const unsigned int msiof2_sync_pins[] = { |
2158 | /* MSIOF2_SYNC */ |
2159 | RCAR_GP_PIN(1, 21), |
2160 | }; |
2161 | static const unsigned int msiof2_sync_mux[] = { |
2162 | MSIOF2_SYNC_MARK, |
2163 | }; |
2164 | static const unsigned int msiof2_ss1_pins[] = { |
2165 | /* MSIOF2_SS1 */ |
2166 | RCAR_GP_PIN(1, 22), |
2167 | }; |
2168 | static const unsigned int msiof2_ss1_mux[] = { |
2169 | MSIOF2_SS1_MARK, |
2170 | }; |
2171 | static const unsigned int msiof2_ss2_pins[] = { |
2172 | /* MSIOF2_SS2 */ |
2173 | RCAR_GP_PIN(1, 23), |
2174 | }; |
2175 | static const unsigned int msiof2_ss2_mux[] = { |
2176 | MSIOF2_SS2_MARK, |
2177 | }; |
2178 | static const unsigned int msiof2_txd_pins[] = { |
2179 | /* MSIOF2_TXD */ |
2180 | RCAR_GP_PIN(1, 19), |
2181 | }; |
2182 | static const unsigned int msiof2_txd_mux[] = { |
2183 | MSIOF2_TXD_MARK, |
2184 | }; |
2185 | static const unsigned int msiof2_rxd_pins[] = { |
2186 | /* MSIOF2_RXD */ |
2187 | RCAR_GP_PIN(1, 18), |
2188 | }; |
2189 | static const unsigned int msiof2_rxd_mux[] = { |
2190 | MSIOF2_RXD_MARK, |
2191 | }; |
2192 | |
2193 | /* - MSIOF3 ----------------------------------------------------------------- */ |
2194 | static const unsigned int msiof3_clk_pins[] = { |
2195 | /* MSIOF3_SCK */ |
2196 | RCAR_GP_PIN(2, 20), |
2197 | }; |
2198 | static const unsigned int msiof3_clk_mux[] = { |
2199 | MSIOF3_SCK_MARK, |
2200 | }; |
2201 | static const unsigned int msiof3_sync_pins[] = { |
2202 | /* MSIOF3_SYNC */ |
2203 | RCAR_GP_PIN(2, 21), |
2204 | }; |
2205 | static const unsigned int msiof3_sync_mux[] = { |
2206 | MSIOF3_SYNC_MARK, |
2207 | }; |
2208 | static const unsigned int msiof3_ss1_pins[] = { |
2209 | /* MSIOF3_SS1 */ |
2210 | RCAR_GP_PIN(2, 16), |
2211 | }; |
2212 | static const unsigned int msiof3_ss1_mux[] = { |
2213 | MSIOF3_SS1_MARK, |
2214 | }; |
2215 | static const unsigned int msiof3_ss2_pins[] = { |
2216 | /* MSIOF3_SS2 */ |
2217 | RCAR_GP_PIN(2, 17), |
2218 | }; |
2219 | static const unsigned int msiof3_ss2_mux[] = { |
2220 | MSIOF3_SS2_MARK, |
2221 | }; |
2222 | static const unsigned int msiof3_txd_pins[] = { |
2223 | /* MSIOF3_TXD */ |
2224 | RCAR_GP_PIN(2, 19), |
2225 | }; |
2226 | static const unsigned int msiof3_txd_mux[] = { |
2227 | MSIOF3_TXD_MARK, |
2228 | }; |
2229 | static const unsigned int msiof3_rxd_pins[] = { |
2230 | /* MSIOF3_RXD */ |
2231 | RCAR_GP_PIN(2, 18), |
2232 | }; |
2233 | static const unsigned int msiof3_rxd_mux[] = { |
2234 | MSIOF3_RXD_MARK, |
2235 | }; |
2236 | |
2237 | /* - MSIOF4 ----------------------------------------------------------------- */ |
2238 | static const unsigned int msiof4_clk_pins[] = { |
2239 | /* MSIOF4_SCK */ |
2240 | RCAR_GP_PIN(2, 6), |
2241 | }; |
2242 | static const unsigned int msiof4_clk_mux[] = { |
2243 | MSIOF4_SCK_MARK, |
2244 | }; |
2245 | static const unsigned int msiof4_sync_pins[] = { |
2246 | /* MSIOF4_SYNC */ |
2247 | RCAR_GP_PIN(2, 7), |
2248 | }; |
2249 | static const unsigned int msiof4_sync_mux[] = { |
2250 | MSIOF4_SYNC_MARK, |
2251 | }; |
2252 | static const unsigned int msiof4_ss1_pins[] = { |
2253 | /* MSIOF4_SS1 */ |
2254 | RCAR_GP_PIN(2, 8), |
2255 | }; |
2256 | static const unsigned int msiof4_ss1_mux[] = { |
2257 | MSIOF4_SS1_MARK, |
2258 | }; |
2259 | static const unsigned int msiof4_ss2_pins[] = { |
2260 | /* MSIOF4_SS2 */ |
2261 | RCAR_GP_PIN(2, 9), |
2262 | }; |
2263 | static const unsigned int msiof4_ss2_mux[] = { |
2264 | MSIOF4_SS2_MARK, |
2265 | }; |
2266 | static const unsigned int msiof4_txd_pins[] = { |
2267 | /* MSIOF4_TXD */ |
2268 | RCAR_GP_PIN(2, 5), |
2269 | }; |
2270 | static const unsigned int msiof4_txd_mux[] = { |
2271 | MSIOF4_TXD_MARK, |
2272 | }; |
2273 | static const unsigned int msiof4_rxd_pins[] = { |
2274 | /* MSIOF4_RXD */ |
2275 | RCAR_GP_PIN(2, 4), |
2276 | }; |
2277 | static const unsigned int msiof4_rxd_mux[] = { |
2278 | MSIOF4_RXD_MARK, |
2279 | }; |
2280 | |
2281 | /* - MSIOF5 ----------------------------------------------------------------- */ |
2282 | static const unsigned int msiof5_clk_pins[] = { |
2283 | /* MSIOF5_SCK */ |
2284 | RCAR_GP_PIN(2, 12), |
2285 | }; |
2286 | static const unsigned int msiof5_clk_mux[] = { |
2287 | MSIOF5_SCK_MARK, |
2288 | }; |
2289 | static const unsigned int msiof5_sync_pins[] = { |
2290 | /* MSIOF5_SYNC */ |
2291 | RCAR_GP_PIN(2, 13), |
2292 | }; |
2293 | static const unsigned int msiof5_sync_mux[] = { |
2294 | MSIOF5_SYNC_MARK, |
2295 | }; |
2296 | static const unsigned int msiof5_ss1_pins[] = { |
2297 | /* MSIOF5_SS1 */ |
2298 | RCAR_GP_PIN(2, 14), |
2299 | }; |
2300 | static const unsigned int msiof5_ss1_mux[] = { |
2301 | MSIOF5_SS1_MARK, |
2302 | }; |
2303 | static const unsigned int msiof5_ss2_pins[] = { |
2304 | /* MSIOF5_SS2 */ |
2305 | RCAR_GP_PIN(2, 15), |
2306 | }; |
2307 | static const unsigned int msiof5_ss2_mux[] = { |
2308 | MSIOF5_SS2_MARK, |
2309 | }; |
2310 | static const unsigned int msiof5_txd_pins[] = { |
2311 | /* MSIOF5_TXD */ |
2312 | RCAR_GP_PIN(2, 11), |
2313 | }; |
2314 | static const unsigned int msiof5_txd_mux[] = { |
2315 | MSIOF5_TXD_MARK, |
2316 | }; |
2317 | static const unsigned int msiof5_rxd_pins[] = { |
2318 | /* MSIOF5_RXD */ |
2319 | RCAR_GP_PIN(2, 10), |
2320 | }; |
2321 | static const unsigned int msiof5_rxd_mux[] = { |
2322 | MSIOF5_RXD_MARK, |
2323 | }; |
2324 | |
2325 | /* - PWM0 ------------------------------------------------------------------- */ |
2326 | static const unsigned int pwm0_pins[] = { |
2327 | /* PWM0 */ |
2328 | RCAR_GP_PIN(3, 5), |
2329 | }; |
2330 | static const unsigned int pwm0_mux[] = { |
2331 | PWM0_MARK, |
2332 | }; |
2333 | |
2334 | /* - PWM1 ------------------------------------------------------------------- */ |
2335 | static const unsigned int pwm1_pins[] = { |
2336 | /* PWM1 */ |
2337 | RCAR_GP_PIN(3, 6), |
2338 | }; |
2339 | static const unsigned int pwm1_mux[] = { |
2340 | PWM1_MARK, |
2341 | }; |
2342 | |
2343 | /* - PWM2 ------------------------------------------------------------------- */ |
2344 | static const unsigned int pwm2_pins[] = { |
2345 | /* PWM2 */ |
2346 | RCAR_GP_PIN(3, 7), |
2347 | }; |
2348 | static const unsigned int pwm2_mux[] = { |
2349 | PWM2_MARK, |
2350 | }; |
2351 | |
2352 | /* - PWM3 ------------------------------------------------------------------- */ |
2353 | static const unsigned int pwm3_pins[] = { |
2354 | /* PWM3 */ |
2355 | RCAR_GP_PIN(3, 8), |
2356 | }; |
2357 | static const unsigned int pwm3_mux[] = { |
2358 | PWM3_MARK, |
2359 | }; |
2360 | |
2361 | /* - PWM4 ------------------------------------------------------------------- */ |
2362 | static const unsigned int pwm4_pins[] = { |
2363 | /* PWM4 */ |
2364 | RCAR_GP_PIN(3, 9), |
2365 | }; |
2366 | static const unsigned int pwm4_mux[] = { |
2367 | PWM4_MARK, |
2368 | }; |
2369 | |
2370 | /* - QSPI0 ------------------------------------------------------------------ */ |
2371 | static const unsigned int qspi0_ctrl_pins[] = { |
2372 | /* SPCLK, SSL */ |
2373 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 5), |
2374 | }; |
2375 | static const unsigned int qspi0_ctrl_mux[] = { |
2376 | QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, |
2377 | }; |
2378 | static const unsigned int qspi0_data_pins[] = { |
2379 | /* MOSI_IO0, MISO_IO1, IO2, IO3 */ |
2380 | RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), |
2381 | RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4), |
2382 | }; |
2383 | static const unsigned int qspi0_data_mux[] = { |
2384 | QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, |
2385 | QSPI0_IO2_MARK, QSPI0_IO3_MARK |
2386 | }; |
2387 | |
2388 | /* - QSPI1 ------------------------------------------------------------------ */ |
2389 | static const unsigned int qspi1_ctrl_pins[] = { |
2390 | /* SPCLK, SSL */ |
2391 | RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 11), |
2392 | }; |
2393 | static const unsigned int qspi1_ctrl_mux[] = { |
2394 | QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, |
2395 | }; |
2396 | static const unsigned int qspi1_data_pins[] = { |
2397 | /* MOSI_IO0, MISO_IO1, IO2, IO3 */ |
2398 | RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), |
2399 | RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), |
2400 | }; |
2401 | static const unsigned int qspi1_data_mux[] = { |
2402 | QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, |
2403 | QSPI1_IO2_MARK, QSPI1_IO3_MARK |
2404 | }; |
2405 | |
2406 | /* - SCIF0 ------------------------------------------------------------------ */ |
2407 | static const unsigned int scif0_data_pins[] = { |
2408 | /* RX0, TX0 */ |
2409 | RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 5), |
2410 | }; |
2411 | static const unsigned int scif0_data_mux[] = { |
2412 | RX0_MARK, TX0_MARK, |
2413 | }; |
2414 | static const unsigned int scif0_clk_pins[] = { |
2415 | /* SCK0 */ |
2416 | RCAR_GP_PIN(1, 2), |
2417 | }; |
2418 | static const unsigned int scif0_clk_mux[] = { |
2419 | SCK0_MARK, |
2420 | }; |
2421 | static const unsigned int scif0_ctrl_pins[] = { |
2422 | /* RTS0#, CTS0# */ |
2423 | RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4), |
2424 | }; |
2425 | static const unsigned int scif0_ctrl_mux[] = { |
2426 | RTS0_N_MARK, CTS0_N_MARK, |
2427 | }; |
2428 | |
2429 | /* - SCIF1 ------------------------------------------------------------------ */ |
2430 | static const unsigned int scif1_data_a_pins[] = { |
2431 | /* RX, TX */ |
2432 | RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), |
2433 | }; |
2434 | static const unsigned int scif1_data_a_mux[] = { |
2435 | RX1_A_MARK, TX1_A_MARK, |
2436 | }; |
2437 | static const unsigned int scif1_data_b_pins[] = { |
2438 | /* RX, TX */ |
2439 | RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 1), |
2440 | }; |
2441 | static const unsigned int scif1_data_b_mux[] = { |
2442 | RX1_B_MARK, TX1_B_MARK, |
2443 | }; |
2444 | static const unsigned int scif1_clk_pins[] = { |
2445 | /* SCK1 */ |
2446 | RCAR_GP_PIN(1, 18), |
2447 | }; |
2448 | static const unsigned int scif1_clk_mux[] = { |
2449 | SCK1_MARK, |
2450 | }; |
2451 | static const unsigned int scif1_ctrl_pins[] = { |
2452 | /* RTS1#, CTS1# */ |
2453 | RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), |
2454 | }; |
2455 | static const unsigned int scif1_ctrl_mux[] = { |
2456 | RTS1_N_MARK, CTS1_N_MARK, |
2457 | }; |
2458 | |
2459 | /* - SCIF3 ------------------------------------------------------------------ */ |
2460 | static const unsigned int scif3_data_pins[] = { |
2461 | /* RX3, TX3 */ |
2462 | RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), |
2463 | }; |
2464 | static const unsigned int scif3_data_mux[] = { |
2465 | RX3_MARK, TX3_MARK, |
2466 | }; |
2467 | static const unsigned int scif3_clk_pins[] = { |
2468 | /* SCK3 */ |
2469 | RCAR_GP_PIN(1, 13), |
2470 | }; |
2471 | static const unsigned int scif3_clk_mux[] = { |
2472 | SCK3_MARK, |
2473 | }; |
2474 | static const unsigned int scif3_ctrl_pins[] = { |
2475 | /* RTS3#, CTS3# */ |
2476 | RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), |
2477 | }; |
2478 | static const unsigned int scif3_ctrl_mux[] = { |
2479 | RTS3_N_MARK, CTS3_N_MARK, |
2480 | }; |
2481 | |
2482 | /* - SCIF4 ------------------------------------------------------------------ */ |
2483 | static const unsigned int scif4_data_pins[] = { |
2484 | /* RX4, TX4 */ |
2485 | RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), |
2486 | }; |
2487 | static const unsigned int scif4_data_mux[] = { |
2488 | RX4_MARK, TX4_MARK, |
2489 | }; |
2490 | static const unsigned int scif4_clk_pins[] = { |
2491 | /* SCK4 */ |
2492 | RCAR_GP_PIN(2, 5), |
2493 | }; |
2494 | static const unsigned int scif4_clk_mux[] = { |
2495 | SCK4_MARK, |
2496 | }; |
2497 | static const unsigned int scif4_ctrl_pins[] = { |
2498 | /* RTS4#, CTS4# */ |
2499 | RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), |
2500 | }; |
2501 | static const unsigned int scif4_ctrl_mux[] = { |
2502 | RTS4_N_MARK, CTS4_N_MARK, |
2503 | }; |
2504 | |
2505 | /* - SCIF Clock ------------------------------------------------------------- */ |
2506 | static const unsigned int scif_clk_pins[] = { |
2507 | /* SCIF_CLK */ |
2508 | RCAR_GP_PIN(1, 0), |
2509 | }; |
2510 | static const unsigned int scif_clk_mux[] = { |
2511 | SCIF_CLK_MARK, |
2512 | }; |
2513 | |
2514 | /* - TMU -------------------------------------------------------------------- */ |
2515 | static const unsigned int tmu_tclk1_a_pins[] = { |
2516 | /* TCLK1 */ |
2517 | RCAR_GP_PIN(2, 23), |
2518 | }; |
2519 | static const unsigned int tmu_tclk1_a_mux[] = { |
2520 | TCLK1_A_MARK, |
2521 | }; |
2522 | static const unsigned int tmu_tclk1_b_pins[] = { |
2523 | /* TCLK1 */ |
2524 | RCAR_GP_PIN(1, 23), |
2525 | }; |
2526 | static const unsigned int tmu_tclk1_b_mux[] = { |
2527 | TCLK1_B_MARK, |
2528 | }; |
2529 | |
2530 | static const unsigned int tmu_tclk2_a_pins[] = { |
2531 | /* TCLK2 */ |
2532 | RCAR_GP_PIN(2, 24), |
2533 | }; |
2534 | static const unsigned int tmu_tclk2_a_mux[] = { |
2535 | TCLK2_A_MARK, |
2536 | }; |
2537 | static const unsigned int tmu_tclk2_b_pins[] = { |
2538 | /* TCLK2 */ |
2539 | RCAR_GP_PIN(2, 10), |
2540 | }; |
2541 | static const unsigned int tmu_tclk2_b_mux[] = { |
2542 | TCLK2_B_MARK, |
2543 | }; |
2544 | |
2545 | static const unsigned int tmu_tclk3_pins[] = { |
2546 | /* TCLK3 */ |
2547 | RCAR_GP_PIN(2, 11), |
2548 | }; |
2549 | static const unsigned int tmu_tclk3_mux[] = { |
2550 | TCLK3_MARK, |
2551 | }; |
2552 | |
2553 | static const unsigned int tmu_tclk4_pins[] = { |
2554 | /* TCLK4 */ |
2555 | RCAR_GP_PIN(2, 12), |
2556 | }; |
2557 | static const unsigned int tmu_tclk4_mux[] = { |
2558 | TCLK4_MARK, |
2559 | }; |
2560 | |
2561 | /* - TPU ------------------------------------------------------------------- */ |
2562 | static const unsigned int tpu_to0_pins[] = { |
2563 | /* TPU0TO0 */ |
2564 | RCAR_GP_PIN(2, 21), |
2565 | }; |
2566 | static const unsigned int tpu_to0_mux[] = { |
2567 | TPU0TO0_MARK, |
2568 | }; |
2569 | static const unsigned int tpu_to1_pins[] = { |
2570 | /* TPU0TO1 */ |
2571 | RCAR_GP_PIN(2, 22), |
2572 | }; |
2573 | static const unsigned int tpu_to1_mux[] = { |
2574 | TPU0TO1_MARK, |
2575 | }; |
2576 | static const unsigned int tpu_to2_pins[] = { |
2577 | /* TPU0TO2 */ |
2578 | RCAR_GP_PIN(3, 5), |
2579 | }; |
2580 | static const unsigned int tpu_to2_mux[] = { |
2581 | TPU0TO2_MARK, |
2582 | }; |
2583 | static const unsigned int tpu_to3_pins[] = { |
2584 | /* TPU0TO3 */ |
2585 | RCAR_GP_PIN(3, 6), |
2586 | }; |
2587 | static const unsigned int tpu_to3_mux[] = { |
2588 | TPU0TO3_MARK, |
2589 | }; |
2590 | |
2591 | static const struct sh_pfc_pin_group pinmux_groups[] = { |
2592 | SH_PFC_PIN_GROUP(avb0_link), |
2593 | SH_PFC_PIN_GROUP(avb0_magic), |
2594 | SH_PFC_PIN_GROUP(avb0_phy_int), |
2595 | SH_PFC_PIN_GROUP(avb0_mdio), |
2596 | SH_PFC_PIN_GROUP(avb0_rgmii), |
2597 | SH_PFC_PIN_GROUP(avb0_txcrefclk), |
2598 | SH_PFC_PIN_GROUP(avb0_avtp_pps), |
2599 | SH_PFC_PIN_GROUP(avb0_avtp_capture), |
2600 | SH_PFC_PIN_GROUP(avb0_avtp_match), |
2601 | |
2602 | SH_PFC_PIN_GROUP(avb1_link), |
2603 | SH_PFC_PIN_GROUP(avb1_magic), |
2604 | SH_PFC_PIN_GROUP(avb1_phy_int), |
2605 | SH_PFC_PIN_GROUP(avb1_mdio), |
2606 | SH_PFC_PIN_GROUP(avb1_rgmii), |
2607 | SH_PFC_PIN_GROUP(avb1_txcrefclk), |
2608 | SH_PFC_PIN_GROUP(avb1_avtp_pps), |
2609 | SH_PFC_PIN_GROUP(avb1_avtp_capture), |
2610 | SH_PFC_PIN_GROUP(avb1_avtp_match), |
2611 | |
2612 | SH_PFC_PIN_GROUP(avb2_link), |
2613 | SH_PFC_PIN_GROUP(avb2_magic), |
2614 | SH_PFC_PIN_GROUP(avb2_phy_int), |
2615 | SH_PFC_PIN_GROUP(avb2_mdio), |
2616 | SH_PFC_PIN_GROUP(avb2_rgmii), |
2617 | SH_PFC_PIN_GROUP(avb2_txcrefclk), |
2618 | SH_PFC_PIN_GROUP(avb2_avtp_pps), |
2619 | SH_PFC_PIN_GROUP(avb2_avtp_capture), |
2620 | SH_PFC_PIN_GROUP(avb2_avtp_match), |
2621 | |
2622 | SH_PFC_PIN_GROUP(avb3_link), |
2623 | SH_PFC_PIN_GROUP(avb3_magic), |
2624 | SH_PFC_PIN_GROUP(avb3_phy_int), |
2625 | SH_PFC_PIN_GROUP(avb3_mdio), |
2626 | SH_PFC_PIN_GROUP(avb3_rgmii), |
2627 | SH_PFC_PIN_GROUP(avb3_txcrefclk), |
2628 | SH_PFC_PIN_GROUP(avb3_avtp_pps), |
2629 | SH_PFC_PIN_GROUP(avb3_avtp_capture), |
2630 | SH_PFC_PIN_GROUP(avb3_avtp_match), |
2631 | |
2632 | SH_PFC_PIN_GROUP(avb4_link), |
2633 | SH_PFC_PIN_GROUP(avb4_magic), |
2634 | SH_PFC_PIN_GROUP(avb4_phy_int), |
2635 | SH_PFC_PIN_GROUP(avb4_mdio), |
2636 | SH_PFC_PIN_GROUP(avb4_rgmii), |
2637 | SH_PFC_PIN_GROUP(avb4_txcrefclk), |
2638 | SH_PFC_PIN_GROUP(avb4_avtp_pps), |
2639 | SH_PFC_PIN_GROUP(avb4_avtp_capture), |
2640 | SH_PFC_PIN_GROUP(avb4_avtp_match), |
2641 | |
2642 | SH_PFC_PIN_GROUP(avb5_link), |
2643 | SH_PFC_PIN_GROUP(avb5_magic), |
2644 | SH_PFC_PIN_GROUP(avb5_phy_int), |
2645 | SH_PFC_PIN_GROUP(avb5_mdio), |
2646 | SH_PFC_PIN_GROUP(avb5_rgmii), |
2647 | SH_PFC_PIN_GROUP(avb5_txcrefclk), |
2648 | SH_PFC_PIN_GROUP(avb5_avtp_pps), |
2649 | SH_PFC_PIN_GROUP(avb5_avtp_capture), |
2650 | SH_PFC_PIN_GROUP(avb5_avtp_match), |
2651 | |
2652 | SH_PFC_PIN_GROUP(canfd0_data), |
2653 | SH_PFC_PIN_GROUP(canfd1_data), |
2654 | SH_PFC_PIN_GROUP(canfd2_data), |
2655 | SH_PFC_PIN_GROUP(canfd3_data), |
2656 | SH_PFC_PIN_GROUP(canfd4_data), |
2657 | SH_PFC_PIN_GROUP(canfd5_data), |
2658 | SH_PFC_PIN_GROUP(canfd6_data), |
2659 | SH_PFC_PIN_GROUP(canfd7_data), |
2660 | SH_PFC_PIN_GROUP(can_clk), |
2661 | |
2662 | SH_PFC_PIN_GROUP(du_rgb888), |
2663 | SH_PFC_PIN_GROUP(du_clk_out), |
2664 | SH_PFC_PIN_GROUP(du_sync), |
2665 | SH_PFC_PIN_GROUP(du_oddf), |
2666 | |
2667 | SH_PFC_PIN_GROUP(hscif0_data), |
2668 | SH_PFC_PIN_GROUP(hscif0_clk), |
2669 | SH_PFC_PIN_GROUP(hscif0_ctrl), |
2670 | SH_PFC_PIN_GROUP(hscif1_data), |
2671 | SH_PFC_PIN_GROUP(hscif1_clk), |
2672 | SH_PFC_PIN_GROUP(hscif1_ctrl), |
2673 | SH_PFC_PIN_GROUP(hscif2_data), |
2674 | SH_PFC_PIN_GROUP(hscif2_clk), |
2675 | SH_PFC_PIN_GROUP(hscif2_ctrl), |
2676 | SH_PFC_PIN_GROUP(hscif3_data), |
2677 | SH_PFC_PIN_GROUP(hscif3_clk), |
2678 | SH_PFC_PIN_GROUP(hscif3_ctrl), |
2679 | |
2680 | SH_PFC_PIN_GROUP(i2c0), |
2681 | SH_PFC_PIN_GROUP(i2c1), |
2682 | SH_PFC_PIN_GROUP(i2c2), |
2683 | SH_PFC_PIN_GROUP(i2c3), |
2684 | SH_PFC_PIN_GROUP(i2c4), |
2685 | SH_PFC_PIN_GROUP(i2c5), |
2686 | SH_PFC_PIN_GROUP(i2c6), |
2687 | |
2688 | SH_PFC_PIN_GROUP(intc_ex_irq0), |
2689 | SH_PFC_PIN_GROUP(intc_ex_irq1), |
2690 | SH_PFC_PIN_GROUP(intc_ex_irq2), |
2691 | SH_PFC_PIN_GROUP(intc_ex_irq3), |
2692 | SH_PFC_PIN_GROUP(intc_ex_irq4), |
2693 | SH_PFC_PIN_GROUP(intc_ex_irq5), |
2694 | |
2695 | BUS_DATA_PIN_GROUP(mmc_data, 1), |
2696 | BUS_DATA_PIN_GROUP(mmc_data, 4), |
2697 | BUS_DATA_PIN_GROUP(mmc_data, 8), |
2698 | SH_PFC_PIN_GROUP(mmc_ctrl), |
2699 | SH_PFC_PIN_GROUP(mmc_cd), |
2700 | SH_PFC_PIN_GROUP(mmc_wp), |
2701 | SH_PFC_PIN_GROUP(mmc_ds), |
2702 | |
2703 | SH_PFC_PIN_GROUP(msiof0_clk), |
2704 | SH_PFC_PIN_GROUP(msiof0_sync), |
2705 | SH_PFC_PIN_GROUP(msiof0_ss1), |
2706 | SH_PFC_PIN_GROUP(msiof0_ss2), |
2707 | SH_PFC_PIN_GROUP(msiof0_txd), |
2708 | SH_PFC_PIN_GROUP(msiof0_rxd), |
2709 | SH_PFC_PIN_GROUP(msiof1_clk), |
2710 | SH_PFC_PIN_GROUP(msiof1_sync), |
2711 | SH_PFC_PIN_GROUP(msiof1_ss1), |
2712 | SH_PFC_PIN_GROUP(msiof1_ss2), |
2713 | SH_PFC_PIN_GROUP(msiof1_txd), |
2714 | SH_PFC_PIN_GROUP(msiof1_rxd), |
2715 | SH_PFC_PIN_GROUP(msiof2_clk), |
2716 | SH_PFC_PIN_GROUP(msiof2_sync), |
2717 | SH_PFC_PIN_GROUP(msiof2_ss1), |
2718 | SH_PFC_PIN_GROUP(msiof2_ss2), |
2719 | SH_PFC_PIN_GROUP(msiof2_txd), |
2720 | SH_PFC_PIN_GROUP(msiof2_rxd), |
2721 | SH_PFC_PIN_GROUP(msiof3_clk), |
2722 | SH_PFC_PIN_GROUP(msiof3_sync), |
2723 | SH_PFC_PIN_GROUP(msiof3_ss1), |
2724 | SH_PFC_PIN_GROUP(msiof3_ss2), |
2725 | SH_PFC_PIN_GROUP(msiof3_txd), |
2726 | SH_PFC_PIN_GROUP(msiof3_rxd), |
2727 | SH_PFC_PIN_GROUP(msiof4_clk), |
2728 | SH_PFC_PIN_GROUP(msiof4_sync), |
2729 | SH_PFC_PIN_GROUP(msiof4_ss1), |
2730 | SH_PFC_PIN_GROUP(msiof4_ss2), |
2731 | SH_PFC_PIN_GROUP(msiof4_txd), |
2732 | SH_PFC_PIN_GROUP(msiof4_rxd), |
2733 | SH_PFC_PIN_GROUP(msiof5_clk), |
2734 | SH_PFC_PIN_GROUP(msiof5_sync), |
2735 | SH_PFC_PIN_GROUP(msiof5_ss1), |
2736 | SH_PFC_PIN_GROUP(msiof5_ss2), |
2737 | SH_PFC_PIN_GROUP(msiof5_txd), |
2738 | SH_PFC_PIN_GROUP(msiof5_rxd), |
2739 | |
2740 | SH_PFC_PIN_GROUP(pwm0), |
2741 | SH_PFC_PIN_GROUP(pwm1), |
2742 | SH_PFC_PIN_GROUP(pwm2), |
2743 | SH_PFC_PIN_GROUP(pwm3), |
2744 | SH_PFC_PIN_GROUP(pwm4), |
2745 | |
2746 | SH_PFC_PIN_GROUP(qspi0_ctrl), |
2747 | BUS_DATA_PIN_GROUP(qspi0_data, 2), |
2748 | BUS_DATA_PIN_GROUP(qspi0_data, 4), |
2749 | SH_PFC_PIN_GROUP(qspi1_ctrl), |
2750 | BUS_DATA_PIN_GROUP(qspi1_data, 2), |
2751 | BUS_DATA_PIN_GROUP(qspi1_data, 4), |
2752 | |
2753 | SH_PFC_PIN_GROUP(scif0_data), |
2754 | SH_PFC_PIN_GROUP(scif0_clk), |
2755 | SH_PFC_PIN_GROUP(scif0_ctrl), |
2756 | SH_PFC_PIN_GROUP(scif1_data_a), |
2757 | SH_PFC_PIN_GROUP(scif1_data_b), |
2758 | SH_PFC_PIN_GROUP(scif1_clk), |
2759 | SH_PFC_PIN_GROUP(scif1_ctrl), |
2760 | SH_PFC_PIN_GROUP(scif3_data), |
2761 | SH_PFC_PIN_GROUP(scif3_clk), |
2762 | SH_PFC_PIN_GROUP(scif3_ctrl), |
2763 | SH_PFC_PIN_GROUP(scif4_data), |
2764 | SH_PFC_PIN_GROUP(scif4_clk), |
2765 | SH_PFC_PIN_GROUP(scif4_ctrl), |
2766 | SH_PFC_PIN_GROUP(scif_clk), |
2767 | |
2768 | SH_PFC_PIN_GROUP(tmu_tclk1_a), |
2769 | SH_PFC_PIN_GROUP(tmu_tclk1_b), |
2770 | SH_PFC_PIN_GROUP(tmu_tclk2_a), |
2771 | SH_PFC_PIN_GROUP(tmu_tclk2_b), |
2772 | SH_PFC_PIN_GROUP(tmu_tclk3), |
2773 | SH_PFC_PIN_GROUP(tmu_tclk4), |
2774 | |
2775 | SH_PFC_PIN_GROUP(tpu_to0), |
2776 | SH_PFC_PIN_GROUP(tpu_to1), |
2777 | SH_PFC_PIN_GROUP(tpu_to2), |
2778 | SH_PFC_PIN_GROUP(tpu_to3), |
2779 | }; |
2780 | |
2781 | static const char * const avb0_groups[] = { |
2782 | "avb0_link" , |
2783 | "avb0_magic" , |
2784 | "avb0_phy_int" , |
2785 | "avb0_mdio" , |
2786 | "avb0_rgmii" , |
2787 | "avb0_txcrefclk" , |
2788 | "avb0_avtp_pps" , |
2789 | "avb0_avtp_capture" , |
2790 | "avb0_avtp_match" , |
2791 | }; |
2792 | |
2793 | static const char * const avb1_groups[] = { |
2794 | "avb1_link" , |
2795 | "avb1_magic" , |
2796 | "avb1_phy_int" , |
2797 | "avb1_mdio" , |
2798 | "avb1_rgmii" , |
2799 | "avb1_txcrefclk" , |
2800 | "avb1_avtp_pps" , |
2801 | "avb1_avtp_capture" , |
2802 | "avb1_avtp_match" , |
2803 | }; |
2804 | |
2805 | static const char * const avb2_groups[] = { |
2806 | "avb2_link" , |
2807 | "avb2_magic" , |
2808 | "avb2_phy_int" , |
2809 | "avb2_mdio" , |
2810 | "avb2_rgmii" , |
2811 | "avb2_txcrefclk" , |
2812 | "avb2_avtp_pps" , |
2813 | "avb2_avtp_capture" , |
2814 | "avb2_avtp_match" , |
2815 | }; |
2816 | |
2817 | static const char * const avb3_groups[] = { |
2818 | "avb3_link" , |
2819 | "avb3_magic" , |
2820 | "avb3_phy_int" , |
2821 | "avb3_mdio" , |
2822 | "avb3_rgmii" , |
2823 | "avb3_txcrefclk" , |
2824 | "avb3_avtp_pps" , |
2825 | "avb3_avtp_capture" , |
2826 | "avb3_avtp_match" , |
2827 | }; |
2828 | |
2829 | static const char * const avb4_groups[] = { |
2830 | "avb4_link" , |
2831 | "avb4_magic" , |
2832 | "avb4_phy_int" , |
2833 | "avb4_mdio" , |
2834 | "avb4_rgmii" , |
2835 | "avb4_txcrefclk" , |
2836 | "avb4_avtp_pps" , |
2837 | "avb4_avtp_capture" , |
2838 | "avb4_avtp_match" , |
2839 | }; |
2840 | |
2841 | static const char * const avb5_groups[] = { |
2842 | "avb5_link" , |
2843 | "avb5_magic" , |
2844 | "avb5_phy_int" , |
2845 | "avb5_mdio" , |
2846 | "avb5_rgmii" , |
2847 | "avb5_txcrefclk" , |
2848 | "avb5_avtp_pps" , |
2849 | "avb5_avtp_capture" , |
2850 | "avb5_avtp_match" , |
2851 | }; |
2852 | |
2853 | static const char * const canfd0_groups[] = { |
2854 | "canfd0_data" , |
2855 | }; |
2856 | |
2857 | static const char * const canfd1_groups[] = { |
2858 | "canfd1_data" , |
2859 | }; |
2860 | |
2861 | static const char * const canfd2_groups[] = { |
2862 | "canfd2_data" , |
2863 | }; |
2864 | |
2865 | static const char * const canfd3_groups[] = { |
2866 | "canfd3_data" , |
2867 | }; |
2868 | |
2869 | static const char * const canfd4_groups[] = { |
2870 | "canfd4_data" , |
2871 | }; |
2872 | |
2873 | static const char * const canfd5_groups[] = { |
2874 | "canfd5_data" , |
2875 | }; |
2876 | |
2877 | static const char * const canfd6_groups[] = { |
2878 | "canfd6_data" , |
2879 | }; |
2880 | |
2881 | static const char * const canfd7_groups[] = { |
2882 | "canfd7_data" , |
2883 | }; |
2884 | |
2885 | static const char * const can_clk_groups[] = { |
2886 | "can_clk" , |
2887 | }; |
2888 | |
2889 | static const char * const du_groups[] = { |
2890 | "du_rgb888" , |
2891 | "du_clk_out" , |
2892 | "du_sync" , |
2893 | "du_oddf" , |
2894 | }; |
2895 | |
2896 | static const char * const hscif0_groups[] = { |
2897 | "hscif0_data" , |
2898 | "hscif0_clk" , |
2899 | "hscif0_ctrl" , |
2900 | }; |
2901 | |
2902 | static const char * const hscif1_groups[] = { |
2903 | "hscif1_data" , |
2904 | "hscif1_clk" , |
2905 | "hscif1_ctrl" , |
2906 | }; |
2907 | |
2908 | static const char * const hscif2_groups[] = { |
2909 | "hscif2_data" , |
2910 | "hscif2_clk" , |
2911 | "hscif2_ctrl" , |
2912 | }; |
2913 | |
2914 | static const char * const hscif3_groups[] = { |
2915 | "hscif3_data" , |
2916 | "hscif3_clk" , |
2917 | "hscif3_ctrl" , |
2918 | }; |
2919 | |
2920 | static const char * const i2c0_groups[] = { |
2921 | "i2c0" , |
2922 | }; |
2923 | |
2924 | static const char * const i2c1_groups[] = { |
2925 | "i2c1" , |
2926 | }; |
2927 | |
2928 | static const char * const i2c2_groups[] = { |
2929 | "i2c2" , |
2930 | }; |
2931 | |
2932 | static const char * const i2c3_groups[] = { |
2933 | "i2c3" , |
2934 | }; |
2935 | |
2936 | static const char * const i2c4_groups[] = { |
2937 | "i2c4" , |
2938 | }; |
2939 | |
2940 | static const char * const i2c5_groups[] = { |
2941 | "i2c5" , |
2942 | }; |
2943 | |
2944 | static const char * const i2c6_groups[] = { |
2945 | "i2c6" , |
2946 | }; |
2947 | |
2948 | static const char * const intc_ex_groups[] = { |
2949 | "intc_ex_irq0" , |
2950 | "intc_ex_irq1" , |
2951 | "intc_ex_irq2" , |
2952 | "intc_ex_irq3" , |
2953 | "intc_ex_irq4" , |
2954 | "intc_ex_irq5" , |
2955 | }; |
2956 | |
2957 | static const char * const mmc_groups[] = { |
2958 | "mmc_data1" , |
2959 | "mmc_data4" , |
2960 | "mmc_data8" , |
2961 | "mmc_ctrl" , |
2962 | "mmc_cd" , |
2963 | "mmc_wp" , |
2964 | "mmc_ds" , |
2965 | }; |
2966 | |
2967 | static const char * const msiof0_groups[] = { |
2968 | "msiof0_clk" , |
2969 | "msiof0_sync" , |
2970 | "msiof0_ss1" , |
2971 | "msiof0_ss2" , |
2972 | "msiof0_txd" , |
2973 | "msiof0_rxd" , |
2974 | }; |
2975 | |
2976 | static const char * const msiof1_groups[] = { |
2977 | "msiof1_clk" , |
2978 | "msiof1_sync" , |
2979 | "msiof1_ss1" , |
2980 | "msiof1_ss2" , |
2981 | "msiof1_txd" , |
2982 | "msiof1_rxd" , |
2983 | }; |
2984 | |
2985 | static const char * const msiof2_groups[] = { |
2986 | "msiof2_clk" , |
2987 | "msiof2_sync" , |
2988 | "msiof2_ss1" , |
2989 | "msiof2_ss2" , |
2990 | "msiof2_txd" , |
2991 | "msiof2_rxd" , |
2992 | }; |
2993 | |
2994 | static const char * const msiof3_groups[] = { |
2995 | "msiof3_clk" , |
2996 | "msiof3_sync" , |
2997 | "msiof3_ss1" , |
2998 | "msiof3_ss2" , |
2999 | "msiof3_txd" , |
3000 | "msiof3_rxd" , |
3001 | }; |
3002 | |
3003 | static const char * const msiof4_groups[] = { |
3004 | "msiof4_clk" , |
3005 | "msiof4_sync" , |
3006 | "msiof4_ss1" , |
3007 | "msiof4_ss2" , |
3008 | "msiof4_txd" , |
3009 | "msiof4_rxd" , |
3010 | }; |
3011 | |
3012 | static const char * const msiof5_groups[] = { |
3013 | "msiof5_clk" , |
3014 | "msiof5_sync" , |
3015 | "msiof5_ss1" , |
3016 | "msiof5_ss2" , |
3017 | "msiof5_txd" , |
3018 | "msiof5_rxd" , |
3019 | }; |
3020 | |
3021 | static const char * const pwm0_groups[] = { |
3022 | "pwm0" , |
3023 | }; |
3024 | |
3025 | static const char * const pwm1_groups[] = { |
3026 | "pwm1" , |
3027 | }; |
3028 | |
3029 | static const char * const pwm2_groups[] = { |
3030 | "pwm2" , |
3031 | }; |
3032 | |
3033 | static const char * const pwm3_groups[] = { |
3034 | "pwm3" , |
3035 | }; |
3036 | |
3037 | static const char * const pwm4_groups[] = { |
3038 | "pwm4" , |
3039 | }; |
3040 | |
3041 | static const char * const qspi0_groups[] = { |
3042 | "qspi0_ctrl" , |
3043 | "qspi0_data2" , |
3044 | "qspi0_data4" , |
3045 | }; |
3046 | |
3047 | static const char * const qspi1_groups[] = { |
3048 | "qspi1_ctrl" , |
3049 | "qspi1_data2" , |
3050 | "qspi1_data4" , |
3051 | }; |
3052 | |
3053 | static const char * const scif0_groups[] = { |
3054 | "scif0_data" , |
3055 | "scif0_clk" , |
3056 | "scif0_ctrl" , |
3057 | }; |
3058 | |
3059 | static const char * const scif1_groups[] = { |
3060 | "scif1_data_a" , |
3061 | "scif1_data_b" , |
3062 | "scif1_clk" , |
3063 | "scif1_ctrl" , |
3064 | }; |
3065 | |
3066 | static const char * const scif3_groups[] = { |
3067 | "scif3_data" , |
3068 | "scif3_clk" , |
3069 | "scif3_ctrl" , |
3070 | }; |
3071 | |
3072 | static const char * const scif4_groups[] = { |
3073 | "scif4_data" , |
3074 | "scif4_clk" , |
3075 | "scif4_ctrl" , |
3076 | }; |
3077 | |
3078 | static const char * const scif_clk_groups[] = { |
3079 | "scif_clk" , |
3080 | }; |
3081 | |
3082 | static const char * const tmu_groups[] = { |
3083 | "tmu_tclk1_a" , |
3084 | "tmu_tclk1_b" , |
3085 | "tmu_tclk2_a" , |
3086 | "tmu_tclk2_b" , |
3087 | "tmu_tclk3" , |
3088 | "tmu_tclk4" , |
3089 | }; |
3090 | |
3091 | static const char * const tpu_groups[] = { |
3092 | "tpu_to0" , |
3093 | "tpu_to1" , |
3094 | "tpu_to2" , |
3095 | "tpu_to3" , |
3096 | }; |
3097 | |
3098 | static const struct sh_pfc_function pinmux_functions[] = { |
3099 | SH_PFC_FUNCTION(avb0), |
3100 | SH_PFC_FUNCTION(avb1), |
3101 | SH_PFC_FUNCTION(avb2), |
3102 | SH_PFC_FUNCTION(avb3), |
3103 | SH_PFC_FUNCTION(avb4), |
3104 | SH_PFC_FUNCTION(avb5), |
3105 | |
3106 | SH_PFC_FUNCTION(canfd0), |
3107 | SH_PFC_FUNCTION(canfd1), |
3108 | SH_PFC_FUNCTION(canfd2), |
3109 | SH_PFC_FUNCTION(canfd3), |
3110 | SH_PFC_FUNCTION(canfd4), |
3111 | SH_PFC_FUNCTION(canfd5), |
3112 | SH_PFC_FUNCTION(canfd6), |
3113 | SH_PFC_FUNCTION(canfd7), |
3114 | SH_PFC_FUNCTION(can_clk), |
3115 | |
3116 | SH_PFC_FUNCTION(du), |
3117 | |
3118 | SH_PFC_FUNCTION(hscif0), |
3119 | SH_PFC_FUNCTION(hscif1), |
3120 | SH_PFC_FUNCTION(hscif2), |
3121 | SH_PFC_FUNCTION(hscif3), |
3122 | |
3123 | SH_PFC_FUNCTION(i2c0), |
3124 | SH_PFC_FUNCTION(i2c1), |
3125 | SH_PFC_FUNCTION(i2c2), |
3126 | SH_PFC_FUNCTION(i2c3), |
3127 | SH_PFC_FUNCTION(i2c4), |
3128 | SH_PFC_FUNCTION(i2c5), |
3129 | SH_PFC_FUNCTION(i2c6), |
3130 | |
3131 | SH_PFC_FUNCTION(intc_ex), |
3132 | |
3133 | SH_PFC_FUNCTION(mmc), |
3134 | |
3135 | SH_PFC_FUNCTION(msiof0), |
3136 | SH_PFC_FUNCTION(msiof1), |
3137 | SH_PFC_FUNCTION(msiof2), |
3138 | SH_PFC_FUNCTION(msiof3), |
3139 | SH_PFC_FUNCTION(msiof4), |
3140 | SH_PFC_FUNCTION(msiof5), |
3141 | |
3142 | SH_PFC_FUNCTION(pwm0), |
3143 | SH_PFC_FUNCTION(pwm1), |
3144 | SH_PFC_FUNCTION(pwm2), |
3145 | SH_PFC_FUNCTION(pwm3), |
3146 | SH_PFC_FUNCTION(pwm4), |
3147 | |
3148 | SH_PFC_FUNCTION(qspi0), |
3149 | SH_PFC_FUNCTION(qspi1), |
3150 | |
3151 | SH_PFC_FUNCTION(scif0), |
3152 | SH_PFC_FUNCTION(scif1), |
3153 | SH_PFC_FUNCTION(scif3), |
3154 | SH_PFC_FUNCTION(scif4), |
3155 | SH_PFC_FUNCTION(scif_clk), |
3156 | |
3157 | SH_PFC_FUNCTION(tmu), |
3158 | |
3159 | SH_PFC_FUNCTION(tpu), |
3160 | }; |
3161 | |
3162 | static const struct pinmux_cfg_reg pinmux_config_regs[] = { |
3163 | #define F_(x, y) FN_##y |
3164 | #define FM(x) FN_##x |
3165 | { PINMUX_CFG_REG("GPSR0" , 0xe6058040, 32, 1, GROUP( |
3166 | 0, 0, |
3167 | 0, 0, |
3168 | 0, 0, |
3169 | 0, 0, |
3170 | GP_0_27_FN, GPSR0_27, |
3171 | GP_0_26_FN, GPSR0_26, |
3172 | GP_0_25_FN, GPSR0_25, |
3173 | GP_0_24_FN, GPSR0_24, |
3174 | GP_0_23_FN, GPSR0_23, |
3175 | GP_0_22_FN, GPSR0_22, |
3176 | GP_0_21_FN, GPSR0_21, |
3177 | GP_0_20_FN, GPSR0_20, |
3178 | GP_0_19_FN, GPSR0_19, |
3179 | GP_0_18_FN, GPSR0_18, |
3180 | GP_0_17_FN, GPSR0_17, |
3181 | GP_0_16_FN, GPSR0_16, |
3182 | GP_0_15_FN, GPSR0_15, |
3183 | GP_0_14_FN, GPSR0_14, |
3184 | GP_0_13_FN, GPSR0_13, |
3185 | GP_0_12_FN, GPSR0_12, |
3186 | GP_0_11_FN, GPSR0_11, |
3187 | GP_0_10_FN, GPSR0_10, |
3188 | GP_0_9_FN, GPSR0_9, |
3189 | GP_0_8_FN, GPSR0_8, |
3190 | GP_0_7_FN, GPSR0_7, |
3191 | GP_0_6_FN, GPSR0_6, |
3192 | GP_0_5_FN, GPSR0_5, |
3193 | GP_0_4_FN, GPSR0_4, |
3194 | GP_0_3_FN, GPSR0_3, |
3195 | GP_0_2_FN, GPSR0_2, |
3196 | GP_0_1_FN, GPSR0_1, |
3197 | GP_0_0_FN, GPSR0_0, )) |
3198 | }, |
3199 | { PINMUX_CFG_REG("GPSR1" , 0xe6050040, 32, 1, GROUP( |
3200 | 0, 0, |
3201 | GP_1_30_FN, GPSR1_30, |
3202 | GP_1_29_FN, GPSR1_29, |
3203 | GP_1_28_FN, GPSR1_28, |
3204 | GP_1_27_FN, GPSR1_27, |
3205 | GP_1_26_FN, GPSR1_26, |
3206 | GP_1_25_FN, GPSR1_25, |
3207 | GP_1_24_FN, GPSR1_24, |
3208 | GP_1_23_FN, GPSR1_23, |
3209 | GP_1_22_FN, GPSR1_22, |
3210 | GP_1_21_FN, GPSR1_21, |
3211 | GP_1_20_FN, GPSR1_20, |
3212 | GP_1_19_FN, GPSR1_19, |
3213 | GP_1_18_FN, GPSR1_18, |
3214 | GP_1_17_FN, GPSR1_17, |
3215 | GP_1_16_FN, GPSR1_16, |
3216 | GP_1_15_FN, GPSR1_15, |
3217 | GP_1_14_FN, GPSR1_14, |
3218 | GP_1_13_FN, GPSR1_13, |
3219 | GP_1_12_FN, GPSR1_12, |
3220 | GP_1_11_FN, GPSR1_11, |
3221 | GP_1_10_FN, GPSR1_10, |
3222 | GP_1_9_FN, GPSR1_9, |
3223 | GP_1_8_FN, GPSR1_8, |
3224 | GP_1_7_FN, GPSR1_7, |
3225 | GP_1_6_FN, GPSR1_6, |
3226 | GP_1_5_FN, GPSR1_5, |
3227 | GP_1_4_FN, GPSR1_4, |
3228 | GP_1_3_FN, GPSR1_3, |
3229 | GP_1_2_FN, GPSR1_2, |
3230 | GP_1_1_FN, GPSR1_1, |
3231 | GP_1_0_FN, GPSR1_0, )) |
3232 | }, |
3233 | { PINMUX_CFG_REG_VAR("GPSR2" , 0xe6050840, 32, |
3234 | GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
3235 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), |
3236 | GROUP( |
3237 | /* GP2_31_25 RESERVED */ |
3238 | GP_2_24_FN, GPSR2_24, |
3239 | GP_2_23_FN, GPSR2_23, |
3240 | GP_2_22_FN, GPSR2_22, |
3241 | GP_2_21_FN, GPSR2_21, |
3242 | GP_2_20_FN, GPSR2_20, |
3243 | GP_2_19_FN, GPSR2_19, |
3244 | GP_2_18_FN, GPSR2_18, |
3245 | GP_2_17_FN, GPSR2_17, |
3246 | GP_2_16_FN, GPSR2_16, |
3247 | GP_2_15_FN, GPSR2_15, |
3248 | GP_2_14_FN, GPSR2_14, |
3249 | GP_2_13_FN, GPSR2_13, |
3250 | GP_2_12_FN, GPSR2_12, |
3251 | GP_2_11_FN, GPSR2_11, |
3252 | GP_2_10_FN, GPSR2_10, |
3253 | GP_2_9_FN, GPSR2_9, |
3254 | GP_2_8_FN, GPSR2_8, |
3255 | GP_2_7_FN, GPSR2_7, |
3256 | GP_2_6_FN, GPSR2_6, |
3257 | GP_2_5_FN, GPSR2_5, |
3258 | GP_2_4_FN, GPSR2_4, |
3259 | GP_2_3_FN, GPSR2_3, |
3260 | GP_2_2_FN, GPSR2_2, |
3261 | GP_2_1_FN, GPSR2_1, |
3262 | GP_2_0_FN, GPSR2_0, )) |
3263 | }, |
3264 | { PINMUX_CFG_REG_VAR("GPSR3" , 0xe6058840, 32, |
3265 | GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
3266 | 1, 1, 1, 1, 1, 1), |
3267 | GROUP( |
3268 | /* GP3_31_17 RESERVED */ |
3269 | GP_3_16_FN, GPSR3_16, |
3270 | GP_3_15_FN, GPSR3_15, |
3271 | GP_3_14_FN, GPSR3_14, |
3272 | GP_3_13_FN, GPSR3_13, |
3273 | GP_3_12_FN, GPSR3_12, |
3274 | GP_3_11_FN, GPSR3_11, |
3275 | GP_3_10_FN, GPSR3_10, |
3276 | GP_3_9_FN, GPSR3_9, |
3277 | GP_3_8_FN, GPSR3_8, |
3278 | GP_3_7_FN, GPSR3_7, |
3279 | GP_3_6_FN, GPSR3_6, |
3280 | GP_3_5_FN, GPSR3_5, |
3281 | GP_3_4_FN, GPSR3_4, |
3282 | GP_3_3_FN, GPSR3_3, |
3283 | GP_3_2_FN, GPSR3_2, |
3284 | GP_3_1_FN, GPSR3_1, |
3285 | GP_3_0_FN, GPSR3_0, )) |
3286 | }, |
3287 | { PINMUX_CFG_REG("GPSR4" , 0xe6060040, 32, 1, GROUP( |
3288 | 0, 0, |
3289 | 0, 0, |
3290 | 0, 0, |
3291 | 0, 0, |
3292 | 0, 0, |
3293 | GP_4_26_FN, GPSR4_26, |
3294 | GP_4_25_FN, GPSR4_25, |
3295 | GP_4_24_FN, GPSR4_24, |
3296 | GP_4_23_FN, GPSR4_23, |
3297 | GP_4_22_FN, GPSR4_22, |
3298 | GP_4_21_FN, GPSR4_21, |
3299 | GP_4_20_FN, GPSR4_20, |
3300 | GP_4_19_FN, GPSR4_19, |
3301 | GP_4_18_FN, GPSR4_18, |
3302 | GP_4_17_FN, GPSR4_17, |
3303 | GP_4_16_FN, GPSR4_16, |
3304 | GP_4_15_FN, GPSR4_15, |
3305 | GP_4_14_FN, GPSR4_14, |
3306 | GP_4_13_FN, GPSR4_13, |
3307 | GP_4_12_FN, GPSR4_12, |
3308 | GP_4_11_FN, GPSR4_11, |
3309 | GP_4_10_FN, GPSR4_10, |
3310 | GP_4_9_FN, GPSR4_9, |
3311 | GP_4_8_FN, GPSR4_8, |
3312 | GP_4_7_FN, GPSR4_7, |
3313 | GP_4_6_FN, GPSR4_6, |
3314 | GP_4_5_FN, GPSR4_5, |
3315 | GP_4_4_FN, GPSR4_4, |
3316 | GP_4_3_FN, GPSR4_3, |
3317 | GP_4_2_FN, GPSR4_2, |
3318 | GP_4_1_FN, GPSR4_1, |
3319 | GP_4_0_FN, GPSR4_0, )) |
3320 | }, |
3321 | { PINMUX_CFG_REG_VAR("GPSR5" , 0xe6060840, 32, |
3322 | GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
3323 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), |
3324 | GROUP( |
3325 | /* GP5_31_21 RESERVED */ |
3326 | GP_5_20_FN, GPSR5_20, |
3327 | GP_5_19_FN, GPSR5_19, |
3328 | GP_5_18_FN, GPSR5_18, |
3329 | GP_5_17_FN, GPSR5_17, |
3330 | GP_5_16_FN, GPSR5_16, |
3331 | GP_5_15_FN, GPSR5_15, |
3332 | GP_5_14_FN, GPSR5_14, |
3333 | GP_5_13_FN, GPSR5_13, |
3334 | GP_5_12_FN, GPSR5_12, |
3335 | GP_5_11_FN, GPSR5_11, |
3336 | GP_5_10_FN, GPSR5_10, |
3337 | GP_5_9_FN, GPSR5_9, |
3338 | GP_5_8_FN, GPSR5_8, |
3339 | GP_5_7_FN, GPSR5_7, |
3340 | GP_5_6_FN, GPSR5_6, |
3341 | GP_5_5_FN, GPSR5_5, |
3342 | GP_5_4_FN, GPSR5_4, |
3343 | GP_5_3_FN, GPSR5_3, |
3344 | GP_5_2_FN, GPSR5_2, |
3345 | GP_5_1_FN, GPSR5_1, |
3346 | GP_5_0_FN, GPSR5_0, )) |
3347 | }, |
3348 | { PINMUX_CFG_REG_VAR("GPSR6" , 0xe6068040, 32, |
3349 | GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
3350 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), |
3351 | GROUP( |
3352 | /* GP6_31_21 RESERVED */ |
3353 | GP_6_20_FN, GPSR6_20, |
3354 | GP_6_19_FN, GPSR6_19, |
3355 | GP_6_18_FN, GPSR6_18, |
3356 | GP_6_17_FN, GPSR6_17, |
3357 | GP_6_16_FN, GPSR6_16, |
3358 | GP_6_15_FN, GPSR6_15, |
3359 | GP_6_14_FN, GPSR6_14, |
3360 | GP_6_13_FN, GPSR6_13, |
3361 | GP_6_12_FN, GPSR6_12, |
3362 | GP_6_11_FN, GPSR6_11, |
3363 | GP_6_10_FN, GPSR6_10, |
3364 | GP_6_9_FN, GPSR6_9, |
3365 | GP_6_8_FN, GPSR6_8, |
3366 | GP_6_7_FN, GPSR6_7, |
3367 | GP_6_6_FN, GPSR6_6, |
3368 | GP_6_5_FN, GPSR6_5, |
3369 | GP_6_4_FN, GPSR6_4, |
3370 | GP_6_3_FN, GPSR6_3, |
3371 | GP_6_2_FN, GPSR6_2, |
3372 | GP_6_1_FN, GPSR6_1, |
3373 | GP_6_0_FN, GPSR6_0, )) |
3374 | }, |
3375 | { PINMUX_CFG_REG_VAR("GPSR7" , 0xe6068840, 32, |
3376 | GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
3377 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), |
3378 | GROUP( |
3379 | /* GP7_31_21 RESERVED */ |
3380 | GP_7_20_FN, GPSR7_20, |
3381 | GP_7_19_FN, GPSR7_19, |
3382 | GP_7_18_FN, GPSR7_18, |
3383 | GP_7_17_FN, GPSR7_17, |
3384 | GP_7_16_FN, GPSR7_16, |
3385 | GP_7_15_FN, GPSR7_15, |
3386 | GP_7_14_FN, GPSR7_14, |
3387 | GP_7_13_FN, GPSR7_13, |
3388 | GP_7_12_FN, GPSR7_12, |
3389 | GP_7_11_FN, GPSR7_11, |
3390 | GP_7_10_FN, GPSR7_10, |
3391 | GP_7_9_FN, GPSR7_9, |
3392 | GP_7_8_FN, GPSR7_8, |
3393 | GP_7_7_FN, GPSR7_7, |
3394 | GP_7_6_FN, GPSR7_6, |
3395 | GP_7_5_FN, GPSR7_5, |
3396 | GP_7_4_FN, GPSR7_4, |
3397 | GP_7_3_FN, GPSR7_3, |
3398 | GP_7_2_FN, GPSR7_2, |
3399 | GP_7_1_FN, GPSR7_1, |
3400 | GP_7_0_FN, GPSR7_0, )) |
3401 | }, |
3402 | { PINMUX_CFG_REG_VAR("GPSR8" , 0xe6069040, 32, |
3403 | GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
3404 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), |
3405 | GROUP( |
3406 | /* GP8_31_21 RESERVED */ |
3407 | GP_8_20_FN, GPSR8_20, |
3408 | GP_8_19_FN, GPSR8_19, |
3409 | GP_8_18_FN, GPSR8_18, |
3410 | GP_8_17_FN, GPSR8_17, |
3411 | GP_8_16_FN, GPSR8_16, |
3412 | GP_8_15_FN, GPSR8_15, |
3413 | GP_8_14_FN, GPSR8_14, |
3414 | GP_8_13_FN, GPSR8_13, |
3415 | GP_8_12_FN, GPSR8_12, |
3416 | GP_8_11_FN, GPSR8_11, |
3417 | GP_8_10_FN, GPSR8_10, |
3418 | GP_8_9_FN, GPSR8_9, |
3419 | GP_8_8_FN, GPSR8_8, |
3420 | GP_8_7_FN, GPSR8_7, |
3421 | GP_8_6_FN, GPSR8_6, |
3422 | GP_8_5_FN, GPSR8_5, |
3423 | GP_8_4_FN, GPSR8_4, |
3424 | GP_8_3_FN, GPSR8_3, |
3425 | GP_8_2_FN, GPSR8_2, |
3426 | GP_8_1_FN, GPSR8_1, |
3427 | GP_8_0_FN, GPSR8_0, )) |
3428 | }, |
3429 | { PINMUX_CFG_REG_VAR("GPSR9" , 0xe6069840, 32, |
3430 | GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
3431 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), |
3432 | GROUP( |
3433 | /* GP9_31_21 RESERVED */ |
3434 | GP_9_20_FN, GPSR9_20, |
3435 | GP_9_19_FN, GPSR9_19, |
3436 | GP_9_18_FN, GPSR9_18, |
3437 | GP_9_17_FN, GPSR9_17, |
3438 | GP_9_16_FN, GPSR9_16, |
3439 | GP_9_15_FN, GPSR9_15, |
3440 | GP_9_14_FN, GPSR9_14, |
3441 | GP_9_13_FN, GPSR9_13, |
3442 | GP_9_12_FN, GPSR9_12, |
3443 | GP_9_11_FN, GPSR9_11, |
3444 | GP_9_10_FN, GPSR9_10, |
3445 | GP_9_9_FN, GPSR9_9, |
3446 | GP_9_8_FN, GPSR9_8, |
3447 | GP_9_7_FN, GPSR9_7, |
3448 | GP_9_6_FN, GPSR9_6, |
3449 | GP_9_5_FN, GPSR9_5, |
3450 | GP_9_4_FN, GPSR9_4, |
3451 | GP_9_3_FN, GPSR9_3, |
3452 | GP_9_2_FN, GPSR9_2, |
3453 | GP_9_1_FN, GPSR9_1, |
3454 | GP_9_0_FN, GPSR9_0, )) |
3455 | }, |
3456 | #undef F_ |
3457 | #undef FM |
3458 | |
3459 | #define F_(x, y) x, |
3460 | #define FM(x) FN_##x, |
3461 | { PINMUX_CFG_REG("IP0SR1" , 0xe6050060, 32, 4, GROUP( |
3462 | IP0SR1_31_28 |
3463 | IP0SR1_27_24 |
3464 | IP0SR1_23_20 |
3465 | IP0SR1_19_16 |
3466 | IP0SR1_15_12 |
3467 | IP0SR1_11_8 |
3468 | IP0SR1_7_4 |
3469 | IP0SR1_3_0)) |
3470 | }, |
3471 | { PINMUX_CFG_REG("IP1SR1" , 0xe6050064, 32, 4, GROUP( |
3472 | IP1SR1_31_28 |
3473 | IP1SR1_27_24 |
3474 | IP1SR1_23_20 |
3475 | IP1SR1_19_16 |
3476 | IP1SR1_15_12 |
3477 | IP1SR1_11_8 |
3478 | IP1SR1_7_4 |
3479 | IP1SR1_3_0)) |
3480 | }, |
3481 | { PINMUX_CFG_REG("IP2SR1" , 0xe6050068, 32, 4, GROUP( |
3482 | IP2SR1_31_28 |
3483 | IP2SR1_27_24 |
3484 | IP2SR1_23_20 |
3485 | IP2SR1_19_16 |
3486 | IP2SR1_15_12 |
3487 | IP2SR1_11_8 |
3488 | IP2SR1_7_4 |
3489 | IP2SR1_3_0)) |
3490 | }, |
3491 | { PINMUX_CFG_REG_VAR("IP3SR1" , 0xe605006c, 32, |
3492 | GROUP(-4, 4, 4, 4, 4, 4, 4, 4), |
3493 | GROUP( |
3494 | /* IP3SR1_31_28 RESERVED */ |
3495 | IP3SR1_27_24 |
3496 | IP3SR1_23_20 |
3497 | IP3SR1_19_16 |
3498 | IP3SR1_15_12 |
3499 | IP3SR1_11_8 |
3500 | IP3SR1_7_4 |
3501 | IP3SR1_3_0)) |
3502 | }, |
3503 | { PINMUX_CFG_REG("IP0SR2" , 0xe6050860, 32, 4, GROUP( |
3504 | IP0SR2_31_28 |
3505 | IP0SR2_27_24 |
3506 | IP0SR2_23_20 |
3507 | IP0SR2_19_16 |
3508 | IP0SR2_15_12 |
3509 | IP0SR2_11_8 |
3510 | IP0SR2_7_4 |
3511 | IP0SR2_3_0)) |
3512 | }, |
3513 | { PINMUX_CFG_REG("IP1SR2" , 0xe6050864, 32, 4, GROUP( |
3514 | IP1SR2_31_28 |
3515 | IP1SR2_27_24 |
3516 | IP1SR2_23_20 |
3517 | IP1SR2_19_16 |
3518 | IP1SR2_15_12 |
3519 | IP1SR2_11_8 |
3520 | IP1SR2_7_4 |
3521 | IP1SR2_3_0)) |
3522 | }, |
3523 | { PINMUX_CFG_REG("IP2SR2" , 0xe6050868, 32, 4, GROUP( |
3524 | IP2SR2_31_28 |
3525 | IP2SR2_27_24 |
3526 | IP2SR2_23_20 |
3527 | IP2SR2_19_16 |
3528 | IP2SR2_15_12 |
3529 | IP2SR2_11_8 |
3530 | IP2SR2_7_4 |
3531 | IP2SR2_3_0)) |
3532 | }, |
3533 | { PINMUX_CFG_REG_VAR("IP0SR3" , 0xe6058860, 32, |
3534 | GROUP(4, 4, 4, -8, 4, 4, -4), |
3535 | GROUP( |
3536 | IP0SR3_31_28 |
3537 | IP0SR3_27_24 |
3538 | IP0SR3_23_20 |
3539 | /* IP0SR3_19_12 RESERVED */ |
3540 | IP0SR3_11_8 |
3541 | IP0SR3_7_4 |
3542 | /* IP0SR3_3_0 RESERVED */ )) |
3543 | }, |
3544 | { PINMUX_CFG_REG_VAR("IP1SR3" , 0xe6058864, 32, |
3545 | GROUP(-8, 4, 4, 4, 4, 4, 4), |
3546 | GROUP( |
3547 | /* IP1SR3_31_24 RESERVED */ |
3548 | IP1SR3_23_20 |
3549 | IP1SR3_19_16 |
3550 | IP1SR3_15_12 |
3551 | IP1SR3_11_8 |
3552 | IP1SR3_7_4 |
3553 | IP1SR3_3_0)) |
3554 | }, |
3555 | { PINMUX_CFG_REG("IP0SR4" , 0xe6060060, 32, 4, GROUP( |
3556 | IP0SR4_31_28 |
3557 | IP0SR4_27_24 |
3558 | IP0SR4_23_20 |
3559 | IP0SR4_19_16 |
3560 | IP0SR4_15_12 |
3561 | IP0SR4_11_8 |
3562 | IP0SR4_7_4 |
3563 | IP0SR4_3_0)) |
3564 | }, |
3565 | { PINMUX_CFG_REG("IP1SR4" , 0xe6060064, 32, 4, GROUP( |
3566 | IP1SR4_31_28 |
3567 | IP1SR4_27_24 |
3568 | IP1SR4_23_20 |
3569 | IP1SR4_19_16 |
3570 | IP1SR4_15_12 |
3571 | IP1SR4_11_8 |
3572 | IP1SR4_7_4 |
3573 | IP1SR4_3_0)) |
3574 | }, |
3575 | { PINMUX_CFG_REG_VAR("IP2SR4" , 0xe6060068, 32, |
3576 | GROUP(-12, 4, 4, 4, 4, -4), |
3577 | GROUP( |
3578 | /* IP2SR4_31_20 RESERVED */ |
3579 | IP2SR4_19_16 |
3580 | IP2SR4_15_12 |
3581 | IP2SR4_11_8 |
3582 | IP2SR4_7_4 |
3583 | /* IP2SR4_3_0 RESERVED */ )) |
3584 | }, |
3585 | { PINMUX_CFG_REG("IP0SR5" , 0xe6060860, 32, 4, GROUP( |
3586 | IP0SR5_31_28 |
3587 | IP0SR5_27_24 |
3588 | IP0SR5_23_20 |
3589 | IP0SR5_19_16 |
3590 | IP0SR5_15_12 |
3591 | IP0SR5_11_8 |
3592 | IP0SR5_7_4 |
3593 | IP0SR5_3_0)) |
3594 | }, |
3595 | { PINMUX_CFG_REG("IP1SR5" , 0xe6060864, 32, 4, GROUP( |
3596 | IP1SR5_31_28 |
3597 | IP1SR5_27_24 |
3598 | IP1SR5_23_20 |
3599 | IP1SR5_19_16 |
3600 | IP1SR5_15_12 |
3601 | IP1SR5_11_8 |
3602 | IP1SR5_7_4 |
3603 | IP1SR5_3_0)) |
3604 | }, |
3605 | { PINMUX_CFG_REG_VAR("IP2SR5" , 0xe6060868, 32, |
3606 | GROUP(-12, 4, 4, 4, 4, -4), |
3607 | GROUP( |
3608 | /* IP2SR5_31_20 RESERVED */ |
3609 | IP2SR5_19_16 |
3610 | IP2SR5_15_12 |
3611 | IP2SR5_11_8 |
3612 | IP2SR5_7_4 |
3613 | /* IP2SR5_3_0 RESERVED */ )) |
3614 | }, |
3615 | #undef F_ |
3616 | #undef FM |
3617 | |
3618 | #define F_(x, y) x, |
3619 | #define FM(x) FN_##x, |
3620 | { PINMUX_CFG_REG_VAR("MOD_SEL2" , 0xe6050900, 32, |
3621 | GROUP(-16, 2, 2, 2, 2, 2, 2, 2, -2), |
3622 | GROUP( |
3623 | /* RESERVED 31-16 */ |
3624 | MOD_SEL2_15_14 |
3625 | MOD_SEL2_13_12 |
3626 | MOD_SEL2_11_10 |
3627 | MOD_SEL2_9_8 |
3628 | MOD_SEL2_7_6 |
3629 | MOD_SEL2_5_4 |
3630 | MOD_SEL2_3_2 |
3631 | /* RESERVED 1-0 */ )) |
3632 | }, |
3633 | { /* sentinel */ } |
3634 | }; |
3635 | |
3636 | static const struct pinmux_drive_reg pinmux_drive_regs[] = { |
3637 | { PINMUX_DRIVE_REG("DRV0CTRL0" , 0xe6058080) { |
3638 | { RCAR_GP_PIN(0, 7), 28, 2 }, /* QSPI1_MOSI_IO0 */ |
3639 | { RCAR_GP_PIN(0, 6), 24, 2 }, /* QSPI1_SPCLK */ |
3640 | { RCAR_GP_PIN(0, 5), 20, 2 }, /* QSPI0_SSL */ |
3641 | { RCAR_GP_PIN(0, 4), 16, 2 }, /* QSPI0_IO3 */ |
3642 | { RCAR_GP_PIN(0, 3), 12, 2 }, /* QSPI0_IO2 */ |
3643 | { RCAR_GP_PIN(0, 2), 8, 2 }, /* QSPI0_MISO_IO1 */ |
3644 | { RCAR_GP_PIN(0, 1), 4, 2 }, /* QSPI0_MOSI_IO0 */ |
3645 | { RCAR_GP_PIN(0, 0), 0, 2 }, /* QSPI0_SPCLK */ |
3646 | } }, |
3647 | { PINMUX_DRIVE_REG("DRV1CTRL0" , 0xe6058084) { |
3648 | { RCAR_GP_PIN(0, 15), 28, 3 }, /* SD_WP */ |
3649 | { RCAR_GP_PIN(0, 14), 24, 2 }, /* RPC_INT_N */ |
3650 | { RCAR_GP_PIN(0, 13), 20, 2 }, /* RPC_WP_N */ |
3651 | { RCAR_GP_PIN(0, 12), 16, 2 }, /* RPC_RESET_N */ |
3652 | { RCAR_GP_PIN(0, 11), 12, 2 }, /* QSPI1_SSL */ |
3653 | { RCAR_GP_PIN(0, 10), 8, 2 }, /* QSPI1_IO3 */ |
3654 | { RCAR_GP_PIN(0, 9), 4, 2 }, /* QSPI1_IO2 */ |
3655 | { RCAR_GP_PIN(0, 8), 0, 2 }, /* QSPI1_MISO_IO1 */ |
3656 | } }, |
3657 | { PINMUX_DRIVE_REG("DRV2CTRL0" , 0xe6058088) { |
3658 | { RCAR_GP_PIN(0, 23), 28, 3 }, /* MMC_SD_CLK */ |
3659 | { RCAR_GP_PIN(0, 22), 24, 3 }, /* MMC_SD_D3 */ |
3660 | { RCAR_GP_PIN(0, 21), 20, 3 }, /* MMC_SD_D2 */ |
3661 | { RCAR_GP_PIN(0, 20), 16, 3 }, /* MMC_SD_D1 */ |
3662 | { RCAR_GP_PIN(0, 19), 12, 3 }, /* MMC_SD_D0 */ |
3663 | { RCAR_GP_PIN(0, 18), 8, 3 }, /* MMC_SD_CMD */ |
3664 | { RCAR_GP_PIN(0, 17), 4, 3 }, /* MMC_DS */ |
3665 | { RCAR_GP_PIN(0, 16), 0, 3 }, /* SD_CD */ |
3666 | } }, |
3667 | { PINMUX_DRIVE_REG("DRV3CTRL0" , 0xe605808c) { |
3668 | { RCAR_GP_PIN(0, 27), 12, 3 }, /* MMC_D7 */ |
3669 | { RCAR_GP_PIN(0, 26), 8, 3 }, /* MMC_D6 */ |
3670 | { RCAR_GP_PIN(0, 25), 4, 3 }, /* MMC_D5 */ |
3671 | { RCAR_GP_PIN(0, 24), 0, 3 }, /* MMC_D4 */ |
3672 | } }, |
3673 | { PINMUX_DRIVE_REG("DRV0CTRL1" , 0xe6050080) { |
3674 | { RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_TXD */ |
3675 | { RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_RXD */ |
3676 | { RCAR_GP_PIN(1, 5), 20, 3 }, /* HTX0 */ |
3677 | { RCAR_GP_PIN(1, 4), 16, 3 }, /* HCTS0_N */ |
3678 | { RCAR_GP_PIN(1, 3), 12, 3 }, /* HRTS0_N */ |
3679 | { RCAR_GP_PIN(1, 2), 8, 3 }, /* HSCK0 */ |
3680 | { RCAR_GP_PIN(1, 1), 4, 3 }, /* HRX0 */ |
3681 | { RCAR_GP_PIN(1, 0), 0, 3 }, /* SCIF_CLK */ |
3682 | } }, |
3683 | { PINMUX_DRIVE_REG("DRV1CTRL1" , 0xe6050084) { |
3684 | { RCAR_GP_PIN(1, 15), 28, 3 }, /* MSIOF1_SYNC */ |
3685 | { RCAR_GP_PIN(1, 14), 24, 3 }, /* MSIOF1_SCK */ |
3686 | { RCAR_GP_PIN(1, 13), 20, 3 }, /* MSIOF1_TXD */ |
3687 | { RCAR_GP_PIN(1, 12), 16, 3 }, /* MSIOF1_RXD */ |
3688 | { RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_SS2 */ |
3689 | { RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SS1 */ |
3690 | { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_SYNC */ |
3691 | { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SCK */ |
3692 | } }, |
3693 | { PINMUX_DRIVE_REG("DRV2CTRL1" , 0xe6050088) { |
3694 | { RCAR_GP_PIN(1, 23), 28, 3 }, /* MSIOF2_SS2 */ |
3695 | { RCAR_GP_PIN(1, 22), 24, 3 }, /* MSIOF2_SS1 */ |
3696 | { RCAR_GP_PIN(1, 21), 20, 3 }, /* MSIOF2_SYNC */ |
3697 | { RCAR_GP_PIN(1, 20), 16, 3 }, /* MSIOF2_SCK */ |
3698 | { RCAR_GP_PIN(1, 19), 12, 3 }, /* MSIOF2_TXD */ |
3699 | { RCAR_GP_PIN(1, 18), 8, 3 }, /* MSIOF2_RXD */ |
3700 | { RCAR_GP_PIN(1, 17), 4, 3 }, /* MSIOF1_SS2 */ |
3701 | { RCAR_GP_PIN(1, 16), 0, 3 }, /* MSIOF1_SS1 */ |
3702 | } }, |
3703 | { PINMUX_DRIVE_REG("DRV3CTRL1" , 0xe605008c) { |
3704 | { RCAR_GP_PIN(1, 30), 24, 3 }, /* GP1_30 */ |
3705 | { RCAR_GP_PIN(1, 29), 20, 3 }, /* GP1_29 */ |
3706 | { RCAR_GP_PIN(1, 28), 16, 3 }, /* GP1_28 */ |
3707 | { RCAR_GP_PIN(1, 27), 12, 3 }, /* IRQ3 */ |
3708 | { RCAR_GP_PIN(1, 26), 8, 3 }, /* IRQ2 */ |
3709 | { RCAR_GP_PIN(1, 25), 4, 3 }, /* IRQ1 */ |
3710 | { RCAR_GP_PIN(1, 24), 0, 3 }, /* IRQ0 */ |
3711 | } }, |
3712 | { PINMUX_DRIVE_REG("DRV0CTRL2" , 0xe6050880) { |
3713 | { RCAR_GP_PIN(2, 7), 28, 3 }, /* GP2_07 */ |
3714 | { RCAR_GP_PIN(2, 6), 24, 3 }, /* GP2_06 */ |
3715 | { RCAR_GP_PIN(2, 5), 20, 3 }, /* GP2_05 */ |
3716 | { RCAR_GP_PIN(2, 4), 16, 3 }, /* GP2_04 */ |
3717 | { RCAR_GP_PIN(2, 3), 12, 3 }, /* GP2_03 */ |
3718 | { RCAR_GP_PIN(2, 2), 8, 3 }, /* GP2_02 */ |
3719 | { RCAR_GP_PIN(2, 1), 4, 2 }, /* IPC_CLKOUT */ |
3720 | { RCAR_GP_PIN(2, 0), 0, 2 }, /* IPC_CLKIN */ |
3721 | } }, |
3722 | { PINMUX_DRIVE_REG("DRV1CTRL2" , 0xe6050884) { |
3723 | { RCAR_GP_PIN(2, 15), 28, 3 }, /* GP2_15 */ |
3724 | { RCAR_GP_PIN(2, 14), 24, 3 }, /* GP2_14 */ |
3725 | { RCAR_GP_PIN(2, 13), 20, 3 }, /* GP2_13 */ |
3726 | { RCAR_GP_PIN(2, 12), 16, 3 }, /* GP2_12 */ |
3727 | { RCAR_GP_PIN(2, 11), 12, 3 }, /* GP2_11 */ |
3728 | { RCAR_GP_PIN(2, 10), 8, 3 }, /* GP2_10 */ |
3729 | { RCAR_GP_PIN(2, 9), 4, 3 }, /* GP2_9 */ |
3730 | { RCAR_GP_PIN(2, 8), 0, 3 }, /* GP2_8 */ |
3731 | } }, |
3732 | { PINMUX_DRIVE_REG("DRV2CTRL2" , 0xe6050888) { |
3733 | { RCAR_GP_PIN(2, 23), 28, 3 }, /* TCLK1_A */ |
3734 | { RCAR_GP_PIN(2, 22), 24, 3 }, /* TPU0TO1 */ |
3735 | { RCAR_GP_PIN(2, 21), 20, 3 }, /* TPU0TO0 */ |
3736 | { RCAR_GP_PIN(2, 20), 16, 3 }, /* CLK_EXTFXR */ |
3737 | { RCAR_GP_PIN(2, 19), 12, 3 }, /* RXDB_EXTFXR */ |
3738 | { RCAR_GP_PIN(2, 18), 8, 3 }, /* FXR_TXDB */ |
3739 | { RCAR_GP_PIN(2, 17), 4, 3 }, /* RXDA_EXTFXR_A */ |
3740 | { RCAR_GP_PIN(2, 16), 0, 3 }, /* FXR_TXDA_A */ |
3741 | } }, |
3742 | { PINMUX_DRIVE_REG("DRV3CTRL2" , 0xe605088c) { |
3743 | { RCAR_GP_PIN(2, 24), 0, 3 }, /* TCLK2_A */ |
3744 | } }, |
3745 | { PINMUX_DRIVE_REG("DRV0CTRL3" , 0xe6058880) { |
3746 | { RCAR_GP_PIN(3, 7), 28, 3 }, /* CANFD3_TX */ |
3747 | { RCAR_GP_PIN(3, 6), 24, 3 }, /* CANFD2_RX */ |
3748 | { RCAR_GP_PIN(3, 5), 20, 3 }, /* CANFD2_TX */ |
3749 | { RCAR_GP_PIN(3, 4), 16, 3 }, /* CANFD1_RX */ |
3750 | { RCAR_GP_PIN(3, 3), 12, 3 }, /* CANFD1_TX */ |
3751 | { RCAR_GP_PIN(3, 2), 8, 3 }, /* CANFD0_RX */ |
3752 | { RCAR_GP_PIN(3, 1), 4, 2 }, /* CANFD0_TX */ |
3753 | { RCAR_GP_PIN(3, 0), 0, 2 }, /* CAN_CLK */ |
3754 | } }, |
3755 | { PINMUX_DRIVE_REG("DRV1CTRL3" , 0xe6058884) { |
3756 | { RCAR_GP_PIN(3, 15), 28, 3 }, /* CANFD7_TX */ |
3757 | { RCAR_GP_PIN(3, 14), 24, 3 }, /* CANFD6_RX */ |
3758 | { RCAR_GP_PIN(3, 13), 20, 3 }, /* CANFD6_TX */ |
3759 | { RCAR_GP_PIN(3, 12), 16, 3 }, /* CANFD5_RX */ |
3760 | { RCAR_GP_PIN(3, 11), 12, 3 }, /* CANFD5_TX */ |
3761 | { RCAR_GP_PIN(3, 10), 8, 3 }, /* CANFD4_RX */ |
3762 | { RCAR_GP_PIN(3, 9), 4, 3 }, /* CANFD4_TX */ |
3763 | { RCAR_GP_PIN(3, 8), 0, 3 }, /* CANFD3_RX */ |
3764 | } }, |
3765 | { PINMUX_DRIVE_REG("DRV2CTRL3" , 0xe6058888) { |
3766 | { RCAR_GP_PIN(3, 16), 0, 3 }, /* CANFD7_RX */ |
3767 | } }, |
3768 | { PINMUX_DRIVE_REG("DRV0CTRL4" , 0xe6060080) { |
3769 | { RCAR_GP_PIN(4, 7), 28, 3 }, /* AVB0_TXC */ |
3770 | { RCAR_GP_PIN(4, 6), 24, 3 }, /* AVB0_TX_CTL */ |
3771 | { RCAR_GP_PIN(4, 5), 20, 3 }, /* AVB0_RD3 */ |
3772 | { RCAR_GP_PIN(4, 4), 16, 3 }, /* AVB0_RD2 */ |
3773 | { RCAR_GP_PIN(4, 3), 12, 3 }, /* AVB0_RD1 */ |
3774 | { RCAR_GP_PIN(4, 2), 8, 3 }, /* AVB0_RD0 */ |
3775 | { RCAR_GP_PIN(4, 1), 4, 3 }, /* AVB0_RXC */ |
3776 | { RCAR_GP_PIN(4, 0), 0, 3 }, /* AVB0_RX_CTL */ |
3777 | } }, |
3778 | { PINMUX_DRIVE_REG("DRV1CTRL4" , 0xe6060084) { |
3779 | { RCAR_GP_PIN(4, 15), 28, 3 }, /* AVB0_MAGIC */ |
3780 | { RCAR_GP_PIN(4, 14), 24, 3 }, /* AVB0_MDC */ |
3781 | { RCAR_GP_PIN(4, 13), 20, 3 }, /* AVB0_MDIO */ |
3782 | { RCAR_GP_PIN(4, 12), 16, 3 }, /* AVB0_TXCREFCLK */ |
3783 | { RCAR_GP_PIN(4, 11), 12, 3 }, /* AVB0_TD3 */ |
3784 | { RCAR_GP_PIN(4, 10), 8, 3 }, /* AVB0_TD2 */ |
3785 | { RCAR_GP_PIN(4, 9), 4, 3 }, /* AVB0_TD1*/ |
3786 | { RCAR_GP_PIN(4, 8), 0, 3 }, /* AVB0_TD0 */ |
3787 | } }, |
3788 | { PINMUX_DRIVE_REG("DRV2CTRL4" , 0xe6060088) { |
3789 | { RCAR_GP_PIN(4, 23), 28, 3 }, /* PCIE2_CLKREQ_N */ |
3790 | { RCAR_GP_PIN(4, 22), 24, 3 }, /* PCIE1_CLKREQ_N */ |
3791 | { RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */ |
3792 | { RCAR_GP_PIN(4, 20), 16, 3 }, /* AVB0_AVTP_PPS */ |
3793 | { RCAR_GP_PIN(4, 19), 12, 3 }, /* AVB0_AVTP_CAPTURE */ |
3794 | { RCAR_GP_PIN(4, 18), 8, 3 }, /* AVB0_AVTP_MATCH */ |
3795 | { RCAR_GP_PIN(4, 17), 4, 3 }, /* AVB0_LINK */ |
3796 | { RCAR_GP_PIN(4, 16), 0, 3 }, /* AVB0_PHY_INT */ |
3797 | } }, |
3798 | { PINMUX_DRIVE_REG("DRV3CTRL4" , 0xe606008c) { |
3799 | { RCAR_GP_PIN(4, 26), 8, 3 }, /* AVS1 */ |
3800 | { RCAR_GP_PIN(4, 25), 4, 3 }, /* AVS0 */ |
3801 | { RCAR_GP_PIN(4, 24), 0, 3 }, /* PCIE3_CLKREQ_N */ |
3802 | } }, |
3803 | { PINMUX_DRIVE_REG("DRV0CTRL5" , 0xe6060880) { |
3804 | { RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB1_TXC */ |
3805 | { RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB1_TX_CTL */ |
3806 | { RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB1_RD3 */ |
3807 | { RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB1_RD2 */ |
3808 | { RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB1_RD1 */ |
3809 | { RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB1_RD0 */ |
3810 | { RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB1_RXC */ |
3811 | { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB1_RX_CTL */ |
3812 | } }, |
3813 | { PINMUX_DRIVE_REG("DRV1CTRL5" , 0xe6060884) { |
3814 | { RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB1_MAGIC */ |
3815 | { RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB1_MDC */ |
3816 | { RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB1_MDIO */ |
3817 | { RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB1_TXCREFCLK */ |
3818 | { RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB1_TD3 */ |
3819 | { RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB1_TD2 */ |
3820 | { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB1_TD1*/ |
3821 | { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB1_TD0 */ |
3822 | } }, |
3823 | { PINMUX_DRIVE_REG("DRV2CTRL5" , 0xe6060888) { |
3824 | { RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB1_AVTP_PPS */ |
3825 | { RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB1_AVTP_CAPTURE */ |
3826 | { RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB1_AVTP_MATCH */ |
3827 | { RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB1_LINK */ |
3828 | { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB1_PHY_INT */ |
3829 | } }, |
3830 | { PINMUX_DRIVE_REG("DRV0CTRL6" , 0xe6068080) { |
3831 | { RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB2_TXC */ |
3832 | { RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB2_TX_CTL */ |
3833 | { RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB2_RD3 */ |
3834 | { RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB2_RD2 */ |
3835 | { RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB2_RD1 */ |
3836 | { RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB2_RD0 */ |
3837 | { RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB2_RXC */ |
3838 | { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB2_RX_CTL */ |
3839 | } }, |
3840 | { PINMUX_DRIVE_REG("DRV1CTRL6" , 0xe6068084) { |
3841 | { RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB2_MAGIC */ |
3842 | { RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB2_MDC */ |
3843 | { RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB2_MDIO */ |
3844 | { RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB2_TXCREFCLK */ |
3845 | { RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB2_TD3 */ |
3846 | { RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB2_TD2 */ |
3847 | { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB2_TD1*/ |
3848 | { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB2_TD0 */ |
3849 | } }, |
3850 | { PINMUX_DRIVE_REG("DRV2CTRL6" , 0xe6068088) { |
3851 | { RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB2_AVTP_PPS */ |
3852 | { RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB2_AVTP_CAPTURE */ |
3853 | { RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB2_AVTP_MATCH */ |
3854 | { RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB2_LINK */ |
3855 | { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB2_PHY_INT */ |
3856 | } }, |
3857 | { PINMUX_DRIVE_REG("DRV0CTRL7" , 0xe6068880) { |
3858 | { RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB3_TXC */ |
3859 | { RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB3_TX_CTL */ |
3860 | { RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB3_RD3 */ |
3861 | { RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB3_RD2 */ |
3862 | { RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB3_RD1 */ |
3863 | { RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB3_RD0 */ |
3864 | { RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB3_RXC */ |
3865 | { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB3_RX_CTL */ |
3866 | } }, |
3867 | { PINMUX_DRIVE_REG("DRV1CTRL7" , 0xe6068884) { |
3868 | { RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB3_MAGIC */ |
3869 | { RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB3_MDC */ |
3870 | { RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB3_MDIO */ |
3871 | { RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB3_TXCREFCLK */ |
3872 | { RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB3_TD3 */ |
3873 | { RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB3_TD2 */ |
3874 | { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB3_TD1*/ |
3875 | { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB3_TD0 */ |
3876 | } }, |
3877 | { PINMUX_DRIVE_REG("DRV2CTRL7" , 0xe6068888) { |
3878 | { RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB3_AVTP_PPS */ |
3879 | { RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB3_AVTP_CAPTURE */ |
3880 | { RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB3_AVTP_MATCH */ |
3881 | { RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB3_LINK */ |
3882 | { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB3_PHY_INT */ |
3883 | } }, |
3884 | { PINMUX_DRIVE_REG("DRV0CTRL8" , 0xe6069080) { |
3885 | { RCAR_GP_PIN(8, 7), 28, 3 }, /* AVB4_TXC */ |
3886 | { RCAR_GP_PIN(8, 6), 24, 3 }, /* AVB4_TX_CTL */ |
3887 | { RCAR_GP_PIN(8, 5), 20, 3 }, /* AVB4_RD3 */ |
3888 | { RCAR_GP_PIN(8, 4), 16, 3 }, /* AVB4_RD2 */ |
3889 | { RCAR_GP_PIN(8, 3), 12, 3 }, /* AVB4_RD1 */ |
3890 | { RCAR_GP_PIN(8, 2), 8, 3 }, /* AVB4_RD0 */ |
3891 | { RCAR_GP_PIN(8, 1), 4, 3 }, /* AVB4_RXC */ |
3892 | { RCAR_GP_PIN(8, 0), 0, 3 }, /* AVB4_RX_CTL */ |
3893 | } }, |
3894 | { PINMUX_DRIVE_REG("DRV1CTRL8" , 0xe6069084) { |
3895 | { RCAR_GP_PIN(8, 15), 28, 3 }, /* AVB4_MAGIC */ |
3896 | { RCAR_GP_PIN(8, 14), 24, 3 }, /* AVB4_MDC */ |
3897 | { RCAR_GP_PIN(8, 13), 20, 3 }, /* AVB4_MDIO */ |
3898 | { RCAR_GP_PIN(8, 12), 16, 3 }, /* AVB4_TXCREFCLK */ |
3899 | { RCAR_GP_PIN(8, 11), 12, 3 }, /* AVB4_TD3 */ |
3900 | { RCAR_GP_PIN(8, 10), 8, 3 }, /* AVB4_TD2 */ |
3901 | { RCAR_GP_PIN(8, 9), 4, 3 }, /* AVB4_TD1*/ |
3902 | { RCAR_GP_PIN(8, 8), 0, 3 }, /* AVB4_TD0 */ |
3903 | } }, |
3904 | { PINMUX_DRIVE_REG("DRV2CTRL8" , 0xe6069088) { |
3905 | { RCAR_GP_PIN(8, 20), 16, 3 }, /* AVB4_AVTP_PPS */ |
3906 | { RCAR_GP_PIN(8, 19), 12, 3 }, /* AVB4_AVTP_CAPTURE */ |
3907 | { RCAR_GP_PIN(8, 18), 8, 3 }, /* AVB4_AVTP_MATCH */ |
3908 | { RCAR_GP_PIN(8, 17), 4, 3 }, /* AVB4_LINK */ |
3909 | { RCAR_GP_PIN(8, 16), 0, 3 }, /* AVB4_PHY_INT */ |
3910 | } }, |
3911 | { PINMUX_DRIVE_REG("DRV0CTRL9" , 0xe6069880) { |
3912 | { RCAR_GP_PIN(9, 7), 28, 3 }, /* AVB5_TXC */ |
3913 | { RCAR_GP_PIN(9, 6), 24, 3 }, /* AVB5_TX_CTL */ |
3914 | { RCAR_GP_PIN(9, 5), 20, 3 }, /* AVB5_RD3 */ |
3915 | { RCAR_GP_PIN(9, 4), 16, 3 }, /* AVB5_RD2 */ |
3916 | { RCAR_GP_PIN(9, 3), 12, 3 }, /* AVB5_RD1 */ |
3917 | { RCAR_GP_PIN(9, 2), 8, 3 }, /* AVB5_RD0 */ |
3918 | { RCAR_GP_PIN(9, 1), 4, 3 }, /* AVB5_RXC */ |
3919 | { RCAR_GP_PIN(9, 0), 0, 3 }, /* AVB5_RX_CTL */ |
3920 | } }, |
3921 | { PINMUX_DRIVE_REG("DRV1CTRL9" , 0xe6069884) { |
3922 | { RCAR_GP_PIN(9, 15), 28, 3 }, /* AVB5_MAGIC */ |
3923 | { RCAR_GP_PIN(9, 14), 24, 3 }, /* AVB5_MDC */ |
3924 | { RCAR_GP_PIN(9, 13), 20, 3 }, /* AVB5_MDIO */ |
3925 | { RCAR_GP_PIN(9, 12), 16, 3 }, /* AVB5_TXCREFCLK */ |
3926 | { RCAR_GP_PIN(9, 11), 12, 3 }, /* AVB5_TD3 */ |
3927 | { RCAR_GP_PIN(9, 10), 8, 3 }, /* AVB5_TD2 */ |
3928 | { RCAR_GP_PIN(9, 9), 4, 3 }, /* AVB5_TD1*/ |
3929 | { RCAR_GP_PIN(9, 8), 0, 3 }, /* AVB5_TD0 */ |
3930 | } }, |
3931 | { PINMUX_DRIVE_REG("DRV2CTRL9" , 0xe6069888) { |
3932 | { RCAR_GP_PIN(9, 20), 16, 3 }, /* AVB5_AVTP_PPS */ |
3933 | { RCAR_GP_PIN(9, 19), 12, 3 }, /* AVB5_AVTP_CAPTURE */ |
3934 | { RCAR_GP_PIN(9, 18), 8, 3 }, /* AVB5_AVTP_MATCH */ |
3935 | { RCAR_GP_PIN(9, 17), 4, 3 }, /* AVB5_LINK */ |
3936 | { RCAR_GP_PIN(9, 16), 0, 3 }, /* AVB5_PHY_INT */ |
3937 | } }, |
3938 | { /* sentinel */ } |
3939 | }; |
3940 | |
3941 | enum ioctrl_regs { |
3942 | POC0, |
3943 | POC1, |
3944 | POC2, |
3945 | POC4, |
3946 | POC5, |
3947 | POC6, |
3948 | POC7, |
3949 | POC8, |
3950 | POC9, |
3951 | TD1SEL0, |
3952 | }; |
3953 | |
3954 | static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { |
3955 | [POC0] = { 0xe60580a0, }, |
3956 | [POC1] = { .reg: 0xe60500a0, }, |
3957 | [POC2] = { .reg: 0xe60508a0, }, |
3958 | [POC4] = { .reg: 0xe60600a0, }, |
3959 | [POC5] = { .reg: 0xe60608a0, }, |
3960 | [POC6] = { .reg: 0xe60680a0, }, |
3961 | [POC7] = { .reg: 0xe60688a0, }, |
3962 | [POC8] = { .reg: 0xe60690a0, }, |
3963 | [POC9] = { .reg: 0xe60698a0, }, |
3964 | [TD1SEL0] = { .reg: 0xe6058124, }, |
3965 | { /* sentinel */ } |
3966 | }; |
3967 | |
3968 | static int r8a779a0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) |
3969 | { |
3970 | int bit = pin & 0x1f; |
3971 | |
3972 | *pocctrl = pinmux_ioctrl_regs[POC0].reg; |
3973 | if (pin >= RCAR_GP_PIN(0, 15) && pin <= RCAR_GP_PIN(0, 27)) |
3974 | return bit; |
3975 | |
3976 | *pocctrl = pinmux_ioctrl_regs[POC1].reg; |
3977 | if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 30)) |
3978 | return bit; |
3979 | |
3980 | *pocctrl = pinmux_ioctrl_regs[POC2].reg; |
3981 | if (pin >= RCAR_GP_PIN(2, 2) && pin <= RCAR_GP_PIN(2, 15)) |
3982 | return bit; |
3983 | |
3984 | *pocctrl = pinmux_ioctrl_regs[POC4].reg; |
3985 | if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) |
3986 | return bit; |
3987 | |
3988 | *pocctrl = pinmux_ioctrl_regs[POC5].reg; |
3989 | if (pin >= RCAR_GP_PIN(5, 0) && pin <= RCAR_GP_PIN(5, 17)) |
3990 | return bit; |
3991 | |
3992 | *pocctrl = pinmux_ioctrl_regs[POC6].reg; |
3993 | if (pin >= RCAR_GP_PIN(6, 0) && pin <= RCAR_GP_PIN(6, 17)) |
3994 | return bit; |
3995 | |
3996 | *pocctrl = pinmux_ioctrl_regs[POC7].reg; |
3997 | if (pin >= RCAR_GP_PIN(7, 0) && pin <= RCAR_GP_PIN(7, 17)) |
3998 | return bit; |
3999 | |
4000 | *pocctrl = pinmux_ioctrl_regs[POC8].reg; |
4001 | if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 17)) |
4002 | return bit; |
4003 | |
4004 | *pocctrl = pinmux_ioctrl_regs[POC9].reg; |
4005 | if (pin >= RCAR_GP_PIN(9, 0) && pin <= RCAR_GP_PIN(9, 17)) |
4006 | return bit; |
4007 | |
4008 | return -EINVAL; |
4009 | } |
4010 | |
4011 | static const struct pinmux_bias_reg pinmux_bias_regs[] = { |
4012 | { PINMUX_BIAS_REG("PUEN0" , 0xe60580c0, "PUD0" , 0xe60580e0) { |
4013 | [ 0] = RCAR_GP_PIN(0, 0), /* QSPI0_SPCLK */ |
4014 | [ 1] = RCAR_GP_PIN(0, 1), /* QSPI0_MOSI_IO0 */ |
4015 | [ 2] = RCAR_GP_PIN(0, 2), /* QSPI0_MISO_IO1 */ |
4016 | [ 3] = RCAR_GP_PIN(0, 3), /* QSPI0_IO2 */ |
4017 | [ 4] = RCAR_GP_PIN(0, 4), /* QSPI0_IO3 */ |
4018 | [ 5] = RCAR_GP_PIN(0, 5), /* QSPI0_SSL */ |
4019 | [ 6] = RCAR_GP_PIN(0, 6), /* QSPI1_SPCLK */ |
4020 | [ 7] = RCAR_GP_PIN(0, 7), /* QSPI1_MOSI_IO0 */ |
4021 | [ 8] = RCAR_GP_PIN(0, 8), /* QSPI1_MISO_IO1 */ |
4022 | [ 9] = RCAR_GP_PIN(0, 9), /* QSPI1_IO2 */ |
4023 | [10] = RCAR_GP_PIN(0, 10), /* QSPI1_IO3 */ |
4024 | [11] = RCAR_GP_PIN(0, 11), /* QSPI1_SSL */ |
4025 | [12] = RCAR_GP_PIN(0, 12), /* RPC_RESET_N */ |
4026 | [13] = RCAR_GP_PIN(0, 13), /* RPC_WP_N */ |
4027 | [14] = RCAR_GP_PIN(0, 14), /* RPC_INT_N */ |
4028 | [15] = RCAR_GP_PIN(0, 15), /* SD_WP */ |
4029 | [16] = RCAR_GP_PIN(0, 16), /* SD_CD */ |
4030 | [17] = RCAR_GP_PIN(0, 17), /* MMC_DS */ |
4031 | [18] = RCAR_GP_PIN(0, 18), /* MMC_SD_CMD */ |
4032 | [19] = RCAR_GP_PIN(0, 19), /* MMC_SD_D0 */ |
4033 | [20] = RCAR_GP_PIN(0, 20), /* MMC_SD_D1 */ |
4034 | [21] = RCAR_GP_PIN(0, 21), /* MMC_SD_D2 */ |
4035 | [22] = RCAR_GP_PIN(0, 22), /* MMC_SD_D3 */ |
4036 | [23] = RCAR_GP_PIN(0, 23), /* MMC_SD_CLK */ |
4037 | [24] = RCAR_GP_PIN(0, 24), /* MMC_D4 */ |
4038 | [25] = RCAR_GP_PIN(0, 25), /* MMC_D5 */ |
4039 | [26] = RCAR_GP_PIN(0, 26), /* MMC_D6 */ |
4040 | [27] = RCAR_GP_PIN(0, 27), /* MMC_D7 */ |
4041 | [28] = SH_PFC_PIN_NONE, |
4042 | [29] = SH_PFC_PIN_NONE, |
4043 | [30] = SH_PFC_PIN_NONE, |
4044 | [31] = SH_PFC_PIN_NONE, |
4045 | } }, |
4046 | { PINMUX_BIAS_REG("PUEN1" , 0xe60500c0, "PUD1" , 0xe60500e0) { |
4047 | [ 0] = RCAR_GP_PIN(1, 0), /* SCIF_CLK */ |
4048 | [ 1] = RCAR_GP_PIN(1, 1), /* HRX0 */ |
4049 | [ 2] = RCAR_GP_PIN(1, 2), /* HSCK0 */ |
4050 | [ 3] = RCAR_GP_PIN(1, 3), /* HRTS0_N */ |
4051 | [ 4] = RCAR_GP_PIN(1, 4), /* HCTS0_N */ |
4052 | [ 5] = RCAR_GP_PIN(1, 5), /* HTX0 */ |
4053 | [ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_RXD */ |
4054 | [ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_TXD */ |
4055 | [ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SCK */ |
4056 | [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_SYNC */ |
4057 | [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SS1 */ |
4058 | [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_SS2 */ |
4059 | [12] = RCAR_GP_PIN(1, 12), /* MSIOF1_RXD */ |
4060 | [13] = RCAR_GP_PIN(1, 13), /* MSIOF1_TXD */ |
4061 | [14] = RCAR_GP_PIN(1, 14), /* MSIOF1_SCK */ |
4062 | [15] = RCAR_GP_PIN(1, 15), /* MSIOF1_SYNC */ |
4063 | [16] = RCAR_GP_PIN(1, 16), /* MSIOF1_SS1 */ |
4064 | [17] = RCAR_GP_PIN(1, 17), /* MSIOF1_SS2 */ |
4065 | [18] = RCAR_GP_PIN(1, 18), /* MSIOF2_RXD */ |
4066 | [19] = RCAR_GP_PIN(1, 19), /* MSIOF2_TXD */ |
4067 | [20] = RCAR_GP_PIN(1, 20), /* MSIOF2_SCK */ |
4068 | [21] = RCAR_GP_PIN(1, 21), /* MSIOF2_SYNC */ |
4069 | [22] = RCAR_GP_PIN(1, 22), /* MSIOF2_SS1 */ |
4070 | [23] = RCAR_GP_PIN(1, 23), /* MSIOF2_SS2 */ |
4071 | [24] = RCAR_GP_PIN(1, 24), /* IRQ0 */ |
4072 | [25] = RCAR_GP_PIN(1, 25), /* IRQ1 */ |
4073 | [26] = RCAR_GP_PIN(1, 26), /* IRQ2 */ |
4074 | [27] = RCAR_GP_PIN(1, 27), /* IRQ3 */ |
4075 | [28] = RCAR_GP_PIN(1, 28), /* GP1_28 */ |
4076 | [29] = RCAR_GP_PIN(1, 29), /* GP1_29 */ |
4077 | [30] = RCAR_GP_PIN(1, 30), /* GP1_30 */ |
4078 | [31] = SH_PFC_PIN_NONE, |
4079 | } }, |
4080 | { PINMUX_BIAS_REG("PUEN2" , 0xe60508c0, "PUD2" , 0xe60508e0) { |
4081 | [ 0] = RCAR_GP_PIN(2, 0), /* IPC_CLKIN */ |
4082 | [ 1] = RCAR_GP_PIN(2, 1), /* IPC_CLKOUT */ |
4083 | [ 2] = RCAR_GP_PIN(2, 2), /* GP2_02 */ |
4084 | [ 3] = RCAR_GP_PIN(2, 3), /* GP2_03 */ |
4085 | [ 4] = RCAR_GP_PIN(2, 4), /* GP2_04 */ |
4086 | [ 5] = RCAR_GP_PIN(2, 5), /* GP2_05 */ |
4087 | [ 6] = RCAR_GP_PIN(2, 6), /* GP2_06 */ |
4088 | [ 7] = RCAR_GP_PIN(2, 7), /* GP2_07 */ |
4089 | [ 8] = RCAR_GP_PIN(2, 8), /* GP2_08 */ |
4090 | [ 9] = RCAR_GP_PIN(2, 9), /* GP2_09 */ |
4091 | [10] = RCAR_GP_PIN(2, 10), /* GP2_10 */ |
4092 | [11] = RCAR_GP_PIN(2, 11), /* GP2_11 */ |
4093 | [12] = RCAR_GP_PIN(2, 12), /* GP2_12 */ |
4094 | [13] = RCAR_GP_PIN(2, 13), /* GP2_13 */ |
4095 | [14] = RCAR_GP_PIN(2, 14), /* GP2_14 */ |
4096 | [15] = RCAR_GP_PIN(2, 15), /* GP2_15 */ |
4097 | [16] = RCAR_GP_PIN(2, 16), /* FXR_TXDA_A */ |
4098 | [17] = RCAR_GP_PIN(2, 17), /* RXDA_EXTFXR_A */ |
4099 | [18] = RCAR_GP_PIN(2, 18), /* FXR_TXDB */ |
4100 | [19] = RCAR_GP_PIN(2, 19), /* RXDB_EXTFXR */ |
4101 | [20] = RCAR_GP_PIN(2, 20), /* CLK_EXTFXR */ |
4102 | [21] = RCAR_GP_PIN(2, 21), /* TPU0TO0 */ |
4103 | [22] = RCAR_GP_PIN(2, 22), /* TPU0TO1 */ |
4104 | [23] = RCAR_GP_PIN(2, 23), /* TCLK1_A */ |
4105 | [24] = RCAR_GP_PIN(2, 24), /* TCLK2_A */ |
4106 | [25] = SH_PFC_PIN_NONE, |
4107 | [26] = SH_PFC_PIN_NONE, |
4108 | [27] = SH_PFC_PIN_NONE, |
4109 | [28] = SH_PFC_PIN_NONE, |
4110 | [29] = SH_PFC_PIN_NONE, |
4111 | [30] = SH_PFC_PIN_NONE, |
4112 | [31] = SH_PFC_PIN_NONE, |
4113 | } }, |
4114 | { PINMUX_BIAS_REG("PUEN3" , 0xe60588c0, "PUD3" , 0xe60588e0) { |
4115 | [ 0] = RCAR_GP_PIN(3, 0), /* CAN_CLK */ |
4116 | [ 1] = RCAR_GP_PIN(3, 1), /* CANFD0_TX */ |
4117 | [ 2] = RCAR_GP_PIN(3, 2), /* CANFD0_RX */ |
4118 | [ 3] = RCAR_GP_PIN(3, 3), /* CANFD1_TX */ |
4119 | [ 4] = RCAR_GP_PIN(3, 4), /* CANFD1_RX */ |
4120 | [ 5] = RCAR_GP_PIN(3, 5), /* CANFD2_TX */ |
4121 | [ 6] = RCAR_GP_PIN(3, 6), /* CANFD2_RX */ |
4122 | [ 7] = RCAR_GP_PIN(3, 7), /* CANFD3_TX */ |
4123 | [ 8] = RCAR_GP_PIN(3, 8), /* CANFD3_RX */ |
4124 | [ 9] = RCAR_GP_PIN(3, 9), /* CANFD4_TX */ |
4125 | [10] = RCAR_GP_PIN(3, 10), /* CANFD4_RX */ |
4126 | [11] = RCAR_GP_PIN(3, 11), /* CANFD5_TX */ |
4127 | [12] = RCAR_GP_PIN(3, 12), /* CANFD5_RX */ |
4128 | [13] = RCAR_GP_PIN(3, 13), /* CANFD6_TX */ |
4129 | [14] = RCAR_GP_PIN(3, 14), /* CANFD6_RX */ |
4130 | [15] = RCAR_GP_PIN(3, 15), /* CANFD7_TX */ |
4131 | [16] = RCAR_GP_PIN(3, 16), /* CANFD7_RX */ |
4132 | [17] = SH_PFC_PIN_NONE, |
4133 | [18] = SH_PFC_PIN_NONE, |
4134 | [19] = SH_PFC_PIN_NONE, |
4135 | [20] = SH_PFC_PIN_NONE, |
4136 | [21] = SH_PFC_PIN_NONE, |
4137 | [22] = SH_PFC_PIN_NONE, |
4138 | [23] = SH_PFC_PIN_NONE, |
4139 | [24] = SH_PFC_PIN_NONE, |
4140 | [25] = SH_PFC_PIN_NONE, |
4141 | [26] = SH_PFC_PIN_NONE, |
4142 | [27] = SH_PFC_PIN_NONE, |
4143 | [28] = SH_PFC_PIN_NONE, |
4144 | [29] = SH_PFC_PIN_NONE, |
4145 | [30] = SH_PFC_PIN_NONE, |
4146 | [31] = SH_PFC_PIN_NONE, |
4147 | } }, |
4148 | { PINMUX_BIAS_REG("PUEN4" , 0xe60600c0, "PUD4" , 0xe60600e0) { |
4149 | [ 0] = RCAR_GP_PIN(4, 0), /* AVB0_RX_CTL */ |
4150 | [ 1] = RCAR_GP_PIN(4, 1), /* AVB0_RXC */ |
4151 | [ 2] = RCAR_GP_PIN(4, 2), /* AVB0_RD0 */ |
4152 | [ 3] = RCAR_GP_PIN(4, 3), /* AVB0_RD1 */ |
4153 | [ 4] = RCAR_GP_PIN(4, 4), /* AVB0_RD2 */ |
4154 | [ 5] = RCAR_GP_PIN(4, 5), /* AVB0_RD3 */ |
4155 | [ 6] = RCAR_GP_PIN(4, 6), /* AVB0_TX_CTL */ |
4156 | [ 7] = RCAR_GP_PIN(4, 7), /* AVB0_TXC */ |
4157 | [ 8] = RCAR_GP_PIN(4, 8), /* AVB0_TD0 */ |
4158 | [ 9] = RCAR_GP_PIN(4, 9), /* AVB0_TD1 */ |
4159 | [10] = RCAR_GP_PIN(4, 10), /* AVB0_TD2 */ |
4160 | [11] = RCAR_GP_PIN(4, 11), /* AVB0_TD3 */ |
4161 | [12] = RCAR_GP_PIN(4, 12), /* AVB0_TXREFCLK */ |
4162 | [13] = RCAR_GP_PIN(4, 13), /* AVB0_MDIO */ |
4163 | [14] = RCAR_GP_PIN(4, 14), /* AVB0_MDC */ |
4164 | [15] = RCAR_GP_PIN(4, 15), /* AVB0_MAGIC */ |
4165 | [16] = RCAR_GP_PIN(4, 16), /* AVB0_PHY_INT */ |
4166 | [17] = RCAR_GP_PIN(4, 17), /* AVB0_LINK */ |
4167 | [18] = RCAR_GP_PIN(4, 18), /* AVB0_AVTP_MATCH */ |
4168 | [19] = RCAR_GP_PIN(4, 19), /* AVB0_AVTP_CAPTURE */ |
4169 | [20] = RCAR_GP_PIN(4, 20), /* AVB0_AVTP_PPS */ |
4170 | [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */ |
4171 | [22] = RCAR_GP_PIN(4, 22), /* PCIE1_CLKREQ_N */ |
4172 | [23] = RCAR_GP_PIN(4, 23), /* PCIE2_CLKREQ_N */ |
4173 | [24] = RCAR_GP_PIN(4, 24), /* PCIE3_CLKREQ_N */ |
4174 | [25] = RCAR_GP_PIN(4, 25), /* AVS0 */ |
4175 | [26] = RCAR_GP_PIN(4, 26), /* AVS1 */ |
4176 | [27] = SH_PFC_PIN_NONE, |
4177 | [28] = SH_PFC_PIN_NONE, |
4178 | [29] = SH_PFC_PIN_NONE, |
4179 | [30] = SH_PFC_PIN_NONE, |
4180 | [31] = SH_PFC_PIN_NONE, |
4181 | } }, |
4182 | { PINMUX_BIAS_REG("PUEN5" , 0xe60608c0, "PUD5" , 0xe60608e0) { |
4183 | [ 0] = RCAR_GP_PIN(5, 0), /* AVB1_RX_CTL */ |
4184 | [ 1] = RCAR_GP_PIN(5, 1), /* AVB1_RXC */ |
4185 | [ 2] = RCAR_GP_PIN(5, 2), /* AVB1_RD0 */ |
4186 | [ 3] = RCAR_GP_PIN(5, 3), /* AVB1_RD1 */ |
4187 | [ 4] = RCAR_GP_PIN(5, 4), /* AVB1_RD2 */ |
4188 | [ 5] = RCAR_GP_PIN(5, 5), /* AVB1_RD3 */ |
4189 | [ 6] = RCAR_GP_PIN(5, 6), /* AVB1_TX_CTL */ |
4190 | [ 7] = RCAR_GP_PIN(5, 7), /* AVB1_TXC */ |
4191 | [ 8] = RCAR_GP_PIN(5, 8), /* AVB1_TD0 */ |
4192 | [ 9] = RCAR_GP_PIN(5, 9), /* AVB1_TD1 */ |
4193 | [10] = RCAR_GP_PIN(5, 10), /* AVB1_TD2 */ |
4194 | [11] = RCAR_GP_PIN(5, 11), /* AVB1_TD3 */ |
4195 | [12] = RCAR_GP_PIN(5, 12), /* AVB1_TXCREFCLK */ |
4196 | [13] = RCAR_GP_PIN(5, 13), /* AVB1_MDIO */ |
4197 | [14] = RCAR_GP_PIN(5, 14), /* AVB1_MDC */ |
4198 | [15] = RCAR_GP_PIN(5, 15), /* AVB1_MAGIC */ |
4199 | [16] = RCAR_GP_PIN(5, 16), /* AVB1_PHY_INT */ |
4200 | [17] = RCAR_GP_PIN(5, 17), /* AVB1_LINK */ |
4201 | [18] = RCAR_GP_PIN(5, 18), /* AVB1_AVTP_MATCH */ |
4202 | [19] = RCAR_GP_PIN(5, 19), /* AVB1_AVTP_CAPTURE */ |
4203 | [20] = RCAR_GP_PIN(5, 20), /* AVB1_AVTP_PPS */ |
4204 | [21] = SH_PFC_PIN_NONE, |
4205 | [22] = SH_PFC_PIN_NONE, |
4206 | [23] = SH_PFC_PIN_NONE, |
4207 | [24] = SH_PFC_PIN_NONE, |
4208 | [25] = SH_PFC_PIN_NONE, |
4209 | [26] = SH_PFC_PIN_NONE, |
4210 | [27] = SH_PFC_PIN_NONE, |
4211 | [28] = SH_PFC_PIN_NONE, |
4212 | [29] = SH_PFC_PIN_NONE, |
4213 | [30] = SH_PFC_PIN_NONE, |
4214 | [31] = SH_PFC_PIN_NONE, |
4215 | } }, |
4216 | { PINMUX_BIAS_REG("PUEN6" , 0xe60680c0, "PUD6" , 0xe60680e0) { |
4217 | [ 0] = RCAR_GP_PIN(6, 0), /* AVB2_RX_CTL */ |
4218 | [ 1] = RCAR_GP_PIN(6, 1), /* AVB2_RXC */ |
4219 | [ 2] = RCAR_GP_PIN(6, 2), /* AVB2_RD0 */ |
4220 | [ 3] = RCAR_GP_PIN(6, 3), /* AVB2_RD1 */ |
4221 | [ 4] = RCAR_GP_PIN(6, 4), /* AVB2_RD2 */ |
4222 | [ 5] = RCAR_GP_PIN(6, 5), /* AVB2_RD3 */ |
4223 | [ 6] = RCAR_GP_PIN(6, 6), /* AVB2_TX_CTL */ |
4224 | [ 7] = RCAR_GP_PIN(6, 7), /* AVB2_TXC */ |
4225 | [ 8] = RCAR_GP_PIN(6, 8), /* AVB2_TD0 */ |
4226 | [ 9] = RCAR_GP_PIN(6, 9), /* AVB2_TD1 */ |
4227 | [10] = RCAR_GP_PIN(6, 10), /* AVB2_TD2 */ |
4228 | [11] = RCAR_GP_PIN(6, 11), /* AVB2_TD3 */ |
4229 | [12] = RCAR_GP_PIN(6, 12), /* AVB2_TXCREFCLK */ |
4230 | [13] = RCAR_GP_PIN(6, 13), /* AVB2_MDIO */ |
4231 | [14] = RCAR_GP_PIN(6, 14), /* AVB2_MDC */ |
4232 | [15] = RCAR_GP_PIN(6, 15), /* AVB2_MAGIC */ |
4233 | [16] = RCAR_GP_PIN(6, 16), /* AVB2_PHY_INT */ |
4234 | [17] = RCAR_GP_PIN(6, 17), /* AVB2_LINK */ |
4235 | [18] = RCAR_GP_PIN(6, 18), /* AVB2_AVTP_MATCH */ |
4236 | [19] = RCAR_GP_PIN(6, 19), /* AVB2_AVTP_CAPTURE */ |
4237 | [20] = RCAR_GP_PIN(6, 20), /* AVB2_AVTP_PPS */ |
4238 | [21] = SH_PFC_PIN_NONE, |
4239 | [22] = SH_PFC_PIN_NONE, |
4240 | [23] = SH_PFC_PIN_NONE, |
4241 | [24] = SH_PFC_PIN_NONE, |
4242 | [25] = SH_PFC_PIN_NONE, |
4243 | [26] = SH_PFC_PIN_NONE, |
4244 | [27] = SH_PFC_PIN_NONE, |
4245 | [28] = SH_PFC_PIN_NONE, |
4246 | [29] = SH_PFC_PIN_NONE, |
4247 | [30] = SH_PFC_PIN_NONE, |
4248 | [31] = SH_PFC_PIN_NONE, |
4249 | } }, |
4250 | { PINMUX_BIAS_REG("PUEN7" , 0xe60688c0, "PUD7" , 0xe60688e0) { |
4251 | [ 0] = RCAR_GP_PIN(7, 0), /* AVB3_RX_CTL */ |
4252 | [ 1] = RCAR_GP_PIN(7, 1), /* AVB3_RXC */ |
4253 | [ 2] = RCAR_GP_PIN(7, 2), /* AVB3_RD0 */ |
4254 | [ 3] = RCAR_GP_PIN(7, 3), /* AVB3_RD1 */ |
4255 | [ 4] = RCAR_GP_PIN(7, 4), /* AVB3_RD2 */ |
4256 | [ 5] = RCAR_GP_PIN(7, 5), /* AVB3_RD3 */ |
4257 | [ 6] = RCAR_GP_PIN(7, 6), /* AVB3_TX_CTL */ |
4258 | [ 7] = RCAR_GP_PIN(7, 7), /* AVB3_TXC */ |
4259 | [ 8] = RCAR_GP_PIN(7, 8), /* AVB3_TD0 */ |
4260 | [ 9] = RCAR_GP_PIN(7, 9), /* AVB3_TD1 */ |
4261 | [10] = RCAR_GP_PIN(7, 10), /* AVB3_TD2 */ |
4262 | [11] = RCAR_GP_PIN(7, 11), /* AVB3_TD3 */ |
4263 | [12] = RCAR_GP_PIN(7, 12), /* AVB3_TXCREFCLK */ |
4264 | [13] = RCAR_GP_PIN(7, 13), /* AVB3_MDIO */ |
4265 | [14] = RCAR_GP_PIN(7, 14), /* AVB3_MDC */ |
4266 | [15] = RCAR_GP_PIN(7, 15), /* AVB3_MAGIC */ |
4267 | [16] = RCAR_GP_PIN(7, 16), /* AVB3_PHY_INT */ |
4268 | [17] = RCAR_GP_PIN(7, 17), /* AVB3_LINK */ |
4269 | [18] = RCAR_GP_PIN(7, 18), /* AVB3_AVTP_MATCH */ |
4270 | [19] = RCAR_GP_PIN(7, 19), /* AVB3_AVTP_CAPTURE */ |
4271 | [20] = RCAR_GP_PIN(7, 20), /* AVB3_AVTP_PPS */ |
4272 | [21] = SH_PFC_PIN_NONE, |
4273 | [22] = SH_PFC_PIN_NONE, |
4274 | [23] = SH_PFC_PIN_NONE, |
4275 | [24] = SH_PFC_PIN_NONE, |
4276 | [25] = SH_PFC_PIN_NONE, |
4277 | [26] = SH_PFC_PIN_NONE, |
4278 | [27] = SH_PFC_PIN_NONE, |
4279 | [28] = SH_PFC_PIN_NONE, |
4280 | [29] = SH_PFC_PIN_NONE, |
4281 | [30] = SH_PFC_PIN_NONE, |
4282 | [31] = SH_PFC_PIN_NONE, |
4283 | } }, |
4284 | { PINMUX_BIAS_REG("PUEN8" , 0xe60690c0, "PUD8" , 0xe60690e0) { |
4285 | [ 0] = RCAR_GP_PIN(8, 0), /* AVB4_RX_CTL */ |
4286 | [ 1] = RCAR_GP_PIN(8, 1), /* AVB4_RXC */ |
4287 | [ 2] = RCAR_GP_PIN(8, 2), /* AVB4_RD0 */ |
4288 | [ 3] = RCAR_GP_PIN(8, 3), /* AVB4_RD1 */ |
4289 | [ 4] = RCAR_GP_PIN(8, 4), /* AVB4_RD2 */ |
4290 | [ 5] = RCAR_GP_PIN(8, 5), /* AVB4_RD3 */ |
4291 | [ 6] = RCAR_GP_PIN(8, 6), /* AVB4_TX_CTL */ |
4292 | [ 7] = RCAR_GP_PIN(8, 7), /* AVB4_TXC */ |
4293 | [ 8] = RCAR_GP_PIN(8, 8), /* AVB4_TD0 */ |
4294 | [ 9] = RCAR_GP_PIN(8, 9), /* AVB4_TD1 */ |
4295 | [10] = RCAR_GP_PIN(8, 10), /* AVB4_TD2 */ |
4296 | [11] = RCAR_GP_PIN(8, 11), /* AVB4_TD3 */ |
4297 | [12] = RCAR_GP_PIN(8, 12), /* AVB4_TXCREFCLK */ |
4298 | [13] = RCAR_GP_PIN(8, 13), /* AVB4_MDIO */ |
4299 | [14] = RCAR_GP_PIN(8, 14), /* AVB4_MDC */ |
4300 | [15] = RCAR_GP_PIN(8, 15), /* AVB4_MAGIC */ |
4301 | [16] = RCAR_GP_PIN(8, 16), /* AVB4_PHY_INT */ |
4302 | [17] = RCAR_GP_PIN(8, 17), /* AVB4_LINK */ |
4303 | [18] = RCAR_GP_PIN(8, 18), /* AVB4_AVTP_MATCH */ |
4304 | [19] = RCAR_GP_PIN(8, 19), /* AVB4_AVTP_CAPTURE */ |
4305 | [20] = RCAR_GP_PIN(8, 20), /* AVB4_AVTP_PPS */ |
4306 | [21] = SH_PFC_PIN_NONE, |
4307 | [22] = SH_PFC_PIN_NONE, |
4308 | [23] = SH_PFC_PIN_NONE, |
4309 | [24] = SH_PFC_PIN_NONE, |
4310 | [25] = SH_PFC_PIN_NONE, |
4311 | [26] = SH_PFC_PIN_NONE, |
4312 | [27] = SH_PFC_PIN_NONE, |
4313 | [28] = SH_PFC_PIN_NONE, |
4314 | [29] = SH_PFC_PIN_NONE, |
4315 | [30] = SH_PFC_PIN_NONE, |
4316 | [31] = SH_PFC_PIN_NONE, |
4317 | } }, |
4318 | { PINMUX_BIAS_REG("PUEN9" , 0xe60698c0, "PUD9" , 0xe60698e0) { |
4319 | [ 0] = RCAR_GP_PIN(9, 0), /* AVB5_RX_CTL */ |
4320 | [ 1] = RCAR_GP_PIN(9, 1), /* AVB5_RXC */ |
4321 | [ 2] = RCAR_GP_PIN(9, 2), /* AVB5_RD0 */ |
4322 | [ 3] = RCAR_GP_PIN(9, 3), /* AVB5_RD1 */ |
4323 | [ 4] = RCAR_GP_PIN(9, 4), /* AVB5_RD2 */ |
4324 | [ 5] = RCAR_GP_PIN(9, 5), /* AVB5_RD3 */ |
4325 | [ 6] = RCAR_GP_PIN(9, 6), /* AVB5_TX_CTL */ |
4326 | [ 7] = RCAR_GP_PIN(9, 7), /* AVB5_TXC */ |
4327 | [ 8] = RCAR_GP_PIN(9, 8), /* AVB5_TD0 */ |
4328 | [ 9] = RCAR_GP_PIN(9, 9), /* AVB5_TD1 */ |
4329 | [10] = RCAR_GP_PIN(9, 10), /* AVB5_TD2 */ |
4330 | [11] = RCAR_GP_PIN(9, 11), /* AVB5_TD3 */ |
4331 | [12] = RCAR_GP_PIN(9, 12), /* AVB5_TXCREFCLK */ |
4332 | [13] = RCAR_GP_PIN(9, 13), /* AVB5_MDIO */ |
4333 | [14] = RCAR_GP_PIN(9, 14), /* AVB5_MDC */ |
4334 | [15] = RCAR_GP_PIN(9, 15), /* AVB5_MAGIC */ |
4335 | [16] = RCAR_GP_PIN(9, 16), /* AVB5_PHY_INT */ |
4336 | [17] = RCAR_GP_PIN(9, 17), /* AVB5_LINK */ |
4337 | [18] = RCAR_GP_PIN(9, 18), /* AVB5_AVTP_MATCH */ |
4338 | [19] = RCAR_GP_PIN(9, 19), /* AVB5_AVTP_CAPTURE */ |
4339 | [20] = RCAR_GP_PIN(9, 20), /* AVB5_AVTP_PPS */ |
4340 | [21] = SH_PFC_PIN_NONE, |
4341 | [22] = SH_PFC_PIN_NONE, |
4342 | [23] = SH_PFC_PIN_NONE, |
4343 | [24] = SH_PFC_PIN_NONE, |
4344 | [25] = SH_PFC_PIN_NONE, |
4345 | [26] = SH_PFC_PIN_NONE, |
4346 | [27] = SH_PFC_PIN_NONE, |
4347 | [28] = SH_PFC_PIN_NONE, |
4348 | [29] = SH_PFC_PIN_NONE, |
4349 | [30] = SH_PFC_PIN_NONE, |
4350 | [31] = SH_PFC_PIN_NONE, |
4351 | } }, |
4352 | { /* sentinel */ } |
4353 | }; |
4354 | |
4355 | static const struct sh_pfc_soc_operations r8a779a0_pfc_ops = { |
4356 | .pin_to_pocctrl = r8a779a0_pin_to_pocctrl, |
4357 | .get_bias = rcar_pinmux_get_bias, |
4358 | .set_bias = rcar_pinmux_set_bias, |
4359 | }; |
4360 | |
4361 | const struct sh_pfc_soc_info r8a779a0_pinmux_info = { |
4362 | .name = "r8a779a0_pfc" , |
4363 | .ops = &r8a779a0_pfc_ops, |
4364 | .unlock_reg = 0x1ff, /* PMMRn mask */ |
4365 | |
4366 | .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, |
4367 | |
4368 | .pins = pinmux_pins, |
4369 | .nr_pins = ARRAY_SIZE(pinmux_pins), |
4370 | .groups = pinmux_groups, |
4371 | .nr_groups = ARRAY_SIZE(pinmux_groups), |
4372 | .functions = pinmux_functions, |
4373 | .nr_functions = ARRAY_SIZE(pinmux_functions), |
4374 | |
4375 | .cfg_regs = pinmux_config_regs, |
4376 | .drive_regs = pinmux_drive_regs, |
4377 | .bias_regs = pinmux_bias_regs, |
4378 | .ioctrl_regs = pinmux_ioctrl_regs, |
4379 | |
4380 | .pinmux_data = pinmux_data, |
4381 | .pinmux_data_size = ARRAY_SIZE(pinmux_data), |
4382 | }; |
4383 | |