1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * sh73a0 processor support - PFC hardware block |
4 | * |
5 | * Copyright (C) 2010 Renesas Solutions Corp. |
6 | * Copyright (C) 2010 NISHIMOTO Hiroki |
7 | */ |
8 | #include <linux/io.h> |
9 | #include <linux/kernel.h> |
10 | #include <linux/module.h> |
11 | #include <linux/pinctrl/pinconf-generic.h> |
12 | #include <linux/regulator/driver.h> |
13 | #include <linux/regulator/machine.h> |
14 | #include <linux/slab.h> |
15 | |
16 | #include "sh_pfc.h" |
17 | |
18 | #define CPU_ALL_PORT(fn, pfx, sfx) \ |
19 | PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \ |
20 | PORT_10(100, fn, pfx##10, sfx), \ |
21 | PORT_1(110, fn, pfx##110, sfx), PORT_1(111, fn, pfx##111, sfx), \ |
22 | PORT_1(112, fn, pfx##112, sfx), PORT_1(113, fn, pfx##113, sfx), \ |
23 | PORT_1(114, fn, pfx##114, sfx), PORT_1(115, fn, pfx##115, sfx), \ |
24 | PORT_1(116, fn, pfx##116, sfx), PORT_1(117, fn, pfx##117, sfx), \ |
25 | PORT_1(118, fn, pfx##118, sfx), \ |
26 | PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \ |
27 | PORT_10(130, fn, pfx##13, sfx), PORT_10(140, fn, pfx##14, sfx), \ |
28 | PORT_10(150, fn, pfx##15, sfx), \ |
29 | PORT_1(160, fn, pfx##160, sfx), PORT_1(161, fn, pfx##161, sfx), \ |
30 | PORT_1(162, fn, pfx##162, sfx), PORT_1(163, fn, pfx##163, sfx), \ |
31 | PORT_1(164, fn, pfx##164, sfx), \ |
32 | PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \ |
33 | PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx), \ |
34 | PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx), \ |
35 | PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx), \ |
36 | PORT_10(200, fn, pfx##20, sfx), PORT_10(210, fn, pfx##21, sfx), \ |
37 | PORT_10(220, fn, pfx##22, sfx), PORT_10(230, fn, pfx##23, sfx), \ |
38 | PORT_10(240, fn, pfx##24, sfx), PORT_10(250, fn, pfx##25, sfx), \ |
39 | PORT_10(260, fn, pfx##26, sfx), PORT_10(270, fn, pfx##27, sfx), \ |
40 | PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx), \ |
41 | PORT_1(282, fn, pfx##282, sfx), \ |
42 | PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \ |
43 | PORT_10(290, fn, pfx##29, sfx), PORT_10(300, fn, pfx##30, sfx) |
44 | |
45 | #define CPU_ALL_NOGP(fn) \ |
46 | PIN_NOGP(A11, "F26", fn) |
47 | |
48 | enum { |
49 | PINMUX_RESERVED = 0, |
50 | |
51 | PINMUX_DATA_BEGIN, |
52 | PORT_ALL(DATA), /* PORT0_DATA -> PORT309_DATA */ |
53 | PINMUX_DATA_END, |
54 | |
55 | PINMUX_INPUT_BEGIN, |
56 | PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */ |
57 | PINMUX_INPUT_END, |
58 | |
59 | PINMUX_OUTPUT_BEGIN, |
60 | PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */ |
61 | PINMUX_OUTPUT_END, |
62 | |
63 | PINMUX_FUNCTION_BEGIN, |
64 | PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT309_FN_IN */ |
65 | PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT309_FN_OUT */ |
66 | PORT_ALL(FN0), /* PORT0_FN0 -> PORT309_FN0 */ |
67 | PORT_ALL(FN1), /* PORT0_FN1 -> PORT309_FN1 */ |
68 | PORT_ALL(FN2), /* PORT0_FN2 -> PORT309_FN2 */ |
69 | PORT_ALL(FN3), /* PORT0_FN3 -> PORT309_FN3 */ |
70 | PORT_ALL(FN4), /* PORT0_FN4 -> PORT309_FN4 */ |
71 | PORT_ALL(FN5), /* PORT0_FN5 -> PORT309_FN5 */ |
72 | PORT_ALL(FN6), /* PORT0_FN6 -> PORT309_FN6 */ |
73 | PORT_ALL(FN7), /* PORT0_FN7 -> PORT309_FN7 */ |
74 | |
75 | MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1, |
76 | MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1, |
77 | MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1, |
78 | MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1, |
79 | MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1, |
80 | MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1, |
81 | MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1, |
82 | MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1, |
83 | MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1, |
84 | MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1, |
85 | MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1, |
86 | MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1, |
87 | MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1, |
88 | MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1, |
89 | MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1, |
90 | MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1, |
91 | MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1, |
92 | MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1, |
93 | MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1, |
94 | MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1, |
95 | MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1, |
96 | MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1, |
97 | MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1, |
98 | MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1, |
99 | MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1, |
100 | MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1, |
101 | MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1, |
102 | MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1, |
103 | MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1, |
104 | MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1, |
105 | MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1, |
106 | MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1, |
107 | MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1, |
108 | MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1, |
109 | MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1, |
110 | MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1, |
111 | MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1, |
112 | MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1, |
113 | MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1, |
114 | MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1, |
115 | MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1, |
116 | MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1, |
117 | PINMUX_FUNCTION_END, |
118 | |
119 | PINMUX_MARK_BEGIN, |
120 | /* Hardware manual Table 25-1 (Function 0-7) */ |
121 | VBUS_0_MARK, |
122 | GPI0_MARK, |
123 | GPI1_MARK, |
124 | GPI2_MARK, |
125 | GPI3_MARK, |
126 | GPI4_MARK, |
127 | GPI5_MARK, |
128 | GPI6_MARK, |
129 | GPI7_MARK, |
130 | SCIFA7_RXD_MARK, |
131 | SCIFA7_CTS__MARK, |
132 | GPO7_MARK, MFG0_OUT2_MARK, |
133 | GPO6_MARK, MFG1_OUT2_MARK, |
134 | GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK, |
135 | SCIFA0_TXD_MARK, |
136 | SCIFA7_TXD_MARK, |
137 | SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK, |
138 | GPO0_MARK, |
139 | GPO1_MARK, |
140 | GPO2_MARK, STATUS0_MARK, |
141 | GPO3_MARK, STATUS1_MARK, |
142 | GPO4_MARK, STATUS2_MARK, |
143 | VINT_MARK, |
144 | TCKON_MARK, |
145 | XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \ |
146 | MFG0_OUT1_MARK, PORT27_IROUT_MARK, |
147 | XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \ |
148 | PORT28_TPU1TO1_MARK, |
149 | SIM_RST_MARK, PORT29_TPU1TO1_MARK, |
150 | SIM_CLK_MARK, PORT30_VIO_CKOR_MARK, |
151 | SIM_D_MARK, PORT31_IROUT_MARK, |
152 | SCIFA4_TXD_MARK, |
153 | SCIFA4_RXD_MARK, XWUP_MARK, |
154 | SCIFA4_RTS__MARK, |
155 | SCIFA4_CTS__MARK, |
156 | FSIBOBT_MARK, FSIBIBT_MARK, |
157 | FSIBOLR_MARK, FSIBILR_MARK, |
158 | FSIBOSLD_MARK, |
159 | FSIBISLD_MARK, |
160 | VACK_MARK, |
161 | XTAL1L_MARK, |
162 | SCIFA0_RTS__MARK, FSICOSLDT2_MARK, |
163 | SCIFA0_RXD_MARK, |
164 | SCIFA0_CTS__MARK, FSICOSLDT1_MARK, |
165 | FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK, |
166 | FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK, |
167 | FSICOSLD_MARK, PORT47_FSICSPDIF_MARK, |
168 | FSICISLD_MARK, FSIDISLD_MARK, |
169 | FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK, |
170 | FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK, |
171 | |
172 | FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK, |
173 | FSIAOSLD_MARK, BBIF2_TXD2_MARK, |
174 | FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \ |
175 | PORT53_FSICSPDIF_MARK, |
176 | FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \ |
177 | FSICCK_MARK, FSICOMC_MARK, |
178 | FSIAISLD_MARK, TPU0TO0_MARK, |
179 | A0_MARK, BS__MARK, |
180 | A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK, |
181 | A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK, |
182 | A14_MARK, KEYOUT5_MARK, |
183 | A15_MARK, KEYOUT4_MARK, |
184 | A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK, |
185 | A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK, |
186 | A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK, |
187 | A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK, |
188 | A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK, |
189 | A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK, |
190 | A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK, |
191 | A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK, |
192 | A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK, |
193 | A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK, |
194 | A26_MARK, KEYIN6_MARK, |
195 | KEYIN7_MARK, |
196 | D0_NAF0_MARK, |
197 | D1_NAF1_MARK, |
198 | D2_NAF2_MARK, |
199 | D3_NAF3_MARK, |
200 | D4_NAF4_MARK, |
201 | D5_NAF5_MARK, |
202 | D6_NAF6_MARK, |
203 | D7_NAF7_MARK, |
204 | D8_NAF8_MARK, |
205 | D9_NAF9_MARK, |
206 | D10_NAF10_MARK, |
207 | D11_NAF11_MARK, |
208 | D12_NAF12_MARK, |
209 | D13_NAF13_MARK, |
210 | D14_NAF14_MARK, |
211 | D15_NAF15_MARK, |
212 | CS4__MARK, |
213 | CS5A__MARK, PORT91_RDWR_MARK, |
214 | CS5B__MARK, FCE1__MARK, |
215 | CS6B__MARK, DACK0_MARK, |
216 | FCE0__MARK, CS6A__MARK, |
217 | WAIT__MARK, DREQ0_MARK, |
218 | RD__FSC_MARK, |
219 | WE0__FWE_MARK, RDWR_FWE_MARK, |
220 | WE1__MARK, |
221 | FRB_MARK, |
222 | CKO_MARK, |
223 | NBRSTOUT__MARK, |
224 | NBRST__MARK, |
225 | BBIF2_TXD_MARK, |
226 | BBIF2_RXD_MARK, |
227 | BBIF2_SYNC_MARK, |
228 | BBIF2_SCK_MARK, |
229 | SCIFA3_CTS__MARK, MFG3_IN2_MARK, |
230 | SCIFA3_RXD_MARK, MFG3_IN1_MARK, |
231 | BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK, |
232 | SCIFA3_TXD_MARK, |
233 | HSI_RX_DATA_MARK, BBIF1_RXD_MARK, |
234 | HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK, |
235 | HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK, |
236 | HSI_TX_READY_MARK, BBIF1_TXD_MARK, |
237 | HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \ |
238 | PORT115_I2C_SCL3_MARK, |
239 | HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \ |
240 | PORT116_I2C_SDA3_MARK, |
241 | HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK, |
242 | HSI_TX_FLAG_MARK, |
243 | VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK, |
244 | |
245 | VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \ |
246 | VIO2_HD_MARK, LCD2D1_MARK, |
247 | VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK, |
248 | VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \ |
249 | PORT131_KEYOUT11_MARK, LCD2D11_MARK, |
250 | VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \ |
251 | PORT132_KEYOUT10_MARK, LCD2D12_MARK, |
252 | VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK, |
253 | VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK, |
254 | VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK, |
255 | VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK, |
256 | VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK, |
257 | VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK, |
258 | VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK, |
259 | VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK, |
260 | VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK, |
261 | VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK, |
262 | VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \ |
263 | VIO2_D5_MARK, LCD2D3_MARK, |
264 | VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK, |
265 | VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \ |
266 | PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK, |
267 | VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \ |
268 | LCD2D18_MARK, |
269 | VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK, |
270 | VIO_CKO_MARK, |
271 | A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK, |
272 | MFG0_IN2_MARK, |
273 | TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK, |
274 | TS_SDAT3_MARK, MSIOF2_RSYNC_MARK, |
275 | TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK, |
276 | SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK, |
277 | SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK, |
278 | SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK, |
279 | SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK, |
280 | DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK, |
281 | PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK, |
282 | PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK, |
283 | PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK, |
284 | PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK, |
285 | PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK, |
286 | LCDD0_MARK, |
287 | LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK, |
288 | LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK, |
289 | LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK, |
290 | LCDD4_MARK, PORT196_SCIFA5_TXD_MARK, |
291 | LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK, |
292 | LCDD6_MARK, |
293 | LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK, |
294 | LCDD8_MARK, D16_MARK, |
295 | LCDD9_MARK, D17_MARK, |
296 | LCDD10_MARK, D18_MARK, |
297 | LCDD11_MARK, D19_MARK, |
298 | LCDD12_MARK, D20_MARK, |
299 | LCDD13_MARK, D21_MARK, |
300 | LCDD14_MARK, D22_MARK, |
301 | LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK, |
302 | LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK, |
303 | LCDD17_MARK, D25_MARK, |
304 | LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK, |
305 | LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK, |
306 | LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK, |
307 | LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK, |
308 | LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK, |
309 | LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK, |
310 | LCDDCK_MARK, LCDWR__MARK, |
311 | LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \ |
312 | VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK, |
313 | LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \ |
314 | PORT218_VIO_CKOR_MARK, |
315 | LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \ |
316 | MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK, |
317 | LCDVSYN_MARK, LCDVSYN2_MARK, |
318 | LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \ |
319 | MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK, |
320 | LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \ |
321 | VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK, |
322 | |
323 | SCIFA1_TXD_MARK, OVCN2_MARK, |
324 | EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK, |
325 | SCIFA1_RTS__MARK, IDIN_MARK, |
326 | SCIFA1_RXD_MARK, |
327 | SCIFA1_CTS__MARK, MFG1_IN1_MARK, |
328 | MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK, |
329 | MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK, |
330 | MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK, |
331 | MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK, |
332 | MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK, |
333 | MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK, |
334 | MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK, |
335 | MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK, |
336 | MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK, |
337 | MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK, |
338 | SCIFA6_TXD_MARK, |
339 | PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK, |
340 | PORT242_IRDA_IN_MARK, MFG4_IN2_MARK, |
341 | PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK, |
342 | PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \ |
343 | MSIOF2R_RXD_MARK, |
344 | PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \ |
345 | MSIOF2R_TXD_MARK, |
346 | PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \ |
347 | TPU1TO0_MARK, |
348 | PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \ |
349 | TPU3TO1_MARK, |
350 | PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \ |
351 | TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK, |
352 | PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \ |
353 | MSIOF2R_TSYNC_MARK, |
354 | SDHICLK0_MARK, |
355 | SDHICD0_MARK, |
356 | SDHID0_0_MARK, |
357 | SDHID0_1_MARK, |
358 | SDHID0_2_MARK, |
359 | SDHID0_3_MARK, |
360 | SDHICMD0_MARK, |
361 | SDHIWP0_MARK, |
362 | SDHICLK1_MARK, |
363 | SDHID1_0_MARK, TS_SPSYNC2_MARK, |
364 | SDHID1_1_MARK, TS_SDAT2_MARK, |
365 | SDHID1_2_MARK, TS_SDEN2_MARK, |
366 | SDHID1_3_MARK, TS_SCK2_MARK, |
367 | SDHICMD1_MARK, |
368 | SDHICLK2_MARK, |
369 | SDHID2_0_MARK, TS_SPSYNC4_MARK, |
370 | SDHID2_1_MARK, TS_SDAT4_MARK, |
371 | SDHID2_2_MARK, TS_SDEN4_MARK, |
372 | SDHID2_3_MARK, TS_SCK4_MARK, |
373 | SDHICMD2_MARK, |
374 | MMCCLK0_MARK, |
375 | MMCD0_0_MARK, |
376 | MMCD0_1_MARK, |
377 | MMCD0_2_MARK, |
378 | MMCD0_3_MARK, |
379 | MMCD0_4_MARK, TS_SPSYNC5_MARK, |
380 | MMCD0_5_MARK, TS_SDAT5_MARK, |
381 | MMCD0_6_MARK, TS_SDEN5_MARK, |
382 | MMCD0_7_MARK, TS_SCK5_MARK, |
383 | MMCCMD0_MARK, |
384 | RESETOUTS__MARK, EXTAL2OUT_MARK, |
385 | MCP_WAIT__MCP_FRB_MARK, |
386 | MCP_CKO_MARK, MMCCLK1_MARK, |
387 | MCP_D15_MCP_NAF15_MARK, |
388 | MCP_D14_MCP_NAF14_MARK, |
389 | MCP_D13_MCP_NAF13_MARK, |
390 | MCP_D12_MCP_NAF12_MARK, |
391 | MCP_D11_MCP_NAF11_MARK, |
392 | MCP_D10_MCP_NAF10_MARK, |
393 | MCP_D9_MCP_NAF9_MARK, |
394 | MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK, |
395 | MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK, |
396 | |
397 | MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK, |
398 | MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK, |
399 | MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK, |
400 | MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK, |
401 | MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK, |
402 | MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK, |
403 | MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK, |
404 | MCP_NBRSTOUT__MARK, |
405 | MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK, |
406 | |
407 | /* MSEL2 special cases */ |
408 | TSIF2_TS_XX1_MARK, |
409 | TSIF2_TS_XX2_MARK, |
410 | TSIF2_TS_XX3_MARK, |
411 | TSIF2_TS_XX4_MARK, |
412 | TSIF2_TS_XX5_MARK, |
413 | TSIF1_TS_XX1_MARK, |
414 | TSIF1_TS_XX2_MARK, |
415 | TSIF1_TS_XX3_MARK, |
416 | TSIF1_TS_XX4_MARK, |
417 | TSIF1_TS_XX5_MARK, |
418 | TSIF0_TS_XX1_MARK, |
419 | TSIF0_TS_XX2_MARK, |
420 | TSIF0_TS_XX3_MARK, |
421 | TSIF0_TS_XX4_MARK, |
422 | TSIF0_TS_XX5_MARK, |
423 | MST1_TS_XX1_MARK, |
424 | MST1_TS_XX2_MARK, |
425 | MST1_TS_XX3_MARK, |
426 | MST1_TS_XX4_MARK, |
427 | MST1_TS_XX5_MARK, |
428 | MST0_TS_XX1_MARK, |
429 | MST0_TS_XX2_MARK, |
430 | MST0_TS_XX3_MARK, |
431 | MST0_TS_XX4_MARK, |
432 | MST0_TS_XX5_MARK, |
433 | |
434 | /* MSEL3 special cases */ |
435 | SDHI0_VCCQ_MC0_ON_MARK, |
436 | SDHI0_VCCQ_MC0_OFF_MARK, |
437 | DEBUG_MON_VIO_MARK, |
438 | DEBUG_MON_LCDD_MARK, |
439 | LCDC_LCDC0_MARK, |
440 | LCDC_LCDC1_MARK, |
441 | |
442 | /* MSEL4 special cases */ |
443 | IRQ9_MEM_INT_MARK, |
444 | IRQ9_MCP_INT_MARK, |
445 | A11_MARK, |
446 | KEYOUT8_MARK, |
447 | TPU4TO3_MARK, |
448 | RESETA_N_PU_ON_MARK, |
449 | RESETA_N_PU_OFF_MARK, |
450 | EDBGREQ_PD_MARK, |
451 | EDBGREQ_PU_MARK, |
452 | |
453 | PINMUX_MARK_END, |
454 | }; |
455 | |
456 | static const u16 pinmux_data[] = { |
457 | /* specify valid pin states for each pin in GPIO mode */ |
458 | PINMUX_DATA_ALL(), |
459 | |
460 | /* Table 25-1 (Function 0-7) */ |
461 | PINMUX_DATA(VBUS_0_MARK, PORT0_FN1), |
462 | PINMUX_DATA(GPI0_MARK, PORT1_FN1), |
463 | PINMUX_DATA(GPI1_MARK, PORT2_FN1), |
464 | PINMUX_DATA(GPI2_MARK, PORT3_FN1), |
465 | PINMUX_DATA(GPI3_MARK, PORT4_FN1), |
466 | PINMUX_DATA(GPI4_MARK, PORT5_FN1), |
467 | PINMUX_DATA(GPI5_MARK, PORT6_FN1), |
468 | PINMUX_DATA(GPI6_MARK, PORT7_FN1), |
469 | PINMUX_DATA(GPI7_MARK, PORT8_FN1), |
470 | PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2), |
471 | PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2), |
472 | PINMUX_DATA(GPO7_MARK, PORT14_FN1), \ |
473 | PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4), |
474 | PINMUX_DATA(GPO6_MARK, PORT15_FN1), \ |
475 | PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4), |
476 | PINMUX_DATA(GPO5_MARK, PORT16_FN1), \ |
477 | PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \ |
478 | PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \ |
479 | PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4), |
480 | PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2), |
481 | PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2), |
482 | PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \ |
483 | PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3), |
484 | PINMUX_DATA(GPO0_MARK, PORT20_FN1), |
485 | PINMUX_DATA(GPO1_MARK, PORT21_FN1), |
486 | PINMUX_DATA(GPO2_MARK, PORT22_FN1), \ |
487 | PINMUX_DATA(STATUS0_MARK, PORT22_FN2), |
488 | PINMUX_DATA(GPO3_MARK, PORT23_FN1), \ |
489 | PINMUX_DATA(STATUS1_MARK, PORT23_FN2), |
490 | PINMUX_DATA(GPO4_MARK, PORT24_FN1), \ |
491 | PINMUX_DATA(STATUS2_MARK, PORT24_FN2), |
492 | PINMUX_DATA(VINT_MARK, PORT25_FN1), |
493 | PINMUX_DATA(TCKON_MARK, PORT26_FN1), |
494 | PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \ |
495 | PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0, |
496 | MSEL2CR_MSEL16_1), \ |
497 | PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0, |
498 | MSEL2CR_MSEL18_1), \ |
499 | PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \ |
500 | PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7), |
501 | PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \ |
502 | PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0, |
503 | MSEL2CR_MSEL16_1), \ |
504 | PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0, |
505 | MSEL2CR_MSEL18_1), \ |
506 | PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7), |
507 | PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \ |
508 | PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4), |
509 | PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \ |
510 | PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4), |
511 | PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \ |
512 | PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4), |
513 | PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2), |
514 | PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \ |
515 | PINMUX_DATA(XWUP_MARK, PORT33_FN3), |
516 | PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2), |
517 | PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2), |
518 | PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \ |
519 | PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2), |
520 | PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \ |
521 | PINMUX_DATA(FSIBILR_MARK, PORT37_FN2), |
522 | PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1), |
523 | PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1), |
524 | PINMUX_DATA(VACK_MARK, PORT40_FN1), |
525 | PINMUX_DATA(XTAL1L_MARK, PORT41_FN1), |
526 | PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \ |
527 | PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3), |
528 | PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2), |
529 | PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \ |
530 | PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3), |
531 | PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \ |
532 | PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \ |
533 | PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \ |
534 | PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4), |
535 | PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \ |
536 | PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \ |
537 | PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \ |
538 | PINMUX_DATA(FSIDILR_MARK, PORT46_FN4), |
539 | PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \ |
540 | PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2), |
541 | PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \ |
542 | PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3), |
543 | PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \ |
544 | PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \ |
545 | PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \ |
546 | PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5), |
547 | PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \ |
548 | PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \ |
549 | PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \ |
550 | PINMUX_DATA(FSIAILR_MARK, PORT50_FN5), |
551 | |
552 | PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \ |
553 | PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \ |
554 | PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \ |
555 | PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5), |
556 | PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \ |
557 | PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2), |
558 | PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \ |
559 | PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \ |
560 | PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \ |
561 | PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \ |
562 | PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6), |
563 | PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \ |
564 | PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \ |
565 | PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \ |
566 | PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \ |
567 | PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \ |
568 | PINMUX_DATA(FSICOMC_MARK, PORT54_FN7), |
569 | PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \ |
570 | PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3), |
571 | PINMUX_DATA(A0_MARK, PORT57_FN1), \ |
572 | PINMUX_DATA(BS__MARK, PORT57_FN2), |
573 | PINMUX_DATA(A12_MARK, PORT58_FN1), \ |
574 | PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \ |
575 | PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4), |
576 | PINMUX_DATA(A13_MARK, PORT59_FN1), \ |
577 | PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \ |
578 | PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4), |
579 | PINMUX_DATA(A14_MARK, PORT60_FN1), \ |
580 | PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2), |
581 | PINMUX_DATA(A15_MARK, PORT61_FN1), \ |
582 | PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2), |
583 | PINMUX_DATA(A16_MARK, PORT62_FN1), \ |
584 | PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \ |
585 | PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0), |
586 | PINMUX_DATA(A17_MARK, PORT63_FN1), \ |
587 | PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \ |
588 | PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0), |
589 | PINMUX_DATA(A18_MARK, PORT64_FN1), \ |
590 | PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \ |
591 | PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0), |
592 | PINMUX_DATA(A19_MARK, PORT65_FN1), \ |
593 | PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \ |
594 | PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0), |
595 | PINMUX_DATA(A20_MARK, PORT66_FN1), \ |
596 | PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \ |
597 | PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0), |
598 | PINMUX_DATA(A21_MARK, PORT67_FN1), \ |
599 | PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \ |
600 | PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0), |
601 | PINMUX_DATA(A22_MARK, PORT68_FN1), \ |
602 | PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \ |
603 | PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0), |
604 | PINMUX_DATA(A23_MARK, PORT69_FN1), \ |
605 | PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \ |
606 | PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0), |
607 | PINMUX_DATA(A24_MARK, PORT70_FN1), \ |
608 | PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \ |
609 | PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0), |
610 | PINMUX_DATA(A25_MARK, PORT71_FN1), \ |
611 | PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \ |
612 | PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0), |
613 | PINMUX_DATA(A26_MARK, PORT72_FN1), \ |
614 | PINMUX_DATA(KEYIN6_MARK, PORT72_FN2), |
615 | PINMUX_DATA(KEYIN7_MARK, PORT73_FN2), |
616 | PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1), |
617 | PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1), |
618 | PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1), |
619 | PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1), |
620 | PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1), |
621 | PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1), |
622 | PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1), |
623 | PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1), |
624 | PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1), |
625 | PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1), |
626 | PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1), |
627 | PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1), |
628 | PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1), |
629 | PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1), |
630 | PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1), |
631 | PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1), |
632 | PINMUX_DATA(CS4__MARK, PORT90_FN1), |
633 | PINMUX_DATA(CS5A__MARK, PORT91_FN1), \ |
634 | PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2), |
635 | PINMUX_DATA(CS5B__MARK, PORT92_FN1), \ |
636 | PINMUX_DATA(FCE1__MARK, PORT92_FN2), |
637 | PINMUX_DATA(CS6B__MARK, PORT93_FN1), \ |
638 | PINMUX_DATA(DACK0_MARK, PORT93_FN4), |
639 | PINMUX_DATA(FCE0__MARK, PORT94_FN1), \ |
640 | PINMUX_DATA(CS6A__MARK, PORT94_FN2), |
641 | PINMUX_DATA(WAIT__MARK, PORT95_FN1), \ |
642 | PINMUX_DATA(DREQ0_MARK, PORT95_FN2), |
643 | PINMUX_DATA(RD__FSC_MARK, PORT96_FN1), |
644 | PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \ |
645 | PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2), |
646 | PINMUX_DATA(WE1__MARK, PORT98_FN1), |
647 | PINMUX_DATA(FRB_MARK, PORT99_FN1), |
648 | PINMUX_DATA(CKO_MARK, PORT100_FN1), |
649 | PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1), |
650 | PINMUX_DATA(NBRST__MARK, PORT102_FN1), |
651 | PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3), |
652 | PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3), |
653 | PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3), |
654 | PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3), |
655 | PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \ |
656 | PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4), |
657 | PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \ |
658 | PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4), |
659 | PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \ |
660 | PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \ |
661 | PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4), |
662 | PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3), |
663 | PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \ |
664 | PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3), |
665 | PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \ |
666 | PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3), |
667 | PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \ |
668 | PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3), |
669 | PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \ |
670 | PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3), |
671 | PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \ |
672 | PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \ |
673 | PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \ |
674 | PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1), |
675 | PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \ |
676 | PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \ |
677 | PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \ |
678 | PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1), |
679 | PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \ |
680 | PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \ |
681 | PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3), |
682 | PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1), |
683 | PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \ |
684 | PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \ |
685 | PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \ |
686 | PINMUX_DATA(LCD2D0_MARK, PORT128_FN7), |
687 | |
688 | PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \ |
689 | PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \ |
690 | PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \ |
691 | PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \ |
692 | PINMUX_DATA(LCD2D1_MARK, PORT129_FN7), |
693 | PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \ |
694 | PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0, |
695 | MSEL4CR_MSEL10_1), \ |
696 | PINMUX_DATA(LCD2D10_MARK, PORT130_FN7), |
697 | PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \ |
698 | PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \ |
699 | PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \ |
700 | PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \ |
701 | PINMUX_DATA(LCD2D11_MARK, PORT131_FN7), |
702 | PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \ |
703 | PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \ |
704 | PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \ |
705 | PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \ |
706 | PINMUX_DATA(LCD2D12_MARK, PORT132_FN7), |
707 | PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \ |
708 | PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \ |
709 | PINMUX_DATA(LCD2D13_MARK, PORT133_FN7), |
710 | PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \ |
711 | PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \ |
712 | PINMUX_DATA(LCD2D14_MARK, PORT134_FN7), |
713 | PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \ |
714 | PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \ |
715 | PINMUX_DATA(LCD2D15_MARK, PORT135_FN7), |
716 | PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \ |
717 | PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \ |
718 | PINMUX_DATA(LCD2D16_MARK, PORT136_FN7), |
719 | PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \ |
720 | PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \ |
721 | PINMUX_DATA(LCD2D17_MARK, PORT137_FN7), |
722 | PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \ |
723 | PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \ |
724 | PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \ |
725 | PINMUX_DATA(LCD2D6_MARK, PORT138_FN7), |
726 | PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \ |
727 | PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \ |
728 | PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \ |
729 | PINMUX_DATA(LCD2D7_MARK, PORT139_FN7), |
730 | PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \ |
731 | PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \ |
732 | PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \ |
733 | PINMUX_DATA(LCD2D8_MARK, PORT140_FN7), |
734 | PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \ |
735 | PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \ |
736 | PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \ |
737 | PINMUX_DATA(LCD2D9_MARK, PORT141_FN7), |
738 | PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \ |
739 | PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \ |
740 | PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \ |
741 | PINMUX_DATA(LCD2D2_MARK, PORT142_FN7), |
742 | PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \ |
743 | PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \ |
744 | PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \ |
745 | PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \ |
746 | PINMUX_DATA(LCD2D3_MARK, PORT143_FN7), |
747 | PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \ |
748 | PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \ |
749 | PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \ |
750 | PINMUX_DATA(LCD2D4_MARK, PORT144_FN7), |
751 | PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \ |
752 | PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \ |
753 | PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \ |
754 | PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \ |
755 | PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \ |
756 | PINMUX_DATA(LCD2D5_MARK, PORT145_FN7), |
757 | PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \ |
758 | PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \ |
759 | PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \ |
760 | PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \ |
761 | PINMUX_DATA(LCD2D18_MARK, PORT146_FN7), |
762 | PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \ |
763 | PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \ |
764 | PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \ |
765 | PINMUX_DATA(LCD2D19_MARK, PORT147_FN7), |
766 | PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1), |
767 | PINMUX_DATA(A27_MARK, PORT149_FN1), \ |
768 | PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \ |
769 | PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \ |
770 | PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4), |
771 | PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3), |
772 | PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \ |
773 | PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5), |
774 | PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \ |
775 | PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5), |
776 | PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \ |
777 | PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \ |
778 | PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5), |
779 | PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \ |
780 | PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5), |
781 | PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \ |
782 | PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5), |
783 | PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \ |
784 | PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5), |
785 | PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \ |
786 | PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0, |
787 | MSEL4CR_MSEL10_0), |
788 | PINMUX_DATA(DINT__MARK, PORT158_FN1), \ |
789 | PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \ |
790 | PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4), |
791 | PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \ |
792 | PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \ |
793 | PINMUX_DATA(NMI_MARK, PORT159_FN3), |
794 | PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \ |
795 | PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1), |
796 | PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \ |
797 | PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1), |
798 | PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \ |
799 | PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1), |
800 | PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \ |
801 | PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \ |
802 | PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5), |
803 | PINMUX_DATA(LCDD0_MARK, PORT192_FN1), |
804 | PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \ |
805 | PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0, |
806 | MSEL4CR_MSEL20_1), \ |
807 | PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5), |
808 | PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \ |
809 | PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0, |
810 | MSEL4CR_MSEL20_1), \ |
811 | PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5), |
812 | PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \ |
813 | PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0, |
814 | MSEL4CR_MSEL20_1), \ |
815 | PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5), |
816 | PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \ |
817 | PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0, |
818 | MSEL4CR_MSEL20_1), |
819 | PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \ |
820 | PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0, |
821 | MSEL4CR_MSEL20_1), \ |
822 | PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \ |
823 | PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7), |
824 | PINMUX_DATA(LCDD6_MARK, PORT198_FN1), |
825 | PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \ |
826 | PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \ |
827 | PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5), |
828 | PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \ |
829 | PINMUX_DATA(D16_MARK, PORT200_FN6), |
830 | PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \ |
831 | PINMUX_DATA(D17_MARK, PORT201_FN6), |
832 | PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \ |
833 | PINMUX_DATA(D18_MARK, PORT202_FN6), |
834 | PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \ |
835 | PINMUX_DATA(D19_MARK, PORT203_FN6), |
836 | PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \ |
837 | PINMUX_DATA(D20_MARK, PORT204_FN6), |
838 | PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \ |
839 | PINMUX_DATA(D21_MARK, PORT205_FN6), |
840 | PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \ |
841 | PINMUX_DATA(D22_MARK, PORT206_FN6), |
842 | PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \ |
843 | PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \ |
844 | PINMUX_DATA(D23_MARK, PORT207_FN6), |
845 | PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \ |
846 | PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \ |
847 | PINMUX_DATA(D24_MARK, PORT208_FN6), |
848 | PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \ |
849 | PINMUX_DATA(D25_MARK, PORT209_FN6), |
850 | PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \ |
851 | PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \ |
852 | PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \ |
853 | PINMUX_DATA(D26_MARK, PORT210_FN6), |
854 | PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \ |
855 | PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \ |
856 | PINMUX_DATA(D27_MARK, PORT211_FN6), |
857 | PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \ |
858 | PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \ |
859 | PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \ |
860 | PINMUX_DATA(D28_MARK, PORT212_FN6), |
861 | PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \ |
862 | PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \ |
863 | PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \ |
864 | PINMUX_DATA(D29_MARK, PORT213_FN6), |
865 | PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \ |
866 | PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \ |
867 | PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \ |
868 | PINMUX_DATA(D30_MARK, PORT214_FN6), |
869 | PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \ |
870 | PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \ |
871 | PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \ |
872 | PINMUX_DATA(D31_MARK, PORT215_FN6), |
873 | PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \ |
874 | PINMUX_DATA(LCDWR__MARK, PORT216_FN2), |
875 | PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \ |
876 | PINMUX_DATA(DACK2_MARK, PORT217_FN2), \ |
877 | PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \ |
878 | PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \ |
879 | PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1, |
880 | MSEL4CR_MSEL26_1), \ |
881 | PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7), |
882 | PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \ |
883 | PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \ |
884 | PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \ |
885 | PINMUX_DATA(DACK3_MARK, PORT218_FN4), \ |
886 | PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5), |
887 | PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \ |
888 | PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \ |
889 | PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \ |
890 | PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \ |
891 | PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \ |
892 | PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1, |
893 | MSEL4CR_MSEL26_1), \ |
894 | PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7), |
895 | PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \ |
896 | PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2), |
897 | PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \ |
898 | PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \ |
899 | PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \ |
900 | PINMUX_DATA(PWEN_MARK, PORT221_FN4), \ |
901 | PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \ |
902 | PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1, |
903 | MSEL4CR_MSEL26_1), \ |
904 | PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7), |
905 | PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \ |
906 | PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \ |
907 | PINMUX_DATA(DACK1_MARK, PORT222_FN3), \ |
908 | PINMUX_DATA(OVCN_MARK, PORT222_FN4), \ |
909 | PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \ |
910 | PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1, |
911 | MSEL4CR_MSEL26_1), \ |
912 | PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1), |
913 | |
914 | PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \ |
915 | PINMUX_DATA(OVCN2_MARK, PORT225_FN4), |
916 | PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \ |
917 | PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \ |
918 | PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5), |
919 | PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \ |
920 | PINMUX_DATA(IDIN_MARK, PORT227_FN4), |
921 | PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2), |
922 | PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \ |
923 | PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3), |
924 | PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \ |
925 | PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1), |
926 | PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \ |
927 | PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1), |
928 | PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \ |
929 | PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1), |
930 | PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \ |
931 | PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1), |
932 | PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \ |
933 | PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \ |
934 | PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1, |
935 | MSEL4CR_MSEL26_0), \ |
936 | PINMUX_DATA(LCD2D20_MARK, PORT234_FN7), |
937 | PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \ |
938 | PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \ |
939 | PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1, |
940 | MSEL4CR_MSEL26_0), \ |
941 | PINMUX_DATA(LCD2D21_MARK, PORT235_FN7), |
942 | PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \ |
943 | PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0, |
944 | MSEL2CR_MSEL16_0), |
945 | PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \ |
946 | PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0, |
947 | MSEL2CR_MSEL16_0), |
948 | PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \ |
949 | PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1, |
950 | MSEL4CR_MSEL26_0), \ |
951 | PINMUX_DATA(LCD2D22_MARK, PORT238_FN7), |
952 | PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \ |
953 | PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1, |
954 | MSEL4CR_MSEL26_0), \ |
955 | PINMUX_DATA(LCD2D23_MARK, PORT239_FN7), |
956 | PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1), |
957 | PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \ |
958 | PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \ |
959 | PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \ |
960 | PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4), |
961 | PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \ |
962 | PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3), |
963 | PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \ |
964 | PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2), |
965 | PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0, |
966 | MSEL4CR_MSEL20_0), \ |
967 | PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \ |
968 | PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \ |
969 | PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1), |
970 | PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0, |
971 | MSEL4CR_MSEL20_0), \ |
972 | PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \ |
973 | PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \ |
974 | PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1), |
975 | PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0, |
976 | MSEL4CR_MSEL20_0), \ |
977 | PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \ |
978 | PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \ |
979 | PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4), |
980 | PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0, |
981 | MSEL4CR_MSEL20_0), \ |
982 | PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \ |
983 | PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \ |
984 | PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4), |
985 | PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0, |
986 | MSEL4CR_MSEL20_0), \ |
987 | PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \ |
988 | PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \ |
989 | PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \ |
990 | PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0, |
991 | MSEL2CR_MSEL18_0), \ |
992 | PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1), |
993 | PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \ |
994 | PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \ |
995 | PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0, |
996 | MSEL2CR_MSEL18_0), \ |
997 | PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1), |
998 | PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1), |
999 | PINMUX_DATA(SDHICD0_MARK, PORT251_FN1), |
1000 | PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1), |
1001 | PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1), |
1002 | PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1), |
1003 | PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1), |
1004 | PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1), |
1005 | PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1), |
1006 | PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1), |
1007 | PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \ |
1008 | PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3), |
1009 | PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \ |
1010 | PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3), |
1011 | PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \ |
1012 | PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3), |
1013 | PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \ |
1014 | PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3), |
1015 | PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1), |
1016 | PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1), |
1017 | PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \ |
1018 | PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3), |
1019 | PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \ |
1020 | PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3), |
1021 | PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \ |
1022 | PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3), |
1023 | PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \ |
1024 | PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3), |
1025 | PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1), |
1026 | PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0), |
1027 | PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0), |
1028 | PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0), |
1029 | PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0), |
1030 | PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0), |
1031 | PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0), |
1032 | PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3), |
1033 | PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0), |
1034 | PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3), |
1035 | PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0), |
1036 | PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3), |
1037 | PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0), |
1038 | PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3), |
1039 | PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0), |
1040 | PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \ |
1041 | PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2), |
1042 | PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1), |
1043 | PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \ |
1044 | PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1), |
1045 | PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1), |
1046 | PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1), |
1047 | PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1), |
1048 | PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1), |
1049 | PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1), |
1050 | PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1), |
1051 | PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1), |
1052 | PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \ |
1053 | PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1), |
1054 | PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \ |
1055 | PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1), |
1056 | |
1057 | PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \ |
1058 | PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1), |
1059 | PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \ |
1060 | PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1), |
1061 | PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \ |
1062 | PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1), |
1063 | PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \ |
1064 | PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1), |
1065 | PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \ |
1066 | PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1), |
1067 | PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \ |
1068 | PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1), |
1069 | PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \ |
1070 | PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1), |
1071 | PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1), |
1072 | PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \ |
1073 | PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2), |
1074 | |
1075 | /* MSEL2 special cases */ |
1076 | PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0, |
1077 | MSEL2CR_MSEL12_0), |
1078 | PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0, |
1079 | MSEL2CR_MSEL12_1), |
1080 | PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1, |
1081 | MSEL2CR_MSEL12_0), |
1082 | PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1, |
1083 | MSEL2CR_MSEL12_1), |
1084 | PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0, |
1085 | MSEL2CR_MSEL12_0), |
1086 | PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0, |
1087 | MSEL2CR_MSEL9_0), |
1088 | PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0, |
1089 | MSEL2CR_MSEL9_1), |
1090 | PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1, |
1091 | MSEL2CR_MSEL9_0), |
1092 | PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1, |
1093 | MSEL2CR_MSEL9_1), |
1094 | PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0, |
1095 | MSEL2CR_MSEL9_0), |
1096 | PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0, |
1097 | MSEL2CR_MSEL6_0), |
1098 | PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0, |
1099 | MSEL2CR_MSEL6_1), |
1100 | PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1, |
1101 | MSEL2CR_MSEL6_0), |
1102 | PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1, |
1103 | MSEL2CR_MSEL6_1), |
1104 | PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0, |
1105 | MSEL2CR_MSEL6_0), |
1106 | PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0, |
1107 | MSEL2CR_MSEL3_0), |
1108 | PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0, |
1109 | MSEL2CR_MSEL3_1), |
1110 | PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1, |
1111 | MSEL2CR_MSEL3_0), |
1112 | PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1, |
1113 | MSEL2CR_MSEL3_1), |
1114 | PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0, |
1115 | MSEL2CR_MSEL3_0), |
1116 | PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0, |
1117 | MSEL2CR_MSEL0_0), |
1118 | PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0, |
1119 | MSEL2CR_MSEL0_1), |
1120 | PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1, |
1121 | MSEL2CR_MSEL0_0), |
1122 | PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1, |
1123 | MSEL2CR_MSEL0_1), |
1124 | PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0, |
1125 | MSEL2CR_MSEL0_0), |
1126 | |
1127 | /* MSEL3 special cases */ |
1128 | PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1), |
1129 | PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0), |
1130 | PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0), |
1131 | PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1), |
1132 | PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0), |
1133 | PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1), |
1134 | |
1135 | /* MSEL4 special cases */ |
1136 | PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0), |
1137 | PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1), |
1138 | PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0), |
1139 | PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1), |
1140 | PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0), |
1141 | PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0), |
1142 | PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1), |
1143 | PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0), |
1144 | PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1), |
1145 | }; |
1146 | |
1147 | #define __I (SH_PFC_PIN_CFG_INPUT) |
1148 | #define __O (SH_PFC_PIN_CFG_OUTPUT) |
1149 | #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) |
1150 | #define __PD (SH_PFC_PIN_CFG_PULL_DOWN) |
1151 | #define __PU (SH_PFC_PIN_CFG_PULL_UP) |
1152 | #define __PUD (SH_PFC_PIN_CFG_PULL_UP_DOWN) |
1153 | |
1154 | #define SH73A0_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD) |
1155 | #define SH73A0_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU) |
1156 | #define SH73A0_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD) |
1157 | #define SH73A0_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO) |
1158 | #define SH73A0_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD) |
1159 | #define SH73A0_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU) |
1160 | #define SH73A0_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD) |
1161 | #define SH73A0_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O) |
1162 | |
1163 | /* |
1164 | * Pins not associated with a GPIO port. |
1165 | */ |
1166 | enum { |
1167 | PORT_ASSIGN_LAST(), |
1168 | NOGP_ALL(), |
1169 | }; |
1170 | |
1171 | static const struct sh_pfc_pin pinmux_pins[] = { |
1172 | /* Table 25-1 (I/O and Pull U/D) */ |
1173 | SH73A0_PIN_I_PD(0), |
1174 | SH73A0_PIN_I_PU(1), |
1175 | SH73A0_PIN_I_PU(2), |
1176 | SH73A0_PIN_I_PU(3), |
1177 | SH73A0_PIN_I_PU(4), |
1178 | SH73A0_PIN_I_PU(5), |
1179 | SH73A0_PIN_I_PU(6), |
1180 | SH73A0_PIN_I_PU(7), |
1181 | SH73A0_PIN_I_PU(8), |
1182 | SH73A0_PIN_I_PD(9), |
1183 | SH73A0_PIN_I_PD(10), |
1184 | SH73A0_PIN_I_PU_PD(11), |
1185 | SH73A0_PIN_IO_PU_PD(12), |
1186 | SH73A0_PIN_IO_PU_PD(13), |
1187 | SH73A0_PIN_IO_PU_PD(14), |
1188 | SH73A0_PIN_IO_PU_PD(15), |
1189 | SH73A0_PIN_IO_PD(16), |
1190 | SH73A0_PIN_IO_PD(17), |
1191 | SH73A0_PIN_IO_PU(18), |
1192 | SH73A0_PIN_IO_PU(19), |
1193 | SH73A0_PIN_O(20), |
1194 | SH73A0_PIN_O(21), |
1195 | SH73A0_PIN_O(22), |
1196 | SH73A0_PIN_O(23), |
1197 | SH73A0_PIN_O(24), |
1198 | SH73A0_PIN_I_PD(25), |
1199 | SH73A0_PIN_I_PD(26), |
1200 | SH73A0_PIN_IO_PU(27), |
1201 | SH73A0_PIN_IO_PU(28), |
1202 | SH73A0_PIN_IO_PD(29), |
1203 | SH73A0_PIN_IO_PD(30), |
1204 | SH73A0_PIN_IO_PU(31), |
1205 | SH73A0_PIN_IO_PD(32), |
1206 | SH73A0_PIN_I_PU_PD(33), |
1207 | SH73A0_PIN_IO_PD(34), |
1208 | SH73A0_PIN_I_PU_PD(35), |
1209 | SH73A0_PIN_IO_PD(36), |
1210 | SH73A0_PIN_IO(37), |
1211 | SH73A0_PIN_O(38), |
1212 | SH73A0_PIN_I_PU(39), |
1213 | SH73A0_PIN_I_PU_PD(40), |
1214 | SH73A0_PIN_O(41), |
1215 | SH73A0_PIN_IO_PD(42), |
1216 | SH73A0_PIN_IO_PU_PD(43), |
1217 | SH73A0_PIN_IO_PU_PD(44), |
1218 | SH73A0_PIN_IO_PD(45), |
1219 | SH73A0_PIN_IO_PD(46), |
1220 | SH73A0_PIN_IO_PD(47), |
1221 | SH73A0_PIN_I_PD(48), |
1222 | SH73A0_PIN_IO_PU_PD(49), |
1223 | SH73A0_PIN_IO_PD(50), |
1224 | SH73A0_PIN_IO_PD(51), |
1225 | SH73A0_PIN_O(52), |
1226 | SH73A0_PIN_IO_PU_PD(53), |
1227 | SH73A0_PIN_IO_PU_PD(54), |
1228 | SH73A0_PIN_IO_PD(55), |
1229 | SH73A0_PIN_I_PU_PD(56), |
1230 | SH73A0_PIN_IO(57), |
1231 | SH73A0_PIN_IO(58), |
1232 | SH73A0_PIN_IO(59), |
1233 | SH73A0_PIN_IO(60), |
1234 | SH73A0_PIN_IO(61), |
1235 | SH73A0_PIN_IO_PD(62), |
1236 | SH73A0_PIN_IO_PD(63), |
1237 | SH73A0_PIN_IO_PU_PD(64), |
1238 | SH73A0_PIN_IO_PD(65), |
1239 | SH73A0_PIN_IO_PU_PD(66), |
1240 | SH73A0_PIN_IO_PU_PD(67), |
1241 | SH73A0_PIN_IO_PU_PD(68), |
1242 | SH73A0_PIN_IO_PU_PD(69), |
1243 | SH73A0_PIN_IO_PU_PD(70), |
1244 | SH73A0_PIN_IO_PU_PD(71), |
1245 | SH73A0_PIN_IO_PU_PD(72), |
1246 | SH73A0_PIN_I_PU_PD(73), |
1247 | SH73A0_PIN_IO_PU(74), |
1248 | SH73A0_PIN_IO_PU(75), |
1249 | SH73A0_PIN_IO_PU(76), |
1250 | SH73A0_PIN_IO_PU(77), |
1251 | SH73A0_PIN_IO_PU(78), |
1252 | SH73A0_PIN_IO_PU(79), |
1253 | SH73A0_PIN_IO_PU(80), |
1254 | SH73A0_PIN_IO_PU(81), |
1255 | SH73A0_PIN_IO_PU(82), |
1256 | SH73A0_PIN_IO_PU(83), |
1257 | SH73A0_PIN_IO_PU(84), |
1258 | SH73A0_PIN_IO_PU(85), |
1259 | SH73A0_PIN_IO_PU(86), |
1260 | SH73A0_PIN_IO_PU(87), |
1261 | SH73A0_PIN_IO_PU(88), |
1262 | SH73A0_PIN_IO_PU(89), |
1263 | SH73A0_PIN_O(90), |
1264 | SH73A0_PIN_IO_PU(91), |
1265 | SH73A0_PIN_O(92), |
1266 | SH73A0_PIN_IO_PU(93), |
1267 | SH73A0_PIN_O(94), |
1268 | SH73A0_PIN_I_PU_PD(95), |
1269 | SH73A0_PIN_IO(96), |
1270 | SH73A0_PIN_IO(97), |
1271 | SH73A0_PIN_IO(98), |
1272 | SH73A0_PIN_I_PU(99), |
1273 | SH73A0_PIN_O(100), |
1274 | SH73A0_PIN_O(101), |
1275 | SH73A0_PIN_I_PU(102), |
1276 | SH73A0_PIN_IO_PD(103), |
1277 | SH73A0_PIN_I_PU_PD(104), |
1278 | SH73A0_PIN_I_PD(105), |
1279 | SH73A0_PIN_I_PD(106), |
1280 | SH73A0_PIN_I_PU_PD(107), |
1281 | SH73A0_PIN_I_PU_PD(108), |
1282 | SH73A0_PIN_IO_PD(109), |
1283 | SH73A0_PIN_IO_PD(110), |
1284 | SH73A0_PIN_IO_PU_PD(111), |
1285 | SH73A0_PIN_IO_PU_PD(112), |
1286 | SH73A0_PIN_IO_PU_PD(113), |
1287 | SH73A0_PIN_IO_PD(114), |
1288 | SH73A0_PIN_IO_PU(115), |
1289 | SH73A0_PIN_IO_PU(116), |
1290 | SH73A0_PIN_IO_PU_PD(117), |
1291 | SH73A0_PIN_IO_PU_PD(118), |
1292 | SH73A0_PIN_IO_PD(128), |
1293 | SH73A0_PIN_IO_PD(129), |
1294 | SH73A0_PIN_IO_PU_PD(130), |
1295 | SH73A0_PIN_IO_PD(131), |
1296 | SH73A0_PIN_IO_PD(132), |
1297 | SH73A0_PIN_IO_PD(133), |
1298 | SH73A0_PIN_IO_PU_PD(134), |
1299 | SH73A0_PIN_IO_PU_PD(135), |
1300 | SH73A0_PIN_IO_PU_PD(136), |
1301 | SH73A0_PIN_IO_PU_PD(137), |
1302 | SH73A0_PIN_IO_PD(138), |
1303 | SH73A0_PIN_IO_PD(139), |
1304 | SH73A0_PIN_IO_PD(140), |
1305 | SH73A0_PIN_IO_PD(141), |
1306 | SH73A0_PIN_IO_PD(142), |
1307 | SH73A0_PIN_IO_PD(143), |
1308 | SH73A0_PIN_IO_PU_PD(144), |
1309 | SH73A0_PIN_IO_PD(145), |
1310 | SH73A0_PIN_IO_PU_PD(146), |
1311 | SH73A0_PIN_IO_PU_PD(147), |
1312 | SH73A0_PIN_IO_PU_PD(148), |
1313 | SH73A0_PIN_IO_PU_PD(149), |
1314 | SH73A0_PIN_I_PU_PD(150), |
1315 | SH73A0_PIN_IO_PU_PD(151), |
1316 | SH73A0_PIN_IO_PU_PD(152), |
1317 | SH73A0_PIN_IO_PD(153), |
1318 | SH73A0_PIN_IO_PD(154), |
1319 | SH73A0_PIN_I_PU_PD(155), |
1320 | SH73A0_PIN_IO_PU_PD(156), |
1321 | SH73A0_PIN_I_PD(157), |
1322 | SH73A0_PIN_IO_PD(158), |
1323 | SH73A0_PIN_IO_PU_PD(159), |
1324 | SH73A0_PIN_IO_PU_PD(160), |
1325 | SH73A0_PIN_I_PU_PD(161), |
1326 | SH73A0_PIN_I_PU_PD(162), |
1327 | SH73A0_PIN_IO_PU_PD(163), |
1328 | SH73A0_PIN_I_PU_PD(164), |
1329 | SH73A0_PIN_IO_PD(192), |
1330 | SH73A0_PIN_IO_PU_PD(193), |
1331 | SH73A0_PIN_IO_PD(194), |
1332 | SH73A0_PIN_IO_PU_PD(195), |
1333 | SH73A0_PIN_IO_PD(196), |
1334 | SH73A0_PIN_IO_PD(197), |
1335 | SH73A0_PIN_IO_PD(198), |
1336 | SH73A0_PIN_IO_PD(199), |
1337 | SH73A0_PIN_IO_PU_PD(200), |
1338 | SH73A0_PIN_IO_PU_PD(201), |
1339 | SH73A0_PIN_IO_PU_PD(202), |
1340 | SH73A0_PIN_IO_PU_PD(203), |
1341 | SH73A0_PIN_IO_PU_PD(204), |
1342 | SH73A0_PIN_IO_PU_PD(205), |
1343 | SH73A0_PIN_IO_PU_PD(206), |
1344 | SH73A0_PIN_IO_PD(207), |
1345 | SH73A0_PIN_IO_PD(208), |
1346 | SH73A0_PIN_IO_PD(209), |
1347 | SH73A0_PIN_IO_PD(210), |
1348 | SH73A0_PIN_IO_PD(211), |
1349 | SH73A0_PIN_IO_PD(212), |
1350 | SH73A0_PIN_IO_PD(213), |
1351 | SH73A0_PIN_IO_PU_PD(214), |
1352 | SH73A0_PIN_IO_PU_PD(215), |
1353 | SH73A0_PIN_IO_PD(216), |
1354 | SH73A0_PIN_IO_PD(217), |
1355 | SH73A0_PIN_O(218), |
1356 | SH73A0_PIN_IO_PD(219), |
1357 | SH73A0_PIN_IO_PD(220), |
1358 | SH73A0_PIN_IO_PU_PD(221), |
1359 | SH73A0_PIN_IO_PU_PD(222), |
1360 | SH73A0_PIN_I_PU_PD(223), |
1361 | SH73A0_PIN_I_PU_PD(224), |
1362 | SH73A0_PIN_IO_PU_PD(225), |
1363 | SH73A0_PIN_O(226), |
1364 | SH73A0_PIN_IO_PU_PD(227), |
1365 | SH73A0_PIN_I_PU_PD(228), |
1366 | SH73A0_PIN_I_PD(229), |
1367 | SH73A0_PIN_IO(230), |
1368 | SH73A0_PIN_IO_PU_PD(231), |
1369 | SH73A0_PIN_IO_PU_PD(232), |
1370 | SH73A0_PIN_I_PU_PD(233), |
1371 | SH73A0_PIN_IO_PU_PD(234), |
1372 | SH73A0_PIN_IO_PU_PD(235), |
1373 | SH73A0_PIN_IO_PU_PD(236), |
1374 | SH73A0_PIN_IO_PD(237), |
1375 | SH73A0_PIN_IO_PU_PD(238), |
1376 | SH73A0_PIN_IO_PU_PD(239), |
1377 | SH73A0_PIN_IO_PU_PD(240), |
1378 | SH73A0_PIN_O(241), |
1379 | SH73A0_PIN_I_PD(242), |
1380 | SH73A0_PIN_IO_PU_PD(243), |
1381 | SH73A0_PIN_IO_PU_PD(244), |
1382 | SH73A0_PIN_IO_PU_PD(245), |
1383 | SH73A0_PIN_IO_PU_PD(246), |
1384 | SH73A0_PIN_IO_PU_PD(247), |
1385 | SH73A0_PIN_IO_PU_PD(248), |
1386 | SH73A0_PIN_IO_PU_PD(249), |
1387 | SH73A0_PIN_IO_PU_PD(250), |
1388 | SH73A0_PIN_IO_PU_PD(251), |
1389 | SH73A0_PIN_IO_PU_PD(252), |
1390 | SH73A0_PIN_IO_PU_PD(253), |
1391 | SH73A0_PIN_IO_PU_PD(254), |
1392 | SH73A0_PIN_IO_PU_PD(255), |
1393 | SH73A0_PIN_IO_PU_PD(256), |
1394 | SH73A0_PIN_IO_PU_PD(257), |
1395 | SH73A0_PIN_IO_PU_PD(258), |
1396 | SH73A0_PIN_IO_PU_PD(259), |
1397 | SH73A0_PIN_IO_PU_PD(260), |
1398 | SH73A0_PIN_IO_PU_PD(261), |
1399 | SH73A0_PIN_IO_PU_PD(262), |
1400 | SH73A0_PIN_IO_PU_PD(263), |
1401 | SH73A0_PIN_IO_PU_PD(264), |
1402 | SH73A0_PIN_IO_PU_PD(265), |
1403 | SH73A0_PIN_IO_PU_PD(266), |
1404 | SH73A0_PIN_IO_PU_PD(267), |
1405 | SH73A0_PIN_IO_PU_PD(268), |
1406 | SH73A0_PIN_IO_PU_PD(269), |
1407 | SH73A0_PIN_IO_PU_PD(270), |
1408 | SH73A0_PIN_IO_PU_PD(271), |
1409 | SH73A0_PIN_IO_PU_PD(272), |
1410 | SH73A0_PIN_IO_PU_PD(273), |
1411 | SH73A0_PIN_IO_PU_PD(274), |
1412 | SH73A0_PIN_IO_PU_PD(275), |
1413 | SH73A0_PIN_IO_PU_PD(276), |
1414 | SH73A0_PIN_IO_PU_PD(277), |
1415 | SH73A0_PIN_IO_PU_PD(278), |
1416 | SH73A0_PIN_IO_PU_PD(279), |
1417 | SH73A0_PIN_IO_PU_PD(280), |
1418 | SH73A0_PIN_O(281), |
1419 | SH73A0_PIN_O(282), |
1420 | SH73A0_PIN_I_PU(288), |
1421 | SH73A0_PIN_IO_PU_PD(289), |
1422 | SH73A0_PIN_IO_PU_PD(290), |
1423 | SH73A0_PIN_IO_PU_PD(291), |
1424 | SH73A0_PIN_IO_PU_PD(292), |
1425 | SH73A0_PIN_IO_PU_PD(293), |
1426 | SH73A0_PIN_IO_PU_PD(294), |
1427 | SH73A0_PIN_IO_PU_PD(295), |
1428 | SH73A0_PIN_IO_PU_PD(296), |
1429 | SH73A0_PIN_IO_PU_PD(297), |
1430 | SH73A0_PIN_IO_PU_PD(298), |
1431 | SH73A0_PIN_IO_PU_PD(299), |
1432 | SH73A0_PIN_IO_PU_PD(300), |
1433 | SH73A0_PIN_IO_PU_PD(301), |
1434 | SH73A0_PIN_IO_PU_PD(302), |
1435 | SH73A0_PIN_IO_PU_PD(303), |
1436 | SH73A0_PIN_IO_PU_PD(304), |
1437 | SH73A0_PIN_IO_PU_PD(305), |
1438 | SH73A0_PIN_O(306), |
1439 | SH73A0_PIN_O(307), |
1440 | SH73A0_PIN_I_PU(308), |
1441 | SH73A0_PIN_O(309), |
1442 | |
1443 | /* Pins not associated with a GPIO port */ |
1444 | PINMUX_NOGP_ALL(), |
1445 | }; |
1446 | |
1447 | /* - BSC -------------------------------------------------------------------- */ |
1448 | static const unsigned int bsc_data_0_7_pins[] = { |
1449 | /* D[0:7] */ |
1450 | 74, 75, 76, 77, 78, 79, 80, 81, |
1451 | }; |
1452 | static const unsigned int bsc_data_0_7_mux[] = { |
1453 | D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, |
1454 | D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, |
1455 | }; |
1456 | static const unsigned int bsc_data_8_15_pins[] = { |
1457 | /* D[8:15] */ |
1458 | 82, 83, 84, 85, 86, 87, 88, 89, |
1459 | }; |
1460 | static const unsigned int bsc_data_8_15_mux[] = { |
1461 | D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, |
1462 | D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, |
1463 | }; |
1464 | static const unsigned int bsc_cs4_pins[] = { |
1465 | /* CS */ |
1466 | 90, |
1467 | }; |
1468 | static const unsigned int bsc_cs4_mux[] = { |
1469 | CS4__MARK, |
1470 | }; |
1471 | static const unsigned int bsc_cs5_a_pins[] = { |
1472 | /* CS */ |
1473 | 91, |
1474 | }; |
1475 | static const unsigned int bsc_cs5_a_mux[] = { |
1476 | CS5A__MARK, |
1477 | }; |
1478 | static const unsigned int bsc_cs5_b_pins[] = { |
1479 | /* CS */ |
1480 | 92, |
1481 | }; |
1482 | static const unsigned int bsc_cs5_b_mux[] = { |
1483 | CS5B__MARK, |
1484 | }; |
1485 | static const unsigned int bsc_cs6_a_pins[] = { |
1486 | /* CS */ |
1487 | 94, |
1488 | }; |
1489 | static const unsigned int bsc_cs6_a_mux[] = { |
1490 | CS6A__MARK, |
1491 | }; |
1492 | static const unsigned int bsc_cs6_b_pins[] = { |
1493 | /* CS */ |
1494 | 93, |
1495 | }; |
1496 | static const unsigned int bsc_cs6_b_mux[] = { |
1497 | CS6B__MARK, |
1498 | }; |
1499 | static const unsigned int bsc_rd_pins[] = { |
1500 | /* RD */ |
1501 | 96, |
1502 | }; |
1503 | static const unsigned int bsc_rd_mux[] = { |
1504 | RD__FSC_MARK, |
1505 | }; |
1506 | static const unsigned int bsc_rdwr_0_pins[] = { |
1507 | /* RDWR */ |
1508 | 91, |
1509 | }; |
1510 | static const unsigned int bsc_rdwr_0_mux[] = { |
1511 | PORT91_RDWR_MARK, |
1512 | }; |
1513 | static const unsigned int bsc_rdwr_1_pins[] = { |
1514 | /* RDWR */ |
1515 | 97, |
1516 | }; |
1517 | static const unsigned int bsc_rdwr_1_mux[] = { |
1518 | RDWR_FWE_MARK, |
1519 | }; |
1520 | static const unsigned int bsc_rdwr_2_pins[] = { |
1521 | /* RDWR */ |
1522 | 149, |
1523 | }; |
1524 | static const unsigned int bsc_rdwr_2_mux[] = { |
1525 | PORT149_RDWR_MARK, |
1526 | }; |
1527 | static const unsigned int bsc_we0_pins[] = { |
1528 | /* WE0 */ |
1529 | 97, |
1530 | }; |
1531 | static const unsigned int bsc_we0_mux[] = { |
1532 | WE0__FWE_MARK, |
1533 | }; |
1534 | static const unsigned int bsc_we1_pins[] = { |
1535 | /* WE1 */ |
1536 | 98, |
1537 | }; |
1538 | static const unsigned int bsc_we1_mux[] = { |
1539 | WE1__MARK, |
1540 | }; |
1541 | /* - FSIA ------------------------------------------------------------------- */ |
1542 | static const unsigned int fsia_mclk_in_pins[] = { |
1543 | /* CK */ |
1544 | 49, |
1545 | }; |
1546 | static const unsigned int fsia_mclk_in_mux[] = { |
1547 | FSIACK_MARK, |
1548 | }; |
1549 | static const unsigned int fsia_mclk_out_pins[] = { |
1550 | /* OMC */ |
1551 | 49, |
1552 | }; |
1553 | static const unsigned int fsia_mclk_out_mux[] = { |
1554 | FSIAOMC_MARK, |
1555 | }; |
1556 | static const unsigned int fsia_sclk_in_pins[] = { |
1557 | /* ILR, IBT */ |
1558 | 50, 51, |
1559 | }; |
1560 | static const unsigned int fsia_sclk_in_mux[] = { |
1561 | FSIAILR_MARK, FSIAIBT_MARK, |
1562 | }; |
1563 | static const unsigned int fsia_sclk_out_pins[] = { |
1564 | /* OLR, OBT */ |
1565 | 50, 51, |
1566 | }; |
1567 | static const unsigned int fsia_sclk_out_mux[] = { |
1568 | FSIAOLR_MARK, FSIAOBT_MARK, |
1569 | }; |
1570 | static const unsigned int fsia_data_in_pins[] = { |
1571 | /* ISLD */ |
1572 | 55, |
1573 | }; |
1574 | static const unsigned int fsia_data_in_mux[] = { |
1575 | FSIAISLD_MARK, |
1576 | }; |
1577 | static const unsigned int fsia_data_out_pins[] = { |
1578 | /* OSLD */ |
1579 | 52, |
1580 | }; |
1581 | static const unsigned int fsia_data_out_mux[] = { |
1582 | FSIAOSLD_MARK, |
1583 | }; |
1584 | static const unsigned int fsia_spdif_pins[] = { |
1585 | /* SPDIF */ |
1586 | 53, |
1587 | }; |
1588 | static const unsigned int fsia_spdif_mux[] = { |
1589 | FSIASPDIF_MARK, |
1590 | }; |
1591 | /* - FSIB ------------------------------------------------------------------- */ |
1592 | static const unsigned int fsib_mclk_in_pins[] = { |
1593 | /* CK */ |
1594 | 54, |
1595 | }; |
1596 | static const unsigned int fsib_mclk_in_mux[] = { |
1597 | FSIBCK_MARK, |
1598 | }; |
1599 | static const unsigned int fsib_mclk_out_pins[] = { |
1600 | /* OMC */ |
1601 | 54, |
1602 | }; |
1603 | static const unsigned int fsib_mclk_out_mux[] = { |
1604 | FSIBOMC_MARK, |
1605 | }; |
1606 | static const unsigned int fsib_sclk_in_pins[] = { |
1607 | /* ILR, IBT */ |
1608 | 37, 36, |
1609 | }; |
1610 | static const unsigned int fsib_sclk_in_mux[] = { |
1611 | FSIBILR_MARK, FSIBIBT_MARK, |
1612 | }; |
1613 | static const unsigned int fsib_sclk_out_pins[] = { |
1614 | /* OLR, OBT */ |
1615 | 37, 36, |
1616 | }; |
1617 | static const unsigned int fsib_sclk_out_mux[] = { |
1618 | FSIBOLR_MARK, FSIBOBT_MARK, |
1619 | }; |
1620 | static const unsigned int fsib_data_in_pins[] = { |
1621 | /* ISLD */ |
1622 | 39, |
1623 | }; |
1624 | static const unsigned int fsib_data_in_mux[] = { |
1625 | FSIBISLD_MARK, |
1626 | }; |
1627 | static const unsigned int fsib_data_out_pins[] = { |
1628 | /* OSLD */ |
1629 | 38, |
1630 | }; |
1631 | static const unsigned int fsib_data_out_mux[] = { |
1632 | FSIBOSLD_MARK, |
1633 | }; |
1634 | static const unsigned int fsib_spdif_pins[] = { |
1635 | /* SPDIF */ |
1636 | 53, |
1637 | }; |
1638 | static const unsigned int fsib_spdif_mux[] = { |
1639 | FSIBSPDIF_MARK, |
1640 | }; |
1641 | /* - FSIC ------------------------------------------------------------------- */ |
1642 | static const unsigned int fsic_mclk_in_pins[] = { |
1643 | /* CK */ |
1644 | 54, |
1645 | }; |
1646 | static const unsigned int fsic_mclk_in_mux[] = { |
1647 | FSICCK_MARK, |
1648 | }; |
1649 | static const unsigned int fsic_mclk_out_pins[] = { |
1650 | /* OMC */ |
1651 | 54, |
1652 | }; |
1653 | static const unsigned int fsic_mclk_out_mux[] = { |
1654 | FSICOMC_MARK, |
1655 | }; |
1656 | static const unsigned int fsic_sclk_in_pins[] = { |
1657 | /* ILR, IBT */ |
1658 | 46, 45, |
1659 | }; |
1660 | static const unsigned int fsic_sclk_in_mux[] = { |
1661 | FSICILR_MARK, FSICIBT_MARK, |
1662 | }; |
1663 | static const unsigned int fsic_sclk_out_pins[] = { |
1664 | /* OLR, OBT */ |
1665 | 46, 45, |
1666 | }; |
1667 | static const unsigned int fsic_sclk_out_mux[] = { |
1668 | FSICOLR_MARK, FSICOBT_MARK, |
1669 | }; |
1670 | static const unsigned int fsic_data_in_pins[] = { |
1671 | /* ISLD */ |
1672 | 48, |
1673 | }; |
1674 | static const unsigned int fsic_data_in_mux[] = { |
1675 | FSICISLD_MARK, |
1676 | }; |
1677 | static const unsigned int fsic_data_out_pins[] = { |
1678 | /* OSLD, OSLDT1, OSLDT2, OSLDT3 */ |
1679 | 47, 44, 42, 16, |
1680 | }; |
1681 | static const unsigned int fsic_data_out_mux[] = { |
1682 | FSICOSLD_MARK, FSICOSLDT1_MARK, FSICOSLDT2_MARK, FSICOSLDT3_MARK, |
1683 | }; |
1684 | static const unsigned int fsic_spdif_0_pins[] = { |
1685 | /* SPDIF */ |
1686 | 53, |
1687 | }; |
1688 | static const unsigned int fsic_spdif_0_mux[] = { |
1689 | PORT53_FSICSPDIF_MARK, |
1690 | }; |
1691 | static const unsigned int fsic_spdif_1_pins[] = { |
1692 | /* SPDIF */ |
1693 | 47, |
1694 | }; |
1695 | static const unsigned int fsic_spdif_1_mux[] = { |
1696 | PORT47_FSICSPDIF_MARK, |
1697 | }; |
1698 | /* - FSID ------------------------------------------------------------------- */ |
1699 | static const unsigned int fsid_sclk_in_pins[] = { |
1700 | /* ILR, IBT */ |
1701 | 46, 45, |
1702 | }; |
1703 | static const unsigned int fsid_sclk_in_mux[] = { |
1704 | FSIDILR_MARK, FSIDIBT_MARK, |
1705 | }; |
1706 | static const unsigned int fsid_sclk_out_pins[] = { |
1707 | /* OLR, OBT */ |
1708 | 46, 45, |
1709 | }; |
1710 | static const unsigned int fsid_sclk_out_mux[] = { |
1711 | FSIDOLR_MARK, FSIDOBT_MARK, |
1712 | }; |
1713 | static const unsigned int fsid_data_in_pins[] = { |
1714 | /* ISLD */ |
1715 | 48, |
1716 | }; |
1717 | static const unsigned int fsid_data_in_mux[] = { |
1718 | FSIDISLD_MARK, |
1719 | }; |
1720 | /* - I2C2 ------------------------------------------------------------------- */ |
1721 | static const unsigned int i2c2_0_pins[] = { |
1722 | /* SCL, SDA */ |
1723 | 237, 236, |
1724 | }; |
1725 | static const unsigned int i2c2_0_mux[] = { |
1726 | PORT237_I2C_SCL2_MARK, PORT236_I2C_SDA2_MARK, |
1727 | }; |
1728 | static const unsigned int i2c2_1_pins[] = { |
1729 | /* SCL, SDA */ |
1730 | 27, 28, |
1731 | }; |
1732 | static const unsigned int i2c2_1_mux[] = { |
1733 | PORT27_I2C_SCL2_MARK, PORT28_I2C_SDA2_MARK, |
1734 | }; |
1735 | static const unsigned int i2c2_2_pins[] = { |
1736 | /* SCL, SDA */ |
1737 | 115, 116, |
1738 | }; |
1739 | static const unsigned int i2c2_2_mux[] = { |
1740 | PORT115_I2C_SCL2_MARK, PORT116_I2C_SDA2_MARK, |
1741 | }; |
1742 | /* - I2C3 ------------------------------------------------------------------- */ |
1743 | static const unsigned int i2c3_0_pins[] = { |
1744 | /* SCL, SDA */ |
1745 | 248, 249, |
1746 | }; |
1747 | static const unsigned int i2c3_0_mux[] = { |
1748 | PORT248_I2C_SCL3_MARK, PORT249_I2C_SDA3_MARK, |
1749 | }; |
1750 | static const unsigned int i2c3_1_pins[] = { |
1751 | /* SCL, SDA */ |
1752 | 27, 28, |
1753 | }; |
1754 | static const unsigned int i2c3_1_mux[] = { |
1755 | PORT27_I2C_SCL3_MARK, PORT28_I2C_SDA3_MARK, |
1756 | }; |
1757 | static const unsigned int i2c3_2_pins[] = { |
1758 | /* SCL, SDA */ |
1759 | 115, 116, |
1760 | }; |
1761 | static const unsigned int i2c3_2_mux[] = { |
1762 | PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK, |
1763 | }; |
1764 | /* - IrDA ------------------------------------------------------------------- */ |
1765 | static const unsigned int irda_0_pins[] = { |
1766 | /* OUT, IN, FIRSEL */ |
1767 | 241, 242, 243, |
1768 | }; |
1769 | static const unsigned int irda_0_mux[] = { |
1770 | PORT241_IRDA_OUT_MARK, PORT242_IRDA_IN_MARK, PORT243_IRDA_FIRSEL_MARK, |
1771 | }; |
1772 | static const unsigned int irda_1_pins[] = { |
1773 | /* OUT, IN, FIRSEL */ |
1774 | 49, 53, 54, |
1775 | }; |
1776 | static const unsigned int irda_1_mux[] = { |
1777 | PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK, |
1778 | }; |
1779 | /* - KEYSC ------------------------------------------------------------------ */ |
1780 | static const unsigned int keysc_in_pins[] = { |
1781 | /* KEYIN[0:7] */ |
1782 | 66, 67, 68, 69, 70, 71, 72, 73, |
1783 | }; |
1784 | static const unsigned int keysc_in_mux[] = { |
1785 | KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, |
1786 | KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK, |
1787 | }; |
1788 | static const unsigned int keysc_out04_pins[] = { |
1789 | /* KEYOUT[0:4] */ |
1790 | 65, 64, 63, 62, 61, |
1791 | }; |
1792 | static const unsigned int keysc_out04_mux[] = { |
1793 | KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, KEYOUT4_MARK, |
1794 | }; |
1795 | static const unsigned int keysc_out5_pins[] = { |
1796 | /* KEYOUT5 */ |
1797 | 60, |
1798 | }; |
1799 | static const unsigned int keysc_out5_mux[] = { |
1800 | KEYOUT5_MARK, |
1801 | }; |
1802 | static const unsigned int keysc_out6_0_pins[] = { |
1803 | /* KEYOUT6 */ |
1804 | 59, |
1805 | }; |
1806 | static const unsigned int keysc_out6_0_mux[] = { |
1807 | PORT59_KEYOUT6_MARK, |
1808 | }; |
1809 | static const unsigned int keysc_out6_1_pins[] = { |
1810 | /* KEYOUT6 */ |
1811 | 131, |
1812 | }; |
1813 | static const unsigned int keysc_out6_1_mux[] = { |
1814 | PORT131_KEYOUT6_MARK, |
1815 | }; |
1816 | static const unsigned int keysc_out6_2_pins[] = { |
1817 | /* KEYOUT6 */ |
1818 | 143, |
1819 | }; |
1820 | static const unsigned int keysc_out6_2_mux[] = { |
1821 | PORT143_KEYOUT6_MARK, |
1822 | }; |
1823 | static const unsigned int keysc_out7_0_pins[] = { |
1824 | /* KEYOUT7 */ |
1825 | 58, |
1826 | }; |
1827 | static const unsigned int keysc_out7_0_mux[] = { |
1828 | PORT58_KEYOUT7_MARK, |
1829 | }; |
1830 | static const unsigned int keysc_out7_1_pins[] = { |
1831 | /* KEYOUT7 */ |
1832 | 132, |
1833 | }; |
1834 | static const unsigned int keysc_out7_1_mux[] = { |
1835 | PORT132_KEYOUT7_MARK, |
1836 | }; |
1837 | static const unsigned int keysc_out7_2_pins[] = { |
1838 | /* KEYOUT7 */ |
1839 | 144, |
1840 | }; |
1841 | static const unsigned int keysc_out7_2_mux[] = { |
1842 | PORT144_KEYOUT7_MARK, |
1843 | }; |
1844 | static const unsigned int keysc_out8_0_pins[] = { |
1845 | /* KEYOUT8 */ |
1846 | PIN_A11, |
1847 | }; |
1848 | static const unsigned int keysc_out8_0_mux[] = { |
1849 | KEYOUT8_MARK, |
1850 | }; |
1851 | static const unsigned int keysc_out8_1_pins[] = { |
1852 | /* KEYOUT8 */ |
1853 | 136, |
1854 | }; |
1855 | static const unsigned int keysc_out8_1_mux[] = { |
1856 | PORT136_KEYOUT8_MARK, |
1857 | }; |
1858 | static const unsigned int keysc_out8_2_pins[] = { |
1859 | /* KEYOUT8 */ |
1860 | 138, |
1861 | }; |
1862 | static const unsigned int keysc_out8_2_mux[] = { |
1863 | PORT138_KEYOUT8_MARK, |
1864 | }; |
1865 | static const unsigned int keysc_out9_0_pins[] = { |
1866 | /* KEYOUT9 */ |
1867 | 137, |
1868 | }; |
1869 | static const unsigned int keysc_out9_0_mux[] = { |
1870 | PORT137_KEYOUT9_MARK, |
1871 | }; |
1872 | static const unsigned int keysc_out9_1_pins[] = { |
1873 | /* KEYOUT9 */ |
1874 | 139, |
1875 | }; |
1876 | static const unsigned int keysc_out9_1_mux[] = { |
1877 | PORT139_KEYOUT9_MARK, |
1878 | }; |
1879 | static const unsigned int keysc_out9_2_pins[] = { |
1880 | /* KEYOUT9 */ |
1881 | 149, |
1882 | }; |
1883 | static const unsigned int keysc_out9_2_mux[] = { |
1884 | PORT149_KEYOUT9_MARK, |
1885 | }; |
1886 | static const unsigned int keysc_out10_0_pins[] = { |
1887 | /* KEYOUT10 */ |
1888 | 132, |
1889 | }; |
1890 | static const unsigned int keysc_out10_0_mux[] = { |
1891 | PORT132_KEYOUT10_MARK, |
1892 | }; |
1893 | static const unsigned int keysc_out10_1_pins[] = { |
1894 | /* KEYOUT10 */ |
1895 | 142, |
1896 | }; |
1897 | static const unsigned int keysc_out10_1_mux[] = { |
1898 | PORT142_KEYOUT10_MARK, |
1899 | }; |
1900 | static const unsigned int keysc_out11_0_pins[] = { |
1901 | /* KEYOUT11 */ |
1902 | 131, |
1903 | }; |
1904 | static const unsigned int keysc_out11_0_mux[] = { |
1905 | PORT131_KEYOUT11_MARK, |
1906 | }; |
1907 | static const unsigned int keysc_out11_1_pins[] = { |
1908 | /* KEYOUT11 */ |
1909 | 143, |
1910 | }; |
1911 | static const unsigned int keysc_out11_1_mux[] = { |
1912 | PORT143_KEYOUT11_MARK, |
1913 | }; |
1914 | /* - LCD -------------------------------------------------------------------- */ |
1915 | static const unsigned int lcd_data_pins[] = { |
1916 | /* D[0:23] */ |
1917 | 192, 193, 194, 195, 196, 197, 198, 199, |
1918 | 200, 201, 202, 203, 204, 205, 206, 207, |
1919 | 208, 209, 210, 211, 212, 213, 214, 215 |
1920 | }; |
1921 | static const unsigned int lcd_data_mux[] = { |
1922 | LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, |
1923 | LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, |
1924 | LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, |
1925 | LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, |
1926 | LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK, |
1927 | LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK, |
1928 | }; |
1929 | static const unsigned int lcd_display_pins[] = { |
1930 | /* DON */ |
1931 | 222, |
1932 | }; |
1933 | static const unsigned int lcd_display_mux[] = { |
1934 | LCDDON_MARK, |
1935 | }; |
1936 | static const unsigned int lcd_lclk_pins[] = { |
1937 | /* LCLK */ |
1938 | 221, |
1939 | }; |
1940 | static const unsigned int lcd_lclk_mux[] = { |
1941 | LCDLCLK_MARK, |
1942 | }; |
1943 | static const unsigned int lcd_sync_pins[] = { |
1944 | /* VSYN, HSYN, DCK, DISP */ |
1945 | 220, 218, 216, 219, |
1946 | }; |
1947 | static const unsigned int lcd_sync_mux[] = { |
1948 | LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK, |
1949 | }; |
1950 | static const unsigned int lcd_sys_pins[] = { |
1951 | /* CS, WR, RD, RS */ |
1952 | 218, 216, 217, 219, |
1953 | }; |
1954 | static const unsigned int lcd_sys_mux[] = { |
1955 | LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK, |
1956 | }; |
1957 | /* - LCD2 ------------------------------------------------------------------- */ |
1958 | static const unsigned int lcd2_data_pins[] = { |
1959 | /* D[0:23] */ |
1960 | 128, 129, 142, 143, 144, 145, 138, 139, |
1961 | 140, 141, 130, 131, 132, 133, 134, 135, |
1962 | 136, 137, 146, 147, 234, 235, 238, 239 |
1963 | }; |
1964 | static const unsigned int lcd2_data_mux[] = { |
1965 | LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, |
1966 | LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, |
1967 | LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK, |
1968 | LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK, |
1969 | LCD2D16_MARK, LCD2D17_MARK, LCD2D18_MARK, LCD2D19_MARK, |
1970 | LCD2D20_MARK, LCD2D21_MARK, LCD2D22_MARK, LCD2D23_MARK, |
1971 | }; |
1972 | static const unsigned int lcd2_sync_0_pins[] = { |
1973 | /* VSYN, HSYN, DCK, DISP */ |
1974 | 128, 129, 146, 145, |
1975 | }; |
1976 | static const unsigned int lcd2_sync_0_mux[] = { |
1977 | PORT128_LCD2VSYN_MARK, PORT129_LCD2HSYN_MARK, |
1978 | LCD2DCK_MARK, PORT145_LCD2DISP_MARK, |
1979 | }; |
1980 | static const unsigned int lcd2_sync_1_pins[] = { |
1981 | /* VSYN, HSYN, DCK, DISP */ |
1982 | 222, 221, 219, 217, |
1983 | }; |
1984 | static const unsigned int lcd2_sync_1_mux[] = { |
1985 | PORT222_LCD2VSYN_MARK, PORT221_LCD2HSYN_MARK, |
1986 | LCD2DCK_2_MARK, PORT217_LCD2DISP_MARK, |
1987 | }; |
1988 | static const unsigned int lcd2_sys_0_pins[] = { |
1989 | /* CS, WR, RD, RS */ |
1990 | 129, 146, 147, 145, |
1991 | }; |
1992 | static const unsigned int lcd2_sys_0_mux[] = { |
1993 | PORT129_LCD2CS__MARK, PORT146_LCD2WR__MARK, |
1994 | LCD2RD__MARK, PORT145_LCD2RS_MARK, |
1995 | }; |
1996 | static const unsigned int lcd2_sys_1_pins[] = { |
1997 | /* CS, WR, RD, RS */ |
1998 | 221, 219, 147, 217, |
1999 | }; |
2000 | static const unsigned int lcd2_sys_1_mux[] = { |
2001 | PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK, |
2002 | LCD2RD__MARK, PORT217_LCD2RS_MARK, |
2003 | }; |
2004 | /* - MMCIF ------------------------------------------------------------------ */ |
2005 | static const unsigned int mmc0_data_0_pins[] = { |
2006 | /* D[0:7] */ |
2007 | 271, 272, 273, 274, 275, 276, 277, 278, |
2008 | }; |
2009 | static const unsigned int mmc0_data_0_mux[] = { |
2010 | MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, |
2011 | MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK, |
2012 | }; |
2013 | static const unsigned int mmc0_ctrl_0_pins[] = { |
2014 | /* CMD, CLK */ |
2015 | 279, 270, |
2016 | }; |
2017 | static const unsigned int mmc0_ctrl_0_mux[] = { |
2018 | MMCCMD0_MARK, MMCCLK0_MARK, |
2019 | }; |
2020 | |
2021 | static const unsigned int mmc0_data_1_pins[] = { |
2022 | /* D[0:7] */ |
2023 | 305, 304, 303, 302, 301, 300, 299, 298, |
2024 | }; |
2025 | static const unsigned int mmc0_data_1_mux[] = { |
2026 | MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, |
2027 | MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK, |
2028 | }; |
2029 | static const unsigned int mmc0_ctrl_1_pins[] = { |
2030 | /* CMD, CLK */ |
2031 | 297, 289, |
2032 | }; |
2033 | static const unsigned int mmc0_ctrl_1_mux[] = { |
2034 | MMCCMD1_MARK, MMCCLK1_MARK, |
2035 | }; |
2036 | /* - MSIOF0 ----------------------------------------------------------------- */ |
2037 | static const unsigned int msiof0_rsck_pins[] = { |
2038 | /* RSCK */ |
2039 | 66, |
2040 | }; |
2041 | static const unsigned int msiof0_rsck_mux[] = { |
2042 | MSIOF0_RSCK_MARK, |
2043 | }; |
2044 | static const unsigned int msiof0_tsck_pins[] = { |
2045 | /* TSCK */ |
2046 | 64, |
2047 | }; |
2048 | static const unsigned int msiof0_tsck_mux[] = { |
2049 | MSIOF0_TSCK_MARK, |
2050 | }; |
2051 | static const unsigned int msiof0_rsync_pins[] = { |
2052 | /* RSYNC */ |
2053 | 67, |
2054 | }; |
2055 | static const unsigned int msiof0_rsync_mux[] = { |
2056 | MSIOF0_RSYNC_MARK, |
2057 | }; |
2058 | static const unsigned int msiof0_tsync_pins[] = { |
2059 | /* TSYNC */ |
2060 | 63, |
2061 | }; |
2062 | static const unsigned int msiof0_tsync_mux[] = { |
2063 | MSIOF0_TSYNC_MARK, |
2064 | }; |
2065 | static const unsigned int msiof0_ss1_pins[] = { |
2066 | /* SS1 */ |
2067 | 62, |
2068 | }; |
2069 | static const unsigned int msiof0_ss1_mux[] = { |
2070 | MSIOF0_SS1_MARK, |
2071 | }; |
2072 | static const unsigned int msiof0_ss2_pins[] = { |
2073 | /* SS2 */ |
2074 | 71, |
2075 | }; |
2076 | static const unsigned int msiof0_ss2_mux[] = { |
2077 | MSIOF0_SS2_MARK, |
2078 | }; |
2079 | static const unsigned int msiof0_rxd_pins[] = { |
2080 | /* RXD */ |
2081 | 70, |
2082 | }; |
2083 | static const unsigned int msiof0_rxd_mux[] = { |
2084 | MSIOF0_RXD_MARK, |
2085 | }; |
2086 | static const unsigned int msiof0_txd_pins[] = { |
2087 | /* TXD */ |
2088 | 65, |
2089 | }; |
2090 | static const unsigned int msiof0_txd_mux[] = { |
2091 | MSIOF0_TXD_MARK, |
2092 | }; |
2093 | static const unsigned int msiof0_mck0_pins[] = { |
2094 | /* MSCK0 */ |
2095 | 68, |
2096 | }; |
2097 | static const unsigned int msiof0_mck0_mux[] = { |
2098 | MSIOF0_MCK0_MARK, |
2099 | }; |
2100 | |
2101 | static const unsigned int msiof0_mck1_pins[] = { |
2102 | /* MSCK1 */ |
2103 | 69, |
2104 | }; |
2105 | static const unsigned int msiof0_mck1_mux[] = { |
2106 | MSIOF0_MCK1_MARK, |
2107 | }; |
2108 | |
2109 | static const unsigned int msiof0l_rsck_pins[] = { |
2110 | /* RSCK */ |
2111 | 214, |
2112 | }; |
2113 | static const unsigned int msiof0l_rsck_mux[] = { |
2114 | MSIOF0L_RSCK_MARK, |
2115 | }; |
2116 | static const unsigned int msiof0l_tsck_pins[] = { |
2117 | /* TSCK */ |
2118 | 219, |
2119 | }; |
2120 | static const unsigned int msiof0l_tsck_mux[] = { |
2121 | MSIOF0L_TSCK_MARK, |
2122 | }; |
2123 | static const unsigned int msiof0l_rsync_pins[] = { |
2124 | /* RSYNC */ |
2125 | 215, |
2126 | }; |
2127 | static const unsigned int msiof0l_rsync_mux[] = { |
2128 | MSIOF0L_RSYNC_MARK, |
2129 | }; |
2130 | static const unsigned int msiof0l_tsync_pins[] = { |
2131 | /* TSYNC */ |
2132 | 217, |
2133 | }; |
2134 | static const unsigned int msiof0l_tsync_mux[] = { |
2135 | MSIOF0L_TSYNC_MARK, |
2136 | }; |
2137 | static const unsigned int msiof0l_ss1_a_pins[] = { |
2138 | /* SS1 */ |
2139 | 207, |
2140 | }; |
2141 | static const unsigned int msiof0l_ss1_a_mux[] = { |
2142 | PORT207_MSIOF0L_SS1_MARK, |
2143 | }; |
2144 | static const unsigned int msiof0l_ss1_b_pins[] = { |
2145 | /* SS1 */ |
2146 | 210, |
2147 | }; |
2148 | static const unsigned int msiof0l_ss1_b_mux[] = { |
2149 | PORT210_MSIOF0L_SS1_MARK, |
2150 | }; |
2151 | static const unsigned int msiof0l_ss2_a_pins[] = { |
2152 | /* SS2 */ |
2153 | 208, |
2154 | }; |
2155 | static const unsigned int msiof0l_ss2_a_mux[] = { |
2156 | PORT208_MSIOF0L_SS2_MARK, |
2157 | }; |
2158 | static const unsigned int msiof0l_ss2_b_pins[] = { |
2159 | /* SS2 */ |
2160 | 211, |
2161 | }; |
2162 | static const unsigned int msiof0l_ss2_b_mux[] = { |
2163 | PORT211_MSIOF0L_SS2_MARK, |
2164 | }; |
2165 | static const unsigned int msiof0l_rxd_pins[] = { |
2166 | /* RXD */ |
2167 | 221, |
2168 | }; |
2169 | static const unsigned int msiof0l_rxd_mux[] = { |
2170 | MSIOF0L_RXD_MARK, |
2171 | }; |
2172 | static const unsigned int msiof0l_txd_pins[] = { |
2173 | /* TXD */ |
2174 | 222, |
2175 | }; |
2176 | static const unsigned int msiof0l_txd_mux[] = { |
2177 | MSIOF0L_TXD_MARK, |
2178 | }; |
2179 | static const unsigned int msiof0l_mck0_pins[] = { |
2180 | /* MSCK0 */ |
2181 | 212, |
2182 | }; |
2183 | static const unsigned int msiof0l_mck0_mux[] = { |
2184 | MSIOF0L_MCK0_MARK, |
2185 | }; |
2186 | static const unsigned int msiof0l_mck1_pins[] = { |
2187 | /* MSCK1 */ |
2188 | 213, |
2189 | }; |
2190 | static const unsigned int msiof0l_mck1_mux[] = { |
2191 | MSIOF0L_MCK1_MARK, |
2192 | }; |
2193 | /* - MSIOF1 ----------------------------------------------------------------- */ |
2194 | static const unsigned int msiof1_rsck_pins[] = { |
2195 | /* RSCK */ |
2196 | 234, |
2197 | }; |
2198 | static const unsigned int msiof1_rsck_mux[] = { |
2199 | MSIOF1_RSCK_MARK, |
2200 | }; |
2201 | static const unsigned int msiof1_tsck_pins[] = { |
2202 | /* TSCK */ |
2203 | 232, |
2204 | }; |
2205 | static const unsigned int msiof1_tsck_mux[] = { |
2206 | MSIOF1_TSCK_MARK, |
2207 | }; |
2208 | static const unsigned int msiof1_rsync_pins[] = { |
2209 | /* RSYNC */ |
2210 | 235, |
2211 | }; |
2212 | static const unsigned int msiof1_rsync_mux[] = { |
2213 | MSIOF1_RSYNC_MARK, |
2214 | }; |
2215 | static const unsigned int msiof1_tsync_pins[] = { |
2216 | /* TSYNC */ |
2217 | 231, |
2218 | }; |
2219 | static const unsigned int msiof1_tsync_mux[] = { |
2220 | MSIOF1_TSYNC_MARK, |
2221 | }; |
2222 | static const unsigned int msiof1_ss1_pins[] = { |
2223 | /* SS1 */ |
2224 | 238, |
2225 | }; |
2226 | static const unsigned int msiof1_ss1_mux[] = { |
2227 | MSIOF1_SS1_MARK, |
2228 | }; |
2229 | static const unsigned int msiof1_ss2_pins[] = { |
2230 | /* SS2 */ |
2231 | 239, |
2232 | }; |
2233 | static const unsigned int msiof1_ss2_mux[] = { |
2234 | MSIOF1_SS2_MARK, |
2235 | }; |
2236 | static const unsigned int msiof1_rxd_pins[] = { |
2237 | /* RXD */ |
2238 | 233, |
2239 | }; |
2240 | static const unsigned int msiof1_rxd_mux[] = { |
2241 | MSIOF1_RXD_MARK, |
2242 | }; |
2243 | static const unsigned int msiof1_txd_pins[] = { |
2244 | /* TXD */ |
2245 | 230, |
2246 | }; |
2247 | static const unsigned int msiof1_txd_mux[] = { |
2248 | MSIOF1_TXD_MARK, |
2249 | }; |
2250 | static const unsigned int msiof1_mck0_pins[] = { |
2251 | /* MSCK0 */ |
2252 | 236, |
2253 | }; |
2254 | static const unsigned int msiof1_mck0_mux[] = { |
2255 | MSIOF1_MCK0_MARK, |
2256 | }; |
2257 | static const unsigned int msiof1_mck1_pins[] = { |
2258 | /* MSCK1 */ |
2259 | 237, |
2260 | }; |
2261 | static const unsigned int msiof1_mck1_mux[] = { |
2262 | MSIOF1_MCK1_MARK, |
2263 | }; |
2264 | /* - MSIOF2 ----------------------------------------------------------------- */ |
2265 | static const unsigned int msiof2_rsck_pins[] = { |
2266 | /* RSCK */ |
2267 | 151, |
2268 | }; |
2269 | static const unsigned int msiof2_rsck_mux[] = { |
2270 | MSIOF2_RSCK_MARK, |
2271 | }; |
2272 | static const unsigned int msiof2_tsck_pins[] = { |
2273 | /* TSCK */ |
2274 | 135, |
2275 | }; |
2276 | static const unsigned int msiof2_tsck_mux[] = { |
2277 | MSIOF2_TSCK_MARK, |
2278 | }; |
2279 | static const unsigned int msiof2_rsync_pins[] = { |
2280 | /* RSYNC */ |
2281 | 152, |
2282 | }; |
2283 | static const unsigned int msiof2_rsync_mux[] = { |
2284 | MSIOF2_RSYNC_MARK, |
2285 | }; |
2286 | static const unsigned int msiof2_tsync_pins[] = { |
2287 | /* TSYNC */ |
2288 | 133, |
2289 | }; |
2290 | static const unsigned int msiof2_tsync_mux[] = { |
2291 | MSIOF2_TSYNC_MARK, |
2292 | }; |
2293 | static const unsigned int msiof2_ss1_a_pins[] = { |
2294 | /* SS1 */ |
2295 | 131, |
2296 | }; |
2297 | static const unsigned int msiof2_ss1_a_mux[] = { |
2298 | PORT131_MSIOF2_SS1_MARK, |
2299 | }; |
2300 | static const unsigned int msiof2_ss1_b_pins[] = { |
2301 | /* SS1 */ |
2302 | 153, |
2303 | }; |
2304 | static const unsigned int msiof2_ss1_b_mux[] = { |
2305 | PORT153_MSIOF2_SS1_MARK, |
2306 | }; |
2307 | static const unsigned int msiof2_ss2_a_pins[] = { |
2308 | /* SS2 */ |
2309 | 132, |
2310 | }; |
2311 | static const unsigned int msiof2_ss2_a_mux[] = { |
2312 | PORT132_MSIOF2_SS2_MARK, |
2313 | }; |
2314 | static const unsigned int msiof2_ss2_b_pins[] = { |
2315 | /* SS2 */ |
2316 | 156, |
2317 | }; |
2318 | static const unsigned int msiof2_ss2_b_mux[] = { |
2319 | PORT156_MSIOF2_SS2_MARK, |
2320 | }; |
2321 | static const unsigned int msiof2_rxd_a_pins[] = { |
2322 | /* RXD */ |
2323 | 130, |
2324 | }; |
2325 | static const unsigned int msiof2_rxd_a_mux[] = { |
2326 | PORT130_MSIOF2_RXD_MARK, |
2327 | }; |
2328 | static const unsigned int msiof2_rxd_b_pins[] = { |
2329 | /* RXD */ |
2330 | 157, |
2331 | }; |
2332 | static const unsigned int msiof2_rxd_b_mux[] = { |
2333 | PORT157_MSIOF2_RXD_MARK, |
2334 | }; |
2335 | static const unsigned int msiof2_txd_pins[] = { |
2336 | /* TXD */ |
2337 | 134, |
2338 | }; |
2339 | static const unsigned int msiof2_txd_mux[] = { |
2340 | MSIOF2_TXD_MARK, |
2341 | }; |
2342 | static const unsigned int msiof2_mck0_pins[] = { |
2343 | /* MSCK0 */ |
2344 | 154, |
2345 | }; |
2346 | static const unsigned int msiof2_mck0_mux[] = { |
2347 | MSIOF2_MCK0_MARK, |
2348 | }; |
2349 | static const unsigned int msiof2_mck1_pins[] = { |
2350 | /* MSCK1 */ |
2351 | 155, |
2352 | }; |
2353 | static const unsigned int msiof2_mck1_mux[] = { |
2354 | MSIOF2_MCK1_MARK, |
2355 | }; |
2356 | |
2357 | static const unsigned int msiof2r_tsck_pins[] = { |
2358 | /* TSCK */ |
2359 | 248, |
2360 | }; |
2361 | static const unsigned int msiof2r_tsck_mux[] = { |
2362 | MSIOF2R_TSCK_MARK, |
2363 | }; |
2364 | static const unsigned int msiof2r_tsync_pins[] = { |
2365 | /* TSYNC */ |
2366 | 249, |
2367 | }; |
2368 | static const unsigned int msiof2r_tsync_mux[] = { |
2369 | MSIOF2R_TSYNC_MARK, |
2370 | }; |
2371 | static const unsigned int msiof2r_rxd_pins[] = { |
2372 | /* RXD */ |
2373 | 244, |
2374 | }; |
2375 | static const unsigned int msiof2r_rxd_mux[] = { |
2376 | MSIOF2R_RXD_MARK, |
2377 | }; |
2378 | static const unsigned int msiof2r_txd_pins[] = { |
2379 | /* TXD */ |
2380 | 245, |
2381 | }; |
2382 | static const unsigned int msiof2r_txd_mux[] = { |
2383 | MSIOF2R_TXD_MARK, |
2384 | }; |
2385 | /* - MSIOF3 (Pin function name of MSIOF3 is named BBIF1) -------------------- */ |
2386 | static const unsigned int msiof3_rsck_pins[] = { |
2387 | /* RSCK */ |
2388 | 115, |
2389 | }; |
2390 | static const unsigned int msiof3_rsck_mux[] = { |
2391 | BBIF1_RSCK_MARK, |
2392 | }; |
2393 | static const unsigned int msiof3_tsck_pins[] = { |
2394 | /* TSCK */ |
2395 | 112, |
2396 | }; |
2397 | static const unsigned int msiof3_tsck_mux[] = { |
2398 | BBIF1_TSCK_MARK, |
2399 | }; |
2400 | static const unsigned int msiof3_rsync_pins[] = { |
2401 | /* RSYNC */ |
2402 | 116, |
2403 | }; |
2404 | static const unsigned int msiof3_rsync_mux[] = { |
2405 | BBIF1_RSYNC_MARK, |
2406 | }; |
2407 | static const unsigned int msiof3_tsync_pins[] = { |
2408 | /* TSYNC */ |
2409 | 113, |
2410 | }; |
2411 | static const unsigned int msiof3_tsync_mux[] = { |
2412 | BBIF1_TSYNC_MARK, |
2413 | }; |
2414 | static const unsigned int msiof3_ss1_pins[] = { |
2415 | /* SS1 */ |
2416 | 117, |
2417 | }; |
2418 | static const unsigned int msiof3_ss1_mux[] = { |
2419 | BBIF1_SS1_MARK, |
2420 | }; |
2421 | static const unsigned int msiof3_ss2_pins[] = { |
2422 | /* SS2 */ |
2423 | 109, |
2424 | }; |
2425 | static const unsigned int msiof3_ss2_mux[] = { |
2426 | BBIF1_SS2_MARK, |
2427 | }; |
2428 | static const unsigned int msiof3_rxd_pins[] = { |
2429 | /* RXD */ |
2430 | 111, |
2431 | }; |
2432 | static const unsigned int msiof3_rxd_mux[] = { |
2433 | BBIF1_RXD_MARK, |
2434 | }; |
2435 | static const unsigned int msiof3_txd_pins[] = { |
2436 | /* TXD */ |
2437 | 114, |
2438 | }; |
2439 | static const unsigned int msiof3_txd_mux[] = { |
2440 | BBIF1_TXD_MARK, |
2441 | }; |
2442 | static const unsigned int msiof3_flow_pins[] = { |
2443 | /* FLOW */ |
2444 | 117, |
2445 | }; |
2446 | static const unsigned int msiof3_flow_mux[] = { |
2447 | BBIF1_FLOW_MARK, |
2448 | }; |
2449 | |
2450 | /* - SCIFA0 ----------------------------------------------------------------- */ |
2451 | static const unsigned int scifa0_data_pins[] = { |
2452 | /* RXD, TXD */ |
2453 | 43, 17, |
2454 | }; |
2455 | static const unsigned int scifa0_data_mux[] = { |
2456 | SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, |
2457 | }; |
2458 | static const unsigned int scifa0_clk_pins[] = { |
2459 | /* SCK */ |
2460 | 16, |
2461 | }; |
2462 | static const unsigned int scifa0_clk_mux[] = { |
2463 | SCIFA0_SCK_MARK, |
2464 | }; |
2465 | static const unsigned int scifa0_ctrl_pins[] = { |
2466 | /* RTS, CTS */ |
2467 | 42, 44, |
2468 | }; |
2469 | static const unsigned int scifa0_ctrl_mux[] = { |
2470 | SCIFA0_RTS__MARK, SCIFA0_CTS__MARK, |
2471 | }; |
2472 | /* - SCIFA1 ----------------------------------------------------------------- */ |
2473 | static const unsigned int scifa1_data_pins[] = { |
2474 | /* RXD, TXD */ |
2475 | 228, 225, |
2476 | }; |
2477 | static const unsigned int scifa1_data_mux[] = { |
2478 | SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, |
2479 | }; |
2480 | static const unsigned int scifa1_clk_pins[] = { |
2481 | /* SCK */ |
2482 | 226, |
2483 | }; |
2484 | static const unsigned int scifa1_clk_mux[] = { |
2485 | SCIFA1_SCK_MARK, |
2486 | }; |
2487 | static const unsigned int scifa1_ctrl_pins[] = { |
2488 | /* RTS, CTS */ |
2489 | 227, 229, |
2490 | }; |
2491 | static const unsigned int scifa1_ctrl_mux[] = { |
2492 | SCIFA1_RTS__MARK, SCIFA1_CTS__MARK, |
2493 | }; |
2494 | /* - SCIFA2 ----------------------------------------------------------------- */ |
2495 | static const unsigned int scifa2_data_0_pins[] = { |
2496 | /* RXD, TXD */ |
2497 | 155, 154, |
2498 | }; |
2499 | static const unsigned int scifa2_data_0_mux[] = { |
2500 | SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK, |
2501 | }; |
2502 | static const unsigned int scifa2_clk_0_pins[] = { |
2503 | /* SCK */ |
2504 | 158, |
2505 | }; |
2506 | static const unsigned int scifa2_clk_0_mux[] = { |
2507 | SCIFA2_SCK1_MARK, |
2508 | }; |
2509 | static const unsigned int scifa2_ctrl_0_pins[] = { |
2510 | /* RTS, CTS */ |
2511 | 156, 157, |
2512 | }; |
2513 | static const unsigned int scifa2_ctrl_0_mux[] = { |
2514 | SCIFA2_RTS1__MARK, SCIFA2_CTS1__MARK, |
2515 | }; |
2516 | static const unsigned int scifa2_data_1_pins[] = { |
2517 | /* RXD, TXD */ |
2518 | 233, 230, |
2519 | }; |
2520 | static const unsigned int scifa2_data_1_mux[] = { |
2521 | SCIFA2_RXD2_MARK, SCIFA2_TXD2_MARK, |
2522 | }; |
2523 | static const unsigned int scifa2_clk_1_pins[] = { |
2524 | /* SCK */ |
2525 | 232, |
2526 | }; |
2527 | static const unsigned int scifa2_clk_1_mux[] = { |
2528 | SCIFA2_SCK2_MARK, |
2529 | }; |
2530 | static const unsigned int scifa2_ctrl_1_pins[] = { |
2531 | /* RTS, CTS */ |
2532 | 234, 231, |
2533 | }; |
2534 | static const unsigned int scifa2_ctrl_1_mux[] = { |
2535 | SCIFA2_RTS2__MARK, SCIFA2_CTS2__MARK, |
2536 | }; |
2537 | /* - SCIFA3 ----------------------------------------------------------------- */ |
2538 | static const unsigned int scifa3_data_pins[] = { |
2539 | /* RXD, TXD */ |
2540 | 108, 110, |
2541 | }; |
2542 | static const unsigned int scifa3_data_mux[] = { |
2543 | SCIFA3_RXD_MARK, SCIFA3_TXD_MARK, |
2544 | }; |
2545 | static const unsigned int scifa3_ctrl_pins[] = { |
2546 | /* RTS, CTS */ |
2547 | 109, 107, |
2548 | }; |
2549 | static const unsigned int scifa3_ctrl_mux[] = { |
2550 | SCIFA3_RTS__MARK, SCIFA3_CTS__MARK, |
2551 | }; |
2552 | /* - SCIFA4 ----------------------------------------------------------------- */ |
2553 | static const unsigned int scifa4_data_pins[] = { |
2554 | /* RXD, TXD */ |
2555 | 33, 32, |
2556 | }; |
2557 | static const unsigned int scifa4_data_mux[] = { |
2558 | SCIFA4_RXD_MARK, SCIFA4_TXD_MARK, |
2559 | }; |
2560 | static const unsigned int scifa4_ctrl_pins[] = { |
2561 | /* RTS, CTS */ |
2562 | 34, 35, |
2563 | }; |
2564 | static const unsigned int scifa4_ctrl_mux[] = { |
2565 | SCIFA4_RTS__MARK, SCIFA4_CTS__MARK, |
2566 | }; |
2567 | /* - SCIFA5 ----------------------------------------------------------------- */ |
2568 | static const unsigned int scifa5_data_0_pins[] = { |
2569 | /* RXD, TXD */ |
2570 | 246, 247, |
2571 | }; |
2572 | static const unsigned int scifa5_data_0_mux[] = { |
2573 | PORT246_SCIFA5_RXD_MARK, PORT247_SCIFA5_TXD_MARK, |
2574 | }; |
2575 | static const unsigned int scifa5_clk_0_pins[] = { |
2576 | /* SCK */ |
2577 | 248, |
2578 | }; |
2579 | static const unsigned int scifa5_clk_0_mux[] = { |
2580 | PORT248_SCIFA5_SCK_MARK, |
2581 | }; |
2582 | static const unsigned int scifa5_ctrl_0_pins[] = { |
2583 | /* RTS, CTS */ |
2584 | 245, 244, |
2585 | }; |
2586 | static const unsigned int scifa5_ctrl_0_mux[] = { |
2587 | PORT245_SCIFA5_RTS__MARK, PORT244_SCIFA5_CTS__MARK, |
2588 | }; |
2589 | static const unsigned int scifa5_data_1_pins[] = { |
2590 | /* RXD, TXD */ |
2591 | 195, 196, |
2592 | }; |
2593 | static const unsigned int scifa5_data_1_mux[] = { |
2594 | PORT195_SCIFA5_RXD_MARK, PORT196_SCIFA5_TXD_MARK, |
2595 | }; |
2596 | static const unsigned int scifa5_clk_1_pins[] = { |
2597 | /* SCK */ |
2598 | 197, |
2599 | }; |
2600 | static const unsigned int scifa5_clk_1_mux[] = { |
2601 | PORT197_SCIFA5_SCK_MARK, |
2602 | }; |
2603 | static const unsigned int scifa5_ctrl_1_pins[] = { |
2604 | /* RTS, CTS */ |
2605 | 194, 193, |
2606 | }; |
2607 | static const unsigned int scifa5_ctrl_1_mux[] = { |
2608 | PORT194_SCIFA5_RTS__MARK, PORT193_SCIFA5_CTS__MARK, |
2609 | }; |
2610 | static const unsigned int scifa5_data_2_pins[] = { |
2611 | /* RXD, TXD */ |
2612 | 162, 160, |
2613 | }; |
2614 | static const unsigned int scifa5_data_2_mux[] = { |
2615 | PORT162_SCIFA5_RXD_MARK, PORT160_SCIFA5_TXD_MARK, |
2616 | }; |
2617 | static const unsigned int scifa5_clk_2_pins[] = { |
2618 | /* SCK */ |
2619 | 159, |
2620 | }; |
2621 | static const unsigned int scifa5_clk_2_mux[] = { |
2622 | PORT159_SCIFA5_SCK_MARK, |
2623 | }; |
2624 | static const unsigned int scifa5_ctrl_2_pins[] = { |
2625 | /* RTS, CTS */ |
2626 | 163, 161, |
2627 | }; |
2628 | static const unsigned int scifa5_ctrl_2_mux[] = { |
2629 | PORT163_SCIFA5_RTS__MARK, PORT161_SCIFA5_CTS__MARK, |
2630 | }; |
2631 | /* - SCIFA6 ----------------------------------------------------------------- */ |
2632 | static const unsigned int scifa6_pins[] = { |
2633 | /* TXD */ |
2634 | 240, |
2635 | }; |
2636 | static const unsigned int scifa6_mux[] = { |
2637 | SCIFA6_TXD_MARK, |
2638 | }; |
2639 | /* - SCIFA7 ----------------------------------------------------------------- */ |
2640 | static const unsigned int scifa7_data_pins[] = { |
2641 | /* RXD, TXD */ |
2642 | 12, 18, |
2643 | }; |
2644 | static const unsigned int scifa7_data_mux[] = { |
2645 | SCIFA7_RXD_MARK, SCIFA7_TXD_MARK, |
2646 | }; |
2647 | static const unsigned int scifa7_ctrl_pins[] = { |
2648 | /* RTS, CTS */ |
2649 | 19, 13, |
2650 | }; |
2651 | static const unsigned int scifa7_ctrl_mux[] = { |
2652 | SCIFA7_RTS__MARK, SCIFA7_CTS__MARK, |
2653 | }; |
2654 | /* - SCIFB ------------------------------------------------------------------ */ |
2655 | static const unsigned int scifb_data_0_pins[] = { |
2656 | /* RXD, TXD */ |
2657 | 162, 160, |
2658 | }; |
2659 | static const unsigned int scifb_data_0_mux[] = { |
2660 | PORT162_SCIFB_RXD_MARK, PORT160_SCIFB_TXD_MARK, |
2661 | }; |
2662 | static const unsigned int scifb_clk_0_pins[] = { |
2663 | /* SCK */ |
2664 | 159, |
2665 | }; |
2666 | static const unsigned int scifb_clk_0_mux[] = { |
2667 | PORT159_SCIFB_SCK_MARK, |
2668 | }; |
2669 | static const unsigned int scifb_ctrl_0_pins[] = { |
2670 | /* RTS, CTS */ |
2671 | 163, 161, |
2672 | }; |
2673 | static const unsigned int scifb_ctrl_0_mux[] = { |
2674 | PORT163_SCIFB_RTS__MARK, PORT161_SCIFB_CTS__MARK, |
2675 | }; |
2676 | static const unsigned int scifb_data_1_pins[] = { |
2677 | /* RXD, TXD */ |
2678 | 246, 247, |
2679 | }; |
2680 | static const unsigned int scifb_data_1_mux[] = { |
2681 | PORT246_SCIFB_RXD_MARK, PORT247_SCIFB_TXD_MARK, |
2682 | }; |
2683 | static const unsigned int scifb_clk_1_pins[] = { |
2684 | /* SCK */ |
2685 | 248, |
2686 | }; |
2687 | static const unsigned int scifb_clk_1_mux[] = { |
2688 | PORT248_SCIFB_SCK_MARK, |
2689 | }; |
2690 | static const unsigned int scifb_ctrl_1_pins[] = { |
2691 | /* RTS, CTS */ |
2692 | 245, 244, |
2693 | }; |
2694 | static const unsigned int scifb_ctrl_1_mux[] = { |
2695 | PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK, |
2696 | }; |
2697 | /* - SDHI0 ------------------------------------------------------------------ */ |
2698 | static const unsigned int sdhi0_data_pins[] = { |
2699 | /* D[0:3] */ |
2700 | 252, 253, 254, 255, |
2701 | }; |
2702 | static const unsigned int sdhi0_data_mux[] = { |
2703 | SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK, |
2704 | }; |
2705 | static const unsigned int sdhi0_ctrl_pins[] = { |
2706 | /* CMD, CLK */ |
2707 | 256, 250, |
2708 | }; |
2709 | static const unsigned int sdhi0_ctrl_mux[] = { |
2710 | SDHICMD0_MARK, SDHICLK0_MARK, |
2711 | }; |
2712 | static const unsigned int sdhi0_cd_pins[] = { |
2713 | /* CD */ |
2714 | 251, |
2715 | }; |
2716 | static const unsigned int sdhi0_cd_mux[] = { |
2717 | SDHICD0_MARK, |
2718 | }; |
2719 | static const unsigned int sdhi0_wp_pins[] = { |
2720 | /* WP */ |
2721 | 257, |
2722 | }; |
2723 | static const unsigned int sdhi0_wp_mux[] = { |
2724 | SDHIWP0_MARK, |
2725 | }; |
2726 | /* - SDHI1 ------------------------------------------------------------------ */ |
2727 | static const unsigned int sdhi1_data_pins[] = { |
2728 | /* D[0:3] */ |
2729 | 259, 260, 261, 262, |
2730 | }; |
2731 | static const unsigned int sdhi1_data_mux[] = { |
2732 | SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK, |
2733 | }; |
2734 | static const unsigned int sdhi1_ctrl_pins[] = { |
2735 | /* CMD, CLK */ |
2736 | 263, 258, |
2737 | }; |
2738 | static const unsigned int sdhi1_ctrl_mux[] = { |
2739 | SDHICMD1_MARK, SDHICLK1_MARK, |
2740 | }; |
2741 | /* - SDHI2 ------------------------------------------------------------------ */ |
2742 | static const unsigned int sdhi2_data_pins[] = { |
2743 | /* D[0:3] */ |
2744 | 265, 266, 267, 268, |
2745 | }; |
2746 | static const unsigned int sdhi2_data_mux[] = { |
2747 | SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK, |
2748 | }; |
2749 | static const unsigned int sdhi2_ctrl_pins[] = { |
2750 | /* CMD, CLK */ |
2751 | 269, 264, |
2752 | }; |
2753 | static const unsigned int sdhi2_ctrl_mux[] = { |
2754 | SDHICMD2_MARK, SDHICLK2_MARK, |
2755 | }; |
2756 | /* - TPU0 ------------------------------------------------------------------- */ |
2757 | static const unsigned int tpu0_to0_pins[] = { |
2758 | /* TO */ |
2759 | 55, |
2760 | }; |
2761 | static const unsigned int tpu0_to0_mux[] = { |
2762 | TPU0TO0_MARK, |
2763 | }; |
2764 | static const unsigned int tpu0_to1_pins[] = { |
2765 | /* TO */ |
2766 | 59, |
2767 | }; |
2768 | static const unsigned int tpu0_to1_mux[] = { |
2769 | TPU0TO1_MARK, |
2770 | }; |
2771 | static const unsigned int tpu0_to2_pins[] = { |
2772 | /* TO */ |
2773 | 140, |
2774 | }; |
2775 | static const unsigned int tpu0_to2_mux[] = { |
2776 | TPU0TO2_MARK, |
2777 | }; |
2778 | static const unsigned int tpu0_to3_pins[] = { |
2779 | /* TO */ |
2780 | 141, |
2781 | }; |
2782 | static const unsigned int tpu0_to3_mux[] = { |
2783 | TPU0TO3_MARK, |
2784 | }; |
2785 | /* - TPU1 ------------------------------------------------------------------- */ |
2786 | static const unsigned int tpu1_to0_pins[] = { |
2787 | /* TO */ |
2788 | 246, |
2789 | }; |
2790 | static const unsigned int tpu1_to0_mux[] = { |
2791 | TPU1TO0_MARK, |
2792 | }; |
2793 | static const unsigned int tpu1_to1_0_pins[] = { |
2794 | /* TO */ |
2795 | 28, |
2796 | }; |
2797 | static const unsigned int tpu1_to1_0_mux[] = { |
2798 | PORT28_TPU1TO1_MARK, |
2799 | }; |
2800 | static const unsigned int tpu1_to1_1_pins[] = { |
2801 | /* TO */ |
2802 | 29, |
2803 | }; |
2804 | static const unsigned int tpu1_to1_1_mux[] = { |
2805 | PORT29_TPU1TO1_MARK, |
2806 | }; |
2807 | static const unsigned int tpu1_to2_pins[] = { |
2808 | /* TO */ |
2809 | 153, |
2810 | }; |
2811 | static const unsigned int tpu1_to2_mux[] = { |
2812 | TPU1TO2_MARK, |
2813 | }; |
2814 | static const unsigned int tpu1_to3_pins[] = { |
2815 | /* TO */ |
2816 | 145, |
2817 | }; |
2818 | static const unsigned int tpu1_to3_mux[] = { |
2819 | TPU1TO3_MARK, |
2820 | }; |
2821 | /* - TPU2 ------------------------------------------------------------------- */ |
2822 | static const unsigned int tpu2_to0_pins[] = { |
2823 | /* TO */ |
2824 | 248, |
2825 | }; |
2826 | static const unsigned int tpu2_to0_mux[] = { |
2827 | TPU2TO0_MARK, |
2828 | }; |
2829 | static const unsigned int tpu2_to1_pins[] = { |
2830 | /* TO */ |
2831 | 197, |
2832 | }; |
2833 | static const unsigned int tpu2_to1_mux[] = { |
2834 | TPU2TO1_MARK, |
2835 | }; |
2836 | static const unsigned int tpu2_to2_pins[] = { |
2837 | /* TO */ |
2838 | 50, |
2839 | }; |
2840 | static const unsigned int tpu2_to2_mux[] = { |
2841 | TPU2TO2_MARK, |
2842 | }; |
2843 | static const unsigned int tpu2_to3_pins[] = { |
2844 | /* TO */ |
2845 | 51, |
2846 | }; |
2847 | static const unsigned int tpu2_to3_mux[] = { |
2848 | TPU2TO3_MARK, |
2849 | }; |
2850 | /* - TPU3 ------------------------------------------------------------------- */ |
2851 | static const unsigned int tpu3_to0_pins[] = { |
2852 | /* TO */ |
2853 | 163, |
2854 | }; |
2855 | static const unsigned int tpu3_to0_mux[] = { |
2856 | TPU3TO0_MARK, |
2857 | }; |
2858 | static const unsigned int tpu3_to1_pins[] = { |
2859 | /* TO */ |
2860 | 247, |
2861 | }; |
2862 | static const unsigned int tpu3_to1_mux[] = { |
2863 | TPU3TO1_MARK, |
2864 | }; |
2865 | static const unsigned int tpu3_to2_pins[] = { |
2866 | /* TO */ |
2867 | 54, |
2868 | }; |
2869 | static const unsigned int tpu3_to2_mux[] = { |
2870 | TPU3TO2_MARK, |
2871 | }; |
2872 | static const unsigned int tpu3_to3_pins[] = { |
2873 | /* TO */ |
2874 | 53, |
2875 | }; |
2876 | static const unsigned int tpu3_to3_mux[] = { |
2877 | TPU3TO3_MARK, |
2878 | }; |
2879 | /* - TPU4 ------------------------------------------------------------------- */ |
2880 | static const unsigned int tpu4_to0_pins[] = { |
2881 | /* TO */ |
2882 | 241, |
2883 | }; |
2884 | static const unsigned int tpu4_to0_mux[] = { |
2885 | TPU4TO0_MARK, |
2886 | }; |
2887 | static const unsigned int tpu4_to1_pins[] = { |
2888 | /* TO */ |
2889 | 199, |
2890 | }; |
2891 | static const unsigned int tpu4_to1_mux[] = { |
2892 | TPU4TO1_MARK, |
2893 | }; |
2894 | static const unsigned int tpu4_to2_pins[] = { |
2895 | /* TO */ |
2896 | 58, |
2897 | }; |
2898 | static const unsigned int tpu4_to2_mux[] = { |
2899 | TPU4TO2_MARK, |
2900 | }; |
2901 | static const unsigned int tpu4_to3_pins[] = { |
2902 | /* TO */ |
2903 | PIN_A11, |
2904 | }; |
2905 | static const unsigned int tpu4_to3_mux[] = { |
2906 | TPU4TO3_MARK, |
2907 | }; |
2908 | /* - USB -------------------------------------------------------------------- */ |
2909 | static const unsigned int usb_vbus_pins[] = { |
2910 | /* VBUS */ |
2911 | 0, |
2912 | }; |
2913 | static const unsigned int usb_vbus_mux[] = { |
2914 | VBUS_0_MARK, |
2915 | }; |
2916 | |
2917 | static const struct sh_pfc_pin_group pinmux_groups[] = { |
2918 | SH_PFC_PIN_GROUP(bsc_data_0_7), |
2919 | SH_PFC_PIN_GROUP(bsc_data_8_15), |
2920 | SH_PFC_PIN_GROUP(bsc_cs4), |
2921 | SH_PFC_PIN_GROUP(bsc_cs5_a), |
2922 | SH_PFC_PIN_GROUP(bsc_cs5_b), |
2923 | SH_PFC_PIN_GROUP(bsc_cs6_a), |
2924 | SH_PFC_PIN_GROUP(bsc_cs6_b), |
2925 | SH_PFC_PIN_GROUP(bsc_rd), |
2926 | SH_PFC_PIN_GROUP(bsc_rdwr_0), |
2927 | SH_PFC_PIN_GROUP(bsc_rdwr_1), |
2928 | SH_PFC_PIN_GROUP(bsc_rdwr_2), |
2929 | SH_PFC_PIN_GROUP(bsc_we0), |
2930 | SH_PFC_PIN_GROUP(bsc_we1), |
2931 | SH_PFC_PIN_GROUP(fsia_mclk_in), |
2932 | SH_PFC_PIN_GROUP(fsia_mclk_out), |
2933 | SH_PFC_PIN_GROUP(fsia_sclk_in), |
2934 | SH_PFC_PIN_GROUP(fsia_sclk_out), |
2935 | SH_PFC_PIN_GROUP(fsia_data_in), |
2936 | SH_PFC_PIN_GROUP(fsia_data_out), |
2937 | SH_PFC_PIN_GROUP(fsia_spdif), |
2938 | SH_PFC_PIN_GROUP(fsib_mclk_in), |
2939 | SH_PFC_PIN_GROUP(fsib_mclk_out), |
2940 | SH_PFC_PIN_GROUP(fsib_sclk_in), |
2941 | SH_PFC_PIN_GROUP(fsib_sclk_out), |
2942 | SH_PFC_PIN_GROUP(fsib_data_in), |
2943 | SH_PFC_PIN_GROUP(fsib_data_out), |
2944 | SH_PFC_PIN_GROUP(fsib_spdif), |
2945 | SH_PFC_PIN_GROUP(fsic_mclk_in), |
2946 | SH_PFC_PIN_GROUP(fsic_mclk_out), |
2947 | SH_PFC_PIN_GROUP(fsic_sclk_in), |
2948 | SH_PFC_PIN_GROUP(fsic_sclk_out), |
2949 | SH_PFC_PIN_GROUP(fsic_data_in), |
2950 | SH_PFC_PIN_GROUP(fsic_data_out), |
2951 | SH_PFC_PIN_GROUP(fsic_spdif_0), |
2952 | SH_PFC_PIN_GROUP(fsic_spdif_1), |
2953 | SH_PFC_PIN_GROUP(fsid_sclk_in), |
2954 | SH_PFC_PIN_GROUP(fsid_sclk_out), |
2955 | SH_PFC_PIN_GROUP(fsid_data_in), |
2956 | SH_PFC_PIN_GROUP(i2c2_0), |
2957 | SH_PFC_PIN_GROUP(i2c2_1), |
2958 | SH_PFC_PIN_GROUP(i2c2_2), |
2959 | SH_PFC_PIN_GROUP(i2c3_0), |
2960 | SH_PFC_PIN_GROUP(i2c3_1), |
2961 | SH_PFC_PIN_GROUP(i2c3_2), |
2962 | SH_PFC_PIN_GROUP(irda_0), |
2963 | SH_PFC_PIN_GROUP(irda_1), |
2964 | BUS_DATA_PIN_GROUP(keysc_in, 5), |
2965 | BUS_DATA_PIN_GROUP(keysc_in, 6), |
2966 | BUS_DATA_PIN_GROUP(keysc_in, 7), |
2967 | BUS_DATA_PIN_GROUP(keysc_in, 8), |
2968 | SH_PFC_PIN_GROUP(keysc_out04), |
2969 | SH_PFC_PIN_GROUP(keysc_out5), |
2970 | SH_PFC_PIN_GROUP(keysc_out6_0), |
2971 | SH_PFC_PIN_GROUP(keysc_out6_1), |
2972 | SH_PFC_PIN_GROUP(keysc_out6_2), |
2973 | SH_PFC_PIN_GROUP(keysc_out7_0), |
2974 | SH_PFC_PIN_GROUP(keysc_out7_1), |
2975 | SH_PFC_PIN_GROUP(keysc_out7_2), |
2976 | SH_PFC_PIN_GROUP(keysc_out8_0), |
2977 | SH_PFC_PIN_GROUP(keysc_out8_1), |
2978 | SH_PFC_PIN_GROUP(keysc_out8_2), |
2979 | SH_PFC_PIN_GROUP(keysc_out9_0), |
2980 | SH_PFC_PIN_GROUP(keysc_out9_1), |
2981 | SH_PFC_PIN_GROUP(keysc_out9_2), |
2982 | SH_PFC_PIN_GROUP(keysc_out10_0), |
2983 | SH_PFC_PIN_GROUP(keysc_out10_1), |
2984 | SH_PFC_PIN_GROUP(keysc_out11_0), |
2985 | SH_PFC_PIN_GROUP(keysc_out11_1), |
2986 | BUS_DATA_PIN_GROUP(lcd_data, 8), |
2987 | BUS_DATA_PIN_GROUP(lcd_data, 9), |
2988 | BUS_DATA_PIN_GROUP(lcd_data, 12), |
2989 | BUS_DATA_PIN_GROUP(lcd_data, 16), |
2990 | BUS_DATA_PIN_GROUP(lcd_data, 18), |
2991 | BUS_DATA_PIN_GROUP(lcd_data, 24), |
2992 | SH_PFC_PIN_GROUP(lcd_display), |
2993 | SH_PFC_PIN_GROUP(lcd_lclk), |
2994 | SH_PFC_PIN_GROUP(lcd_sync), |
2995 | SH_PFC_PIN_GROUP(lcd_sys), |
2996 | BUS_DATA_PIN_GROUP(lcd2_data, 8), |
2997 | BUS_DATA_PIN_GROUP(lcd2_data, 9), |
2998 | BUS_DATA_PIN_GROUP(lcd2_data, 12), |
2999 | BUS_DATA_PIN_GROUP(lcd2_data, 16), |
3000 | BUS_DATA_PIN_GROUP(lcd2_data, 18), |
3001 | BUS_DATA_PIN_GROUP(lcd2_data, 24), |
3002 | SH_PFC_PIN_GROUP(lcd2_sync_0), |
3003 | SH_PFC_PIN_GROUP(lcd2_sync_1), |
3004 | SH_PFC_PIN_GROUP(lcd2_sys_0), |
3005 | SH_PFC_PIN_GROUP(lcd2_sys_1), |
3006 | BUS_DATA_PIN_GROUP(mmc0_data, 1, _0), |
3007 | BUS_DATA_PIN_GROUP(mmc0_data, 4, _0), |
3008 | BUS_DATA_PIN_GROUP(mmc0_data, 8, _0), |
3009 | SH_PFC_PIN_GROUP(mmc0_ctrl_0), |
3010 | BUS_DATA_PIN_GROUP(mmc0_data, 1, _1), |
3011 | BUS_DATA_PIN_GROUP(mmc0_data, 4, _1), |
3012 | BUS_DATA_PIN_GROUP(mmc0_data, 8, _1), |
3013 | SH_PFC_PIN_GROUP(mmc0_ctrl_1), |
3014 | SH_PFC_PIN_GROUP(msiof0_rsck), |
3015 | SH_PFC_PIN_GROUP(msiof0_tsck), |
3016 | SH_PFC_PIN_GROUP(msiof0_rsync), |
3017 | SH_PFC_PIN_GROUP(msiof0_tsync), |
3018 | SH_PFC_PIN_GROUP(msiof0_ss1), |
3019 | SH_PFC_PIN_GROUP(msiof0_ss2), |
3020 | SH_PFC_PIN_GROUP(msiof0_rxd), |
3021 | SH_PFC_PIN_GROUP(msiof0_txd), |
3022 | SH_PFC_PIN_GROUP(msiof0_mck0), |
3023 | SH_PFC_PIN_GROUP(msiof0_mck1), |
3024 | SH_PFC_PIN_GROUP(msiof0l_rsck), |
3025 | SH_PFC_PIN_GROUP(msiof0l_tsck), |
3026 | SH_PFC_PIN_GROUP(msiof0l_rsync), |
3027 | SH_PFC_PIN_GROUP(msiof0l_tsync), |
3028 | SH_PFC_PIN_GROUP(msiof0l_ss1_a), |
3029 | SH_PFC_PIN_GROUP(msiof0l_ss1_b), |
3030 | SH_PFC_PIN_GROUP(msiof0l_ss2_a), |
3031 | SH_PFC_PIN_GROUP(msiof0l_ss2_b), |
3032 | SH_PFC_PIN_GROUP(msiof0l_rxd), |
3033 | SH_PFC_PIN_GROUP(msiof0l_txd), |
3034 | SH_PFC_PIN_GROUP(msiof0l_mck0), |
3035 | SH_PFC_PIN_GROUP(msiof0l_mck1), |
3036 | SH_PFC_PIN_GROUP(msiof1_rsck), |
3037 | SH_PFC_PIN_GROUP(msiof1_tsck), |
3038 | SH_PFC_PIN_GROUP(msiof1_rsync), |
3039 | SH_PFC_PIN_GROUP(msiof1_tsync), |
3040 | SH_PFC_PIN_GROUP(msiof1_ss1), |
3041 | SH_PFC_PIN_GROUP(msiof1_ss2), |
3042 | SH_PFC_PIN_GROUP(msiof1_rxd), |
3043 | SH_PFC_PIN_GROUP(msiof1_txd), |
3044 | SH_PFC_PIN_GROUP(msiof1_mck0), |
3045 | SH_PFC_PIN_GROUP(msiof1_mck1), |
3046 | SH_PFC_PIN_GROUP(msiof2_rsck), |
3047 | SH_PFC_PIN_GROUP(msiof2_tsck), |
3048 | SH_PFC_PIN_GROUP(msiof2_rsync), |
3049 | SH_PFC_PIN_GROUP(msiof2_tsync), |
3050 | SH_PFC_PIN_GROUP(msiof2_ss1_a), |
3051 | SH_PFC_PIN_GROUP(msiof2_ss1_b), |
3052 | SH_PFC_PIN_GROUP(msiof2_ss2_a), |
3053 | SH_PFC_PIN_GROUP(msiof2_ss2_b), |
3054 | SH_PFC_PIN_GROUP(msiof2_rxd_a), |
3055 | SH_PFC_PIN_GROUP(msiof2_rxd_b), |
3056 | SH_PFC_PIN_GROUP(msiof2_txd), |
3057 | SH_PFC_PIN_GROUP(msiof2_mck0), |
3058 | SH_PFC_PIN_GROUP(msiof2_mck1), |
3059 | SH_PFC_PIN_GROUP(msiof2r_tsck), |
3060 | SH_PFC_PIN_GROUP(msiof2r_tsync), |
3061 | SH_PFC_PIN_GROUP(msiof2r_rxd), |
3062 | SH_PFC_PIN_GROUP(msiof2r_txd), |
3063 | SH_PFC_PIN_GROUP(msiof3_rsck), |
3064 | SH_PFC_PIN_GROUP(msiof3_tsck), |
3065 | SH_PFC_PIN_GROUP(msiof3_rsync), |
3066 | SH_PFC_PIN_GROUP(msiof3_tsync), |
3067 | SH_PFC_PIN_GROUP(msiof3_ss1), |
3068 | SH_PFC_PIN_GROUP(msiof3_ss2), |
3069 | SH_PFC_PIN_GROUP(msiof3_rxd), |
3070 | SH_PFC_PIN_GROUP(msiof3_txd), |
3071 | SH_PFC_PIN_GROUP(msiof3_flow), |
3072 | SH_PFC_PIN_GROUP(scifa0_data), |
3073 | SH_PFC_PIN_GROUP(scifa0_clk), |
3074 | SH_PFC_PIN_GROUP(scifa0_ctrl), |
3075 | SH_PFC_PIN_GROUP(scifa1_data), |
3076 | SH_PFC_PIN_GROUP(scifa1_clk), |
3077 | SH_PFC_PIN_GROUP(scifa1_ctrl), |
3078 | SH_PFC_PIN_GROUP(scifa2_data_0), |
3079 | SH_PFC_PIN_GROUP(scifa2_clk_0), |
3080 | SH_PFC_PIN_GROUP(scifa2_ctrl_0), |
3081 | SH_PFC_PIN_GROUP(scifa2_data_1), |
3082 | SH_PFC_PIN_GROUP(scifa2_clk_1), |
3083 | SH_PFC_PIN_GROUP(scifa2_ctrl_1), |
3084 | SH_PFC_PIN_GROUP(scifa3_data), |
3085 | SH_PFC_PIN_GROUP(scifa3_ctrl), |
3086 | SH_PFC_PIN_GROUP(scifa4_data), |
3087 | SH_PFC_PIN_GROUP(scifa4_ctrl), |
3088 | SH_PFC_PIN_GROUP(scifa5_data_0), |
3089 | SH_PFC_PIN_GROUP(scifa5_clk_0), |
3090 | SH_PFC_PIN_GROUP(scifa5_ctrl_0), |
3091 | SH_PFC_PIN_GROUP(scifa5_data_1), |
3092 | SH_PFC_PIN_GROUP(scifa5_clk_1), |
3093 | SH_PFC_PIN_GROUP(scifa5_ctrl_1), |
3094 | SH_PFC_PIN_GROUP(scifa5_data_2), |
3095 | SH_PFC_PIN_GROUP(scifa5_clk_2), |
3096 | SH_PFC_PIN_GROUP(scifa5_ctrl_2), |
3097 | SH_PFC_PIN_GROUP(scifa6), |
3098 | SH_PFC_PIN_GROUP(scifa7_data), |
3099 | SH_PFC_PIN_GROUP(scifa7_ctrl), |
3100 | SH_PFC_PIN_GROUP(scifb_data_0), |
3101 | SH_PFC_PIN_GROUP(scifb_clk_0), |
3102 | SH_PFC_PIN_GROUP(scifb_ctrl_0), |
3103 | SH_PFC_PIN_GROUP(scifb_data_1), |
3104 | SH_PFC_PIN_GROUP(scifb_clk_1), |
3105 | SH_PFC_PIN_GROUP(scifb_ctrl_1), |
3106 | BUS_DATA_PIN_GROUP(sdhi0_data, 1), |
3107 | BUS_DATA_PIN_GROUP(sdhi0_data, 4), |
3108 | SH_PFC_PIN_GROUP(sdhi0_ctrl), |
3109 | SH_PFC_PIN_GROUP(sdhi0_cd), |
3110 | SH_PFC_PIN_GROUP(sdhi0_wp), |
3111 | BUS_DATA_PIN_GROUP(sdhi1_data, 1), |
3112 | BUS_DATA_PIN_GROUP(sdhi1_data, 4), |
3113 | SH_PFC_PIN_GROUP(sdhi1_ctrl), |
3114 | BUS_DATA_PIN_GROUP(sdhi2_data, 1), |
3115 | BUS_DATA_PIN_GROUP(sdhi2_data, 4), |
3116 | SH_PFC_PIN_GROUP(sdhi2_ctrl), |
3117 | SH_PFC_PIN_GROUP(tpu0_to0), |
3118 | SH_PFC_PIN_GROUP(tpu0_to1), |
3119 | SH_PFC_PIN_GROUP(tpu0_to2), |
3120 | SH_PFC_PIN_GROUP(tpu0_to3), |
3121 | SH_PFC_PIN_GROUP(tpu1_to0), |
3122 | SH_PFC_PIN_GROUP(tpu1_to1_0), |
3123 | SH_PFC_PIN_GROUP(tpu1_to1_1), |
3124 | SH_PFC_PIN_GROUP(tpu1_to2), |
3125 | SH_PFC_PIN_GROUP(tpu1_to3), |
3126 | SH_PFC_PIN_GROUP(tpu2_to0), |
3127 | SH_PFC_PIN_GROUP(tpu2_to1), |
3128 | SH_PFC_PIN_GROUP(tpu2_to2), |
3129 | SH_PFC_PIN_GROUP(tpu2_to3), |
3130 | SH_PFC_PIN_GROUP(tpu3_to0), |
3131 | SH_PFC_PIN_GROUP(tpu3_to1), |
3132 | SH_PFC_PIN_GROUP(tpu3_to2), |
3133 | SH_PFC_PIN_GROUP(tpu3_to3), |
3134 | SH_PFC_PIN_GROUP(tpu4_to0), |
3135 | SH_PFC_PIN_GROUP(tpu4_to1), |
3136 | SH_PFC_PIN_GROUP(tpu4_to2), |
3137 | SH_PFC_PIN_GROUP(tpu4_to3), |
3138 | SH_PFC_PIN_GROUP(usb_vbus), |
3139 | }; |
3140 | |
3141 | static const char * const bsc_groups[] = { |
3142 | "bsc_data_0_7" , |
3143 | "bsc_data_8_15" , |
3144 | "bsc_cs4" , |
3145 | "bsc_cs5_a" , |
3146 | "bsc_cs5_b" , |
3147 | "bsc_cs6_a" , |
3148 | "bsc_cs6_b" , |
3149 | "bsc_rd" , |
3150 | "bsc_rdwr_0" , |
3151 | "bsc_rdwr_1" , |
3152 | "bsc_rdwr_2" , |
3153 | "bsc_we0" , |
3154 | "bsc_we1" , |
3155 | }; |
3156 | |
3157 | static const char * const fsia_groups[] = { |
3158 | "fsia_mclk_in" , |
3159 | "fsia_mclk_out" , |
3160 | "fsia_sclk_in" , |
3161 | "fsia_sclk_out" , |
3162 | "fsia_data_in" , |
3163 | "fsia_data_out" , |
3164 | "fsia_spdif" , |
3165 | }; |
3166 | |
3167 | static const char * const fsib_groups[] = { |
3168 | "fsib_mclk_in" , |
3169 | "fsib_mclk_out" , |
3170 | "fsib_sclk_in" , |
3171 | "fsib_sclk_out" , |
3172 | "fsib_data_in" , |
3173 | "fsib_data_out" , |
3174 | "fsib_spdif" , |
3175 | }; |
3176 | |
3177 | static const char * const fsic_groups[] = { |
3178 | "fsic_mclk_in" , |
3179 | "fsic_mclk_out" , |
3180 | "fsic_sclk_in" , |
3181 | "fsic_sclk_out" , |
3182 | "fsic_data_in" , |
3183 | "fsic_data_out" , |
3184 | "fsic_spdif_0" , |
3185 | "fsic_spdif_1" , |
3186 | }; |
3187 | |
3188 | static const char * const fsid_groups[] = { |
3189 | "fsid_sclk_in" , |
3190 | "fsid_sclk_out" , |
3191 | "fsid_data_in" , |
3192 | }; |
3193 | |
3194 | static const char * const i2c2_groups[] = { |
3195 | "i2c2_0" , |
3196 | "i2c2_1" , |
3197 | "i2c2_2" , |
3198 | }; |
3199 | |
3200 | static const char * const i2c3_groups[] = { |
3201 | "i2c3_0" , |
3202 | "i2c3_1" , |
3203 | "i2c3_2" , |
3204 | }; |
3205 | |
3206 | static const char * const irda_groups[] = { |
3207 | "irda_0" , |
3208 | "irda_1" , |
3209 | }; |
3210 | |
3211 | static const char * const keysc_groups[] = { |
3212 | "keysc_in5" , |
3213 | "keysc_in6" , |
3214 | "keysc_in7" , |
3215 | "keysc_in8" , |
3216 | "keysc_out04" , |
3217 | "keysc_out5" , |
3218 | "keysc_out6_0" , |
3219 | "keysc_out6_1" , |
3220 | "keysc_out6_2" , |
3221 | "keysc_out7_0" , |
3222 | "keysc_out7_1" , |
3223 | "keysc_out7_2" , |
3224 | "keysc_out8_0" , |
3225 | "keysc_out8_1" , |
3226 | "keysc_out8_2" , |
3227 | "keysc_out9_0" , |
3228 | "keysc_out9_1" , |
3229 | "keysc_out9_2" , |
3230 | "keysc_out10_0" , |
3231 | "keysc_out10_1" , |
3232 | "keysc_out11_0" , |
3233 | "keysc_out11_1" , |
3234 | }; |
3235 | |
3236 | static const char * const lcd_groups[] = { |
3237 | "lcd_data8" , |
3238 | "lcd_data9" , |
3239 | "lcd_data12" , |
3240 | "lcd_data16" , |
3241 | "lcd_data18" , |
3242 | "lcd_data24" , |
3243 | "lcd_display" , |
3244 | "lcd_lclk" , |
3245 | "lcd_sync" , |
3246 | "lcd_sys" , |
3247 | }; |
3248 | |
3249 | static const char * const lcd2_groups[] = { |
3250 | "lcd2_data8" , |
3251 | "lcd2_data9" , |
3252 | "lcd2_data12" , |
3253 | "lcd2_data16" , |
3254 | "lcd2_data18" , |
3255 | "lcd2_data24" , |
3256 | "lcd2_sync_0" , |
3257 | "lcd2_sync_1" , |
3258 | "lcd2_sys_0" , |
3259 | "lcd2_sys_1" , |
3260 | }; |
3261 | |
3262 | static const char * const mmc0_groups[] = { |
3263 | "mmc0_data1_0" , |
3264 | "mmc0_data4_0" , |
3265 | "mmc0_data8_0" , |
3266 | "mmc0_ctrl_0" , |
3267 | "mmc0_data1_1" , |
3268 | "mmc0_data4_1" , |
3269 | "mmc0_data8_1" , |
3270 | "mmc0_ctrl_1" , |
3271 | }; |
3272 | |
3273 | static const char * const msiof0_groups[] = { |
3274 | "msiof0_rsck" , |
3275 | "msiof0_tsck" , |
3276 | "msiof0_rsync" , |
3277 | "msiof0_tsync" , |
3278 | "msiof0_ss1" , |
3279 | "msiof0_ss2" , |
3280 | "msiof0_rxd" , |
3281 | "msiof0_txd" , |
3282 | "msiof0_mck0" , |
3283 | "msiof0_mck1" , |
3284 | "msiof0l_rsck" , |
3285 | "msiof0l_tsck" , |
3286 | "msiof0l_rsync" , |
3287 | "msiof0l_tsync" , |
3288 | "msiof0l_ss1_a" , |
3289 | "msiof0l_ss1_b" , |
3290 | "msiof0l_ss2_a" , |
3291 | "msiof0l_ss2_b" , |
3292 | "msiof0l_rxd" , |
3293 | "msiof0l_txd" , |
3294 | "msiof0l_mck0" , |
3295 | "msiof0l_mck1" , |
3296 | }; |
3297 | |
3298 | static const char * const msiof1_groups[] = { |
3299 | "msiof1_rsck" , |
3300 | "msiof1_tsck" , |
3301 | "msiof1_rsync" , |
3302 | "msiof1_tsync" , |
3303 | "msiof1_ss1" , |
3304 | "msiof1_ss2" , |
3305 | "msiof1_rxd" , |
3306 | "msiof1_txd" , |
3307 | "msiof1_mck0" , |
3308 | "msiof1_mck1" , |
3309 | }; |
3310 | |
3311 | static const char * const msiof2_groups[] = { |
3312 | "msiof2_rsck" , |
3313 | "msiof2_tsck" , |
3314 | "msiof2_rsync" , |
3315 | "msiof2_tsync" , |
3316 | "msiof2_ss1_a" , |
3317 | "msiof2_ss1_b" , |
3318 | "msiof2_ss2_a" , |
3319 | "msiof2_ss2_b" , |
3320 | "msiof2_rxd_a" , |
3321 | "msiof2_rxd_b" , |
3322 | "msiof2_txd" , |
3323 | "msiof2_mck0" , |
3324 | "msiof2_mck1" , |
3325 | "msiof2r_tsck" , |
3326 | "msiof2r_tsync" , |
3327 | "msiof2r_rxd" , |
3328 | "msiof2r_txd" , |
3329 | }; |
3330 | |
3331 | static const char * const msiof3_groups[] = { |
3332 | "msiof3_rsck" , |
3333 | "msiof3_tsck" , |
3334 | "msiof3_rsync" , |
3335 | "msiof3_tsync" , |
3336 | "msiof3_ss1" , |
3337 | "msiof3_ss2" , |
3338 | "msiof3_rxd" , |
3339 | "msiof3_txd" , |
3340 | "msiof3_flow" , |
3341 | }; |
3342 | |
3343 | static const char * const scifa0_groups[] = { |
3344 | "scifa0_data" , |
3345 | "scifa0_clk" , |
3346 | "scifa0_ctrl" , |
3347 | }; |
3348 | |
3349 | static const char * const scifa1_groups[] = { |
3350 | "scifa1_data" , |
3351 | "scifa1_clk" , |
3352 | "scifa1_ctrl" , |
3353 | }; |
3354 | |
3355 | static const char * const scifa2_groups[] = { |
3356 | "scifa2_data_0" , |
3357 | "scifa2_clk_0" , |
3358 | "scifa2_ctrl_0" , |
3359 | "scifa2_data_1" , |
3360 | "scifa2_clk_1" , |
3361 | "scifa2_ctrl_1" , |
3362 | }; |
3363 | |
3364 | static const char * const scifa3_groups[] = { |
3365 | "scifa3_data" , |
3366 | "scifa3_ctrl" , |
3367 | }; |
3368 | |
3369 | static const char * const scifa4_groups[] = { |
3370 | "scifa4_data" , |
3371 | "scifa4_ctrl" , |
3372 | }; |
3373 | |
3374 | static const char * const scifa5_groups[] = { |
3375 | "scifa5_data_0" , |
3376 | "scifa5_clk_0" , |
3377 | "scifa5_ctrl_0" , |
3378 | "scifa5_data_1" , |
3379 | "scifa5_clk_1" , |
3380 | "scifa5_ctrl_1" , |
3381 | "scifa5_data_2" , |
3382 | "scifa5_clk_2" , |
3383 | "scifa5_ctrl_2" , |
3384 | }; |
3385 | |
3386 | static const char * const scifa6_groups[] = { |
3387 | "scifa6" , |
3388 | }; |
3389 | |
3390 | static const char * const scifa7_groups[] = { |
3391 | "scifa7_data" , |
3392 | "scifa7_ctrl" , |
3393 | }; |
3394 | |
3395 | static const char * const scifb_groups[] = { |
3396 | "scifb_data_0" , |
3397 | "scifb_clk_0" , |
3398 | "scifb_ctrl_0" , |
3399 | "scifb_data_1" , |
3400 | "scifb_clk_1" , |
3401 | "scifb_ctrl_1" , |
3402 | }; |
3403 | |
3404 | static const char * const sdhi0_groups[] = { |
3405 | "sdhi0_data1" , |
3406 | "sdhi0_data4" , |
3407 | "sdhi0_ctrl" , |
3408 | "sdhi0_cd" , |
3409 | "sdhi0_wp" , |
3410 | }; |
3411 | |
3412 | static const char * const sdhi1_groups[] = { |
3413 | "sdhi1_data1" , |
3414 | "sdhi1_data4" , |
3415 | "sdhi1_ctrl" , |
3416 | }; |
3417 | |
3418 | static const char * const sdhi2_groups[] = { |
3419 | "sdhi2_data1" , |
3420 | "sdhi2_data4" , |
3421 | "sdhi2_ctrl" , |
3422 | }; |
3423 | |
3424 | static const char * const usb_groups[] = { |
3425 | "usb_vbus" , |
3426 | }; |
3427 | |
3428 | static const char * const tpu0_groups[] = { |
3429 | "tpu0_to0" , |
3430 | "tpu0_to1" , |
3431 | "tpu0_to2" , |
3432 | "tpu0_to3" , |
3433 | }; |
3434 | |
3435 | static const char * const tpu1_groups[] = { |
3436 | "tpu1_to0" , |
3437 | "tpu1_to1_0" , |
3438 | "tpu1_to1_1" , |
3439 | "tpu1_to2" , |
3440 | "tpu1_to3" , |
3441 | }; |
3442 | |
3443 | static const char * const tpu2_groups[] = { |
3444 | "tpu2_to0" , |
3445 | "tpu2_to1" , |
3446 | "tpu2_to2" , |
3447 | "tpu2_to3" , |
3448 | }; |
3449 | |
3450 | static const char * const tpu3_groups[] = { |
3451 | "tpu3_to0" , |
3452 | "tpu3_to1" , |
3453 | "tpu3_to2" , |
3454 | "tpu3_to3" , |
3455 | }; |
3456 | |
3457 | static const char * const tpu4_groups[] = { |
3458 | "tpu4_to0" , |
3459 | "tpu4_to1" , |
3460 | "tpu4_to2" , |
3461 | "tpu4_to3" , |
3462 | }; |
3463 | |
3464 | static const struct sh_pfc_function pinmux_functions[] = { |
3465 | SH_PFC_FUNCTION(bsc), |
3466 | SH_PFC_FUNCTION(fsia), |
3467 | SH_PFC_FUNCTION(fsib), |
3468 | SH_PFC_FUNCTION(fsic), |
3469 | SH_PFC_FUNCTION(fsid), |
3470 | SH_PFC_FUNCTION(i2c2), |
3471 | SH_PFC_FUNCTION(i2c3), |
3472 | SH_PFC_FUNCTION(irda), |
3473 | SH_PFC_FUNCTION(keysc), |
3474 | SH_PFC_FUNCTION(lcd), |
3475 | SH_PFC_FUNCTION(lcd2), |
3476 | SH_PFC_FUNCTION(mmc0), |
3477 | SH_PFC_FUNCTION(msiof0), |
3478 | SH_PFC_FUNCTION(msiof1), |
3479 | SH_PFC_FUNCTION(msiof2), |
3480 | SH_PFC_FUNCTION(msiof3), |
3481 | SH_PFC_FUNCTION(scifa0), |
3482 | SH_PFC_FUNCTION(scifa1), |
3483 | SH_PFC_FUNCTION(scifa2), |
3484 | SH_PFC_FUNCTION(scifa3), |
3485 | SH_PFC_FUNCTION(scifa4), |
3486 | SH_PFC_FUNCTION(scifa5), |
3487 | SH_PFC_FUNCTION(scifa6), |
3488 | SH_PFC_FUNCTION(scifa7), |
3489 | SH_PFC_FUNCTION(scifb), |
3490 | SH_PFC_FUNCTION(sdhi0), |
3491 | SH_PFC_FUNCTION(sdhi1), |
3492 | SH_PFC_FUNCTION(sdhi2), |
3493 | SH_PFC_FUNCTION(tpu0), |
3494 | SH_PFC_FUNCTION(tpu1), |
3495 | SH_PFC_FUNCTION(tpu2), |
3496 | SH_PFC_FUNCTION(tpu3), |
3497 | SH_PFC_FUNCTION(tpu4), |
3498 | SH_PFC_FUNCTION(usb), |
3499 | }; |
3500 | |
3501 | static const struct pinmux_cfg_reg pinmux_config_regs[] = { |
3502 | PORTCR(0, 0xe6050000), /* PORT0CR */ |
3503 | PORTCR(1, 0xe6050001), /* PORT1CR */ |
3504 | PORTCR(2, 0xe6050002), /* PORT2CR */ |
3505 | PORTCR(3, 0xe6050003), /* PORT3CR */ |
3506 | PORTCR(4, 0xe6050004), /* PORT4CR */ |
3507 | PORTCR(5, 0xe6050005), /* PORT5CR */ |
3508 | PORTCR(6, 0xe6050006), /* PORT6CR */ |
3509 | PORTCR(7, 0xe6050007), /* PORT7CR */ |
3510 | PORTCR(8, 0xe6050008), /* PORT8CR */ |
3511 | PORTCR(9, 0xe6050009), /* PORT9CR */ |
3512 | |
3513 | PORTCR(10, 0xe605000a), /* PORT10CR */ |
3514 | PORTCR(11, 0xe605000b), /* PORT11CR */ |
3515 | PORTCR(12, 0xe605000c), /* PORT12CR */ |
3516 | PORTCR(13, 0xe605000d), /* PORT13CR */ |
3517 | PORTCR(14, 0xe605000e), /* PORT14CR */ |
3518 | PORTCR(15, 0xe605000f), /* PORT15CR */ |
3519 | PORTCR(16, 0xe6050010), /* PORT16CR */ |
3520 | PORTCR(17, 0xe6050011), /* PORT17CR */ |
3521 | PORTCR(18, 0xe6050012), /* PORT18CR */ |
3522 | PORTCR(19, 0xe6050013), /* PORT19CR */ |
3523 | |
3524 | PORTCR(20, 0xe6050014), /* PORT20CR */ |
3525 | PORTCR(21, 0xe6050015), /* PORT21CR */ |
3526 | PORTCR(22, 0xe6050016), /* PORT22CR */ |
3527 | PORTCR(23, 0xe6050017), /* PORT23CR */ |
3528 | PORTCR(24, 0xe6050018), /* PORT24CR */ |
3529 | PORTCR(25, 0xe6050019), /* PORT25CR */ |
3530 | PORTCR(26, 0xe605001a), /* PORT26CR */ |
3531 | PORTCR(27, 0xe605001b), /* PORT27CR */ |
3532 | PORTCR(28, 0xe605001c), /* PORT28CR */ |
3533 | PORTCR(29, 0xe605001d), /* PORT29CR */ |
3534 | |
3535 | PORTCR(30, 0xe605001e), /* PORT30CR */ |
3536 | PORTCR(31, 0xe605001f), /* PORT31CR */ |
3537 | PORTCR(32, 0xe6051020), /* PORT32CR */ |
3538 | PORTCR(33, 0xe6051021), /* PORT33CR */ |
3539 | PORTCR(34, 0xe6051022), /* PORT34CR */ |
3540 | PORTCR(35, 0xe6051023), /* PORT35CR */ |
3541 | PORTCR(36, 0xe6051024), /* PORT36CR */ |
3542 | PORTCR(37, 0xe6051025), /* PORT37CR */ |
3543 | PORTCR(38, 0xe6051026), /* PORT38CR */ |
3544 | PORTCR(39, 0xe6051027), /* PORT39CR */ |
3545 | |
3546 | PORTCR(40, 0xe6051028), /* PORT40CR */ |
3547 | PORTCR(41, 0xe6051029), /* PORT41CR */ |
3548 | PORTCR(42, 0xe605102a), /* PORT42CR */ |
3549 | PORTCR(43, 0xe605102b), /* PORT43CR */ |
3550 | PORTCR(44, 0xe605102c), /* PORT44CR */ |
3551 | PORTCR(45, 0xe605102d), /* PORT45CR */ |
3552 | PORTCR(46, 0xe605102e), /* PORT46CR */ |
3553 | PORTCR(47, 0xe605102f), /* PORT47CR */ |
3554 | PORTCR(48, 0xe6051030), /* PORT48CR */ |
3555 | PORTCR(49, 0xe6051031), /* PORT49CR */ |
3556 | |
3557 | PORTCR(50, 0xe6051032), /* PORT50CR */ |
3558 | PORTCR(51, 0xe6051033), /* PORT51CR */ |
3559 | PORTCR(52, 0xe6051034), /* PORT52CR */ |
3560 | PORTCR(53, 0xe6051035), /* PORT53CR */ |
3561 | PORTCR(54, 0xe6051036), /* PORT54CR */ |
3562 | PORTCR(55, 0xe6051037), /* PORT55CR */ |
3563 | PORTCR(56, 0xe6051038), /* PORT56CR */ |
3564 | PORTCR(57, 0xe6051039), /* PORT57CR */ |
3565 | PORTCR(58, 0xe605103a), /* PORT58CR */ |
3566 | PORTCR(59, 0xe605103b), /* PORT59CR */ |
3567 | |
3568 | PORTCR(60, 0xe605103c), /* PORT60CR */ |
3569 | PORTCR(61, 0xe605103d), /* PORT61CR */ |
3570 | PORTCR(62, 0xe605103e), /* PORT62CR */ |
3571 | PORTCR(63, 0xe605103f), /* PORT63CR */ |
3572 | PORTCR(64, 0xe6051040), /* PORT64CR */ |
3573 | PORTCR(65, 0xe6051041), /* PORT65CR */ |
3574 | PORTCR(66, 0xe6051042), /* PORT66CR */ |
3575 | PORTCR(67, 0xe6051043), /* PORT67CR */ |
3576 | PORTCR(68, 0xe6051044), /* PORT68CR */ |
3577 | PORTCR(69, 0xe6051045), /* PORT69CR */ |
3578 | |
3579 | PORTCR(70, 0xe6051046), /* PORT70CR */ |
3580 | PORTCR(71, 0xe6051047), /* PORT71CR */ |
3581 | PORTCR(72, 0xe6051048), /* PORT72CR */ |
3582 | PORTCR(73, 0xe6051049), /* PORT73CR */ |
3583 | PORTCR(74, 0xe605104a), /* PORT74CR */ |
3584 | PORTCR(75, 0xe605104b), /* PORT75CR */ |
3585 | PORTCR(76, 0xe605104c), /* PORT76CR */ |
3586 | PORTCR(77, 0xe605104d), /* PORT77CR */ |
3587 | PORTCR(78, 0xe605104e), /* PORT78CR */ |
3588 | PORTCR(79, 0xe605104f), /* PORT79CR */ |
3589 | |
3590 | PORTCR(80, 0xe6051050), /* PORT80CR */ |
3591 | PORTCR(81, 0xe6051051), /* PORT81CR */ |
3592 | PORTCR(82, 0xe6051052), /* PORT82CR */ |
3593 | PORTCR(83, 0xe6051053), /* PORT83CR */ |
3594 | PORTCR(84, 0xe6051054), /* PORT84CR */ |
3595 | PORTCR(85, 0xe6051055), /* PORT85CR */ |
3596 | PORTCR(86, 0xe6051056), /* PORT86CR */ |
3597 | PORTCR(87, 0xe6051057), /* PORT87CR */ |
3598 | PORTCR(88, 0xe6051058), /* PORT88CR */ |
3599 | PORTCR(89, 0xe6051059), /* PORT89CR */ |
3600 | |
3601 | PORTCR(90, 0xe605105a), /* PORT90CR */ |
3602 | PORTCR(91, 0xe605105b), /* PORT91CR */ |
3603 | PORTCR(92, 0xe605105c), /* PORT92CR */ |
3604 | PORTCR(93, 0xe605105d), /* PORT93CR */ |
3605 | PORTCR(94, 0xe605105e), /* PORT94CR */ |
3606 | PORTCR(95, 0xe605105f), /* PORT95CR */ |
3607 | PORTCR(96, 0xe6052060), /* PORT96CR */ |
3608 | PORTCR(97, 0xe6052061), /* PORT97CR */ |
3609 | PORTCR(98, 0xe6052062), /* PORT98CR */ |
3610 | PORTCR(99, 0xe6052063), /* PORT99CR */ |
3611 | |
3612 | PORTCR(100, 0xe6052064), /* PORT100CR */ |
3613 | PORTCR(101, 0xe6052065), /* PORT101CR */ |
3614 | PORTCR(102, 0xe6052066), /* PORT102CR */ |
3615 | PORTCR(103, 0xe6052067), /* PORT103CR */ |
3616 | PORTCR(104, 0xe6052068), /* PORT104CR */ |
3617 | PORTCR(105, 0xe6052069), /* PORT105CR */ |
3618 | PORTCR(106, 0xe605206a), /* PORT106CR */ |
3619 | PORTCR(107, 0xe605206b), /* PORT107CR */ |
3620 | PORTCR(108, 0xe605206c), /* PORT108CR */ |
3621 | PORTCR(109, 0xe605206d), /* PORT109CR */ |
3622 | |
3623 | PORTCR(110, 0xe605206e), /* PORT110CR */ |
3624 | PORTCR(111, 0xe605206f), /* PORT111CR */ |
3625 | PORTCR(112, 0xe6052070), /* PORT112CR */ |
3626 | PORTCR(113, 0xe6052071), /* PORT113CR */ |
3627 | PORTCR(114, 0xe6052072), /* PORT114CR */ |
3628 | PORTCR(115, 0xe6052073), /* PORT115CR */ |
3629 | PORTCR(116, 0xe6052074), /* PORT116CR */ |
3630 | PORTCR(117, 0xe6052075), /* PORT117CR */ |
3631 | PORTCR(118, 0xe6052076), /* PORT118CR */ |
3632 | |
3633 | PORTCR(128, 0xe6052080), /* PORT128CR */ |
3634 | PORTCR(129, 0xe6052081), /* PORT129CR */ |
3635 | |
3636 | PORTCR(130, 0xe6052082), /* PORT130CR */ |
3637 | PORTCR(131, 0xe6052083), /* PORT131CR */ |
3638 | PORTCR(132, 0xe6052084), /* PORT132CR */ |
3639 | PORTCR(133, 0xe6052085), /* PORT133CR */ |
3640 | PORTCR(134, 0xe6052086), /* PORT134CR */ |
3641 | PORTCR(135, 0xe6052087), /* PORT135CR */ |
3642 | PORTCR(136, 0xe6052088), /* PORT136CR */ |
3643 | PORTCR(137, 0xe6052089), /* PORT137CR */ |
3644 | PORTCR(138, 0xe605208a), /* PORT138CR */ |
3645 | PORTCR(139, 0xe605208b), /* PORT139CR */ |
3646 | |
3647 | PORTCR(140, 0xe605208c), /* PORT140CR */ |
3648 | PORTCR(141, 0xe605208d), /* PORT141CR */ |
3649 | PORTCR(142, 0xe605208e), /* PORT142CR */ |
3650 | PORTCR(143, 0xe605208f), /* PORT143CR */ |
3651 | PORTCR(144, 0xe6052090), /* PORT144CR */ |
3652 | PORTCR(145, 0xe6052091), /* PORT145CR */ |
3653 | PORTCR(146, 0xe6052092), /* PORT146CR */ |
3654 | PORTCR(147, 0xe6052093), /* PORT147CR */ |
3655 | PORTCR(148, 0xe6052094), /* PORT148CR */ |
3656 | PORTCR(149, 0xe6052095), /* PORT149CR */ |
3657 | |
3658 | PORTCR(150, 0xe6052096), /* PORT150CR */ |
3659 | PORTCR(151, 0xe6052097), /* PORT151CR */ |
3660 | PORTCR(152, 0xe6052098), /* PORT152CR */ |
3661 | PORTCR(153, 0xe6052099), /* PORT153CR */ |
3662 | PORTCR(154, 0xe605209a), /* PORT154CR */ |
3663 | PORTCR(155, 0xe605209b), /* PORT155CR */ |
3664 | PORTCR(156, 0xe605209c), /* PORT156CR */ |
3665 | PORTCR(157, 0xe605209d), /* PORT157CR */ |
3666 | PORTCR(158, 0xe605209e), /* PORT158CR */ |
3667 | PORTCR(159, 0xe605209f), /* PORT159CR */ |
3668 | |
3669 | PORTCR(160, 0xe60520a0), /* PORT160CR */ |
3670 | PORTCR(161, 0xe60520a1), /* PORT161CR */ |
3671 | PORTCR(162, 0xe60520a2), /* PORT162CR */ |
3672 | PORTCR(163, 0xe60520a3), /* PORT163CR */ |
3673 | PORTCR(164, 0xe60520a4), /* PORT164CR */ |
3674 | |
3675 | PORTCR(192, 0xe60520c0), /* PORT192CR */ |
3676 | PORTCR(193, 0xe60520c1), /* PORT193CR */ |
3677 | PORTCR(194, 0xe60520c2), /* PORT194CR */ |
3678 | PORTCR(195, 0xe60520c3), /* PORT195CR */ |
3679 | PORTCR(196, 0xe60520c4), /* PORT196CR */ |
3680 | PORTCR(197, 0xe60520c5), /* PORT197CR */ |
3681 | PORTCR(198, 0xe60520c6), /* PORT198CR */ |
3682 | PORTCR(199, 0xe60520c7), /* PORT199CR */ |
3683 | |
3684 | PORTCR(200, 0xe60520c8), /* PORT200CR */ |
3685 | PORTCR(201, 0xe60520c9), /* PORT201CR */ |
3686 | PORTCR(202, 0xe60520ca), /* PORT202CR */ |
3687 | PORTCR(203, 0xe60520cb), /* PORT203CR */ |
3688 | PORTCR(204, 0xe60520cc), /* PORT204CR */ |
3689 | PORTCR(205, 0xe60520cd), /* PORT205CR */ |
3690 | PORTCR(206, 0xe60520ce), /* PORT206CR */ |
3691 | PORTCR(207, 0xe60520cf), /* PORT207CR */ |
3692 | PORTCR(208, 0xe60520d0), /* PORT208CR */ |
3693 | PORTCR(209, 0xe60520d1), /* PORT209CR */ |
3694 | |
3695 | PORTCR(210, 0xe60520d2), /* PORT210CR */ |
3696 | PORTCR(211, 0xe60520d3), /* PORT211CR */ |
3697 | PORTCR(212, 0xe60520d4), /* PORT212CR */ |
3698 | PORTCR(213, 0xe60520d5), /* PORT213CR */ |
3699 | PORTCR(214, 0xe60520d6), /* PORT214CR */ |
3700 | PORTCR(215, 0xe60520d7), /* PORT215CR */ |
3701 | PORTCR(216, 0xe60520d8), /* PORT216CR */ |
3702 | PORTCR(217, 0xe60520d9), /* PORT217CR */ |
3703 | PORTCR(218, 0xe60520da), /* PORT218CR */ |
3704 | PORTCR(219, 0xe60520db), /* PORT219CR */ |
3705 | |
3706 | PORTCR(220, 0xe60520dc), /* PORT220CR */ |
3707 | PORTCR(221, 0xe60520dd), /* PORT221CR */ |
3708 | PORTCR(222, 0xe60520de), /* PORT222CR */ |
3709 | PORTCR(223, 0xe60520df), /* PORT223CR */ |
3710 | PORTCR(224, 0xe60530e0), /* PORT224CR */ |
3711 | PORTCR(225, 0xe60530e1), /* PORT225CR */ |
3712 | PORTCR(226, 0xe60530e2), /* PORT226CR */ |
3713 | PORTCR(227, 0xe60530e3), /* PORT227CR */ |
3714 | PORTCR(228, 0xe60530e4), /* PORT228CR */ |
3715 | PORTCR(229, 0xe60530e5), /* PORT229CR */ |
3716 | |
3717 | PORTCR(230, 0xe60530e6), /* PORT230CR */ |
3718 | PORTCR(231, 0xe60530e7), /* PORT231CR */ |
3719 | PORTCR(232, 0xe60530e8), /* PORT232CR */ |
3720 | PORTCR(233, 0xe60530e9), /* PORT233CR */ |
3721 | PORTCR(234, 0xe60530ea), /* PORT234CR */ |
3722 | PORTCR(235, 0xe60530eb), /* PORT235CR */ |
3723 | PORTCR(236, 0xe60530ec), /* PORT236CR */ |
3724 | PORTCR(237, 0xe60530ed), /* PORT237CR */ |
3725 | PORTCR(238, 0xe60530ee), /* PORT238CR */ |
3726 | PORTCR(239, 0xe60530ef), /* PORT239CR */ |
3727 | |
3728 | PORTCR(240, 0xe60530f0), /* PORT240CR */ |
3729 | PORTCR(241, 0xe60530f1), /* PORT241CR */ |
3730 | PORTCR(242, 0xe60530f2), /* PORT242CR */ |
3731 | PORTCR(243, 0xe60530f3), /* PORT243CR */ |
3732 | PORTCR(244, 0xe60530f4), /* PORT244CR */ |
3733 | PORTCR(245, 0xe60530f5), /* PORT245CR */ |
3734 | PORTCR(246, 0xe60530f6), /* PORT246CR */ |
3735 | PORTCR(247, 0xe60530f7), /* PORT247CR */ |
3736 | PORTCR(248, 0xe60530f8), /* PORT248CR */ |
3737 | PORTCR(249, 0xe60530f9), /* PORT249CR */ |
3738 | |
3739 | PORTCR(250, 0xe60530fa), /* PORT250CR */ |
3740 | PORTCR(251, 0xe60530fb), /* PORT251CR */ |
3741 | PORTCR(252, 0xe60530fc), /* PORT252CR */ |
3742 | PORTCR(253, 0xe60530fd), /* PORT253CR */ |
3743 | PORTCR(254, 0xe60530fe), /* PORT254CR */ |
3744 | PORTCR(255, 0xe60530ff), /* PORT255CR */ |
3745 | PORTCR(256, 0xe6053100), /* PORT256CR */ |
3746 | PORTCR(257, 0xe6053101), /* PORT257CR */ |
3747 | PORTCR(258, 0xe6053102), /* PORT258CR */ |
3748 | PORTCR(259, 0xe6053103), /* PORT259CR */ |
3749 | |
3750 | PORTCR(260, 0xe6053104), /* PORT260CR */ |
3751 | PORTCR(261, 0xe6053105), /* PORT261CR */ |
3752 | PORTCR(262, 0xe6053106), /* PORT262CR */ |
3753 | PORTCR(263, 0xe6053107), /* PORT263CR */ |
3754 | PORTCR(264, 0xe6053108), /* PORT264CR */ |
3755 | PORTCR(265, 0xe6053109), /* PORT265CR */ |
3756 | PORTCR(266, 0xe605310a), /* PORT266CR */ |
3757 | PORTCR(267, 0xe605310b), /* PORT267CR */ |
3758 | PORTCR(268, 0xe605310c), /* PORT268CR */ |
3759 | PORTCR(269, 0xe605310d), /* PORT269CR */ |
3760 | |
3761 | PORTCR(270, 0xe605310e), /* PORT270CR */ |
3762 | PORTCR(271, 0xe605310f), /* PORT271CR */ |
3763 | PORTCR(272, 0xe6053110), /* PORT272CR */ |
3764 | PORTCR(273, 0xe6053111), /* PORT273CR */ |
3765 | PORTCR(274, 0xe6053112), /* PORT274CR */ |
3766 | PORTCR(275, 0xe6053113), /* PORT275CR */ |
3767 | PORTCR(276, 0xe6053114), /* PORT276CR */ |
3768 | PORTCR(277, 0xe6053115), /* PORT277CR */ |
3769 | PORTCR(278, 0xe6053116), /* PORT278CR */ |
3770 | PORTCR(279, 0xe6053117), /* PORT279CR */ |
3771 | |
3772 | PORTCR(280, 0xe6053118), /* PORT280CR */ |
3773 | PORTCR(281, 0xe6053119), /* PORT281CR */ |
3774 | PORTCR(282, 0xe605311a), /* PORT282CR */ |
3775 | |
3776 | PORTCR(288, 0xe6052120), /* PORT288CR */ |
3777 | PORTCR(289, 0xe6052121), /* PORT289CR */ |
3778 | |
3779 | PORTCR(290, 0xe6052122), /* PORT290CR */ |
3780 | PORTCR(291, 0xe6052123), /* PORT291CR */ |
3781 | PORTCR(292, 0xe6052124), /* PORT292CR */ |
3782 | PORTCR(293, 0xe6052125), /* PORT293CR */ |
3783 | PORTCR(294, 0xe6052126), /* PORT294CR */ |
3784 | PORTCR(295, 0xe6052127), /* PORT295CR */ |
3785 | PORTCR(296, 0xe6052128), /* PORT296CR */ |
3786 | PORTCR(297, 0xe6052129), /* PORT297CR */ |
3787 | PORTCR(298, 0xe605212a), /* PORT298CR */ |
3788 | PORTCR(299, 0xe605212b), /* PORT299CR */ |
3789 | |
3790 | PORTCR(300, 0xe605212c), /* PORT300CR */ |
3791 | PORTCR(301, 0xe605212d), /* PORT301CR */ |
3792 | PORTCR(302, 0xe605212e), /* PORT302CR */ |
3793 | PORTCR(303, 0xe605212f), /* PORT303CR */ |
3794 | PORTCR(304, 0xe6052130), /* PORT304CR */ |
3795 | PORTCR(305, 0xe6052131), /* PORT305CR */ |
3796 | PORTCR(306, 0xe6052132), /* PORT306CR */ |
3797 | PORTCR(307, 0xe6052133), /* PORT307CR */ |
3798 | PORTCR(308, 0xe6052134), /* PORT308CR */ |
3799 | PORTCR(309, 0xe6052135), /* PORT309CR */ |
3800 | |
3801 | { PINMUX_CFG_REG_VAR("MSEL2CR" , 0xe605801c, 32, |
3802 | GROUP(-12, 1, 1, 1, 1, -1, 1, 1, 1, 1, 1, 1, |
3803 | 1, 1, 1, 1, 1, 1, 1, 1, 1), |
3804 | GROUP( |
3805 | /* RESERVED [12] */ |
3806 | MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1, |
3807 | MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1, |
3808 | MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1, |
3809 | MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1, |
3810 | /* RESERVED [1] */ |
3811 | MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1, |
3812 | MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1, |
3813 | MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1, |
3814 | MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1, |
3815 | MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1, |
3816 | MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1, |
3817 | MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1, |
3818 | MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1, |
3819 | MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1, |
3820 | MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1, |
3821 | MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1, |
3822 | MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1, |
3823 | MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1, |
3824 | MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1, |
3825 | MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1, |
3826 | )) |
3827 | }, |
3828 | { PINMUX_CFG_REG_VAR("MSEL3CR" , 0xe6058020, 32, |
3829 | GROUP(-3, 1, -12, 1, -3, 1, -1, 1, -2, 1, -3, 1, |
3830 | -2), |
3831 | GROUP( |
3832 | /* RESERVED [3] */ |
3833 | MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1, |
3834 | /* RESERVED [12] */ |
3835 | MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1, |
3836 | /* RESERVED [3] */ |
3837 | MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1, |
3838 | /* RESERVED [1] */ |
3839 | MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1, |
3840 | /* RESERVED [2] */ |
3841 | MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1, |
3842 | /* RESERVED [3] */ |
3843 | MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1, |
3844 | /* RESERVED [2] */ |
3845 | )) |
3846 | }, |
3847 | { PINMUX_CFG_REG_VAR("MSEL4CR" , 0xe6058024, 32, |
3848 | GROUP(-2, 1, -1, 1, 1, -3, 1, 1, 1, 1, -3, 1, |
3849 | -1, 1, 1, 1, 1, 1, 1, 1, -2, 1, -2, 1, |
3850 | -1), |
3851 | GROUP( |
3852 | /* RESERVED [2] */ |
3853 | MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1, |
3854 | /* RESERVED [1] */ |
3855 | MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1, |
3856 | MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1, |
3857 | /* RESERVED [3] */ |
3858 | MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1, |
3859 | MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1, |
3860 | MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1, |
3861 | MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1, |
3862 | /* RESERVED [3] */ |
3863 | MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1, |
3864 | /* RESERVED [1] */ |
3865 | MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1, |
3866 | MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1, |
3867 | MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1, |
3868 | MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1, |
3869 | MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1, |
3870 | MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1, |
3871 | MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1, |
3872 | /* RESERVED [2] */ |
3873 | MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1, |
3874 | /* RESERVED [2] */ |
3875 | MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1, |
3876 | /* RESERVED [1] */ |
3877 | )) |
3878 | }, |
3879 | { /* sentinel */ } |
3880 | }; |
3881 | |
3882 | static const struct pinmux_data_reg pinmux_data_regs[] = { |
3883 | { PINMUX_DATA_REG("PORTL031_000DR" , 0xe6054000, 32, GROUP( |
3884 | PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, |
3885 | PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, |
3886 | PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA, |
3887 | PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA, |
3888 | PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA, |
3889 | PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA, |
3890 | PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA, |
3891 | PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA )) |
3892 | }, |
3893 | { PINMUX_DATA_REG("PORTD063_032DR" , 0xe6055000, 32, GROUP( |
3894 | PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA, |
3895 | PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA, |
3896 | PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA, |
3897 | PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA, |
3898 | PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA, |
3899 | PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA, |
3900 | PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA, |
3901 | PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA )) |
3902 | }, |
3903 | { PINMUX_DATA_REG("PORTD095_064DR" , 0xe6055004, 32, GROUP( |
3904 | PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, |
3905 | PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, |
3906 | PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA, |
3907 | PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA, |
3908 | PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA, |
3909 | PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA, |
3910 | PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA, |
3911 | PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA )) |
3912 | }, |
3913 | { PINMUX_DATA_REG("PORTR127_096DR" , 0xe6056000, 32, GROUP( |
3914 | 0, 0, 0, 0, |
3915 | 0, 0, 0, 0, |
3916 | 0, PORT118_DATA, PORT117_DATA, PORT116_DATA, |
3917 | PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA, |
3918 | PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA, |
3919 | PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA, |
3920 | PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA, |
3921 | PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA )) |
3922 | }, |
3923 | { PINMUX_DATA_REG("PORTR159_128DR" , 0xe6056004, 32, GROUP( |
3924 | PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA, |
3925 | PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA, |
3926 | PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA, |
3927 | PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA, |
3928 | PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA, |
3929 | PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA, |
3930 | PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA, |
3931 | PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA )) |
3932 | }, |
3933 | { PINMUX_DATA_REG("PORTR191_160DR" , 0xe6056008, 32, GROUP( |
3934 | 0, 0, 0, 0, |
3935 | 0, 0, 0, 0, |
3936 | 0, 0, 0, 0, |
3937 | 0, 0, 0, 0, |
3938 | 0, 0, 0, 0, |
3939 | 0, 0, 0, 0, |
3940 | 0, 0, 0, PORT164_DATA, |
3941 | PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA )) |
3942 | }, |
3943 | { PINMUX_DATA_REG("PORTR223_192DR" , 0xe605600C, 32, GROUP( |
3944 | PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA, |
3945 | PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA, |
3946 | PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA, |
3947 | PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA, |
3948 | PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA, |
3949 | PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA, |
3950 | PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA, |
3951 | PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA )) |
3952 | }, |
3953 | { PINMUX_DATA_REG("PORTU255_224DR" , 0xe6057000, 32, GROUP( |
3954 | PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA, |
3955 | PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA, |
3956 | PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA, |
3957 | PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA, |
3958 | PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA, |
3959 | PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA, |
3960 | PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA, |
3961 | PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA )) |
3962 | }, |
3963 | { PINMUX_DATA_REG("PORTU287_256DR" , 0xe6057004, 32, GROUP( |
3964 | 0, 0, 0, 0, |
3965 | 0, PORT282_DATA, PORT281_DATA, PORT280_DATA, |
3966 | PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA, |
3967 | PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA, |
3968 | PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA, |
3969 | PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA, |
3970 | PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA, |
3971 | PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA )) |
3972 | }, |
3973 | { PINMUX_DATA_REG("PORTR319_288DR" , 0xe6056010, 32, GROUP( |
3974 | 0, 0, 0, 0, |
3975 | 0, 0, 0, 0, |
3976 | 0, 0, PORT309_DATA, PORT308_DATA, |
3977 | PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA, |
3978 | PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA, |
3979 | PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA, |
3980 | PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA, |
3981 | PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA )) |
3982 | }, |
3983 | { /* sentinel */ } |
3984 | }; |
3985 | |
3986 | static const struct pinmux_irq pinmux_irqs[] = { |
3987 | PINMUX_IRQ(11), /* IRQ0 */ |
3988 | PINMUX_IRQ(10), /* IRQ1 */ |
3989 | PINMUX_IRQ(149), /* IRQ2 */ |
3990 | PINMUX_IRQ(224), /* IRQ3 */ |
3991 | PINMUX_IRQ(159), /* IRQ4 */ |
3992 | PINMUX_IRQ(227), /* IRQ5 */ |
3993 | PINMUX_IRQ(147), /* IRQ6 */ |
3994 | PINMUX_IRQ(150), /* IRQ7 */ |
3995 | PINMUX_IRQ(223), /* IRQ8 */ |
3996 | PINMUX_IRQ(56, 308), /* IRQ9 */ |
3997 | PINMUX_IRQ(54), /* IRQ10 */ |
3998 | PINMUX_IRQ(238), /* IRQ11 */ |
3999 | PINMUX_IRQ(156), /* IRQ12 */ |
4000 | PINMUX_IRQ(239), /* IRQ13 */ |
4001 | PINMUX_IRQ(251), /* IRQ14 */ |
4002 | PINMUX_IRQ(0), /* IRQ15 */ |
4003 | PINMUX_IRQ(249), /* IRQ16 */ |
4004 | PINMUX_IRQ(234), /* IRQ17 */ |
4005 | PINMUX_IRQ(13), /* IRQ18 */ |
4006 | PINMUX_IRQ(9), /* IRQ19 */ |
4007 | PINMUX_IRQ(14), /* IRQ20 */ |
4008 | PINMUX_IRQ(15), /* IRQ21 */ |
4009 | PINMUX_IRQ(40), /* IRQ22 */ |
4010 | PINMUX_IRQ(53), /* IRQ23 */ |
4011 | PINMUX_IRQ(118), /* IRQ24 */ |
4012 | PINMUX_IRQ(164), /* IRQ25 */ |
4013 | PINMUX_IRQ(115), /* IRQ26 */ |
4014 | PINMUX_IRQ(116), /* IRQ27 */ |
4015 | PINMUX_IRQ(117), /* IRQ28 */ |
4016 | PINMUX_IRQ(28), /* IRQ29 */ |
4017 | PINMUX_IRQ(27), /* IRQ30 */ |
4018 | PINMUX_IRQ(26), /* IRQ31 */ |
4019 | }; |
4020 | |
4021 | /* ----------------------------------------------------------------------------- |
4022 | * VCCQ MC0 regulator |
4023 | */ |
4024 | |
4025 | static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable) |
4026 | { |
4027 | struct sh_pfc *pfc = reg->reg_data; |
4028 | void __iomem *addr = pfc->windows[1].virt + 4; |
4029 | unsigned long flags; |
4030 | u32 value; |
4031 | |
4032 | spin_lock_irqsave(&pfc->lock, flags); |
4033 | |
4034 | value = ioread32(addr); |
4035 | |
4036 | if (enable) |
4037 | value |= BIT(28); |
4038 | else |
4039 | value &= ~BIT(28); |
4040 | |
4041 | iowrite32(value, addr); |
4042 | |
4043 | spin_unlock_irqrestore(lock: &pfc->lock, flags); |
4044 | } |
4045 | |
4046 | static int sh73a0_vccq_mc0_enable(struct regulator_dev *reg) |
4047 | { |
4048 | sh73a0_vccq_mc0_endisable(reg, enable: true); |
4049 | return 0; |
4050 | } |
4051 | |
4052 | static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg) |
4053 | { |
4054 | sh73a0_vccq_mc0_endisable(reg, enable: false); |
4055 | return 0; |
4056 | } |
4057 | |
4058 | static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg) |
4059 | { |
4060 | struct sh_pfc *pfc = reg->reg_data; |
4061 | void __iomem *addr = pfc->windows[1].virt + 4; |
4062 | unsigned long flags; |
4063 | u32 value; |
4064 | |
4065 | spin_lock_irqsave(&pfc->lock, flags); |
4066 | value = ioread32(addr); |
4067 | spin_unlock_irqrestore(lock: &pfc->lock, flags); |
4068 | |
4069 | return !!(value & BIT(28)); |
4070 | } |
4071 | |
4072 | static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg) |
4073 | { |
4074 | return 3300000; |
4075 | } |
4076 | |
4077 | static const struct regulator_ops sh73a0_vccq_mc0_ops = { |
4078 | .enable = sh73a0_vccq_mc0_enable, |
4079 | .disable = sh73a0_vccq_mc0_disable, |
4080 | .is_enabled = sh73a0_vccq_mc0_is_enabled, |
4081 | .get_voltage = sh73a0_vccq_mc0_get_voltage, |
4082 | }; |
4083 | |
4084 | static const struct regulator_desc sh73a0_vccq_mc0_desc = { |
4085 | .owner = THIS_MODULE, |
4086 | .name = "vccq_mc0" , |
4087 | .type = REGULATOR_VOLTAGE, |
4088 | .ops = &sh73a0_vccq_mc0_ops, |
4089 | }; |
4090 | |
4091 | static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = { |
4092 | REGULATOR_SUPPLY("vqmmc" , "sh_mobile_sdhi.0" ), |
4093 | REGULATOR_SUPPLY("vqmmc" , "ee100000.sdhi" ), |
4094 | }; |
4095 | |
4096 | static const struct regulator_init_data sh73a0_vccq_mc0_init_data = { |
4097 | .constraints = { |
4098 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
4099 | }, |
4100 | .num_consumer_supplies = ARRAY_SIZE(sh73a0_vccq_mc0_consumers), |
4101 | .consumer_supplies = sh73a0_vccq_mc0_consumers, |
4102 | }; |
4103 | |
4104 | /* ----------------------------------------------------------------------------- |
4105 | * Pin bias |
4106 | */ |
4107 | |
4108 | static const unsigned int sh73a0_portcr_offsets[] = { |
4109 | 0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000, |
4110 | 0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000, |
4111 | }; |
4112 | |
4113 | static int sh73a0_pin_to_portcr(unsigned int pin) |
4114 | { |
4115 | return sh73a0_portcr_offsets[pin >> 5] + pin; |
4116 | } |
4117 | |
4118 | /* ----------------------------------------------------------------------------- |
4119 | * SoC information |
4120 | */ |
4121 | |
4122 | static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc) |
4123 | { |
4124 | struct regulator_config cfg = { }; |
4125 | struct regulator_dev *vccq; |
4126 | int ret; |
4127 | |
4128 | cfg.dev = pfc->dev; |
4129 | cfg.init_data = &sh73a0_vccq_mc0_init_data; |
4130 | cfg.driver_data = pfc; |
4131 | |
4132 | vccq = devm_regulator_register(dev: pfc->dev, regulator_desc: &sh73a0_vccq_mc0_desc, config: &cfg); |
4133 | if (IS_ERR(ptr: vccq)) { |
4134 | ret = PTR_ERR(ptr: vccq); |
4135 | dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n" , |
4136 | ret); |
4137 | return ret; |
4138 | } |
4139 | |
4140 | return 0; |
4141 | } |
4142 | |
4143 | static const struct sh_pfc_soc_operations sh73a0_pfc_ops = { |
4144 | .init = sh73a0_pinmux_soc_init, |
4145 | .get_bias = rmobile_pinmux_get_bias, |
4146 | .set_bias = rmobile_pinmux_set_bias, |
4147 | .pin_to_portcr = sh73a0_pin_to_portcr, |
4148 | }; |
4149 | |
4150 | const struct sh_pfc_soc_info sh73a0_pinmux_info = { |
4151 | .name = "sh73a0_pfc" , |
4152 | .ops = &sh73a0_pfc_ops, |
4153 | |
4154 | .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, |
4155 | .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, |
4156 | .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, |
4157 | |
4158 | .pins = pinmux_pins, |
4159 | .nr_pins = ARRAY_SIZE(pinmux_pins), |
4160 | .groups = pinmux_groups, |
4161 | .nr_groups = ARRAY_SIZE(pinmux_groups), |
4162 | .functions = pinmux_functions, |
4163 | .nr_functions = ARRAY_SIZE(pinmux_functions), |
4164 | |
4165 | .cfg_regs = pinmux_config_regs, |
4166 | .data_regs = pinmux_data_regs, |
4167 | |
4168 | .pinmux_data = pinmux_data, |
4169 | .pinmux_data_size = ARRAY_SIZE(pinmux_data), |
4170 | |
4171 | .gpio_irq = pinmux_irqs, |
4172 | .gpio_irq_size = ARRAY_SIZE(pinmux_irqs), |
4173 | }; |
4174 | |