1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * SP7021 Pin Controller Driver. |
4 | * Copyright (C) Sunplus Tech / Tibbo Tech. |
5 | */ |
6 | |
7 | #include <linux/gpio/driver.h> |
8 | #include <linux/kernel.h> |
9 | #include <linux/pinctrl/pinctrl.h> |
10 | |
11 | #include "sppctl.h" |
12 | |
13 | #define D_PIS(x, y) "P" __stringify(x) "_0" __stringify(y) |
14 | #define D(x, y) ((x) * 8 + (y)) |
15 | #define P(x, y) PINCTRL_PIN(D(x, y), D_PIS(x, y)) |
16 | |
17 | const char * const sppctl_gpio_list_s[] = { |
18 | D_PIS(0, 0), D_PIS(0, 1), D_PIS(0, 2), D_PIS(0, 3), |
19 | D_PIS(0, 4), D_PIS(0, 5), D_PIS(0, 6), D_PIS(0, 7), |
20 | D_PIS(1, 0), D_PIS(1, 1), D_PIS(1, 2), D_PIS(1, 3), |
21 | D_PIS(1, 4), D_PIS(1, 5), D_PIS(1, 6), D_PIS(1, 7), |
22 | D_PIS(2, 0), D_PIS(2, 1), D_PIS(2, 2), D_PIS(2, 3), |
23 | D_PIS(2, 4), D_PIS(2, 5), D_PIS(2, 6), D_PIS(2, 7), |
24 | D_PIS(3, 0), D_PIS(3, 1), D_PIS(3, 2), D_PIS(3, 3), |
25 | D_PIS(3, 4), D_PIS(3, 5), D_PIS(3, 6), D_PIS(3, 7), |
26 | D_PIS(4, 0), D_PIS(4, 1), D_PIS(4, 2), D_PIS(4, 3), |
27 | D_PIS(4, 4), D_PIS(4, 5), D_PIS(4, 6), D_PIS(4, 7), |
28 | D_PIS(5, 0), D_PIS(5, 1), D_PIS(5, 2), D_PIS(5, 3), |
29 | D_PIS(5, 4), D_PIS(5, 5), D_PIS(5, 6), D_PIS(5, 7), |
30 | D_PIS(6, 0), D_PIS(6, 1), D_PIS(6, 2), D_PIS(6, 3), |
31 | D_PIS(6, 4), D_PIS(6, 5), D_PIS(6, 6), D_PIS(6, 7), |
32 | D_PIS(7, 0), D_PIS(7, 1), D_PIS(7, 2), D_PIS(7, 3), |
33 | D_PIS(7, 4), D_PIS(7, 5), D_PIS(7, 6), D_PIS(7, 7), |
34 | D_PIS(8, 0), D_PIS(8, 1), D_PIS(8, 2), D_PIS(8, 3), |
35 | D_PIS(8, 4), D_PIS(8, 5), D_PIS(8, 6), D_PIS(8, 7), |
36 | D_PIS(9, 0), D_PIS(9, 1), D_PIS(9, 2), D_PIS(9, 3), |
37 | D_PIS(9, 4), D_PIS(9, 5), D_PIS(9, 6), D_PIS(9, 7), |
38 | D_PIS(10, 0), D_PIS(10, 1), D_PIS(10, 2), D_PIS(10, 3), |
39 | D_PIS(10, 4), D_PIS(10, 5), D_PIS(10, 6), D_PIS(10, 7), |
40 | D_PIS(11, 0), D_PIS(11, 1), D_PIS(11, 2), D_PIS(11, 3), |
41 | D_PIS(11, 4), D_PIS(11, 5), D_PIS(11, 6), D_PIS(11, 7), |
42 | D_PIS(12, 0), D_PIS(12, 1), D_PIS(12, 2), |
43 | }; |
44 | |
45 | const size_t sppctl_gpio_list_sz = ARRAY_SIZE(sppctl_gpio_list_s); |
46 | |
47 | const unsigned int sppctl_pins_gpio[] = { |
48 | D(0, 0), D(0, 1), D(0, 2), D(0, 3), D(0, 4), D(0, 5), D(0, 6), D(0, 7), |
49 | D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7), |
50 | D(2, 0), D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7), |
51 | D(3, 0), D(3, 1), D(3, 2), D(3, 3), D(3, 4), D(3, 5), D(3, 6), D(3, 7), |
52 | D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), D(4, 6), D(4, 7), |
53 | D(5, 0), D(5, 1), D(5, 2), D(5, 3), D(5, 4), D(5, 5), D(5, 6), D(5, 7), |
54 | D(6, 0), D(6, 1), D(6, 2), D(6, 3), D(6, 4), D(6, 5), D(6, 6), D(6, 7), |
55 | D(7, 0), D(7, 1), D(7, 2), D(7, 3), D(7, 4), D(7, 5), D(7, 6), D(7, 7), |
56 | D(8, 0), D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), D(8, 6), D(8, 7), |
57 | D(9, 0), D(9, 1), D(9, 2), D(9, 3), D(9, 4), D(9, 5), D(9, 6), D(9, 7), |
58 | D(10, 0), D(10, 1), D(10, 2), D(10, 3), D(10, 4), D(10, 5), D(10, 6), D(10, 7), |
59 | D(11, 0), D(11, 1), D(11, 2), D(11, 3), D(11, 4), D(11, 5), D(11, 6), D(11, 7), |
60 | D(12, 0), D(12, 1), D(12, 2), |
61 | }; |
62 | |
63 | const struct pinctrl_pin_desc sppctl_pins_all[] = { |
64 | /* gpio and iop only */ |
65 | P(0, 0), P(0, 1), P(0, 2), P(0, 3), P(0, 4), P(0, 5), P(0, 6), P(0, 7), |
66 | /* gpio, iop, muxable */ |
67 | P(1, 0), P(1, 1), P(1, 2), P(1, 3), P(1, 4), P(1, 5), P(1, 6), P(1, 7), |
68 | P(2, 0), P(2, 1), P(2, 2), P(2, 3), P(2, 4), P(2, 5), P(2, 6), P(2, 7), |
69 | P(3, 0), P(3, 1), P(3, 2), P(3, 3), P(3, 4), P(3, 5), P(3, 6), P(3, 7), |
70 | P(4, 0), P(4, 1), P(4, 2), P(4, 3), P(4, 4), P(4, 5), P(4, 6), P(4, 7), |
71 | P(5, 0), P(5, 1), P(5, 2), P(5, 3), P(5, 4), P(5, 5), P(5, 6), P(5, 7), |
72 | P(6, 0), P(6, 1), P(6, 2), P(6, 3), P(6, 4), P(6, 5), P(6, 6), P(6, 7), |
73 | P(7, 0), P(7, 1), P(7, 2), P(7, 3), P(7, 4), P(7, 5), P(7, 6), P(7, 7), |
74 | P(8, 0), P(8, 1), P(8, 2), P(8, 3), P(8, 4), P(8, 5), P(8, 6), P(8, 7), |
75 | /* gpio and iop only */ |
76 | P(9, 0), P(9, 1), P(9, 2), P(9, 3), P(9, 4), P(9, 5), P(9, 6), P(9, 7), |
77 | P(10, 0), P(10, 1), P(10, 2), P(10, 3), P(10, 4), P(10, 5), P(10, 6), P(10, 7), |
78 | P(11, 0), P(11, 1), P(11, 2), P(11, 3), P(11, 4), P(11, 5), P(11, 6), P(11, 7), |
79 | P(12, 0), P(12, 1), P(12, 2), |
80 | }; |
81 | |
82 | const size_t sppctl_pins_all_sz = ARRAY_SIZE(sppctl_pins_all); |
83 | |
84 | const char * const sppctl_pmux_list_s[] = { |
85 | D_PIS(0, 0), |
86 | D_PIS(1, 0), D_PIS(1, 1), D_PIS(1, 2), D_PIS(1, 3), |
87 | D_PIS(1, 4), D_PIS(1, 5), D_PIS(1, 6), D_PIS(1, 7), |
88 | D_PIS(2, 0), D_PIS(2, 1), D_PIS(2, 2), D_PIS(2, 3), |
89 | D_PIS(2, 4), D_PIS(2, 5), D_PIS(2, 6), D_PIS(2, 7), |
90 | D_PIS(3, 0), D_PIS(3, 1), D_PIS(3, 2), D_PIS(3, 3), |
91 | D_PIS(3, 4), D_PIS(3, 5), D_PIS(3, 6), D_PIS(3, 7), |
92 | D_PIS(4, 0), D_PIS(4, 1), D_PIS(4, 2), D_PIS(4, 3), |
93 | D_PIS(4, 4), D_PIS(4, 5), D_PIS(4, 6), D_PIS(4, 7), |
94 | D_PIS(5, 0), D_PIS(5, 1), D_PIS(5, 2), D_PIS(5, 3), |
95 | D_PIS(5, 4), D_PIS(5, 5), D_PIS(5, 6), D_PIS(5, 7), |
96 | D_PIS(6, 0), D_PIS(6, 1), D_PIS(6, 2), D_PIS(6, 3), |
97 | D_PIS(6, 4), D_PIS(6, 5), D_PIS(6, 6), D_PIS(6, 7), |
98 | D_PIS(7, 0), D_PIS(7, 1), D_PIS(7, 2), D_PIS(7, 3), |
99 | D_PIS(7, 4), D_PIS(7, 5), D_PIS(7, 6), D_PIS(7, 7), |
100 | D_PIS(8, 0), D_PIS(8, 1), D_PIS(8, 2), D_PIS(8, 3), |
101 | D_PIS(8, 4), D_PIS(8, 5), D_PIS(8, 6), D_PIS(8, 7), |
102 | }; |
103 | |
104 | const size_t sppctl_pmux_list_sz = ARRAY_SIZE(sppctl_pmux_list_s); |
105 | |
106 | static const unsigned int pins_spif1[] = { |
107 | D(10, 3), D(10, 4), D(10, 6), D(10, 7), |
108 | }; |
109 | |
110 | static const unsigned int pins_spif2[] = { |
111 | D(9, 4), D(9, 6), D(9, 7), D(10, 1), |
112 | }; |
113 | |
114 | static const struct sppctl_grp sp7021grps_spif[] = { |
115 | EGRP("SPI_FLASH1" , 1, pins_spif1), |
116 | EGRP("SPI_FLASH2" , 2, pins_spif2), |
117 | }; |
118 | |
119 | static const unsigned int pins_spi41[] = { |
120 | D(10, 2), D(10, 5), |
121 | }; |
122 | |
123 | static const unsigned int pins_spi42[] = { |
124 | D(9, 5), D(9, 8), |
125 | }; |
126 | |
127 | static const struct sppctl_grp sp7021grps_spi4[] = { |
128 | EGRP("SPI_FLASH_4BIT1" , 1, pins_spi41), |
129 | EGRP("SPI_FLASH_4BIT2" , 2, pins_spi42), |
130 | }; |
131 | |
132 | static const unsigned int pins_snan[] = { |
133 | D(9, 4), D(9, 5), D(9, 6), D(9, 7), D(10, 0), D(10, 1), |
134 | }; |
135 | |
136 | static const struct sppctl_grp sp7021grps_snan[] = { |
137 | EGRP("SPI_NAND" , 1, pins_snan), |
138 | }; |
139 | |
140 | static const unsigned int pins_emmc[] = { |
141 | D(9, 0), D(9, 1), D(9, 2), D(9, 3), D(9, 4), D(9, 5), |
142 | D(9, 6), D(9, 7), D(10, 0), D(10, 1), |
143 | }; |
144 | |
145 | static const struct sppctl_grp sp7021grps_emmc[] = { |
146 | EGRP("CARD0_EMMC" , 1, pins_emmc), |
147 | }; |
148 | |
149 | static const unsigned int pins_sdsd[] = { |
150 | D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), D(8, 6), |
151 | }; |
152 | |
153 | static const struct sppctl_grp sp7021grps_sdsd[] = { |
154 | EGRP("SD_CARD" , 1, pins_sdsd), |
155 | }; |
156 | |
157 | static const unsigned int pins_uar0[] = { |
158 | D(11, 0), D(11, 1), |
159 | }; |
160 | |
161 | static const struct sppctl_grp sp7021grps_uar0[] = { |
162 | EGRP("UA0" , 1, pins_uar0), |
163 | }; |
164 | |
165 | static const unsigned int pins_adbg1[] = { |
166 | D(10, 2), D(10, 3), |
167 | }; |
168 | |
169 | static const unsigned int pins_adbg2[] = { |
170 | D(7, 1), D(7, 2), |
171 | }; |
172 | |
173 | static const struct sppctl_grp sp7021grps_adbg[] = { |
174 | EGRP("ACHIP_DEBUG1" , 1, pins_adbg1), |
175 | EGRP("ACHIP_DEBUG2" , 2, pins_adbg2), |
176 | }; |
177 | |
178 | static const unsigned int pins_aua2axi1[] = { |
179 | D(2, 0), D(2, 1), D(2, 2), |
180 | }; |
181 | |
182 | static const unsigned int pins_aua2axi2[] = { |
183 | D(1, 0), D(1, 1), D(1, 2), |
184 | }; |
185 | |
186 | static const struct sppctl_grp sp7021grps_au2x[] = { |
187 | EGRP("ACHIP_UA2AXI1" , 1, pins_aua2axi1), |
188 | EGRP("ACHIP_UA2AXI2" , 2, pins_aua2axi2), |
189 | }; |
190 | |
191 | static const unsigned int pins_fpga[] = { |
192 | D(0, 2), D(0, 3), D(0, 4), D(0, 5), D(0, 6), D(0, 7), |
193 | D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), |
194 | D(1, 6), D(1, 7), D(2, 0), D(2, 1), D(2, 2), D(2, 3), |
195 | D(2, 4), D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), |
196 | D(3, 2), D(3, 3), D(3, 4), D(3, 5), D(3, 6), D(3, 7), |
197 | D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), |
198 | D(4, 6), D(4, 7), D(5, 0), D(5, 1), D(5, 2), |
199 | }; |
200 | |
201 | static const struct sppctl_grp sp7021grps_fpga[] = { |
202 | EGRP("FPGA_IFX" , 1, pins_fpga), |
203 | }; |
204 | |
205 | static const unsigned int pins_hdmi1[] = { |
206 | D(10, 6), D(12, 2), D(12, 1), |
207 | }; |
208 | |
209 | static const unsigned int pins_hdmi2[] = { |
210 | D(8, 3), D(8, 5), D(8, 6), |
211 | }; |
212 | |
213 | static const unsigned int pins_hdmi3[] = { |
214 | D(7, 4), D(7, 6), D(7, 7), |
215 | }; |
216 | |
217 | static const struct sppctl_grp sp7021grps_hdmi[] = { |
218 | EGRP("HDMI_TX1" , 1, pins_hdmi1), |
219 | EGRP("HDMI_TX2" , 2, pins_hdmi2), |
220 | EGRP("HDMI_TX3" , 3, pins_hdmi3), |
221 | }; |
222 | |
223 | static const unsigned int pins_eadc[] = { |
224 | D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), |
225 | }; |
226 | |
227 | static const struct sppctl_grp sp7021grps_eadc[] = { |
228 | EGRP("AUD_EXT_ADC_IFX0" , 1, pins_eadc), |
229 | }; |
230 | |
231 | static const unsigned int pins_edac[] = { |
232 | D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), D(3, 2), D(3, 4), |
233 | }; |
234 | |
235 | static const struct sppctl_grp sp7021grps_edac[] = { |
236 | EGRP("AUD_EXT_DAC_IFX0" , 1, pins_edac), |
237 | }; |
238 | |
239 | static const unsigned int pins_spdi[] = { |
240 | D(2, 4), |
241 | }; |
242 | |
243 | static const struct sppctl_grp sp7021grps_spdi[] = { |
244 | EGRP("AUD_IEC_RX0" , 1, pins_spdi), |
245 | }; |
246 | |
247 | static const unsigned int pins_spdo[] = { |
248 | D(3, 6), |
249 | }; |
250 | |
251 | static const struct sppctl_grp sp7021grps_spdo[] = { |
252 | EGRP("AUD_IEC_TX0" , 1, pins_spdo), |
253 | }; |
254 | |
255 | static const unsigned int pins_tdmt[] = { |
256 | D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), D(3, 2), |
257 | }; |
258 | |
259 | static const struct sppctl_grp sp7021grps_tdmt[] = { |
260 | EGRP("TDMTX_IFX0" , 1, pins_tdmt), |
261 | }; |
262 | |
263 | static const unsigned int pins_tdmr[] = { |
264 | D(1, 7), D(2, 0), D(2, 1), D(2, 2), |
265 | }; |
266 | |
267 | static const struct sppctl_grp sp7021grps_tdmr[] = { |
268 | EGRP("TDMRX_IFX0" , 1, pins_tdmr), |
269 | }; |
270 | |
271 | static const unsigned int pins_pdmr[] = { |
272 | D(1, 7), D(2, 0), D(2, 1), D(2, 2), D(2, 3), |
273 | }; |
274 | |
275 | static const struct sppctl_grp sp7021grps_pdmr[] = { |
276 | EGRP("PDMRX_IFX0" , 1, pins_pdmr), |
277 | }; |
278 | |
279 | static const unsigned int pins_pcmt[] = { |
280 | D(3, 7), D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), |
281 | }; |
282 | |
283 | static const struct sppctl_grp sp7021grps_pcmt[] = { |
284 | EGRP("PCM_IEC_TX" , 1, pins_pcmt), |
285 | }; |
286 | |
287 | static const unsigned int pins_lcdi[] = { |
288 | D(1, 4), D(1, 5), D(1, 6), D(1, 7), D(2, 0), D(2, 1), D(2, 2), D(2, 3), |
289 | D(2, 4), D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), D(3, 2), D(3, 3), |
290 | D(3, 4), D(3, 5), D(3, 6), D(3, 7), D(4, 0), D(4, 1), D(4, 2), D(4, 3), |
291 | D(4, 4), D(4, 5), D(4, 6), D(4, 7), |
292 | }; |
293 | |
294 | static const struct sppctl_grp sp7021grps_lcdi[] = { |
295 | EGRP("LCDIF" , 1, pins_lcdi), |
296 | }; |
297 | |
298 | static const unsigned int pins_dvdd[] = { |
299 | D(7, 0), D(7, 1), D(7, 2), D(7, 3), D(7, 4), D(7, 5), D(7, 6), D(7, 7), |
300 | D(8, 0), D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), |
301 | }; |
302 | |
303 | static const struct sppctl_grp sp7021grps_dvdd[] = { |
304 | EGRP("DVD_DSP_DEBUG" , 1, pins_dvdd), |
305 | }; |
306 | |
307 | static const unsigned int pins_i2cd[] = { |
308 | D(1, 0), D(1, 1), |
309 | }; |
310 | |
311 | static const struct sppctl_grp sp7021grps_i2cd[] = { |
312 | EGRP("I2C_DEBUG" , 1, pins_i2cd), |
313 | }; |
314 | |
315 | static const unsigned int pins_i2cs[] = { |
316 | D(0, 0), D(0, 1), |
317 | }; |
318 | |
319 | static const struct sppctl_grp sp7021grps_i2cs[] = { |
320 | EGRP("I2C_SLAVE" , 1, pins_i2cs), |
321 | }; |
322 | |
323 | static const unsigned int pins_wakp[] = { |
324 | D(10, 5), |
325 | }; |
326 | |
327 | static const struct sppctl_grp sp7021grps_wakp[] = { |
328 | EGRP("WAKEUP" , 1, pins_wakp), |
329 | }; |
330 | |
331 | static const unsigned int pins_u2ax[] = { |
332 | D(2, 0), D(2, 1), D(3, 0), D(3, 1), |
333 | }; |
334 | |
335 | static const struct sppctl_grp sp7021grps_u2ax[] = { |
336 | EGRP("UART2AXI" , 1, pins_u2ax), |
337 | }; |
338 | |
339 | static const unsigned int pins_u0ic[] = { |
340 | D(0, 0), D(0, 1), D(0, 4), D(0, 5), D(1, 0), D(1, 1), |
341 | }; |
342 | |
343 | static const struct sppctl_grp sp7021grps_u0ic[] = { |
344 | EGRP("USB0_I2C" , 1, pins_u0ic), |
345 | }; |
346 | |
347 | static const unsigned int pins_u1ic[] = { |
348 | D(0, 2), D(0, 3), D(0, 6), D(0, 7), D(1, 2), D(1, 3), |
349 | }; |
350 | |
351 | static const struct sppctl_grp sp7021grps_u1ic[] = { |
352 | EGRP("USB1_I2C" , 1, pins_u1ic), |
353 | }; |
354 | |
355 | static const unsigned int pins_u0ot[] = { |
356 | D(11, 2), |
357 | }; |
358 | |
359 | static const struct sppctl_grp sp7021grps_u0ot[] = { |
360 | EGRP("USB0_OTG" , 1, pins_u0ot), |
361 | }; |
362 | |
363 | static const unsigned int pins_u1ot[] = { |
364 | D(11, 3), |
365 | }; |
366 | |
367 | static const struct sppctl_grp sp7021grps_u1ot[] = { |
368 | EGRP("USB1_OTG" , 1, pins_u1ot), |
369 | }; |
370 | |
371 | static const unsigned int pins_uphd[] = { |
372 | D(0, 1), D(0, 2), D(0, 3), D(7, 4), D(7, 5), D(7, 6), |
373 | D(7, 7), D(8, 0), D(8, 1), D(8, 2), D(8, 3), |
374 | D(9, 7), D(10, 2), D(10, 3), D(10, 4), |
375 | }; |
376 | |
377 | static const struct sppctl_grp sp7021grps_up0d[] = { |
378 | EGRP("UPHY0_DEBUG" , 1, pins_uphd), |
379 | }; |
380 | |
381 | static const struct sppctl_grp sp7021grps_up1d[] = { |
382 | EGRP("UPHY1_DEBUG" , 1, pins_uphd), |
383 | }; |
384 | |
385 | static const unsigned int pins_upex[] = { |
386 | D(0, 0), D(0, 1), D(0, 2), D(0, 3), D(0, 4), D(0, 5), D(0, 6), D(0, 7), |
387 | D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7), |
388 | D(2, 0), D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7), |
389 | D(3, 0), D(3, 1), D(3, 2), D(3, 3), D(3, 4), D(3, 5), D(3, 6), D(3, 7), |
390 | D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), D(4, 6), D(4, 7), |
391 | D(5, 0), D(5, 1), D(5, 2), D(5, 3), D(5, 4), D(5, 5), D(5, 6), D(5, 7), |
392 | D(6, 0), D(6, 1), D(6, 2), D(6, 3), D(6, 4), D(6, 5), D(6, 6), D(6, 7), |
393 | D(7, 0), D(7, 1), D(7, 2), D(7, 3), D(7, 4), D(7, 5), D(7, 6), D(7, 7), |
394 | D(8, 0), D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), D(8, 6), D(8, 7), |
395 | D(9, 0), D(9, 1), D(9, 2), D(9, 3), D(9, 4), D(9, 5), D(9, 6), D(9, 7), |
396 | D(10, 0), D(10, 1), D(10, 2), D(10, 3), D(10, 4), D(10, 5), D(10, 6), D(10, 7), |
397 | }; |
398 | |
399 | static const struct sppctl_grp sp7021grps_upex[] = { |
400 | EGRP("UPHY0_EXT" , 1, pins_upex), |
401 | }; |
402 | |
403 | static const unsigned int pins_prp1[] = { |
404 | D(0, 6), D(0, 7), |
405 | D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7), |
406 | D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7), |
407 | D(3, 0), D(3, 1), D(3, 2), |
408 | }; |
409 | |
410 | static const unsigned int pins_prp2[] = { |
411 | D(3, 4), D(3, 6), D(3, 7), |
412 | D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), D(4, 6), D(4, 7), |
413 | D(5, 0), D(5, 1), D(5, 2), D(5, 3), D(5, 4), D(5, 5), D(5, 6), D(5, 7), |
414 | D(6, 4), |
415 | }; |
416 | |
417 | static const struct sppctl_grp sp7021grps_prbp[] = { |
418 | EGRP("PROBE_PORT1" , 1, pins_prp1), |
419 | EGRP("PROBE_PORT2" , 2, pins_prp2), |
420 | }; |
421 | |
422 | /* |
423 | * Due to compatible reason, the first valid item should start at the third |
424 | * position of the array. Please keep the first two items of the table |
425 | * no use (dummy). |
426 | */ |
427 | const struct sppctl_func sppctl_list_funcs[] = { |
428 | FNCN("" , pinmux_type_fpmx, 0x00, 0, 0), |
429 | FNCN("" , pinmux_type_fpmx, 0x00, 0, 0), |
430 | |
431 | FNCN("L2SW_CLK_OUT" , pinmux_type_fpmx, 0x00, 0, 7), |
432 | FNCN("L2SW_MAC_SMI_MDC" , pinmux_type_fpmx, 0x00, 8, 7), |
433 | FNCN("L2SW_LED_FLASH0" , pinmux_type_fpmx, 0x01, 0, 7), |
434 | FNCN("L2SW_LED_FLASH1" , pinmux_type_fpmx, 0x01, 8, 7), |
435 | FNCN("L2SW_LED_ON0" , pinmux_type_fpmx, 0x02, 0, 7), |
436 | FNCN("L2SW_LED_ON1" , pinmux_type_fpmx, 0x02, 8, 7), |
437 | FNCN("L2SW_MAC_SMI_MDIO" , pinmux_type_fpmx, 0x03, 0, 7), |
438 | FNCN("L2SW_P0_MAC_RMII_TXEN" , pinmux_type_fpmx, 0x03, 8, 7), |
439 | FNCN("L2SW_P0_MAC_RMII_TXD0" , pinmux_type_fpmx, 0x04, 0, 7), |
440 | FNCN("L2SW_P0_MAC_RMII_TXD1" , pinmux_type_fpmx, 0x04, 8, 7), |
441 | FNCN("L2SW_P0_MAC_RMII_CRSDV" , pinmux_type_fpmx, 0x05, 0, 7), |
442 | FNCN("L2SW_P0_MAC_RMII_RXD0" , pinmux_type_fpmx, 0x05, 8, 7), |
443 | FNCN("L2SW_P0_MAC_RMII_RXD1" , pinmux_type_fpmx, 0x06, 0, 7), |
444 | FNCN("L2SW_P0_MAC_RMII_RXER" , pinmux_type_fpmx, 0x06, 8, 7), |
445 | FNCN("L2SW_P1_MAC_RMII_TXEN" , pinmux_type_fpmx, 0x07, 0, 7), |
446 | FNCN("L2SW_P1_MAC_RMII_TXD0" , pinmux_type_fpmx, 0x07, 8, 7), |
447 | FNCN("L2SW_P1_MAC_RMII_TXD1" , pinmux_type_fpmx, 0x08, 0, 7), |
448 | FNCN("L2SW_P1_MAC_RMII_CRSDV" , pinmux_type_fpmx, 0x08, 8, 7), |
449 | FNCN("L2SW_P1_MAC_RMII_RXD0" , pinmux_type_fpmx, 0x09, 0, 7), |
450 | FNCN("L2SW_P1_MAC_RMII_RXD1" , pinmux_type_fpmx, 0x09, 8, 7), |
451 | FNCN("L2SW_P1_MAC_RMII_RXER" , pinmux_type_fpmx, 0x0A, 0, 7), |
452 | FNCN("DAISY_MODE" , pinmux_type_fpmx, 0x0A, 8, 7), |
453 | FNCN("SDIO_CLK" , pinmux_type_fpmx, 0x0B, 0, 7), /* 1x SDIO */ |
454 | FNCN("SDIO_CMD" , pinmux_type_fpmx, 0x0B, 8, 7), |
455 | FNCN("SDIO_D0" , pinmux_type_fpmx, 0x0C, 0, 7), |
456 | FNCN("SDIO_D1" , pinmux_type_fpmx, 0x0C, 8, 7), |
457 | FNCN("SDIO_D2" , pinmux_type_fpmx, 0x0D, 0, 7), |
458 | FNCN("SDIO_D3" , pinmux_type_fpmx, 0x0D, 8, 7), |
459 | FNCN("PWM0" , pinmux_type_fpmx, 0x0E, 0, 7), /* 8x PWM */ |
460 | FNCN("PWM1" , pinmux_type_fpmx, 0x0E, 8, 7), |
461 | FNCN("PWM2" , pinmux_type_fpmx, 0x0F, 0, 7), |
462 | FNCN("PWM3" , pinmux_type_fpmx, 0x0F, 8, 7), |
463 | |
464 | FNCN("PWM4" , pinmux_type_fpmx, 0x10, 0, 7), |
465 | FNCN("PWM5" , pinmux_type_fpmx, 0x10, 8, 7), |
466 | FNCN("PWM6" , pinmux_type_fpmx, 0x11, 0, 7), |
467 | FNCN("PWM7" , pinmux_type_fpmx, 0x11, 8, 7), |
468 | FNCN("ICM0_D" , pinmux_type_fpmx, 0x12, 0, 7), /* 4x Input captures */ |
469 | FNCN("ICM1_D" , pinmux_type_fpmx, 0x12, 8, 7), |
470 | FNCN("ICM2_D" , pinmux_type_fpmx, 0x13, 0, 7), |
471 | FNCN("ICM3_D" , pinmux_type_fpmx, 0x13, 8, 7), |
472 | FNCN("ICM0_CLK" , pinmux_type_fpmx, 0x14, 0, 7), |
473 | FNCN("ICM1_CLK" , pinmux_type_fpmx, 0x14, 8, 7), |
474 | FNCN("ICM2_CLK" , pinmux_type_fpmx, 0x15, 0, 7), |
475 | FNCN("ICM3_CLK" , pinmux_type_fpmx, 0x15, 8, 7), |
476 | FNCN("SPIM0_INT" , pinmux_type_fpmx, 0x16, 0, 7), /* 4x SPI masters */ |
477 | FNCN("SPIM0_CLK" , pinmux_type_fpmx, 0x16, 8, 7), |
478 | FNCN("SPIM0_EN" , pinmux_type_fpmx, 0x17, 0, 7), |
479 | FNCN("SPIM0_DO" , pinmux_type_fpmx, 0x17, 8, 7), |
480 | FNCN("SPIM0_DI" , pinmux_type_fpmx, 0x18, 0, 7), |
481 | FNCN("SPIM1_INT" , pinmux_type_fpmx, 0x18, 8, 7), |
482 | FNCN("SPIM1_CLK" , pinmux_type_fpmx, 0x19, 0, 7), |
483 | FNCN("SPIM1_EN" , pinmux_type_fpmx, 0x19, 8, 7), |
484 | FNCN("SPIM1_DO" , pinmux_type_fpmx, 0x1A, 0, 7), |
485 | FNCN("SPIM1_DI" , pinmux_type_fpmx, 0x1A, 8, 7), |
486 | FNCN("SPIM2_INT" , pinmux_type_fpmx, 0x1B, 0, 7), |
487 | FNCN("SPIM2_CLK" , pinmux_type_fpmx, 0x1B, 8, 7), |
488 | FNCN("SPIM2_EN" , pinmux_type_fpmx, 0x1C, 0, 7), |
489 | FNCN("SPIM2_DO" , pinmux_type_fpmx, 0x1C, 8, 7), |
490 | FNCN("SPIM2_DI" , pinmux_type_fpmx, 0x1D, 0, 7), |
491 | FNCN("SPIM3_INT" , pinmux_type_fpmx, 0x1D, 8, 7), |
492 | FNCN("SPIM3_CLK" , pinmux_type_fpmx, 0x1E, 0, 7), |
493 | FNCN("SPIM3_EN" , pinmux_type_fpmx, 0x1E, 8, 7), |
494 | FNCN("SPIM3_DO" , pinmux_type_fpmx, 0x1F, 0, 7), |
495 | FNCN("SPIM3_DI" , pinmux_type_fpmx, 0x1F, 8, 7), |
496 | |
497 | FNCN("SPI0S_INT" , pinmux_type_fpmx, 0x20, 0, 7), /* 4x SPI slaves */ |
498 | FNCN("SPI0S_CLK" , pinmux_type_fpmx, 0x20, 8, 7), |
499 | FNCN("SPI0S_EN" , pinmux_type_fpmx, 0x21, 0, 7), |
500 | FNCN("SPI0S_DO" , pinmux_type_fpmx, 0x21, 8, 7), |
501 | FNCN("SPI0S_DI" , pinmux_type_fpmx, 0x22, 0, 7), |
502 | FNCN("SPI1S_INT" , pinmux_type_fpmx, 0x22, 8, 7), |
503 | FNCN("SPI1S_CLK" , pinmux_type_fpmx, 0x23, 0, 7), |
504 | FNCN("SPI1S_EN" , pinmux_type_fpmx, 0x23, 8, 7), |
505 | FNCN("SPI1S_DO" , pinmux_type_fpmx, 0x24, 0, 7), |
506 | FNCN("SPI1S_DI" , pinmux_type_fpmx, 0x24, 8, 7), |
507 | FNCN("SPI2S_INT" , pinmux_type_fpmx, 0x25, 0, 7), |
508 | FNCN("SPI2S_CLK" , pinmux_type_fpmx, 0x25, 8, 7), |
509 | FNCN("SPI2S_EN" , pinmux_type_fpmx, 0x26, 0, 7), |
510 | FNCN("SPI2S_DO" , pinmux_type_fpmx, 0x26, 8, 7), |
511 | FNCN("SPI2S_DI" , pinmux_type_fpmx, 0x27, 0, 7), |
512 | FNCN("SPI3S_INT" , pinmux_type_fpmx, 0x27, 8, 7), |
513 | FNCN("SPI3S_CLK" , pinmux_type_fpmx, 0x28, 0, 7), |
514 | FNCN("SPI3S_EN" , pinmux_type_fpmx, 0x28, 8, 7), |
515 | FNCN("SPI3S_DO" , pinmux_type_fpmx, 0x29, 0, 7), |
516 | FNCN("SPI3S_DI" , pinmux_type_fpmx, 0x29, 8, 7), |
517 | FNCN("I2CM0_CLK" , pinmux_type_fpmx, 0x2A, 0, 7), /* 4x I2C masters */ |
518 | FNCN("I2CM0_DAT" , pinmux_type_fpmx, 0x2A, 8, 7), |
519 | FNCN("I2CM1_CLK" , pinmux_type_fpmx, 0x2B, 0, 7), |
520 | FNCN("I2CM1_DAT" , pinmux_type_fpmx, 0x2B, 8, 7), |
521 | FNCN("I2CM2_CLK" , pinmux_type_fpmx, 0x2C, 0, 7), |
522 | FNCN("I2CM2_DAT" , pinmux_type_fpmx, 0x2C, 8, 7), |
523 | FNCN("I2CM3_CLK" , pinmux_type_fpmx, 0x2D, 0, 7), |
524 | FNCN("I2CM3_DAT" , pinmux_type_fpmx, 0x2D, 8, 7), |
525 | FNCN("UA1_TX" , pinmux_type_fpmx, 0x2E, 0, 7), /* 4x UARTS */ |
526 | FNCN("UA1_RX" , pinmux_type_fpmx, 0x2E, 8, 7), |
527 | FNCN("UA1_CTS" , pinmux_type_fpmx, 0x2F, 0, 7), |
528 | FNCN("UA1_RTS" , pinmux_type_fpmx, 0x2F, 8, 7), |
529 | |
530 | FNCN("UA2_TX" , pinmux_type_fpmx, 0x30, 0, 7), |
531 | FNCN("UA2_RX" , pinmux_type_fpmx, 0x30, 8, 7), |
532 | FNCN("UA2_CTS" , pinmux_type_fpmx, 0x31, 0, 7), |
533 | FNCN("UA2_RTS" , pinmux_type_fpmx, 0x31, 8, 7), |
534 | FNCN("UA3_TX" , pinmux_type_fpmx, 0x32, 0, 7), |
535 | FNCN("UA3_RX" , pinmux_type_fpmx, 0x32, 8, 7), |
536 | FNCN("UA3_CTS" , pinmux_type_fpmx, 0x33, 0, 7), |
537 | FNCN("UA3_RTS" , pinmux_type_fpmx, 0x33, 8, 7), |
538 | FNCN("UA4_TX" , pinmux_type_fpmx, 0x34, 0, 7), |
539 | FNCN("UA4_RX" , pinmux_type_fpmx, 0x34, 8, 7), |
540 | FNCN("UA4_CTS" , pinmux_type_fpmx, 0x35, 0, 7), |
541 | FNCN("UA4_RTS" , pinmux_type_fpmx, 0x35, 8, 7), |
542 | FNCN("TIMER0_INT" , pinmux_type_fpmx, 0x36, 0, 7), /* 4x timer int. */ |
543 | FNCN("TIMER1_INT" , pinmux_type_fpmx, 0x36, 8, 7), |
544 | FNCN("TIMER2_INT" , pinmux_type_fpmx, 0x37, 0, 7), |
545 | FNCN("TIMER3_INT" , pinmux_type_fpmx, 0x37, 8, 7), |
546 | FNCN("GPIO_INT0" , pinmux_type_fpmx, 0x38, 0, 7), /* 8x GPIO int. */ |
547 | FNCN("GPIO_INT1" , pinmux_type_fpmx, 0x38, 8, 7), |
548 | FNCN("GPIO_INT2" , pinmux_type_fpmx, 0x39, 0, 7), |
549 | FNCN("GPIO_INT3" , pinmux_type_fpmx, 0x39, 8, 7), |
550 | FNCN("GPIO_INT4" , pinmux_type_fpmx, 0x3A, 0, 7), |
551 | FNCN("GPIO_INT5" , pinmux_type_fpmx, 0x3A, 8, 7), |
552 | FNCN("GPIO_INT6" , pinmux_type_fpmx, 0x3B, 0, 7), |
553 | FNCN("GPIO_INT7" , pinmux_type_fpmx, 0x3B, 8, 7), |
554 | |
555 | /* MOON1 register */ |
556 | FNCE("SPI_FLASH" , pinmux_type_grp, 0x01, 0, 2, sp7021grps_spif), |
557 | FNCE("SPI_FLASH_4BIT" , pinmux_type_grp, 0x01, 2, 2, sp7021grps_spi4), |
558 | FNCE("SPI_NAND" , pinmux_type_grp, 0x01, 4, 1, sp7021grps_snan), |
559 | FNCE("CARD0_EMMC" , pinmux_type_grp, 0x01, 5, 1, sp7021grps_emmc), |
560 | FNCE("SD_CARD" , pinmux_type_grp, 0x01, 6, 1, sp7021grps_sdsd), |
561 | FNCE("UA0" , pinmux_type_grp, 0x01, 7, 1, sp7021grps_uar0), |
562 | FNCE("ACHIP_DEBUG" , pinmux_type_grp, 0x01, 8, 2, sp7021grps_adbg), |
563 | FNCE("ACHIP_UA2AXI" , pinmux_type_grp, 0x01, 10, 2, sp7021grps_au2x), |
564 | FNCE("FPGA_IFX" , pinmux_type_grp, 0x01, 12, 1, sp7021grps_fpga), |
565 | FNCE("HDMI_TX" , pinmux_type_grp, 0x01, 13, 2, sp7021grps_hdmi), |
566 | |
567 | FNCE("AUD_EXT_ADC_IFX0" , pinmux_type_grp, 0x01, 15, 1, sp7021grps_eadc), |
568 | FNCE("AUD_EXT_DAC_IFX0" , pinmux_type_grp, 0x02, 0, 1, sp7021grps_edac), |
569 | FNCE("SPDIF_RX" , pinmux_type_grp, 0x02, 2, 1, sp7021grps_spdi), |
570 | FNCE("SPDIF_TX" , pinmux_type_grp, 0x02, 3, 1, sp7021grps_spdo), |
571 | FNCE("TDMTX_IFX0" , pinmux_type_grp, 0x02, 4, 1, sp7021grps_tdmt), |
572 | FNCE("TDMRX_IFX0" , pinmux_type_grp, 0x02, 5, 1, sp7021grps_tdmr), |
573 | FNCE("PDMRX_IFX0" , pinmux_type_grp, 0x02, 6, 1, sp7021grps_pdmr), |
574 | FNCE("PCM_IEC_TX" , pinmux_type_grp, 0x02, 7, 1, sp7021grps_pcmt), |
575 | FNCE("LCDIF" , pinmux_type_grp, 0x04, 6, 1, sp7021grps_lcdi), |
576 | FNCE("DVD_DSP_DEBUG" , pinmux_type_grp, 0x02, 8, 1, sp7021grps_dvdd), |
577 | FNCE("I2C_DEBUG" , pinmux_type_grp, 0x02, 9, 1, sp7021grps_i2cd), |
578 | FNCE("I2C_SLAVE" , pinmux_type_grp, 0x02, 10, 1, sp7021grps_i2cs), |
579 | FNCE("WAKEUP" , pinmux_type_grp, 0x02, 11, 1, sp7021grps_wakp), |
580 | FNCE("UART2AXI" , pinmux_type_grp, 0x02, 12, 2, sp7021grps_u2ax), |
581 | FNCE("USB0_I2C" , pinmux_type_grp, 0x02, 14, 2, sp7021grps_u0ic), |
582 | FNCE("USB1_I2C" , pinmux_type_grp, 0x03, 0, 2, sp7021grps_u1ic), |
583 | FNCE("USB0_OTG" , pinmux_type_grp, 0x03, 2, 1, sp7021grps_u0ot), |
584 | FNCE("USB1_OTG" , pinmux_type_grp, 0x03, 3, 1, sp7021grps_u1ot), |
585 | FNCE("UPHY0_DEBUG" , pinmux_type_grp, 0x03, 4, 1, sp7021grps_up0d), |
586 | FNCE("UPHY1_DEBUG" , pinmux_type_grp, 0x03, 5, 1, sp7021grps_up1d), |
587 | FNCE("UPHY0_EXT" , pinmux_type_grp, 0x03, 6, 1, sp7021grps_upex), |
588 | FNCE("PROBE_PORT" , pinmux_type_grp, 0x03, 7, 2, sp7021grps_prbp), |
589 | }; |
590 | |
591 | const size_t sppctl_list_funcs_sz = ARRAY_SIZE(sppctl_list_funcs); |
592 | |