1 | /* |
2 | * Allwinner A80 SoCs pinctrl driver. |
3 | * |
4 | * Copyright (C) 2014 Maxime Ripard |
5 | * |
6 | * Maxime Ripard <maxime.ripard@free-electrons.com> |
7 | * |
8 | * This file is licensed under the terms of the GNU General Public |
9 | * License version 2. This program is licensed "as is" without any |
10 | * warranty of any kind, whether express or implied. |
11 | */ |
12 | |
13 | #include <linux/init.h> |
14 | #include <linux/platform_device.h> |
15 | #include <linux/of.h> |
16 | #include <linux/pinctrl/pinctrl.h> |
17 | |
18 | #include "pinctrl-sunxi.h" |
19 | |
20 | static const struct sunxi_desc_pin sun9i_a80_pins[] = { |
21 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), |
22 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
23 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
24 | SUNXI_FUNCTION(0x2, "gmac" ), /* RXD3 */ |
25 | SUNXI_FUNCTION(0x4, "uart1" ), /* TX */ |
26 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */ |
27 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), |
28 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
29 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
30 | SUNXI_FUNCTION(0x2, "gmac" ), /* RXD2 */ |
31 | SUNXI_FUNCTION(0x4, "uart1" ), /* RX */ |
32 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */ |
33 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), |
34 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
35 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
36 | SUNXI_FUNCTION(0x2, "gmac" ), /* RXD1 */ |
37 | SUNXI_FUNCTION(0x4, "uart1" ), /* RTS */ |
38 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */ |
39 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), |
40 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
41 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
42 | SUNXI_FUNCTION(0x2, "gmac" ), /* RXD0 */ |
43 | SUNXI_FUNCTION(0x4, "uart1" ), /* CTS */ |
44 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */ |
45 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), |
46 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
47 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
48 | SUNXI_FUNCTION(0x2, "gmac" ), /* RXCK */ |
49 | SUNXI_FUNCTION(0x4, "uart1" ), /* DTR */ |
50 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */ |
51 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), |
52 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
53 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
54 | SUNXI_FUNCTION(0x2, "gmac" ), /* RXCTL */ |
55 | SUNXI_FUNCTION(0x4, "uart1" ), /* DSR */ |
56 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */ |
57 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), |
58 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
59 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
60 | SUNXI_FUNCTION(0x2, "gmac" ), /* RXERR */ |
61 | SUNXI_FUNCTION(0x4, "uart1" ), /* DCD */ |
62 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */ |
63 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), |
64 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
65 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
66 | SUNXI_FUNCTION(0x2, "gmac" ), /* TXD3 */ |
67 | SUNXI_FUNCTION(0x4, "uart1" ), /* RING */ |
68 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */ |
69 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), |
70 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
71 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
72 | SUNXI_FUNCTION(0x2, "gmac" ), /* TXD2 */ |
73 | SUNXI_FUNCTION(0x4, "eclk" ), /* IN0 */ |
74 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */ |
75 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), |
76 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
77 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
78 | SUNXI_FUNCTION(0x2, "gmac" ), /* TXEN */ |
79 | SUNXI_FUNCTION(0x4, "eclk" ), /* IN1 */ |
80 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */ |
81 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), |
82 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
83 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
84 | SUNXI_FUNCTION(0x2, "gmac" ), /* TXD0 */ |
85 | SUNXI_FUNCTION(0x4, "clk_out_a" ), |
86 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */ |
87 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), |
88 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
89 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
90 | SUNXI_FUNCTION(0x2, "gmac" ), /* MII-CRS */ |
91 | SUNXI_FUNCTION(0x4, "clk_out_b" ), |
92 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */ |
93 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), |
94 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
95 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
96 | SUNXI_FUNCTION(0x2, "gmac" ), /* TXCK */ |
97 | SUNXI_FUNCTION(0x4, "pwm3" ), /* PWM_P */ |
98 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */ |
99 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13), |
100 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
101 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
102 | SUNXI_FUNCTION(0x2, "gmac" ), /* RGMII-TXCK / GMII-TXEN */ |
103 | SUNXI_FUNCTION(0x4, "pwm3" ), /* PWM_N */ |
104 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */ |
105 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14), |
106 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
107 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
108 | SUNXI_FUNCTION(0x2, "gmac" ), /* MII-TXERR */ |
109 | SUNXI_FUNCTION(0x4, "spi1" ), /* CS0 */ |
110 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */ |
111 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15), |
112 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
113 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
114 | SUNXI_FUNCTION(0x2, "gmac" ), /* RGMII-CLKIN / MII-COL */ |
115 | SUNXI_FUNCTION(0x4, "spi1" ), /* CLK */ |
116 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */ |
117 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), |
118 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
119 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
120 | SUNXI_FUNCTION(0x2, "gmac" ), /* EMDC */ |
121 | SUNXI_FUNCTION(0x4, "spi1" ), /* MOSI */ |
122 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */ |
123 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), |
124 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
125 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
126 | SUNXI_FUNCTION(0x2, "gmac" ), /* EMDIO */ |
127 | SUNXI_FUNCTION(0x4, "spi1" ), /* MISO */ |
128 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */ |
129 | |
130 | /* Hole */ |
131 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), |
132 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
133 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
134 | SUNXI_FUNCTION(0x3, "uart3" ), /* TX */ |
135 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */ |
136 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), |
137 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
138 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
139 | SUNXI_FUNCTION(0x3, "uart3" ), /* RX */ |
140 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PB_EINT6 */ |
141 | |
142 | /* Hole */ |
143 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14), |
144 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
145 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
146 | SUNXI_FUNCTION(0x3, "mcsi" ), /* MCLK */ |
147 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)), /* PB_EINT14 */ |
148 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15), |
149 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
150 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
151 | SUNXI_FUNCTION(0x3, "mcsi" ), /* SCK */ |
152 | SUNXI_FUNCTION(0x4, "i2c4" ), /* SCK */ |
153 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), /* PB_EINT15 */ |
154 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16), |
155 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
156 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
157 | SUNXI_FUNCTION(0x3, "mcsi" ), /* SDA */ |
158 | SUNXI_FUNCTION(0x4, "i2c4" ), /* SDA */ |
159 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)), /* PB_EINT16 */ |
160 | |
161 | /* Hole */ |
162 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), |
163 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
164 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
165 | SUNXI_FUNCTION(0x2, "nand0" ), /* WE */ |
166 | SUNXI_FUNCTION(0x3, "spi0" )), /* MOSI */ |
167 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), |
168 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
169 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
170 | SUNXI_FUNCTION(0x2, "nand0" ), /* ALE */ |
171 | SUNXI_FUNCTION(0x3, "spi0" )), /* MISO */ |
172 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), |
173 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
174 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
175 | SUNXI_FUNCTION(0x2, "nand0" ), /* CLE */ |
176 | SUNXI_FUNCTION(0x3, "spi0" )), /* CLK */ |
177 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), |
178 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
179 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
180 | SUNXI_FUNCTION(0x2, "nand0" )), /* CE1 */ |
181 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), |
182 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
183 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
184 | SUNXI_FUNCTION(0x2, "nand0" )), /* CE0 */ |
185 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), |
186 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
187 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
188 | SUNXI_FUNCTION(0x2, "nand0" )), /* RE */ |
189 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), |
190 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
191 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
192 | SUNXI_FUNCTION(0x2, "nand0" ), /* RB0 */ |
193 | SUNXI_FUNCTION(0x3, "mmc2" )), /* CMD */ |
194 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), |
195 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
196 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
197 | SUNXI_FUNCTION(0x2, "nand0" ), /* RB1 */ |
198 | SUNXI_FUNCTION(0x3, "mmc2" )), /* CLK */ |
199 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), |
200 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
201 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
202 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQ0 */ |
203 | SUNXI_FUNCTION(0x3, "mmc2" )), /* D0 */ |
204 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), |
205 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
206 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
207 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQ1 */ |
208 | SUNXI_FUNCTION(0x3, "mmc2" )), /* D1 */ |
209 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), |
210 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
211 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
212 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQ2 */ |
213 | SUNXI_FUNCTION(0x3, "mmc2" )), /* D2 */ |
214 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), |
215 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
216 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
217 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQ3 */ |
218 | SUNXI_FUNCTION(0x3, "mmc2" )), /* D3 */ |
219 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), |
220 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
221 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
222 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQ4 */ |
223 | SUNXI_FUNCTION(0x3, "mmc2" )), /* D4 */ |
224 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), |
225 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
226 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
227 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQ5 */ |
228 | SUNXI_FUNCTION(0x3, "mmc2" )), /* D5 */ |
229 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), |
230 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
231 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
232 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQ6 */ |
233 | SUNXI_FUNCTION(0x3, "mmc2" )), /* D6 */ |
234 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), |
235 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
236 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
237 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQ7 */ |
238 | SUNXI_FUNCTION(0x3, "mmc2" )), /* D7 */ |
239 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), |
240 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
241 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
242 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQS */ |
243 | SUNXI_FUNCTION(0x3, "mmc2" )), /* RST */ |
244 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17), |
245 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
246 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
247 | SUNXI_FUNCTION(0x2, "nand0" ), /* CE2 */ |
248 | SUNXI_FUNCTION(0x3, "nand0_b" )), /* RE */ |
249 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18), |
250 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
251 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
252 | SUNXI_FUNCTION(0x2, "nand0" ), /* CE3 */ |
253 | SUNXI_FUNCTION(0x3, "nand0_b" )), /* DQS */ |
254 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19), |
255 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
256 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
257 | SUNXI_FUNCTION(0x3, "spi0" )), /* CS0 */ |
258 | |
259 | /* Hole */ |
260 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), |
261 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
262 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
263 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D0 */ |
264 | SUNXI_FUNCTION(0x3, "lvds0" )), /* VP0 */ |
265 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), |
266 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
267 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
268 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D1 */ |
269 | SUNXI_FUNCTION(0x3, "lvds0" )), /* VN0 */ |
270 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), |
271 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
272 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
273 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D2 */ |
274 | SUNXI_FUNCTION(0x3, "lvds0" )), /* VP1 */ |
275 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), |
276 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
277 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
278 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D3 */ |
279 | SUNXI_FUNCTION(0x3, "lvds0" )), /* VN1 */ |
280 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), |
281 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
282 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
283 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D4 */ |
284 | SUNXI_FUNCTION(0x3, "lvds0" )), /* VP2 */ |
285 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), |
286 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
287 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
288 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D5 */ |
289 | SUNXI_FUNCTION(0x3, "lvds0" )), /* VN2 */ |
290 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), |
291 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
292 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
293 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D6 */ |
294 | SUNXI_FUNCTION(0x3, "lvds0" )), /* VPC */ |
295 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), |
296 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
297 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
298 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D7 */ |
299 | SUNXI_FUNCTION(0x3, "lvds0" )), /* VNC */ |
300 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), |
301 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
302 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
303 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D8 */ |
304 | SUNXI_FUNCTION(0x3, "lvds0" )), /* VP3 */ |
305 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), |
306 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
307 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
308 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D9 */ |
309 | SUNXI_FUNCTION(0x3, "lvds0" )), /* VN3 */ |
310 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), |
311 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
312 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
313 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D10 */ |
314 | SUNXI_FUNCTION(0x3, "lvds1" )), /* VP0 */ |
315 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), |
316 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
317 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
318 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D11 */ |
319 | SUNXI_FUNCTION(0x3, "lvds1" )), /* VN0 */ |
320 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), |
321 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
322 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
323 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D12 */ |
324 | SUNXI_FUNCTION(0x3, "lvds1" )), /* VP1 */ |
325 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), |
326 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
327 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
328 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D13 */ |
329 | SUNXI_FUNCTION(0x3, "lvds1" )), /* VN1 */ |
330 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), |
331 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
332 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
333 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D14 */ |
334 | SUNXI_FUNCTION(0x3, "lvds1" )), /* VP2 */ |
335 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), |
336 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
337 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
338 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D15 */ |
339 | SUNXI_FUNCTION(0x3, "lvds1" )), /* VN2 */ |
340 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), |
341 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
342 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
343 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D16 */ |
344 | SUNXI_FUNCTION(0x3, "lvds1" )), /* VPC */ |
345 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), |
346 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
347 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
348 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D17 */ |
349 | SUNXI_FUNCTION(0x3, "lvds1" )), /* VNC */ |
350 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), |
351 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
352 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
353 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D18 */ |
354 | SUNXI_FUNCTION(0x3, "lvds1" )), /* VP3 */ |
355 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), |
356 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
357 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
358 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D19 */ |
359 | SUNXI_FUNCTION(0x3, "lvds1" )), /* VN3 */ |
360 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), |
361 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
362 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
363 | SUNXI_FUNCTION(0x2, "lcd0" )), /* D20 */ |
364 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), |
365 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
366 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
367 | SUNXI_FUNCTION(0x2, "lcd0" )), /* D21 */ |
368 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), |
369 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
370 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
371 | SUNXI_FUNCTION(0x2, "lcd0" )), /* D22 */ |
372 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), |
373 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
374 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
375 | SUNXI_FUNCTION(0x2, "lcd0" )), /* D23 */ |
376 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), |
377 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
378 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
379 | SUNXI_FUNCTION(0x2, "lcd0" )), /* CLK */ |
380 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), |
381 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
382 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
383 | SUNXI_FUNCTION(0x2, "lcd0" )), /* DE */ |
384 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), |
385 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
386 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
387 | SUNXI_FUNCTION(0x2, "lcd0" )), /* HSYNC */ |
388 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), |
389 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
390 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
391 | SUNXI_FUNCTION(0x2, "lcd0" )), /* VSYNC */ |
392 | |
393 | /* Hole */ |
394 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), |
395 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
396 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
397 | SUNXI_FUNCTION(0x2, "csi" ), /* PCLK */ |
398 | SUNXI_FUNCTION(0x3, "ts" ), /* CLK */ |
399 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PE_EINT0 */ |
400 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), |
401 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
402 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
403 | SUNXI_FUNCTION(0x2, "csi" ), /* MCLK */ |
404 | SUNXI_FUNCTION(0x3, "ts" ), /* ERR */ |
405 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PE_EINT1 */ |
406 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), |
407 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
408 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
409 | SUNXI_FUNCTION(0x2, "csi" ), /* HSYNC */ |
410 | SUNXI_FUNCTION(0x3, "ts" ), /* SYNC */ |
411 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PE_EINT2 */ |
412 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), |
413 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
414 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
415 | SUNXI_FUNCTION(0x2, "csi" ), /* VSYNC */ |
416 | SUNXI_FUNCTION(0x3, "ts" ), /* DVLD */ |
417 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PE_EINT3 */ |
418 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), |
419 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
420 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
421 | SUNXI_FUNCTION(0x2, "csi" ), /* D0 */ |
422 | SUNXI_FUNCTION(0x3, "spi2" ), /* CS0 */ |
423 | SUNXI_FUNCTION(0x4, "uart5" ), /* TX */ |
424 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PE_EINT4 */ |
425 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), |
426 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
427 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
428 | SUNXI_FUNCTION(0x2, "csi" ), /* D1 */ |
429 | SUNXI_FUNCTION(0x3, "spi2" ), /* CLK */ |
430 | SUNXI_FUNCTION(0x4, "uart5" ), /* RX */ |
431 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PE_EINT5 */ |
432 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), |
433 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
434 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
435 | SUNXI_FUNCTION(0x2, "csi" ), /* D2 */ |
436 | SUNXI_FUNCTION(0x3, "spi2" ), /* MOSI */ |
437 | SUNXI_FUNCTION(0x4, "uart5" ), /* RTS */ |
438 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PE_EINT6 */ |
439 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), |
440 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
441 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
442 | SUNXI_FUNCTION(0x2, "csi" ), /* D3 */ |
443 | SUNXI_FUNCTION(0x3, "spi2" ), /* MISO */ |
444 | SUNXI_FUNCTION(0x4, "uart5" ), /* CTS */ |
445 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PE_EINT7 */ |
446 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), |
447 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
448 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
449 | SUNXI_FUNCTION(0x2, "csi" ), /* D4 */ |
450 | SUNXI_FUNCTION(0x3, "ts" ), /* D0 */ |
451 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PE_EINT8 */ |
452 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), |
453 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
454 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
455 | SUNXI_FUNCTION(0x2, "csi" ), /* D5 */ |
456 | SUNXI_FUNCTION(0x3, "ts" ), /* D1 */ |
457 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PE_EINT9 */ |
458 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), |
459 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
460 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
461 | SUNXI_FUNCTION(0x2, "csi" ), /* D6 */ |
462 | SUNXI_FUNCTION(0x3, "ts" ), /* D2 */ |
463 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PE_EINT10 */ |
464 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), |
465 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
466 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
467 | SUNXI_FUNCTION(0x2, "csi" ), /* D7 */ |
468 | SUNXI_FUNCTION(0x3, "ts" ), /* D3 */ |
469 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PE_EINT11 */ |
470 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), |
471 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
472 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
473 | SUNXI_FUNCTION(0x2, "csi" ), /* D8 */ |
474 | SUNXI_FUNCTION(0x3, "ts" ), /* D4 */ |
475 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PE_EINT12 */ |
476 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), |
477 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
478 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
479 | SUNXI_FUNCTION(0x2, "csi" ), /* D9 */ |
480 | SUNXI_FUNCTION(0x3, "ts" ), /* D5 */ |
481 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PE_EINT13 */ |
482 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), |
483 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
484 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
485 | SUNXI_FUNCTION(0x2, "csi" ), /* D10 */ |
486 | SUNXI_FUNCTION(0x3, "ts" ), /* D6 */ |
487 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PE_EINT14 */ |
488 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), |
489 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
490 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
491 | SUNXI_FUNCTION(0x2, "csi" ), /* D11 */ |
492 | SUNXI_FUNCTION(0x3, "ts" ), /* D7 */ |
493 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PE_EINT15 */ |
494 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), |
495 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
496 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
497 | SUNXI_FUNCTION(0x2, "csi" ), /* SCK */ |
498 | SUNXI_FUNCTION(0x3, "i2c4" ), /* SCK */ |
499 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), /* PE_EINT16 */ |
500 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17), |
501 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
502 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
503 | SUNXI_FUNCTION(0x2, "csi" ), /* SDA */ |
504 | SUNXI_FUNCTION(0x3, "i2c4" ), /* SDA */ |
505 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)), /* PE_EINT17 */ |
506 | |
507 | /* Hole */ |
508 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), |
509 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
510 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
511 | SUNXI_FUNCTION(0x2, "mmc0" )), /* D1 */ |
512 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), |
513 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
514 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
515 | SUNXI_FUNCTION(0x2, "mmc0" )), /* D0 */ |
516 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), |
517 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
518 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
519 | SUNXI_FUNCTION(0x2, "mmc0" ), /* CLK */ |
520 | SUNXI_FUNCTION(0x4, "uart0" )), /* TX */ |
521 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), |
522 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
523 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
524 | SUNXI_FUNCTION(0x2, "mmc0" )), /* CMD */ |
525 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), |
526 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
527 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
528 | SUNXI_FUNCTION(0x2, "mmc0" ), /* D3 */ |
529 | SUNXI_FUNCTION(0x4, "uart0" )), /* RX */ |
530 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), |
531 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
532 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
533 | SUNXI_FUNCTION(0x2, "mmc0" )), /* D2 */ |
534 | |
535 | /* Hole */ |
536 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), |
537 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
538 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
539 | SUNXI_FUNCTION(0x2, "mmc1" ), /* CLK */ |
540 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PG_EINT0 */ |
541 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), |
542 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
543 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
544 | SUNXI_FUNCTION(0x2, "mmc1" ), /* CMD */ |
545 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PG_EINT1 */ |
546 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), |
547 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
548 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
549 | SUNXI_FUNCTION(0x2, "mmc1" ), /* D0 */ |
550 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PG_EINT2 */ |
551 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), |
552 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
553 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
554 | SUNXI_FUNCTION(0x2, "mmc1" ), /* D1 */ |
555 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PG_EINT3 */ |
556 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), |
557 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
558 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
559 | SUNXI_FUNCTION(0x2, "mmc1" ), /* D2 */ |
560 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PG_EINT4 */ |
561 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), |
562 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
563 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
564 | SUNXI_FUNCTION(0x2, "mmc1" ), /* D3 */ |
565 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PG_EINT5 */ |
566 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), |
567 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
568 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
569 | SUNXI_FUNCTION(0x2, "uart2" ), /* TX */ |
570 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PG_EINT6 */ |
571 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), |
572 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
573 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
574 | SUNXI_FUNCTION(0x2, "uart2" ), /* RX */ |
575 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PG_EINT7 */ |
576 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), |
577 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
578 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
579 | SUNXI_FUNCTION(0x2, "uart2" ), /* RTS */ |
580 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PG_EINT8 */ |
581 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), |
582 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
583 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
584 | SUNXI_FUNCTION(0x2, "uart2" ), /* CTS */ |
585 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PG_EINT9 */ |
586 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), |
587 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
588 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
589 | SUNXI_FUNCTION(0x2, "i2c3" ), /* SCK */ |
590 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PG_EINT10 */ |
591 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), |
592 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
593 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
594 | SUNXI_FUNCTION(0x2, "i2c3" ), /* SDA */ |
595 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PG_EINT11 */ |
596 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), |
597 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
598 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
599 | SUNXI_FUNCTION(0x2, "uart4" ), /* TX */ |
600 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PG_EINT12 */ |
601 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), |
602 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
603 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
604 | SUNXI_FUNCTION(0x2, "uart4" ), /* RX */ |
605 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PG_EINT13 */ |
606 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14), |
607 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
608 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
609 | SUNXI_FUNCTION(0x2, "uart4" ), /* RTS */ |
610 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PG_EINT14 */ |
611 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15), |
612 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
613 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
614 | SUNXI_FUNCTION(0x2, "uart4" ), /* CTS */ |
615 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PG_EINT15 */ |
616 | |
617 | /* Hole */ |
618 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), |
619 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
620 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
621 | SUNXI_FUNCTION(0x2, "i2c0" )), /* SCK */ |
622 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), |
623 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
624 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
625 | SUNXI_FUNCTION(0x2, "i2c0" )), /* SDA */ |
626 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), |
627 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
628 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
629 | SUNXI_FUNCTION(0x2, "i2c1" )), /* SCK */ |
630 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), |
631 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
632 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
633 | SUNXI_FUNCTION(0x2, "i2c1" )), /* SDA */ |
634 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), |
635 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
636 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
637 | SUNXI_FUNCTION(0x2, "i2c2" )), /* SCK */ |
638 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), |
639 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
640 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
641 | SUNXI_FUNCTION(0x2, "i2c2" )), /* SDA */ |
642 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), |
643 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
644 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
645 | SUNXI_FUNCTION(0x2, "pwm0" )), |
646 | |
647 | /* Hole */ |
648 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), |
649 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
650 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
651 | SUNXI_FUNCTION(0x3, "pwm1" ), /* Positive */ |
652 | SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 8)), /* PH_EINT8 */ |
653 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), |
654 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
655 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
656 | SUNXI_FUNCTION(0x3, "pwm1" ), /* Negative */ |
657 | SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 9)), /* PH_EINT9 */ |
658 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10), |
659 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
660 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
661 | SUNXI_FUNCTION(0x3, "pwm2" ), /* Positive */ |
662 | SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 10)), /* PH_EINT10 */ |
663 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11), |
664 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
665 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
666 | SUNXI_FUNCTION(0x3, "pwm2" ), /* Negative */ |
667 | SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 11)), /* PH_EINT12 */ |
668 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12), |
669 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
670 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
671 | SUNXI_FUNCTION(0x2, "uart0" ), /* TX */ |
672 | SUNXI_FUNCTION(0x3, "spi3" ), /* CS2 */ |
673 | SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 12)), /* PH_EINT12 */ |
674 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13), |
675 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
676 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
677 | SUNXI_FUNCTION(0x2, "uart0" ), /* RX */ |
678 | SUNXI_FUNCTION(0x3, "spi3" ), /* CS2 */ |
679 | SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 13)), /* PH_EINT13 */ |
680 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14), |
681 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
682 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
683 | SUNXI_FUNCTION(0x2, "spi3" ), /* CLK */ |
684 | SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 14)), /* PH_EINT14 */ |
685 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15), |
686 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
687 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
688 | SUNXI_FUNCTION(0x2, "spi3" ), /* MOSI */ |
689 | SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 15)), /* PH_EINT15 */ |
690 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16), |
691 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
692 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
693 | SUNXI_FUNCTION(0x2, "spi3" ), /* MISO */ |
694 | SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 16)), /* PH_EINT16 */ |
695 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17), |
696 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
697 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
698 | SUNXI_FUNCTION(0x2, "spi3" ), /* CS0 */ |
699 | SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 17)), /* PH_EINT17 */ |
700 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18), |
701 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
702 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
703 | SUNXI_FUNCTION(0x2, "spi3" ), /* CS1 */ |
704 | SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 18)), /* PH_EINT18 */ |
705 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19), |
706 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
707 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
708 | SUNXI_FUNCTION(0x2, "hdmi" )), /* SCL */ |
709 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20), |
710 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
711 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
712 | SUNXI_FUNCTION(0x2, "hdmi" )), /* SDA */ |
713 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21), |
714 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
715 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
716 | SUNXI_FUNCTION(0x2, "hdmi" )), /* CEC */ |
717 | }; |
718 | |
719 | static const struct sunxi_pinctrl_desc sun9i_a80_pinctrl_data = { |
720 | .pins = sun9i_a80_pins, |
721 | .npins = ARRAY_SIZE(sun9i_a80_pins), |
722 | .irq_banks = 5, |
723 | .disable_strict_mode = true, |
724 | .io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG, |
725 | }; |
726 | |
727 | static int sun9i_a80_pinctrl_probe(struct platform_device *pdev) |
728 | { |
729 | return sunxi_pinctrl_init(pdev, |
730 | &sun9i_a80_pinctrl_data); |
731 | } |
732 | |
733 | static const struct of_device_id sun9i_a80_pinctrl_match[] = { |
734 | { .compatible = "allwinner,sun9i-a80-pinctrl" , }, |
735 | {} |
736 | }; |
737 | |
738 | static struct platform_driver sun9i_a80_pinctrl_driver = { |
739 | .probe = sun9i_a80_pinctrl_probe, |
740 | .driver = { |
741 | .name = "sun9i-a80-pinctrl" , |
742 | .of_match_table = sun9i_a80_pinctrl_match, |
743 | }, |
744 | }; |
745 | builtin_platform_driver(sun9i_a80_pinctrl_driver); |
746 | |