1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /* |
3 | * Copyright (C) 2015-2017 Socionext Inc. |
4 | * Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
5 | */ |
6 | |
7 | #ifndef __PINCTRL_UNIPHIER_H__ |
8 | #define __PINCTRL_UNIPHIER_H__ |
9 | |
10 | #include <linux/bits.h> |
11 | #include <linux/build_bug.h> |
12 | #include <linux/kernel.h> |
13 | #include <linux/types.h> |
14 | |
15 | struct platform_device; |
16 | |
17 | /* input enable control register bit */ |
18 | #define UNIPHIER_PIN_IECTRL_SHIFT 0 |
19 | #define UNIPHIER_PIN_IECTRL_BITS 3 |
20 | #define UNIPHIER_PIN_IECTRL_MASK ((1UL << (UNIPHIER_PIN_IECTRL_BITS)) \ |
21 | - 1) |
22 | |
23 | /* drive strength control register number */ |
24 | #define UNIPHIER_PIN_DRVCTRL_SHIFT ((UNIPHIER_PIN_IECTRL_SHIFT) + \ |
25 | (UNIPHIER_PIN_IECTRL_BITS)) |
26 | #define UNIPHIER_PIN_DRVCTRL_BITS 9 |
27 | #define UNIPHIER_PIN_DRVCTRL_MASK ((1UL << (UNIPHIER_PIN_DRVCTRL_BITS)) \ |
28 | - 1) |
29 | |
30 | /* drive control type */ |
31 | #define UNIPHIER_PIN_DRV_TYPE_SHIFT ((UNIPHIER_PIN_DRVCTRL_SHIFT) + \ |
32 | (UNIPHIER_PIN_DRVCTRL_BITS)) |
33 | #define UNIPHIER_PIN_DRV_TYPE_BITS 3 |
34 | #define UNIPHIER_PIN_DRV_TYPE_MASK ((1UL << (UNIPHIER_PIN_DRV_TYPE_BITS)) \ |
35 | - 1) |
36 | |
37 | /* pull-up / pull-down register number */ |
38 | #define UNIPHIER_PIN_PUPDCTRL_SHIFT ((UNIPHIER_PIN_DRV_TYPE_SHIFT) + \ |
39 | (UNIPHIER_PIN_DRV_TYPE_BITS)) |
40 | #define UNIPHIER_PIN_PUPDCTRL_BITS 9 |
41 | #define UNIPHIER_PIN_PUPDCTRL_MASK ((1UL << (UNIPHIER_PIN_PUPDCTRL_BITS))\ |
42 | - 1) |
43 | |
44 | /* direction of pull register */ |
45 | #define UNIPHIER_PIN_PULL_DIR_SHIFT ((UNIPHIER_PIN_PUPDCTRL_SHIFT) + \ |
46 | (UNIPHIER_PIN_PUPDCTRL_BITS)) |
47 | #define UNIPHIER_PIN_PULL_DIR_BITS 3 |
48 | #define UNIPHIER_PIN_PULL_DIR_MASK ((1UL << (UNIPHIER_PIN_PULL_DIR_BITS))\ |
49 | - 1) |
50 | |
51 | #if UNIPHIER_PIN_PULL_DIR_SHIFT + UNIPHIER_PIN_PULL_DIR_BITS > BITS_PER_LONG |
52 | #error "unable to pack pin attributes." |
53 | #endif |
54 | |
55 | #define UNIPHIER_PIN_IECTRL_NONE (UNIPHIER_PIN_IECTRL_MASK) |
56 | #define UNIPHIER_PIN_IECTRL_EXIST 0 |
57 | |
58 | /* drive control type */ |
59 | enum uniphier_pin_drv_type { |
60 | UNIPHIER_PIN_DRV_1BIT, /* 2 level control: 4/8 mA */ |
61 | UNIPHIER_PIN_DRV_2BIT, /* 4 level control: 8/12/16/20 mA */ |
62 | UNIPHIER_PIN_DRV_3BIT, /* 8 level control: 4/5/7/9/11/12/14/16 mA */ |
63 | UNIPHIER_PIN_DRV_FIXED4, /* fixed to 4mA */ |
64 | UNIPHIER_PIN_DRV_FIXED5, /* fixed to 5mA */ |
65 | UNIPHIER_PIN_DRV_FIXED8, /* fixed to 8mA */ |
66 | UNIPHIER_PIN_DRV_NONE, /* no support (input only pin) */ |
67 | }; |
68 | |
69 | /* direction of pull register (no pin supports bi-directional pull biasing) */ |
70 | enum uniphier_pin_pull_dir { |
71 | UNIPHIER_PIN_PULL_UP, /* pull-up or disabled */ |
72 | UNIPHIER_PIN_PULL_DOWN, /* pull-down or disabled */ |
73 | UNIPHIER_PIN_PULL_UP_FIXED, /* always pull-up */ |
74 | UNIPHIER_PIN_PULL_DOWN_FIXED, /* always pull-down */ |
75 | UNIPHIER_PIN_PULL_NONE, /* no pull register */ |
76 | }; |
77 | |
78 | #define UNIPHIER_PIN_IECTRL(x) \ |
79 | (((x) & (UNIPHIER_PIN_IECTRL_MASK)) << (UNIPHIER_PIN_IECTRL_SHIFT)) |
80 | #define UNIPHIER_PIN_DRVCTRL(x) \ |
81 | (((x) & (UNIPHIER_PIN_DRVCTRL_MASK)) << (UNIPHIER_PIN_DRVCTRL_SHIFT)) |
82 | #define UNIPHIER_PIN_DRV_TYPE(x) \ |
83 | (((x) & (UNIPHIER_PIN_DRV_TYPE_MASK)) << (UNIPHIER_PIN_DRV_TYPE_SHIFT)) |
84 | #define UNIPHIER_PIN_PUPDCTRL(x) \ |
85 | (((x) & (UNIPHIER_PIN_PUPDCTRL_MASK)) << (UNIPHIER_PIN_PUPDCTRL_SHIFT)) |
86 | #define UNIPHIER_PIN_PULL_DIR(x) \ |
87 | (((x) & (UNIPHIER_PIN_PULL_DIR_MASK)) << (UNIPHIER_PIN_PULL_DIR_SHIFT)) |
88 | |
89 | #define UNIPHIER_PIN_ATTR_PACKED(iectrl, drvctrl, drv_type, pupdctrl, pull_dir)\ |
90 | (UNIPHIER_PIN_IECTRL(iectrl) | \ |
91 | UNIPHIER_PIN_DRVCTRL(drvctrl) | \ |
92 | UNIPHIER_PIN_DRV_TYPE(drv_type) | \ |
93 | UNIPHIER_PIN_PUPDCTRL(pupdctrl) | \ |
94 | UNIPHIER_PIN_PULL_DIR(pull_dir)) |
95 | |
96 | static inline unsigned int uniphier_pin_get_iectrl(void *drv_data) |
97 | { |
98 | return ((unsigned long)drv_data >> UNIPHIER_PIN_IECTRL_SHIFT) & |
99 | UNIPHIER_PIN_IECTRL_MASK; |
100 | } |
101 | |
102 | static inline unsigned int uniphier_pin_get_drvctrl(void *drv_data) |
103 | { |
104 | return ((unsigned long)drv_data >> UNIPHIER_PIN_DRVCTRL_SHIFT) & |
105 | UNIPHIER_PIN_DRVCTRL_MASK; |
106 | } |
107 | |
108 | static inline unsigned int uniphier_pin_get_drv_type(void *drv_data) |
109 | { |
110 | return ((unsigned long)drv_data >> UNIPHIER_PIN_DRV_TYPE_SHIFT) & |
111 | UNIPHIER_PIN_DRV_TYPE_MASK; |
112 | } |
113 | |
114 | static inline unsigned int uniphier_pin_get_pupdctrl(void *drv_data) |
115 | { |
116 | return ((unsigned long)drv_data >> UNIPHIER_PIN_PUPDCTRL_SHIFT) & |
117 | UNIPHIER_PIN_PUPDCTRL_MASK; |
118 | } |
119 | |
120 | static inline unsigned int uniphier_pin_get_pull_dir(void *drv_data) |
121 | { |
122 | return ((unsigned long)drv_data >> UNIPHIER_PIN_PULL_DIR_SHIFT) & |
123 | UNIPHIER_PIN_PULL_DIR_MASK; |
124 | } |
125 | |
126 | struct uniphier_pinctrl_group { |
127 | const char *name; |
128 | const unsigned *pins; |
129 | unsigned num_pins; |
130 | const int *muxvals; |
131 | }; |
132 | |
133 | struct uniphier_pinmux_function { |
134 | const char *name; |
135 | const char * const *groups; |
136 | unsigned num_groups; |
137 | }; |
138 | |
139 | struct uniphier_pinctrl_socdata { |
140 | const struct pinctrl_pin_desc *pins; |
141 | unsigned int npins; |
142 | const struct uniphier_pinctrl_group *groups; |
143 | int groups_count; |
144 | const struct uniphier_pinmux_function *functions; |
145 | int functions_count; |
146 | int (*get_gpio_muxval)(unsigned int pin, unsigned int gpio_offset); |
147 | unsigned int caps; |
148 | #define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(1) |
149 | #define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(0) |
150 | }; |
151 | |
152 | #define UNIPHIER_PINCTRL_PIN(a, b, c, d, e, f, g) \ |
153 | { \ |
154 | .number = a, \ |
155 | .name = b, \ |
156 | .drv_data = (void *)UNIPHIER_PIN_ATTR_PACKED(c, d, e, f, g), \ |
157 | } |
158 | |
159 | #define __UNIPHIER_PINCTRL_GROUP(grp, mux) \ |
160 | { \ |
161 | .name = #grp, \ |
162 | .pins = grp##_pins, \ |
163 | .num_pins = ARRAY_SIZE(grp##_pins), \ |
164 | .muxvals = mux, \ |
165 | } |
166 | |
167 | #define UNIPHIER_PINCTRL_GROUP(grp) \ |
168 | __UNIPHIER_PINCTRL_GROUP(grp, \ |
169 | grp##_muxvals + \ |
170 | BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) != \ |
171 | ARRAY_SIZE(grp##_muxvals))) |
172 | |
173 | #define UNIPHIER_PINCTRL_GROUP_GPIO(grp) \ |
174 | __UNIPHIER_PINCTRL_GROUP(grp, NULL) |
175 | |
176 | #define UNIPHIER_PINMUX_FUNCTION(func) \ |
177 | { \ |
178 | .name = #func, \ |
179 | .groups = func##_groups, \ |
180 | .num_groups = ARRAY_SIZE(func##_groups), \ |
181 | } |
182 | |
183 | int uniphier_pinctrl_probe(struct platform_device *pdev, |
184 | const struct uniphier_pinctrl_socdata *socdata); |
185 | |
186 | extern const struct dev_pm_ops uniphier_pinctrl_pm_ops; |
187 | |
188 | #endif /* __PINCTRL_UNIPHIER_H__ */ |
189 | |