1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (c) 2009-2010 Intel Corporation |
4 | * |
5 | * Authors: |
6 | * Jesse Barnes <jbarnes@virtuousgeek.org> |
7 | */ |
8 | |
9 | /* |
10 | * Some Intel Ibex Peak based platforms support so-called "intelligent |
11 | * power sharing", which allows the CPU and GPU to cooperate to maximize |
12 | * performance within a given TDP (thermal design point). This driver |
13 | * performs the coordination between the CPU and GPU, monitors thermal and |
14 | * power statistics in the platform, and initializes power monitoring |
15 | * hardware. It also provides a few tunables to control behavior. Its |
16 | * primary purpose is to safely allow CPU and GPU turbo modes to be enabled |
17 | * by tracking power and thermal budget; secondarily it can boost turbo |
18 | * performance by allocating more power or thermal budget to the CPU or GPU |
19 | * based on available headroom and activity. |
20 | * |
21 | * The basic algorithm is driven by a 5s moving average of temperature. If |
22 | * thermal headroom is available, the CPU and/or GPU power clamps may be |
23 | * adjusted upwards. If we hit the thermal ceiling or a thermal trigger, |
24 | * we scale back the clamp. Aside from trigger events (when we're critically |
25 | * close or over our TDP) we don't adjust the clamps more than once every |
26 | * five seconds. |
27 | * |
28 | * The thermal device (device 31, function 6) has a set of registers that |
29 | * are updated by the ME firmware. The ME should also take the clamp values |
30 | * written to those registers and write them to the CPU, but we currently |
31 | * bypass that functionality and write the CPU MSR directly. |
32 | * |
33 | * UNSUPPORTED: |
34 | * - dual MCP configs |
35 | * |
36 | * TODO: |
37 | * - handle CPU hotplug |
38 | * - provide turbo enable/disable api |
39 | * |
40 | * Related documents: |
41 | * - CDI 403777, 403778 - Auburndale EDS vol 1 & 2 |
42 | * - CDI 401376 - Ibex Peak EDS |
43 | * - ref 26037, 26641 - IPS BIOS spec |
44 | * - ref 26489 - Nehalem BIOS writer's guide |
45 | * - ref 26921 - Ibex Peak BIOS Specification |
46 | */ |
47 | |
48 | #include <linux/debugfs.h> |
49 | #include <linux/delay.h> |
50 | #include <linux/interrupt.h> |
51 | #include <linux/kernel.h> |
52 | #include <linux/kthread.h> |
53 | #include <linux/module.h> |
54 | #include <linux/pci.h> |
55 | #include <linux/sched.h> |
56 | #include <linux/sched/loadavg.h> |
57 | #include <linux/seq_file.h> |
58 | #include <linux/string.h> |
59 | #include <linux/tick.h> |
60 | #include <linux/timer.h> |
61 | #include <linux/dmi.h> |
62 | #include <drm/i915_drm.h> |
63 | #include <asm/msr.h> |
64 | #include <asm/processor.h> |
65 | #include "intel_ips.h" |
66 | |
67 | #include <linux/io-64-nonatomic-lo-hi.h> |
68 | |
69 | #define PCI_DEVICE_ID_INTEL_THERMAL_SENSOR 0x3b32 |
70 | |
71 | /* |
72 | * Package level MSRs for monitor/control |
73 | */ |
74 | #define PLATFORM_INFO 0xce |
75 | #define PLATFORM_TDP (1<<29) |
76 | #define PLATFORM_RATIO (1<<28) |
77 | |
78 | #define IA32_MISC_ENABLE 0x1a0 |
79 | #define IA32_MISC_TURBO_EN (1ULL<<38) |
80 | |
81 | #define TURBO_POWER_CURRENT_LIMIT 0x1ac |
82 | #define TURBO_TDC_OVR_EN (1UL<<31) |
83 | #define TURBO_TDC_MASK (0x000000007fff0000UL) |
84 | #define TURBO_TDC_SHIFT (16) |
85 | #define TURBO_TDP_OVR_EN (1UL<<15) |
86 | #define TURBO_TDP_MASK (0x0000000000003fffUL) |
87 | |
88 | /* |
89 | * Core/thread MSRs for monitoring |
90 | */ |
91 | #define IA32_PERF_CTL 0x199 |
92 | #define IA32_PERF_TURBO_DIS (1ULL<<32) |
93 | |
94 | /* |
95 | * Thermal PCI device regs |
96 | */ |
97 | #define THM_CFG_TBAR 0x10 |
98 | #define THM_CFG_TBAR_HI 0x14 |
99 | |
100 | #define THM_TSIU 0x00 |
101 | #define THM_TSE 0x01 |
102 | #define TSE_EN 0xb8 |
103 | #define THM_TSS 0x02 |
104 | #define THM_TSTR 0x03 |
105 | #define THM_TSTTP 0x04 |
106 | #define THM_TSCO 0x08 |
107 | #define THM_TSES 0x0c |
108 | #define THM_TSGPEN 0x0d |
109 | #define TSGPEN_HOT_LOHI (1<<1) |
110 | #define TSGPEN_CRIT_LOHI (1<<2) |
111 | #define THM_TSPC 0x0e |
112 | #define THM_PPEC 0x10 |
113 | #define THM_CTA 0x12 |
114 | #define THM_PTA 0x14 |
115 | #define PTA_SLOPE_MASK (0xff00) |
116 | #define PTA_SLOPE_SHIFT 8 |
117 | #define PTA_OFFSET_MASK (0x00ff) |
118 | #define THM_MGTA 0x16 |
119 | #define MGTA_SLOPE_MASK (0xff00) |
120 | #define MGTA_SLOPE_SHIFT 8 |
121 | #define MGTA_OFFSET_MASK (0x00ff) |
122 | #define THM_TRC 0x1a |
123 | #define TRC_CORE2_EN (1<<15) |
124 | #define TRC_THM_EN (1<<12) |
125 | #define TRC_C6_WAR (1<<8) |
126 | #define TRC_CORE1_EN (1<<7) |
127 | #define TRC_CORE_PWR (1<<6) |
128 | #define TRC_PCH_EN (1<<5) |
129 | #define TRC_MCH_EN (1<<4) |
130 | #define TRC_DIMM4 (1<<3) |
131 | #define TRC_DIMM3 (1<<2) |
132 | #define TRC_DIMM2 (1<<1) |
133 | #define TRC_DIMM1 (1<<0) |
134 | #define THM_TES 0x20 |
135 | #define THM_TEN 0x21 |
136 | #define TEN_UPDATE_EN 1 |
137 | #define THM_PSC 0x24 |
138 | #define PSC_NTG (1<<0) /* No GFX turbo support */ |
139 | #define PSC_NTPC (1<<1) /* No CPU turbo support */ |
140 | #define PSC_PP_DEF (0<<2) /* Perf policy up to driver */ |
141 | #define PSP_PP_PC (1<<2) /* BIOS prefers CPU perf */ |
142 | #define PSP_PP_BAL (2<<2) /* BIOS wants balanced perf */ |
143 | #define PSP_PP_GFX (3<<2) /* BIOS prefers GFX perf */ |
144 | #define PSP_PBRT (1<<4) /* BIOS run time support */ |
145 | #define THM_CTV1 0x30 |
146 | #define CTV_TEMP_ERROR (1<<15) |
147 | #define CTV_TEMP_MASK 0x3f |
148 | #define CTV_ |
149 | #define THM_CTV2 0x32 |
150 | #define THM_CEC 0x34 /* undocumented power accumulator in joules */ |
151 | #define THM_AE 0x3f |
152 | #define THM_HTS 0x50 /* 32 bits */ |
153 | #define HTS_PCPL_MASK (0x7fe00000) |
154 | #define HTS_PCPL_SHIFT 21 |
155 | #define HTS_GPL_MASK (0x001ff000) |
156 | #define HTS_GPL_SHIFT 12 |
157 | #define HTS_PP_MASK (0x00000c00) |
158 | #define HTS_PP_SHIFT 10 |
159 | #define HTS_PP_DEF 0 |
160 | #define HTS_PP_PROC 1 |
161 | #define HTS_PP_BAL 2 |
162 | #define HTS_PP_GFX 3 |
163 | #define HTS_PCTD_DIS (1<<9) |
164 | #define HTS_GTD_DIS (1<<8) |
165 | #define HTS_PTL_MASK (0x000000fe) |
166 | #define HTS_PTL_SHIFT 1 |
167 | #define HTS_NVV (1<<0) |
168 | #define THM_HTSHI 0x54 /* 16 bits */ |
169 | #define HTS2_PPL_MASK (0x03ff) |
170 | #define HTS2_PRST_MASK (0x3c00) |
171 | #define HTS2_PRST_SHIFT 10 |
172 | #define HTS2_PRST_UNLOADED 0 |
173 | #define HTS2_PRST_RUNNING 1 |
174 | #define HTS2_PRST_TDISOP 2 /* turbo disabled due to power */ |
175 | #define HTS2_PRST_TDISHT 3 /* turbo disabled due to high temp */ |
176 | #define HTS2_PRST_TDISUSR 4 /* user disabled turbo */ |
177 | #define HTS2_PRST_TDISPLAT 5 /* platform disabled turbo */ |
178 | #define HTS2_PRST_TDISPM 6 /* power management disabled turbo */ |
179 | #define HTS2_PRST_TDISERR 7 /* some kind of error disabled turbo */ |
180 | #define THM_PTL 0x56 |
181 | #define THM_MGTV 0x58 |
182 | #define TV_MASK 0x000000000000ff00 |
183 | #define TV_SHIFT 8 |
184 | #define THM_PTV 0x60 |
185 | #define PTV_MASK 0x00ff |
186 | #define THM_MMGPC 0x64 |
187 | #define THM_MPPC 0x66 |
188 | #define THM_MPCPC 0x68 |
189 | #define THM_TSPIEN 0x82 |
190 | #define TSPIEN_AUX_LOHI (1<<0) |
191 | #define TSPIEN_HOT_LOHI (1<<1) |
192 | #define TSPIEN_CRIT_LOHI (1<<2) |
193 | #define TSPIEN_AUX2_LOHI (1<<3) |
194 | #define THM_TSLOCK 0x83 |
195 | #define THM_ATR 0x84 |
196 | #define THM_TOF 0x87 |
197 | #define THM_STS 0x98 |
198 | #define STS_PCPL_MASK (0x7fe00000) |
199 | #define STS_PCPL_SHIFT 21 |
200 | #define STS_GPL_MASK (0x001ff000) |
201 | #define STS_GPL_SHIFT 12 |
202 | #define STS_PP_MASK (0x00000c00) |
203 | #define STS_PP_SHIFT 10 |
204 | #define STS_PP_DEF 0 |
205 | #define STS_PP_PROC 1 |
206 | #define STS_PP_BAL 2 |
207 | #define STS_PP_GFX 3 |
208 | #define STS_PCTD_DIS (1<<9) |
209 | #define STS_GTD_DIS (1<<8) |
210 | #define STS_PTL_MASK (0x000000fe) |
211 | #define STS_PTL_SHIFT 1 |
212 | #define STS_NVV (1<<0) |
213 | #define THM_SEC 0x9c |
214 | #define SEC_ACK (1<<0) |
215 | #define THM_TC3 0xa4 |
216 | #define THM_TC1 0xa8 |
217 | #define STS_PPL_MASK (0x0003ff00) |
218 | #define STS_PPL_SHIFT 16 |
219 | #define THM_TC2 0xac |
220 | #define THM_DTV 0xb0 |
221 | #define THM_ITV 0xd8 |
222 | #define ITV_ME_SEQNO_MASK 0x00ff0000 /* ME should update every ~200ms */ |
223 | #define ITV_ME_SEQNO_SHIFT (16) |
224 | #define ITV_MCH_TEMP_MASK 0x0000ff00 |
225 | #define ITV_MCH_TEMP_SHIFT (8) |
226 | #define ITV_PCH_TEMP_MASK 0x000000ff |
227 | |
228 | #define thm_readb(off) readb(ips->regmap + (off)) |
229 | #define thm_readw(off) readw(ips->regmap + (off)) |
230 | #define thm_readl(off) readl(ips->regmap + (off)) |
231 | #define thm_readq(off) readq(ips->regmap + (off)) |
232 | |
233 | #define thm_writeb(off, val) writeb((val), ips->regmap + (off)) |
234 | #define thm_writew(off, val) writew((val), ips->regmap + (off)) |
235 | #define thm_writel(off, val) writel((val), ips->regmap + (off)) |
236 | |
237 | static const int IPS_ADJUST_PERIOD = 5000; /* ms */ |
238 | static bool late_i915_load = false; |
239 | |
240 | /* For initial average collection */ |
241 | static const int IPS_SAMPLE_PERIOD = 200; /* ms */ |
242 | static const int IPS_SAMPLE_WINDOW = 5000; /* 5s moving window of samples */ |
243 | #define IPS_SAMPLE_COUNT (IPS_SAMPLE_WINDOW / IPS_SAMPLE_PERIOD) |
244 | |
245 | /* Per-SKU limits */ |
246 | struct ips_mcp_limits { |
247 | int mcp_power_limit; /* mW units */ |
248 | int core_power_limit; |
249 | int mch_power_limit; |
250 | int core_temp_limit; /* degrees C */ |
251 | int mch_temp_limit; |
252 | }; |
253 | |
254 | /* Max temps are -10 degrees C to avoid PROCHOT# */ |
255 | |
256 | static struct ips_mcp_limits ips_sv_limits = { |
257 | .mcp_power_limit = 35000, |
258 | .core_power_limit = 29000, |
259 | .mch_power_limit = 20000, |
260 | .core_temp_limit = 95, |
261 | .mch_temp_limit = 90 |
262 | }; |
263 | |
264 | static struct ips_mcp_limits ips_lv_limits = { |
265 | .mcp_power_limit = 25000, |
266 | .core_power_limit = 21000, |
267 | .mch_power_limit = 13000, |
268 | .core_temp_limit = 95, |
269 | .mch_temp_limit = 90 |
270 | }; |
271 | |
272 | static struct ips_mcp_limits ips_ulv_limits = { |
273 | .mcp_power_limit = 18000, |
274 | .core_power_limit = 14000, |
275 | .mch_power_limit = 11000, |
276 | .core_temp_limit = 95, |
277 | .mch_temp_limit = 90 |
278 | }; |
279 | |
280 | struct ips_driver { |
281 | struct device *dev; |
282 | void __iomem *regmap; |
283 | int irq; |
284 | |
285 | struct task_struct *monitor; |
286 | struct task_struct *adjust; |
287 | struct dentry *debug_root; |
288 | struct timer_list timer; |
289 | |
290 | /* Average CPU core temps (all averages in .01 degrees C for precision) */ |
291 | u16 ctv1_avg_temp; |
292 | u16 ctv2_avg_temp; |
293 | /* GMCH average */ |
294 | u16 mch_avg_temp; |
295 | /* Average for the CPU (both cores?) */ |
296 | u16 mcp_avg_temp; |
297 | /* Average power consumption (in mW) */ |
298 | u32 cpu_avg_power; |
299 | u32 mch_avg_power; |
300 | |
301 | /* Offset values */ |
302 | u16 cta_val; |
303 | u16 pta_val; |
304 | u16 mgta_val; |
305 | |
306 | /* Maximums & prefs, protected by turbo status lock */ |
307 | spinlock_t turbo_status_lock; |
308 | u16 mcp_temp_limit; |
309 | u16 mcp_power_limit; |
310 | u16 core_power_limit; |
311 | u16 mch_power_limit; |
312 | bool cpu_turbo_enabled; |
313 | bool __cpu_turbo_on; |
314 | bool gpu_turbo_enabled; |
315 | bool __gpu_turbo_on; |
316 | bool gpu_preferred; |
317 | bool poll_turbo_status; |
318 | bool second_cpu; |
319 | bool turbo_toggle_allowed; |
320 | struct ips_mcp_limits *limits; |
321 | |
322 | /* Optional MCH interfaces for if i915 is in use */ |
323 | unsigned long (*read_mch_val)(void); |
324 | bool (*gpu_raise)(void); |
325 | bool (*gpu_lower)(void); |
326 | bool (*gpu_busy)(void); |
327 | bool (*gpu_turbo_disable)(void); |
328 | |
329 | /* For restoration at unload */ |
330 | u64 orig_turbo_limit; |
331 | u64 orig_turbo_ratios; |
332 | }; |
333 | |
334 | static bool |
335 | ips_gpu_turbo_enabled(struct ips_driver *ips); |
336 | |
337 | /** |
338 | * ips_cpu_busy - is CPU busy? |
339 | * @ips: IPS driver struct |
340 | * |
341 | * Check CPU for load to see whether we should increase its thermal budget. |
342 | * |
343 | * RETURNS: |
344 | * True if the CPU could use more power, false otherwise. |
345 | */ |
346 | static bool ips_cpu_busy(struct ips_driver *ips) |
347 | { |
348 | if ((avenrun[0] >> FSHIFT) > 1) |
349 | return true; |
350 | |
351 | return false; |
352 | } |
353 | |
354 | /** |
355 | * ips_cpu_raise - raise CPU power clamp |
356 | * @ips: IPS driver struct |
357 | * |
358 | * Raise the CPU power clamp by %IPS_CPU_STEP, in accordance with TDP for |
359 | * this platform. |
360 | * |
361 | * We do this by adjusting the TURBO_POWER_CURRENT_LIMIT MSR upwards (as |
362 | * long as we haven't hit the TDP limit for the SKU). |
363 | */ |
364 | static void ips_cpu_raise(struct ips_driver *ips) |
365 | { |
366 | u64 turbo_override; |
367 | u16 cur_tdp_limit, new_tdp_limit; |
368 | |
369 | if (!ips->cpu_turbo_enabled) |
370 | return; |
371 | |
372 | rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); |
373 | |
374 | cur_tdp_limit = turbo_override & TURBO_TDP_MASK; |
375 | new_tdp_limit = cur_tdp_limit + 8; /* 1W increase */ |
376 | |
377 | /* Clamp to SKU TDP limit */ |
378 | if (((new_tdp_limit * 10) / 8) > ips->core_power_limit) |
379 | new_tdp_limit = cur_tdp_limit; |
380 | |
381 | thm_writew(THM_MPCPC, (new_tdp_limit * 10) / 8); |
382 | |
383 | turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN; |
384 | wrmsrl(TURBO_POWER_CURRENT_LIMIT, val: turbo_override); |
385 | |
386 | turbo_override &= ~TURBO_TDP_MASK; |
387 | turbo_override |= new_tdp_limit; |
388 | |
389 | wrmsrl(TURBO_POWER_CURRENT_LIMIT, val: turbo_override); |
390 | } |
391 | |
392 | /** |
393 | * ips_cpu_lower - lower CPU power clamp |
394 | * @ips: IPS driver struct |
395 | * |
396 | * Lower CPU power clamp b %IPS_CPU_STEP if possible. |
397 | * |
398 | * We do this by adjusting the TURBO_POWER_CURRENT_LIMIT MSR down, going |
399 | * as low as the platform limits will allow (though we could go lower there |
400 | * wouldn't be much point). |
401 | */ |
402 | static void ips_cpu_lower(struct ips_driver *ips) |
403 | { |
404 | u64 turbo_override; |
405 | u16 cur_limit, new_limit; |
406 | |
407 | rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); |
408 | |
409 | cur_limit = turbo_override & TURBO_TDP_MASK; |
410 | new_limit = cur_limit - 8; /* 1W decrease */ |
411 | |
412 | /* Clamp to SKU TDP limit */ |
413 | if (new_limit < (ips->orig_turbo_limit & TURBO_TDP_MASK)) |
414 | new_limit = ips->orig_turbo_limit & TURBO_TDP_MASK; |
415 | |
416 | thm_writew(THM_MPCPC, (new_limit * 10) / 8); |
417 | |
418 | turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN; |
419 | wrmsrl(TURBO_POWER_CURRENT_LIMIT, val: turbo_override); |
420 | |
421 | turbo_override &= ~TURBO_TDP_MASK; |
422 | turbo_override |= new_limit; |
423 | |
424 | wrmsrl(TURBO_POWER_CURRENT_LIMIT, val: turbo_override); |
425 | } |
426 | |
427 | /** |
428 | * do_enable_cpu_turbo - internal turbo enable function |
429 | * @data: unused |
430 | * |
431 | * Internal function for actually updating MSRs. When we enable/disable |
432 | * turbo, we need to do it on each CPU; this function is the one called |
433 | * by on_each_cpu() when needed. |
434 | */ |
435 | static void do_enable_cpu_turbo(void *data) |
436 | { |
437 | u64 perf_ctl; |
438 | |
439 | rdmsrl(IA32_PERF_CTL, perf_ctl); |
440 | if (perf_ctl & IA32_PERF_TURBO_DIS) { |
441 | perf_ctl &= ~IA32_PERF_TURBO_DIS; |
442 | wrmsrl(IA32_PERF_CTL, val: perf_ctl); |
443 | } |
444 | } |
445 | |
446 | /** |
447 | * ips_enable_cpu_turbo - enable turbo mode on all CPUs |
448 | * @ips: IPS driver struct |
449 | * |
450 | * Enable turbo mode by clearing the disable bit in IA32_PERF_CTL on |
451 | * all logical threads. |
452 | */ |
453 | static void ips_enable_cpu_turbo(struct ips_driver *ips) |
454 | { |
455 | /* Already on, no need to mess with MSRs */ |
456 | if (ips->__cpu_turbo_on) |
457 | return; |
458 | |
459 | if (ips->turbo_toggle_allowed) |
460 | on_each_cpu(func: do_enable_cpu_turbo, info: ips, wait: 1); |
461 | |
462 | ips->__cpu_turbo_on = true; |
463 | } |
464 | |
465 | /** |
466 | * do_disable_cpu_turbo - internal turbo disable function |
467 | * @data: unused |
468 | * |
469 | * Internal function for actually updating MSRs. When we enable/disable |
470 | * turbo, we need to do it on each CPU; this function is the one called |
471 | * by on_each_cpu() when needed. |
472 | */ |
473 | static void do_disable_cpu_turbo(void *data) |
474 | { |
475 | u64 perf_ctl; |
476 | |
477 | rdmsrl(IA32_PERF_CTL, perf_ctl); |
478 | if (!(perf_ctl & IA32_PERF_TURBO_DIS)) { |
479 | perf_ctl |= IA32_PERF_TURBO_DIS; |
480 | wrmsrl(IA32_PERF_CTL, val: perf_ctl); |
481 | } |
482 | } |
483 | |
484 | /** |
485 | * ips_disable_cpu_turbo - disable turbo mode on all CPUs |
486 | * @ips: IPS driver struct |
487 | * |
488 | * Disable turbo mode by setting the disable bit in IA32_PERF_CTL on |
489 | * all logical threads. |
490 | */ |
491 | static void ips_disable_cpu_turbo(struct ips_driver *ips) |
492 | { |
493 | /* Already off, leave it */ |
494 | if (!ips->__cpu_turbo_on) |
495 | return; |
496 | |
497 | if (ips->turbo_toggle_allowed) |
498 | on_each_cpu(func: do_disable_cpu_turbo, info: ips, wait: 1); |
499 | |
500 | ips->__cpu_turbo_on = false; |
501 | } |
502 | |
503 | /** |
504 | * ips_gpu_busy - is GPU busy? |
505 | * @ips: IPS driver struct |
506 | * |
507 | * Check GPU for load to see whether we should increase its thermal budget. |
508 | * We need to call into the i915 driver in this case. |
509 | * |
510 | * RETURNS: |
511 | * True if the GPU could use more power, false otherwise. |
512 | */ |
513 | static bool ips_gpu_busy(struct ips_driver *ips) |
514 | { |
515 | if (!ips_gpu_turbo_enabled(ips)) |
516 | return false; |
517 | |
518 | return ips->gpu_busy(); |
519 | } |
520 | |
521 | /** |
522 | * ips_gpu_raise - raise GPU power clamp |
523 | * @ips: IPS driver struct |
524 | * |
525 | * Raise the GPU frequency/power if possible. We need to call into the |
526 | * i915 driver in this case. |
527 | */ |
528 | static void ips_gpu_raise(struct ips_driver *ips) |
529 | { |
530 | if (!ips_gpu_turbo_enabled(ips)) |
531 | return; |
532 | |
533 | if (!ips->gpu_raise()) |
534 | ips->gpu_turbo_enabled = false; |
535 | |
536 | return; |
537 | } |
538 | |
539 | /** |
540 | * ips_gpu_lower - lower GPU power clamp |
541 | * @ips: IPS driver struct |
542 | * |
543 | * Lower GPU frequency/power if possible. Need to call i915. |
544 | */ |
545 | static void ips_gpu_lower(struct ips_driver *ips) |
546 | { |
547 | if (!ips_gpu_turbo_enabled(ips)) |
548 | return; |
549 | |
550 | if (!ips->gpu_lower()) |
551 | ips->gpu_turbo_enabled = false; |
552 | |
553 | return; |
554 | } |
555 | |
556 | /** |
557 | * ips_enable_gpu_turbo - notify the gfx driver turbo is available |
558 | * @ips: IPS driver struct |
559 | * |
560 | * Call into the graphics driver indicating that it can safely use |
561 | * turbo mode. |
562 | */ |
563 | static void ips_enable_gpu_turbo(struct ips_driver *ips) |
564 | { |
565 | if (ips->__gpu_turbo_on) |
566 | return; |
567 | ips->__gpu_turbo_on = true; |
568 | } |
569 | |
570 | /** |
571 | * ips_disable_gpu_turbo - notify the gfx driver to disable turbo mode |
572 | * @ips: IPS driver struct |
573 | * |
574 | * Request that the graphics driver disable turbo mode. |
575 | */ |
576 | static void ips_disable_gpu_turbo(struct ips_driver *ips) |
577 | { |
578 | /* Avoid calling i915 if turbo is already disabled */ |
579 | if (!ips->__gpu_turbo_on) |
580 | return; |
581 | |
582 | if (!ips->gpu_turbo_disable()) |
583 | dev_err(ips->dev, "failed to disable graphics turbo\n" ); |
584 | else |
585 | ips->__gpu_turbo_on = false; |
586 | } |
587 | |
588 | /** |
589 | * mcp_exceeded - check whether we're outside our thermal & power limits |
590 | * @ips: IPS driver struct |
591 | * |
592 | * Check whether the MCP is over its thermal or power budget. |
593 | * |
594 | * Returns: %true if the temp or power has exceeded its maximum, else %false |
595 | */ |
596 | static bool mcp_exceeded(struct ips_driver *ips) |
597 | { |
598 | unsigned long flags; |
599 | bool ret = false; |
600 | u32 temp_limit; |
601 | u32 avg_power; |
602 | |
603 | spin_lock_irqsave(&ips->turbo_status_lock, flags); |
604 | |
605 | temp_limit = ips->mcp_temp_limit * 100; |
606 | if (ips->mcp_avg_temp > temp_limit) |
607 | ret = true; |
608 | |
609 | avg_power = ips->cpu_avg_power + ips->mch_avg_power; |
610 | if (avg_power > ips->mcp_power_limit) |
611 | ret = true; |
612 | |
613 | spin_unlock_irqrestore(lock: &ips->turbo_status_lock, flags); |
614 | |
615 | return ret; |
616 | } |
617 | |
618 | /** |
619 | * cpu_exceeded - check whether a CPU core is outside its limits |
620 | * @ips: IPS driver struct |
621 | * @cpu: CPU number to check |
622 | * |
623 | * Check a given CPU's average temp or power is over its limit. |
624 | * |
625 | * Returns: %true if the temp or power has exceeded its maximum, else %false |
626 | */ |
627 | static bool cpu_exceeded(struct ips_driver *ips, int cpu) |
628 | { |
629 | unsigned long flags; |
630 | int avg; |
631 | bool ret = false; |
632 | |
633 | spin_lock_irqsave(&ips->turbo_status_lock, flags); |
634 | avg = cpu ? ips->ctv2_avg_temp : ips->ctv1_avg_temp; |
635 | if (avg > (ips->limits->core_temp_limit * 100)) |
636 | ret = true; |
637 | if (ips->cpu_avg_power > ips->core_power_limit * 100) |
638 | ret = true; |
639 | spin_unlock_irqrestore(lock: &ips->turbo_status_lock, flags); |
640 | |
641 | if (ret) |
642 | dev_info(ips->dev, "CPU power or thermal limit exceeded\n" ); |
643 | |
644 | return ret; |
645 | } |
646 | |
647 | /** |
648 | * mch_exceeded - check whether the GPU is over budget |
649 | * @ips: IPS driver struct |
650 | * |
651 | * Check the MCH temp & power against their maximums. |
652 | * |
653 | * Returns: %true if the temp or power has exceeded its maximum, else %false |
654 | */ |
655 | static bool mch_exceeded(struct ips_driver *ips) |
656 | { |
657 | unsigned long flags; |
658 | bool ret = false; |
659 | |
660 | spin_lock_irqsave(&ips->turbo_status_lock, flags); |
661 | if (ips->mch_avg_temp > (ips->limits->mch_temp_limit * 100)) |
662 | ret = true; |
663 | if (ips->mch_avg_power > ips->mch_power_limit) |
664 | ret = true; |
665 | spin_unlock_irqrestore(lock: &ips->turbo_status_lock, flags); |
666 | |
667 | return ret; |
668 | } |
669 | |
670 | /** |
671 | * verify_limits - verify BIOS provided limits |
672 | * @ips: IPS structure |
673 | * |
674 | * BIOS can optionally provide non-default limits for power and temp. Check |
675 | * them here and use the defaults if the BIOS values are not provided or |
676 | * are otherwise unusable. |
677 | */ |
678 | static void verify_limits(struct ips_driver *ips) |
679 | { |
680 | if (ips->mcp_power_limit < ips->limits->mcp_power_limit || |
681 | ips->mcp_power_limit > 35000) |
682 | ips->mcp_power_limit = ips->limits->mcp_power_limit; |
683 | |
684 | if (ips->mcp_temp_limit < ips->limits->core_temp_limit || |
685 | ips->mcp_temp_limit < ips->limits->mch_temp_limit || |
686 | ips->mcp_temp_limit > 150) |
687 | ips->mcp_temp_limit = min(ips->limits->core_temp_limit, |
688 | ips->limits->mch_temp_limit); |
689 | } |
690 | |
691 | /** |
692 | * update_turbo_limits - get various limits & settings from regs |
693 | * @ips: IPS driver struct |
694 | * |
695 | * Update the IPS power & temp limits, along with turbo enable flags, |
696 | * based on latest register contents. |
697 | * |
698 | * Used at init time and for runtime BIOS support, which requires polling |
699 | * the regs for updates (as a result of AC->DC transition for example). |
700 | * |
701 | * LOCKING: |
702 | * Caller must hold turbo_status_lock (outside of init) |
703 | */ |
704 | static void update_turbo_limits(struct ips_driver *ips) |
705 | { |
706 | u32 hts = thm_readl(THM_HTS); |
707 | |
708 | ips->cpu_turbo_enabled = !(hts & HTS_PCTD_DIS); |
709 | /* |
710 | * Disable turbo for now, until we can figure out why the power figures |
711 | * are wrong |
712 | */ |
713 | ips->cpu_turbo_enabled = false; |
714 | |
715 | if (ips->gpu_busy) |
716 | ips->gpu_turbo_enabled = !(hts & HTS_GTD_DIS); |
717 | |
718 | ips->core_power_limit = thm_readw(THM_MPCPC); |
719 | ips->mch_power_limit = thm_readw(THM_MMGPC); |
720 | ips->mcp_temp_limit = thm_readw(THM_PTL); |
721 | ips->mcp_power_limit = thm_readw(THM_MPPC); |
722 | |
723 | verify_limits(ips); |
724 | /* Ignore BIOS CPU vs GPU pref */ |
725 | } |
726 | |
727 | /** |
728 | * ips_adjust - adjust power clamp based on thermal state |
729 | * @data: ips driver structure |
730 | * |
731 | * Wake up every 5s or so and check whether we should adjust the power clamp. |
732 | * Check CPU and GPU load to determine which needs adjustment. There are |
733 | * several things to consider here: |
734 | * - do we need to adjust up or down? |
735 | * - is CPU busy? |
736 | * - is GPU busy? |
737 | * - is CPU in turbo? |
738 | * - is GPU in turbo? |
739 | * - is CPU or GPU preferred? (CPU is default) |
740 | * |
741 | * So, given the above, we do the following: |
742 | * - up (TDP available) |
743 | * - CPU not busy, GPU not busy - nothing |
744 | * - CPU busy, GPU not busy - adjust CPU up |
745 | * - CPU not busy, GPU busy - adjust GPU up |
746 | * - CPU busy, GPU busy - adjust preferred unit up, taking headroom from |
747 | * non-preferred unit if necessary |
748 | * - down (at TDP limit) |
749 | * - adjust both CPU and GPU down if possible |
750 | * |
751 | * |cpu+ gpu+ cpu+gpu- cpu-gpu+ cpu-gpu- |
752 | * cpu < gpu < |cpu+gpu+ cpu+ gpu+ nothing |
753 | * cpu < gpu >= |cpu+gpu-(mcp<) cpu+gpu-(mcp<) gpu- gpu- |
754 | * cpu >= gpu < |cpu-gpu+(mcp<) cpu- cpu-gpu+(mcp<) cpu- |
755 | * cpu >= gpu >=|cpu-gpu- cpu-gpu- cpu-gpu- cpu-gpu- |
756 | * |
757 | * Returns: %0 |
758 | */ |
759 | static int ips_adjust(void *data) |
760 | { |
761 | struct ips_driver *ips = data; |
762 | unsigned long flags; |
763 | |
764 | dev_dbg(ips->dev, "starting ips-adjust thread\n" ); |
765 | |
766 | /* |
767 | * Adjust CPU and GPU clamps every 5s if needed. Doing it more |
768 | * often isn't recommended due to ME interaction. |
769 | */ |
770 | do { |
771 | bool cpu_busy = ips_cpu_busy(ips); |
772 | bool gpu_busy = ips_gpu_busy(ips); |
773 | |
774 | spin_lock_irqsave(&ips->turbo_status_lock, flags); |
775 | if (ips->poll_turbo_status) |
776 | update_turbo_limits(ips); |
777 | spin_unlock_irqrestore(lock: &ips->turbo_status_lock, flags); |
778 | |
779 | /* Update turbo status if necessary */ |
780 | if (ips->cpu_turbo_enabled) |
781 | ips_enable_cpu_turbo(ips); |
782 | else |
783 | ips_disable_cpu_turbo(ips); |
784 | |
785 | if (ips->gpu_turbo_enabled) |
786 | ips_enable_gpu_turbo(ips); |
787 | else |
788 | ips_disable_gpu_turbo(ips); |
789 | |
790 | /* We're outside our comfort zone, crank them down */ |
791 | if (mcp_exceeded(ips)) { |
792 | ips_cpu_lower(ips); |
793 | ips_gpu_lower(ips); |
794 | goto sleep; |
795 | } |
796 | |
797 | if (!cpu_exceeded(ips, cpu: 0) && cpu_busy) |
798 | ips_cpu_raise(ips); |
799 | else |
800 | ips_cpu_lower(ips); |
801 | |
802 | if (!mch_exceeded(ips) && gpu_busy) |
803 | ips_gpu_raise(ips); |
804 | else |
805 | ips_gpu_lower(ips); |
806 | |
807 | sleep: |
808 | schedule_timeout_interruptible(timeout: msecs_to_jiffies(m: IPS_ADJUST_PERIOD)); |
809 | } while (!kthread_should_stop()); |
810 | |
811 | dev_dbg(ips->dev, "ips-adjust thread stopped\n" ); |
812 | |
813 | return 0; |
814 | } |
815 | |
816 | /* |
817 | * Helpers for reading out temp/power values and calculating their |
818 | * averages for the decision making and monitoring functions. |
819 | */ |
820 | |
821 | static u16 calc_avg_temp(struct ips_driver *ips, u16 *array) |
822 | { |
823 | u64 total = 0; |
824 | int i; |
825 | u16 avg; |
826 | |
827 | for (i = 0; i < IPS_SAMPLE_COUNT; i++) |
828 | total += (u64)(array[i] * 100); |
829 | |
830 | do_div(total, IPS_SAMPLE_COUNT); |
831 | |
832 | avg = (u16)total; |
833 | |
834 | return avg; |
835 | } |
836 | |
837 | static u16 read_mgtv(struct ips_driver *ips) |
838 | { |
839 | u16 __maybe_unused ret; |
840 | u64 slope, offset; |
841 | u64 val; |
842 | |
843 | val = thm_readq(THM_MGTV); |
844 | val = (val & TV_MASK) >> TV_SHIFT; |
845 | |
846 | slope = offset = thm_readw(THM_MGTA); |
847 | slope = (slope & MGTA_SLOPE_MASK) >> MGTA_SLOPE_SHIFT; |
848 | offset = offset & MGTA_OFFSET_MASK; |
849 | |
850 | ret = ((val * slope + 0x40) >> 7) + offset; |
851 | |
852 | return 0; /* MCH temp reporting buggy */ |
853 | } |
854 | |
855 | static u16 read_ptv(struct ips_driver *ips) |
856 | { |
857 | u16 val; |
858 | |
859 | val = thm_readw(THM_PTV) & PTV_MASK; |
860 | |
861 | return val; |
862 | } |
863 | |
864 | static u16 read_ctv(struct ips_driver *ips, int cpu) |
865 | { |
866 | int reg = cpu ? THM_CTV2 : THM_CTV1; |
867 | u16 val; |
868 | |
869 | val = thm_readw(reg); |
870 | if (!(val & CTV_TEMP_ERROR)) |
871 | val = (val) >> 6; /* discard fractional component */ |
872 | else |
873 | val = 0; |
874 | |
875 | return val; |
876 | } |
877 | |
878 | static u32 get_cpu_power(struct ips_driver *ips, u32 *last, int period) |
879 | { |
880 | u32 val; |
881 | u32 ret; |
882 | |
883 | /* |
884 | * CEC is in joules/65535. Take difference over time to |
885 | * get watts. |
886 | */ |
887 | val = thm_readl(THM_CEC); |
888 | |
889 | /* period is in ms and we want mW */ |
890 | ret = (((val - *last) * 1000) / period); |
891 | ret = (ret * 1000) / 65535; |
892 | *last = val; |
893 | |
894 | return 0; |
895 | } |
896 | |
897 | static const u16 temp_decay_factor = 2; |
898 | static u16 update_average_temp(u16 avg, u16 val) |
899 | { |
900 | u16 ret; |
901 | |
902 | /* Multiply by 100 for extra precision */ |
903 | ret = (val * 100 / temp_decay_factor) + |
904 | (((temp_decay_factor - 1) * avg) / temp_decay_factor); |
905 | return ret; |
906 | } |
907 | |
908 | static const u16 power_decay_factor = 2; |
909 | static u16 update_average_power(u32 avg, u32 val) |
910 | { |
911 | u32 ret; |
912 | |
913 | ret = (val / power_decay_factor) + |
914 | (((power_decay_factor - 1) * avg) / power_decay_factor); |
915 | |
916 | return ret; |
917 | } |
918 | |
919 | static u32 calc_avg_power(struct ips_driver *ips, u32 *array) |
920 | { |
921 | u64 total = 0; |
922 | u32 avg; |
923 | int i; |
924 | |
925 | for (i = 0; i < IPS_SAMPLE_COUNT; i++) |
926 | total += array[i]; |
927 | |
928 | do_div(total, IPS_SAMPLE_COUNT); |
929 | avg = (u32)total; |
930 | |
931 | return avg; |
932 | } |
933 | |
934 | static void monitor_timeout(struct timer_list *t) |
935 | { |
936 | struct ips_driver *ips = from_timer(ips, t, timer); |
937 | wake_up_process(tsk: ips->monitor); |
938 | } |
939 | |
940 | /** |
941 | * ips_monitor - temp/power monitoring thread |
942 | * @data: ips driver structure |
943 | * |
944 | * This is the main function for the IPS driver. It monitors power and |
945 | * temperature in the MCP and adjusts CPU and GPU power clamps accordingly. |
946 | * |
947 | * We keep a 5s moving average of power consumption and temperature. Using |
948 | * that data, along with CPU vs GPU preference, we adjust the power clamps |
949 | * up or down. |
950 | * |
951 | * Returns: %0 on success or -errno on error |
952 | */ |
953 | static int ips_monitor(void *data) |
954 | { |
955 | struct ips_driver *ips = data; |
956 | unsigned long seqno_timestamp, expire, last_msecs, last_sample_period; |
957 | int i; |
958 | u32 *cpu_samples, *mchp_samples, old_cpu_power; |
959 | u16 *mcp_samples, *ctv1_samples, *ctv2_samples, *mch_samples; |
960 | u8 cur_seqno, last_seqno; |
961 | |
962 | mcp_samples = kcalloc(IPS_SAMPLE_COUNT, size: sizeof(u16), GFP_KERNEL); |
963 | ctv1_samples = kcalloc(IPS_SAMPLE_COUNT, size: sizeof(u16), GFP_KERNEL); |
964 | ctv2_samples = kcalloc(IPS_SAMPLE_COUNT, size: sizeof(u16), GFP_KERNEL); |
965 | mch_samples = kcalloc(IPS_SAMPLE_COUNT, size: sizeof(u16), GFP_KERNEL); |
966 | cpu_samples = kcalloc(IPS_SAMPLE_COUNT, size: sizeof(u32), GFP_KERNEL); |
967 | mchp_samples = kcalloc(IPS_SAMPLE_COUNT, size: sizeof(u32), GFP_KERNEL); |
968 | if (!mcp_samples || !ctv1_samples || !ctv2_samples || !mch_samples || |
969 | !cpu_samples || !mchp_samples) { |
970 | dev_err(ips->dev, |
971 | "failed to allocate sample array, ips disabled\n" ); |
972 | kfree(objp: mcp_samples); |
973 | kfree(objp: ctv1_samples); |
974 | kfree(objp: ctv2_samples); |
975 | kfree(objp: mch_samples); |
976 | kfree(objp: cpu_samples); |
977 | kfree(objp: mchp_samples); |
978 | return -ENOMEM; |
979 | } |
980 | |
981 | last_seqno = (thm_readl(THM_ITV) & ITV_ME_SEQNO_MASK) >> |
982 | ITV_ME_SEQNO_SHIFT; |
983 | seqno_timestamp = get_jiffies_64(); |
984 | |
985 | old_cpu_power = thm_readl(THM_CEC); |
986 | schedule_timeout_interruptible(timeout: msecs_to_jiffies(m: IPS_SAMPLE_PERIOD)); |
987 | |
988 | /* Collect an initial average */ |
989 | for (i = 0; i < IPS_SAMPLE_COUNT; i++) { |
990 | u32 mchp, cpu_power; |
991 | u16 val; |
992 | |
993 | mcp_samples[i] = read_ptv(ips); |
994 | |
995 | val = read_ctv(ips, cpu: 0); |
996 | ctv1_samples[i] = val; |
997 | |
998 | val = read_ctv(ips, cpu: 1); |
999 | ctv2_samples[i] = val; |
1000 | |
1001 | val = read_mgtv(ips); |
1002 | mch_samples[i] = val; |
1003 | |
1004 | cpu_power = get_cpu_power(ips, last: &old_cpu_power, |
1005 | period: IPS_SAMPLE_PERIOD); |
1006 | cpu_samples[i] = cpu_power; |
1007 | |
1008 | if (ips->read_mch_val) { |
1009 | mchp = ips->read_mch_val(); |
1010 | mchp_samples[i] = mchp; |
1011 | } |
1012 | |
1013 | schedule_timeout_interruptible(timeout: msecs_to_jiffies(m: IPS_SAMPLE_PERIOD)); |
1014 | if (kthread_should_stop()) |
1015 | break; |
1016 | } |
1017 | |
1018 | ips->mcp_avg_temp = calc_avg_temp(ips, array: mcp_samples); |
1019 | ips->ctv1_avg_temp = calc_avg_temp(ips, array: ctv1_samples); |
1020 | ips->ctv2_avg_temp = calc_avg_temp(ips, array: ctv2_samples); |
1021 | ips->mch_avg_temp = calc_avg_temp(ips, array: mch_samples); |
1022 | ips->cpu_avg_power = calc_avg_power(ips, array: cpu_samples); |
1023 | ips->mch_avg_power = calc_avg_power(ips, array: mchp_samples); |
1024 | kfree(objp: mcp_samples); |
1025 | kfree(objp: ctv1_samples); |
1026 | kfree(objp: ctv2_samples); |
1027 | kfree(objp: mch_samples); |
1028 | kfree(objp: cpu_samples); |
1029 | kfree(objp: mchp_samples); |
1030 | |
1031 | /* Start the adjustment thread now that we have data */ |
1032 | wake_up_process(tsk: ips->adjust); |
1033 | |
1034 | /* |
1035 | * Ok, now we have an initial avg. From here on out, we track the |
1036 | * running avg using a decaying average calculation. This allows |
1037 | * us to reduce the sample frequency if the CPU and GPU are idle. |
1038 | */ |
1039 | old_cpu_power = thm_readl(THM_CEC); |
1040 | schedule_timeout_interruptible(timeout: msecs_to_jiffies(m: IPS_SAMPLE_PERIOD)); |
1041 | last_sample_period = IPS_SAMPLE_PERIOD; |
1042 | |
1043 | timer_setup(&ips->timer, monitor_timeout, TIMER_DEFERRABLE); |
1044 | do { |
1045 | u32 cpu_val, mch_val; |
1046 | u16 val; |
1047 | |
1048 | /* MCP itself */ |
1049 | val = read_ptv(ips); |
1050 | ips->mcp_avg_temp = update_average_temp(avg: ips->mcp_avg_temp, val); |
1051 | |
1052 | /* Processor 0 */ |
1053 | val = read_ctv(ips, cpu: 0); |
1054 | ips->ctv1_avg_temp = |
1055 | update_average_temp(avg: ips->ctv1_avg_temp, val); |
1056 | /* Power */ |
1057 | cpu_val = get_cpu_power(ips, last: &old_cpu_power, |
1058 | period: last_sample_period); |
1059 | ips->cpu_avg_power = |
1060 | update_average_power(avg: ips->cpu_avg_power, val: cpu_val); |
1061 | |
1062 | if (ips->second_cpu) { |
1063 | /* Processor 1 */ |
1064 | val = read_ctv(ips, cpu: 1); |
1065 | ips->ctv2_avg_temp = |
1066 | update_average_temp(avg: ips->ctv2_avg_temp, val); |
1067 | } |
1068 | |
1069 | /* MCH */ |
1070 | val = read_mgtv(ips); |
1071 | ips->mch_avg_temp = update_average_temp(avg: ips->mch_avg_temp, val); |
1072 | /* Power */ |
1073 | if (ips->read_mch_val) { |
1074 | mch_val = ips->read_mch_val(); |
1075 | ips->mch_avg_power = |
1076 | update_average_power(avg: ips->mch_avg_power, |
1077 | val: mch_val); |
1078 | } |
1079 | |
1080 | /* |
1081 | * Make sure ME is updating thermal regs. |
1082 | * Note: |
1083 | * If it's been more than a second since the last update, |
1084 | * the ME is probably hung. |
1085 | */ |
1086 | cur_seqno = (thm_readl(THM_ITV) & ITV_ME_SEQNO_MASK) >> |
1087 | ITV_ME_SEQNO_SHIFT; |
1088 | if (cur_seqno == last_seqno && |
1089 | time_after(jiffies, seqno_timestamp + HZ)) { |
1090 | dev_warn(ips->dev, |
1091 | "ME failed to update for more than 1s, likely hung\n" ); |
1092 | } else { |
1093 | seqno_timestamp = get_jiffies_64(); |
1094 | last_seqno = cur_seqno; |
1095 | } |
1096 | |
1097 | last_msecs = jiffies_to_msecs(j: jiffies); |
1098 | expire = jiffies + msecs_to_jiffies(m: IPS_SAMPLE_PERIOD); |
1099 | |
1100 | __set_current_state(TASK_INTERRUPTIBLE); |
1101 | mod_timer(timer: &ips->timer, expires: expire); |
1102 | schedule(); |
1103 | |
1104 | /* Calculate actual sample period for power averaging */ |
1105 | last_sample_period = jiffies_to_msecs(j: jiffies) - last_msecs; |
1106 | if (!last_sample_period) |
1107 | last_sample_period = 1; |
1108 | } while (!kthread_should_stop()); |
1109 | |
1110 | del_timer_sync(timer: &ips->timer); |
1111 | |
1112 | dev_dbg(ips->dev, "ips-monitor thread stopped\n" ); |
1113 | |
1114 | return 0; |
1115 | } |
1116 | |
1117 | /** |
1118 | * ips_irq_handler - handle temperature triggers and other IPS events |
1119 | * @irq: irq number |
1120 | * @arg: unused |
1121 | * |
1122 | * Handle temperature limit trigger events, generally by lowering the clamps. |
1123 | * If we're at a critical limit, we clamp back to the lowest possible value |
1124 | * to prevent emergency shutdown. |
1125 | * |
1126 | * Returns: IRQ_NONE or IRQ_HANDLED |
1127 | */ |
1128 | static irqreturn_t ips_irq_handler(int irq, void *arg) |
1129 | { |
1130 | struct ips_driver *ips = arg; |
1131 | u8 tses = thm_readb(THM_TSES); |
1132 | u8 tes = thm_readb(THM_TES); |
1133 | |
1134 | if (!tses && !tes) |
1135 | return IRQ_NONE; |
1136 | |
1137 | dev_info(ips->dev, "TSES: 0x%02x\n" , tses); |
1138 | dev_info(ips->dev, "TES: 0x%02x\n" , tes); |
1139 | |
1140 | /* STS update from EC? */ |
1141 | if (tes & 1) { |
1142 | u32 sts, tc1; |
1143 | |
1144 | sts = thm_readl(THM_STS); |
1145 | tc1 = thm_readl(THM_TC1); |
1146 | |
1147 | if (sts & STS_NVV) { |
1148 | spin_lock(lock: &ips->turbo_status_lock); |
1149 | ips->core_power_limit = (sts & STS_PCPL_MASK) >> |
1150 | STS_PCPL_SHIFT; |
1151 | ips->mch_power_limit = (sts & STS_GPL_MASK) >> |
1152 | STS_GPL_SHIFT; |
1153 | /* ignore EC CPU vs GPU pref */ |
1154 | ips->cpu_turbo_enabled = !(sts & STS_PCTD_DIS); |
1155 | /* |
1156 | * Disable turbo for now, until we can figure |
1157 | * out why the power figures are wrong |
1158 | */ |
1159 | ips->cpu_turbo_enabled = false; |
1160 | if (ips->gpu_busy) |
1161 | ips->gpu_turbo_enabled = !(sts & STS_GTD_DIS); |
1162 | ips->mcp_temp_limit = (sts & STS_PTL_MASK) >> |
1163 | STS_PTL_SHIFT; |
1164 | ips->mcp_power_limit = (tc1 & STS_PPL_MASK) >> |
1165 | STS_PPL_SHIFT; |
1166 | verify_limits(ips); |
1167 | spin_unlock(lock: &ips->turbo_status_lock); |
1168 | |
1169 | thm_writeb(THM_SEC, SEC_ACK); |
1170 | } |
1171 | thm_writeb(THM_TES, tes); |
1172 | } |
1173 | |
1174 | /* Thermal trip */ |
1175 | if (tses) { |
1176 | dev_warn(ips->dev, "thermal trip occurred, tses: 0x%04x\n" , |
1177 | tses); |
1178 | thm_writeb(THM_TSES, tses); |
1179 | } |
1180 | |
1181 | return IRQ_HANDLED; |
1182 | } |
1183 | |
1184 | #ifndef CONFIG_DEBUG_FS |
1185 | static void ips_debugfs_init(struct ips_driver *ips) { return; } |
1186 | static void ips_debugfs_cleanup(struct ips_driver *ips) { return; } |
1187 | #else |
1188 | |
1189 | /* Expose current state and limits in debugfs if possible */ |
1190 | |
1191 | static int cpu_temp_show(struct seq_file *m, void *data) |
1192 | { |
1193 | struct ips_driver *ips = m->private; |
1194 | |
1195 | seq_printf(m, fmt: "%d.%02d\n" , ips->ctv1_avg_temp / 100, |
1196 | ips->ctv1_avg_temp % 100); |
1197 | |
1198 | return 0; |
1199 | } |
1200 | DEFINE_SHOW_ATTRIBUTE(cpu_temp); |
1201 | |
1202 | static int cpu_power_show(struct seq_file *m, void *data) |
1203 | { |
1204 | struct ips_driver *ips = m->private; |
1205 | |
1206 | seq_printf(m, fmt: "%dmW\n" , ips->cpu_avg_power); |
1207 | |
1208 | return 0; |
1209 | } |
1210 | DEFINE_SHOW_ATTRIBUTE(cpu_power); |
1211 | |
1212 | static int cpu_clamp_show(struct seq_file *m, void *data) |
1213 | { |
1214 | u64 turbo_override; |
1215 | int tdp, tdc; |
1216 | |
1217 | rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); |
1218 | |
1219 | tdp = (int)(turbo_override & TURBO_TDP_MASK); |
1220 | tdc = (int)((turbo_override & TURBO_TDC_MASK) >> TURBO_TDC_SHIFT); |
1221 | |
1222 | /* Convert to .1W/A units */ |
1223 | tdp = tdp * 10 / 8; |
1224 | tdc = tdc * 10 / 8; |
1225 | |
1226 | /* Watts Amperes */ |
1227 | seq_printf(m, fmt: "%d.%dW %d.%dA\n" , tdp / 10, tdp % 10, |
1228 | tdc / 10, tdc % 10); |
1229 | |
1230 | return 0; |
1231 | } |
1232 | DEFINE_SHOW_ATTRIBUTE(cpu_clamp); |
1233 | |
1234 | static int mch_temp_show(struct seq_file *m, void *data) |
1235 | { |
1236 | struct ips_driver *ips = m->private; |
1237 | |
1238 | seq_printf(m, fmt: "%d.%02d\n" , ips->mch_avg_temp / 100, |
1239 | ips->mch_avg_temp % 100); |
1240 | |
1241 | return 0; |
1242 | } |
1243 | DEFINE_SHOW_ATTRIBUTE(mch_temp); |
1244 | |
1245 | static int mch_power_show(struct seq_file *m, void *data) |
1246 | { |
1247 | struct ips_driver *ips = m->private; |
1248 | |
1249 | seq_printf(m, fmt: "%dmW\n" , ips->mch_avg_power); |
1250 | |
1251 | return 0; |
1252 | } |
1253 | DEFINE_SHOW_ATTRIBUTE(mch_power); |
1254 | |
1255 | static void ips_debugfs_cleanup(struct ips_driver *ips) |
1256 | { |
1257 | debugfs_remove_recursive(dentry: ips->debug_root); |
1258 | } |
1259 | |
1260 | static void ips_debugfs_init(struct ips_driver *ips) |
1261 | { |
1262 | ips->debug_root = debugfs_create_dir(name: "ips" , NULL); |
1263 | |
1264 | debugfs_create_file(name: "cpu_temp" , mode: 0444, parent: ips->debug_root, data: ips, fops: &cpu_temp_fops); |
1265 | debugfs_create_file(name: "cpu_power" , mode: 0444, parent: ips->debug_root, data: ips, fops: &cpu_power_fops); |
1266 | debugfs_create_file(name: "cpu_clamp" , mode: 0444, parent: ips->debug_root, data: ips, fops: &cpu_clamp_fops); |
1267 | debugfs_create_file(name: "mch_temp" , mode: 0444, parent: ips->debug_root, data: ips, fops: &mch_temp_fops); |
1268 | debugfs_create_file(name: "mch_power" , mode: 0444, parent: ips->debug_root, data: ips, fops: &mch_power_fops); |
1269 | } |
1270 | #endif /* CONFIG_DEBUG_FS */ |
1271 | |
1272 | /** |
1273 | * ips_detect_cpu - detect whether CPU supports IPS |
1274 | * @ips: IPS driver struct |
1275 | * |
1276 | * Walk our list and see if we're on a supported CPU. If we find one, |
1277 | * return the limits for it. |
1278 | * |
1279 | * Returns: the &ips_mcp_limits struct that matches the boot CPU or %NULL |
1280 | */ |
1281 | static struct ips_mcp_limits *ips_detect_cpu(struct ips_driver *ips) |
1282 | { |
1283 | u64 turbo_power, misc_en; |
1284 | struct ips_mcp_limits *limits = NULL; |
1285 | u16 tdp; |
1286 | |
1287 | if (!(boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 37)) { |
1288 | dev_info(ips->dev, "Non-IPS CPU detected.\n" ); |
1289 | return NULL; |
1290 | } |
1291 | |
1292 | rdmsrl(IA32_MISC_ENABLE, misc_en); |
1293 | /* |
1294 | * If the turbo enable bit isn't set, we shouldn't try to enable/disable |
1295 | * turbo manually or we'll get an illegal MSR access, even though |
1296 | * turbo will still be available. |
1297 | */ |
1298 | if (misc_en & IA32_MISC_TURBO_EN) |
1299 | ips->turbo_toggle_allowed = true; |
1300 | else |
1301 | ips->turbo_toggle_allowed = false; |
1302 | |
1303 | if (strstr(boot_cpu_data.x86_model_id, "CPU M" )) |
1304 | limits = &ips_sv_limits; |
1305 | else if (strstr(boot_cpu_data.x86_model_id, "CPU L" )) |
1306 | limits = &ips_lv_limits; |
1307 | else if (strstr(boot_cpu_data.x86_model_id, "CPU U" )) |
1308 | limits = &ips_ulv_limits; |
1309 | else { |
1310 | dev_info(ips->dev, "No CPUID match found.\n" ); |
1311 | return NULL; |
1312 | } |
1313 | |
1314 | rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_power); |
1315 | tdp = turbo_power & TURBO_TDP_MASK; |
1316 | |
1317 | /* Sanity check TDP against CPU */ |
1318 | if (limits->core_power_limit != (tdp / 8) * 1000) { |
1319 | dev_info(ips->dev, |
1320 | "CPU TDP doesn't match expected value (found %d, expected %d)\n" , |
1321 | tdp / 8, limits->core_power_limit / 1000); |
1322 | limits->core_power_limit = (tdp / 8) * 1000; |
1323 | } |
1324 | |
1325 | return limits; |
1326 | } |
1327 | |
1328 | /** |
1329 | * ips_get_i915_syms - try to get GPU control methods from i915 driver |
1330 | * @ips: IPS driver |
1331 | * |
1332 | * The i915 driver exports several interfaces to allow the IPS driver to |
1333 | * monitor and control graphics turbo mode. If we can find them, we can |
1334 | * enable graphics turbo, otherwise we must disable it to avoid exceeding |
1335 | * thermal and power limits in the MCP. |
1336 | * |
1337 | * Returns: %true if the required symbols are found, else %false |
1338 | */ |
1339 | static bool ips_get_i915_syms(struct ips_driver *ips) |
1340 | { |
1341 | ips->read_mch_val = symbol_get(i915_read_mch_val); |
1342 | if (!ips->read_mch_val) |
1343 | goto out_err; |
1344 | ips->gpu_raise = symbol_get(i915_gpu_raise); |
1345 | if (!ips->gpu_raise) |
1346 | goto out_put_mch; |
1347 | ips->gpu_lower = symbol_get(i915_gpu_lower); |
1348 | if (!ips->gpu_lower) |
1349 | goto out_put_raise; |
1350 | ips->gpu_busy = symbol_get(i915_gpu_busy); |
1351 | if (!ips->gpu_busy) |
1352 | goto out_put_lower; |
1353 | ips->gpu_turbo_disable = symbol_get(i915_gpu_turbo_disable); |
1354 | if (!ips->gpu_turbo_disable) |
1355 | goto out_put_busy; |
1356 | |
1357 | return true; |
1358 | |
1359 | out_put_busy: |
1360 | symbol_put(i915_gpu_busy); |
1361 | out_put_lower: |
1362 | symbol_put(i915_gpu_lower); |
1363 | out_put_raise: |
1364 | symbol_put(i915_gpu_raise); |
1365 | out_put_mch: |
1366 | symbol_put(i915_read_mch_val); |
1367 | out_err: |
1368 | return false; |
1369 | } |
1370 | |
1371 | static bool |
1372 | ips_gpu_turbo_enabled(struct ips_driver *ips) |
1373 | { |
1374 | if (!ips->gpu_busy && late_i915_load) { |
1375 | if (ips_get_i915_syms(ips)) { |
1376 | dev_info(ips->dev, |
1377 | "i915 driver attached, reenabling gpu turbo\n" ); |
1378 | ips->gpu_turbo_enabled = !(thm_readl(THM_HTS) & HTS_GTD_DIS); |
1379 | } |
1380 | } |
1381 | |
1382 | return ips->gpu_turbo_enabled; |
1383 | } |
1384 | |
1385 | void |
1386 | ips_link_to_i915_driver(void) |
1387 | { |
1388 | /* We can't cleanly get at the various ips_driver structs from |
1389 | * this caller (the i915 driver), so just set a flag saying |
1390 | * that it's time to try getting the symbols again. |
1391 | */ |
1392 | late_i915_load = true; |
1393 | } |
1394 | EXPORT_SYMBOL_GPL(ips_link_to_i915_driver); |
1395 | |
1396 | static const struct pci_device_id ips_id_table[] = { |
1397 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_THERMAL_SENSOR), }, |
1398 | { 0, } |
1399 | }; |
1400 | |
1401 | MODULE_DEVICE_TABLE(pci, ips_id_table); |
1402 | |
1403 | static int ips_blacklist_callback(const struct dmi_system_id *id) |
1404 | { |
1405 | pr_info("Blacklisted intel_ips for %s\n" , id->ident); |
1406 | return 1; |
1407 | } |
1408 | |
1409 | static const struct dmi_system_id ips_blacklist[] = { |
1410 | { |
1411 | .callback = ips_blacklist_callback, |
1412 | .ident = "HP ProBook" , |
1413 | .matches = { |
1414 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard" ), |
1415 | DMI_MATCH(DMI_PRODUCT_NAME, "HP ProBook" ), |
1416 | }, |
1417 | }, |
1418 | { } /* terminating entry */ |
1419 | }; |
1420 | |
1421 | static int ips_probe(struct pci_dev *dev, const struct pci_device_id *id) |
1422 | { |
1423 | u64 platform_info; |
1424 | struct ips_driver *ips; |
1425 | u32 hts; |
1426 | int ret = 0; |
1427 | u16 htshi, trc, trc_required_mask; |
1428 | u8 tse; |
1429 | |
1430 | if (dmi_check_system(list: ips_blacklist)) |
1431 | return -ENODEV; |
1432 | |
1433 | ips = devm_kzalloc(dev: &dev->dev, size: sizeof(*ips), GFP_KERNEL); |
1434 | if (!ips) |
1435 | return -ENOMEM; |
1436 | |
1437 | spin_lock_init(&ips->turbo_status_lock); |
1438 | ips->dev = &dev->dev; |
1439 | |
1440 | ips->limits = ips_detect_cpu(ips); |
1441 | if (!ips->limits) { |
1442 | dev_info(&dev->dev, "IPS not supported on this CPU\n" ); |
1443 | return -ENXIO; |
1444 | } |
1445 | |
1446 | ret = pcim_enable_device(pdev: dev); |
1447 | if (ret) { |
1448 | dev_err(&dev->dev, "can't enable PCI device, aborting\n" ); |
1449 | return ret; |
1450 | } |
1451 | |
1452 | ret = pcim_iomap_regions(pdev: dev, mask: 1 << 0, name: pci_name(pdev: dev)); |
1453 | if (ret) { |
1454 | dev_err(&dev->dev, "failed to map thermal regs, aborting\n" ); |
1455 | return ret; |
1456 | } |
1457 | ips->regmap = pcim_iomap_table(pdev: dev)[0]; |
1458 | |
1459 | pci_set_drvdata(pdev: dev, data: ips); |
1460 | |
1461 | tse = thm_readb(THM_TSE); |
1462 | if (tse != TSE_EN) { |
1463 | dev_err(&dev->dev, "thermal device not enabled (0x%02x), aborting\n" , tse); |
1464 | return -ENXIO; |
1465 | } |
1466 | |
1467 | trc = thm_readw(THM_TRC); |
1468 | trc_required_mask = TRC_CORE1_EN | TRC_CORE_PWR | TRC_MCH_EN; |
1469 | if ((trc & trc_required_mask) != trc_required_mask) { |
1470 | dev_err(&dev->dev, "thermal reporting for required devices not enabled, aborting\n" ); |
1471 | return -ENXIO; |
1472 | } |
1473 | |
1474 | if (trc & TRC_CORE2_EN) |
1475 | ips->second_cpu = true; |
1476 | |
1477 | update_turbo_limits(ips); |
1478 | dev_dbg(&dev->dev, "max cpu power clamp: %dW\n" , |
1479 | ips->mcp_power_limit / 10); |
1480 | dev_dbg(&dev->dev, "max core power clamp: %dW\n" , |
1481 | ips->core_power_limit / 10); |
1482 | /* BIOS may update limits at runtime */ |
1483 | if (thm_readl(THM_PSC) & PSP_PBRT) |
1484 | ips->poll_turbo_status = true; |
1485 | |
1486 | if (!ips_get_i915_syms(ips)) { |
1487 | dev_info(&dev->dev, "failed to get i915 symbols, graphics turbo disabled until i915 loads\n" ); |
1488 | ips->gpu_turbo_enabled = false; |
1489 | } else { |
1490 | dev_dbg(&dev->dev, "graphics turbo enabled\n" ); |
1491 | ips->gpu_turbo_enabled = true; |
1492 | } |
1493 | |
1494 | /* |
1495 | * Check PLATFORM_INFO MSR to make sure this chip is |
1496 | * turbo capable. |
1497 | */ |
1498 | rdmsrl(PLATFORM_INFO, platform_info); |
1499 | if (!(platform_info & PLATFORM_TDP)) { |
1500 | dev_err(&dev->dev, "platform indicates TDP override unavailable, aborting\n" ); |
1501 | return -ENODEV; |
1502 | } |
1503 | |
1504 | /* |
1505 | * IRQ handler for ME interaction |
1506 | * Note: don't use MSI here as the PCH has bugs. |
1507 | */ |
1508 | ret = pci_alloc_irq_vectors(dev, min_vecs: 1, max_vecs: 1, PCI_IRQ_LEGACY); |
1509 | if (ret < 0) |
1510 | return ret; |
1511 | |
1512 | ips->irq = pci_irq_vector(dev, nr: 0); |
1513 | |
1514 | ret = request_irq(irq: ips->irq, handler: ips_irq_handler, IRQF_SHARED, name: "ips" , dev: ips); |
1515 | if (ret) { |
1516 | dev_err(&dev->dev, "request irq failed, aborting\n" ); |
1517 | return ret; |
1518 | } |
1519 | |
1520 | /* Enable aux, hot & critical interrupts */ |
1521 | thm_writeb(THM_TSPIEN, TSPIEN_AUX2_LOHI | TSPIEN_CRIT_LOHI | |
1522 | TSPIEN_HOT_LOHI | TSPIEN_AUX_LOHI); |
1523 | thm_writeb(THM_TEN, TEN_UPDATE_EN); |
1524 | |
1525 | /* Collect adjustment values */ |
1526 | ips->cta_val = thm_readw(THM_CTA); |
1527 | ips->pta_val = thm_readw(THM_PTA); |
1528 | ips->mgta_val = thm_readw(THM_MGTA); |
1529 | |
1530 | /* Save turbo limits & ratios */ |
1531 | rdmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit); |
1532 | |
1533 | ips_disable_cpu_turbo(ips); |
1534 | ips->cpu_turbo_enabled = false; |
1535 | |
1536 | /* Create thermal adjust thread */ |
1537 | ips->adjust = kthread_create(ips_adjust, ips, "ips-adjust" ); |
1538 | if (IS_ERR(ptr: ips->adjust)) { |
1539 | dev_err(&dev->dev, |
1540 | "failed to create thermal adjust thread, aborting\n" ); |
1541 | ret = -ENOMEM; |
1542 | goto error_free_irq; |
1543 | |
1544 | } |
1545 | |
1546 | /* |
1547 | * Set up the work queue and monitor thread. The monitor thread |
1548 | * will wake up ips_adjust thread. |
1549 | */ |
1550 | ips->monitor = kthread_run(ips_monitor, ips, "ips-monitor" ); |
1551 | if (IS_ERR(ptr: ips->monitor)) { |
1552 | dev_err(&dev->dev, |
1553 | "failed to create thermal monitor thread, aborting\n" ); |
1554 | ret = -ENOMEM; |
1555 | goto error_thread_cleanup; |
1556 | } |
1557 | |
1558 | hts = (ips->core_power_limit << HTS_PCPL_SHIFT) | |
1559 | (ips->mcp_temp_limit << HTS_PTL_SHIFT) | HTS_NVV; |
1560 | htshi = HTS2_PRST_RUNNING << HTS2_PRST_SHIFT; |
1561 | |
1562 | thm_writew(THM_HTSHI, htshi); |
1563 | thm_writel(THM_HTS, hts); |
1564 | |
1565 | ips_debugfs_init(ips); |
1566 | |
1567 | dev_info(&dev->dev, "IPS driver initialized, MCP temp limit %d\n" , |
1568 | ips->mcp_temp_limit); |
1569 | return ret; |
1570 | |
1571 | error_thread_cleanup: |
1572 | kthread_stop(k: ips->adjust); |
1573 | error_free_irq: |
1574 | free_irq(ips->irq, ips); |
1575 | pci_free_irq_vectors(dev); |
1576 | return ret; |
1577 | } |
1578 | |
1579 | static void ips_remove(struct pci_dev *dev) |
1580 | { |
1581 | struct ips_driver *ips = pci_get_drvdata(pdev: dev); |
1582 | u64 turbo_override; |
1583 | |
1584 | ips_debugfs_cleanup(ips); |
1585 | |
1586 | /* Release i915 driver */ |
1587 | if (ips->read_mch_val) |
1588 | symbol_put(i915_read_mch_val); |
1589 | if (ips->gpu_raise) |
1590 | symbol_put(i915_gpu_raise); |
1591 | if (ips->gpu_lower) |
1592 | symbol_put(i915_gpu_lower); |
1593 | if (ips->gpu_busy) |
1594 | symbol_put(i915_gpu_busy); |
1595 | if (ips->gpu_turbo_disable) |
1596 | symbol_put(i915_gpu_turbo_disable); |
1597 | |
1598 | rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); |
1599 | turbo_override &= ~(TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN); |
1600 | wrmsrl(TURBO_POWER_CURRENT_LIMIT, val: turbo_override); |
1601 | wrmsrl(TURBO_POWER_CURRENT_LIMIT, val: ips->orig_turbo_limit); |
1602 | |
1603 | free_irq(ips->irq, ips); |
1604 | pci_free_irq_vectors(dev); |
1605 | if (ips->adjust) |
1606 | kthread_stop(k: ips->adjust); |
1607 | if (ips->monitor) |
1608 | kthread_stop(k: ips->monitor); |
1609 | dev_dbg(&dev->dev, "IPS driver removed\n" ); |
1610 | } |
1611 | |
1612 | static struct pci_driver ips_pci_driver = { |
1613 | .name = "intel ips" , |
1614 | .id_table = ips_id_table, |
1615 | .probe = ips_probe, |
1616 | .remove = ips_remove, |
1617 | }; |
1618 | |
1619 | module_pci_driver(ips_pci_driver); |
1620 | |
1621 | MODULE_LICENSE("GPL v2" ); |
1622 | MODULE_AUTHOR("Jesse Barnes <jbarnes@virtuousgeek.org>" ); |
1623 | MODULE_DESCRIPTION("Intelligent Power Sharing Driver" ); |
1624 | |