1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (C) ST-Ericsson SA 2010 |
4 | * |
5 | * Author: Arun R Murthy <arun.murthy@stericsson.com> |
6 | * Datasheet: https://web.archive.org/web/20130614115108/http://www.stericsson.com/developers/CD00291561_UM1031_AB8500_user_manual-rev5_CTDS_public.pdf |
7 | */ |
8 | #include <linux/err.h> |
9 | #include <linux/platform_device.h> |
10 | #include <linux/slab.h> |
11 | #include <linux/pwm.h> |
12 | #include <linux/mfd/abx500.h> |
13 | #include <linux/mfd/abx500/ab8500.h> |
14 | #include <linux/module.h> |
15 | |
16 | /* |
17 | * PWM Out generators |
18 | * Bank: 0x10 |
19 | */ |
20 | #define AB8500_PWM_OUT_CTRL1_REG 0x60 |
21 | #define AB8500_PWM_OUT_CTRL2_REG 0x61 |
22 | #define AB8500_PWM_OUT_CTRL7_REG 0x66 |
23 | |
24 | #define AB8500_PWM_CLKRATE 9600000 |
25 | |
26 | struct ab8500_pwm_chip { |
27 | unsigned int hwid; |
28 | }; |
29 | |
30 | static struct ab8500_pwm_chip *ab8500_pwm_from_chip(struct pwm_chip *chip) |
31 | { |
32 | return pwmchip_get_drvdata(chip); |
33 | } |
34 | |
35 | static int ab8500_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
36 | const struct pwm_state *state) |
37 | { |
38 | int ret; |
39 | u8 reg; |
40 | u8 higher_val, lower_val; |
41 | unsigned int duty_steps, div; |
42 | struct ab8500_pwm_chip *ab8500 = ab8500_pwm_from_chip(chip); |
43 | |
44 | if (state->polarity != PWM_POLARITY_NORMAL) |
45 | return -EINVAL; |
46 | |
47 | if (state->enabled) { |
48 | /* |
49 | * A time quantum is |
50 | * q = (32 - FreqPWMOutx[3:0]) / AB8500_PWM_CLKRATE |
51 | * The period is always 1024 q, duty_cycle is between 1q and 1024q. |
52 | * |
53 | * FreqPWMOutx[3:0] | output frequency | output frequency | 1024q = period |
54 | * | (from manual) | (1 / 1024q) | = 1 / freq |
55 | * -----------------+------------------+------------------+-------------- |
56 | * b0000 | 293 Hz | 292.968750 Hz | 3413333.33 ns |
57 | * b0001 | 302 Hz | 302.419355 Hz | 3306666.66 ns |
58 | * b0010 | 312 Hz | 312.500000 Hz | 3200000 ns |
59 | * b0011 | 323 Hz | 323.275862 Hz | 3093333.33 ns |
60 | * b0100 | 334 Hz | 334.821429 Hz | 2986666.66 ns |
61 | * b0101 | 347 Hz | 347.222222 Hz | 2880000 ns |
62 | * b0110 | 360 Hz | 360.576923 Hz | 2773333.33 ns |
63 | * b0111 | 375 Hz | 375.000000 Hz | 2666666.66 ns |
64 | * b1000 | 390 Hz | 390.625000 Hz | 2560000 ns |
65 | * b1001 | 407 Hz | 407.608696 Hz | 2453333.33 ns |
66 | * b1010 | 426 Hz | 426.136364 Hz | 2346666.66 ns |
67 | * b1011 | 446 Hz | 446.428571 Hz | 2240000 ns |
68 | * b1100 | 468 Hz | 468.750000 Hz | 2133333.33 ns |
69 | * b1101 | 493 Hz | 493.421053 Hz | 2026666.66 ns |
70 | * b1110 | 520 Hz | 520.833333 Hz | 1920000 ns |
71 | * b1111 | 551 Hz | 551.470588 Hz | 1813333.33 ns |
72 | * |
73 | * |
74 | * AB8500_PWM_CLKRATE is a multiple of 1024, so the division by |
75 | * 1024 can be done in this factor without loss of precision. |
76 | */ |
77 | div = min_t(u64, mul_u64_u64_div_u64(state->period, |
78 | AB8500_PWM_CLKRATE >> 10, |
79 | NSEC_PER_SEC), 32); /* 32 - FreqPWMOutx[3:0] */ |
80 | if (div <= 16) |
81 | /* requested period < 3413333.33 */ |
82 | return -EINVAL; |
83 | |
84 | duty_steps = max_t(u64, mul_u64_u64_div_u64(state->duty_cycle, |
85 | AB8500_PWM_CLKRATE, |
86 | (u64)NSEC_PER_SEC * div), 1024); |
87 | } |
88 | |
89 | /* |
90 | * The hardware doesn't support duty_steps = 0 explicitly, but emits low |
91 | * when disabled. |
92 | */ |
93 | if (!state->enabled || duty_steps == 0) { |
94 | ret = abx500_mask_and_set_register_interruptible(dev: pwmchip_parent(chip), |
95 | AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG, |
96 | bitmask: 1 << ab8500->hwid, bitvalues: 0); |
97 | |
98 | if (ret < 0) |
99 | dev_err(pwmchip_parent(chip), "%s: Failed to disable PWM, Error %d\n" , |
100 | pwm->label, ret); |
101 | return ret; |
102 | } |
103 | |
104 | /* |
105 | * The lower 8 bits of duty_steps is written to ... |
106 | * AB8500_PWM_OUT_CTRL1_REG[0:7] |
107 | */ |
108 | lower_val = (duty_steps - 1) & 0x00ff; |
109 | /* |
110 | * The two remaining high bits to |
111 | * AB8500_PWM_OUT_CTRL2_REG[0:1]; together with FreqPWMOutx. |
112 | */ |
113 | higher_val = ((duty_steps - 1) & 0x0300) >> 8 | (32 - div) << 4; |
114 | |
115 | reg = AB8500_PWM_OUT_CTRL1_REG + (ab8500->hwid * 2); |
116 | |
117 | ret = abx500_set_register_interruptible(dev: pwmchip_parent(chip), AB8500_MISC, |
118 | reg, value: lower_val); |
119 | if (ret < 0) |
120 | return ret; |
121 | |
122 | ret = abx500_set_register_interruptible(dev: pwmchip_parent(chip), AB8500_MISC, |
123 | reg: (reg + 1), value: higher_val); |
124 | if (ret < 0) |
125 | return ret; |
126 | |
127 | /* enable */ |
128 | ret = abx500_mask_and_set_register_interruptible(dev: pwmchip_parent(chip), |
129 | AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG, |
130 | bitmask: 1 << ab8500->hwid, bitvalues: 1 << ab8500->hwid); |
131 | if (ret < 0) |
132 | dev_err(pwmchip_parent(chip), "%s: Failed to enable PWM, Error %d\n" , |
133 | pwm->label, ret); |
134 | |
135 | return ret; |
136 | } |
137 | |
138 | static int ab8500_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, |
139 | struct pwm_state *state) |
140 | { |
141 | u8 ctrl7, lower_val, higher_val; |
142 | int ret; |
143 | struct ab8500_pwm_chip *ab8500 = ab8500_pwm_from_chip(chip); |
144 | unsigned int div, duty_steps; |
145 | |
146 | ret = abx500_get_register_interruptible(dev: pwmchip_parent(chip), AB8500_MISC, |
147 | AB8500_PWM_OUT_CTRL7_REG, |
148 | value: &ctrl7); |
149 | if (ret) |
150 | return ret; |
151 | |
152 | state->polarity = PWM_POLARITY_NORMAL; |
153 | |
154 | if (!(ctrl7 & 1 << ab8500->hwid)) { |
155 | state->enabled = false; |
156 | return 0; |
157 | } |
158 | |
159 | ret = abx500_get_register_interruptible(dev: pwmchip_parent(chip), AB8500_MISC, |
160 | AB8500_PWM_OUT_CTRL1_REG + (ab8500->hwid * 2), |
161 | value: &lower_val); |
162 | if (ret) |
163 | return ret; |
164 | |
165 | ret = abx500_get_register_interruptible(dev: pwmchip_parent(chip), AB8500_MISC, |
166 | AB8500_PWM_OUT_CTRL2_REG + (ab8500->hwid * 2), |
167 | value: &higher_val); |
168 | if (ret) |
169 | return ret; |
170 | |
171 | div = 32 - ((higher_val & 0xf0) >> 4); |
172 | duty_steps = ((higher_val & 3) << 8 | lower_val) + 1; |
173 | |
174 | state->period = DIV64_U64_ROUND_UP((u64)div << 10, AB8500_PWM_CLKRATE); |
175 | state->duty_cycle = DIV64_U64_ROUND_UP((u64)div * duty_steps, AB8500_PWM_CLKRATE); |
176 | |
177 | return 0; |
178 | } |
179 | |
180 | static const struct pwm_ops ab8500_pwm_ops = { |
181 | .apply = ab8500_pwm_apply, |
182 | .get_state = ab8500_pwm_get_state, |
183 | }; |
184 | |
185 | static int ab8500_pwm_probe(struct platform_device *pdev) |
186 | { |
187 | struct pwm_chip *chip; |
188 | struct ab8500_pwm_chip *ab8500; |
189 | int err; |
190 | |
191 | if (pdev->id < 1 || pdev->id > 31) |
192 | return dev_err_probe(dev: &pdev->dev, err: -EINVAL, fmt: "Invalid device id %d\n" , pdev->id); |
193 | |
194 | /* |
195 | * Nothing to be done in probe, this is required to get the |
196 | * device which is required for ab8500 read and write |
197 | */ |
198 | chip = devm_pwmchip_alloc(parent: &pdev->dev, npwm: 1, sizeof_priv: sizeof(*ab8500)); |
199 | if (IS_ERR(ptr: chip)) |
200 | return PTR_ERR(ptr: chip); |
201 | |
202 | ab8500 = ab8500_pwm_from_chip(chip); |
203 | |
204 | chip->ops = &ab8500_pwm_ops; |
205 | ab8500->hwid = pdev->id - 1; |
206 | |
207 | err = devm_pwmchip_add(&pdev->dev, chip); |
208 | if (err < 0) |
209 | return dev_err_probe(dev: &pdev->dev, err, fmt: "Failed to add pwm chip\n" ); |
210 | |
211 | dev_dbg(&pdev->dev, "pwm probe successful\n" ); |
212 | |
213 | return 0; |
214 | } |
215 | |
216 | static struct platform_driver ab8500_pwm_driver = { |
217 | .driver = { |
218 | .name = "ab8500-pwm" , |
219 | }, |
220 | .probe = ab8500_pwm_probe, |
221 | }; |
222 | module_platform_driver(ab8500_pwm_driver); |
223 | |
224 | MODULE_AUTHOR("Arun MURTHY <arun.murthy@stericsson.com>" ); |
225 | MODULE_DESCRIPTION("AB8500 Pulse Width Modulation Driver" ); |
226 | MODULE_ALIAS("platform:ab8500-pwm" ); |
227 | MODULE_LICENSE("GPL v2" ); |
228 | |