1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (C) STMicroelectronics 2016 |
4 | * |
5 | * Author: Gerald Baeza <gerald.baeza@st.com> |
6 | * |
7 | * Inspired by timer-stm32.c from Maxime Coquelin |
8 | * pwm-atmel.c from Bo Shen |
9 | */ |
10 | |
11 | #include <linux/bitfield.h> |
12 | #include <linux/mfd/stm32-timers.h> |
13 | #include <linux/module.h> |
14 | #include <linux/of.h> |
15 | #include <linux/pinctrl/consumer.h> |
16 | #include <linux/platform_device.h> |
17 | #include <linux/pwm.h> |
18 | |
19 | #define CCMR_CHANNEL_SHIFT 8 |
20 | #define CCMR_CHANNEL_MASK 0xFF |
21 | #define MAX_BREAKINPUT 2 |
22 | |
23 | struct stm32_breakinput { |
24 | u32 index; |
25 | u32 level; |
26 | u32 filter; |
27 | }; |
28 | |
29 | struct stm32_pwm { |
30 | struct mutex lock; /* protect pwm config/enable */ |
31 | struct clk *clk; |
32 | struct regmap *regmap; |
33 | u32 max_arr; |
34 | bool have_complementary_output; |
35 | struct stm32_breakinput breakinputs[MAX_BREAKINPUT]; |
36 | unsigned int num_breakinputs; |
37 | u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */ |
38 | }; |
39 | |
40 | static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip) |
41 | { |
42 | return pwmchip_get_drvdata(chip); |
43 | } |
44 | |
45 | static u32 active_channels(struct stm32_pwm *dev) |
46 | { |
47 | u32 ccer; |
48 | |
49 | regmap_read(map: dev->regmap, TIM_CCER, val: &ccer); |
50 | |
51 | return ccer & TIM_CCER_CCXE; |
52 | } |
53 | |
54 | #define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P) |
55 | #define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E) |
56 | #define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P) |
57 | #define TIM_CCER_CC34E (TIM_CCER_CC3E | TIM_CCER_CC4E) |
58 | |
59 | /* |
60 | * Capture using PWM input mode: |
61 | * ___ ___ |
62 | * TI[1, 2, 3 or 4]: ........._| |________| |
63 | * ^0 ^1 ^2 |
64 | * . . . |
65 | * . . XXXXX |
66 | * . . XXXXX | |
67 | * . XXXXX . | |
68 | * XXXXX . . | |
69 | * COUNTER: ______XXXXX . . . |_XXX |
70 | * start^ . . . ^stop |
71 | * . . . . |
72 | * v v . v |
73 | * v |
74 | * CCR1/CCR3: tx..........t0...........t2 |
75 | * CCR2/CCR4: tx..............t1......... |
76 | * |
77 | * DMA burst transfer: | | |
78 | * v v |
79 | * DMA buffer: { t0, tx } { t2, t1 } |
80 | * DMA done: ^ |
81 | * |
82 | * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3 |
83 | * + DMA transfer CCR[1/3] & CCR[2/4] values (t0, tx: doesn't care) |
84 | * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4 |
85 | * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3 |
86 | * + DMA transfer CCR[1/3] & CCR[2/4] values (t2, t1) |
87 | * |
88 | * DMA done, compute: |
89 | * - Period = t2 - t0 |
90 | * - Duty cycle = t1 - t0 |
91 | */ |
92 | static int stm32_pwm_raw_capture(struct pwm_chip *chip, struct pwm_device *pwm, |
93 | unsigned long tmo_ms, u32 *raw_prd, |
94 | u32 *raw_dty) |
95 | { |
96 | struct stm32_pwm *priv = to_stm32_pwm_dev(chip); |
97 | struct device *parent = pwmchip_parent(chip)->parent; |
98 | enum stm32_timers_dmas dma_id; |
99 | u32 ccen, ccr; |
100 | int ret; |
101 | |
102 | /* Ensure registers have been updated, enable counter and capture */ |
103 | regmap_set_bits(map: priv->regmap, TIM_EGR, TIM_EGR_UG); |
104 | regmap_set_bits(map: priv->regmap, TIM_CR1, TIM_CR1_CEN); |
105 | |
106 | /* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */ |
107 | dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3; |
108 | ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E; |
109 | ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3; |
110 | regmap_set_bits(map: priv->regmap, TIM_CCER, bits: ccen); |
111 | |
112 | /* |
113 | * Timer DMA burst mode. Request 2 registers, 2 bursts, to get both |
114 | * CCR1 & CCR2 (or CCR3 & CCR4) on each capture event. |
115 | * We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 } |
116 | * or { CCR3, CCR4 }, { CCR3, CCR4 } |
117 | */ |
118 | ret = stm32_timers_dma_burst_read(dev: parent, buf: priv->capture, id: dma_id, reg: ccr, num_reg: 2, |
119 | bursts: 2, tmo_ms); |
120 | if (ret) |
121 | goto stop; |
122 | |
123 | /* Period: t2 - t0 (take care of counter overflow) */ |
124 | if (priv->capture[0] <= priv->capture[2]) |
125 | *raw_prd = priv->capture[2] - priv->capture[0]; |
126 | else |
127 | *raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2]; |
128 | |
129 | /* Duty cycle capture requires at least two capture units */ |
130 | if (pwm->chip->npwm < 2) |
131 | *raw_dty = 0; |
132 | else if (priv->capture[0] <= priv->capture[3]) |
133 | *raw_dty = priv->capture[3] - priv->capture[0]; |
134 | else |
135 | *raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3]; |
136 | |
137 | if (*raw_dty > *raw_prd) { |
138 | /* |
139 | * Race beetween PWM input and DMA: it may happen |
140 | * falling edge triggers new capture on TI2/4 before DMA |
141 | * had a chance to read CCR2/4. It means capture[1] |
142 | * contains period + duty_cycle. So, subtract period. |
143 | */ |
144 | *raw_dty -= *raw_prd; |
145 | } |
146 | |
147 | stop: |
148 | regmap_clear_bits(map: priv->regmap, TIM_CCER, bits: ccen); |
149 | regmap_clear_bits(map: priv->regmap, TIM_CR1, TIM_CR1_CEN); |
150 | |
151 | return ret; |
152 | } |
153 | |
154 | static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm, |
155 | struct pwm_capture *result, unsigned long tmo_ms) |
156 | { |
157 | struct stm32_pwm *priv = to_stm32_pwm_dev(chip); |
158 | unsigned long long prd, div, dty; |
159 | unsigned long rate; |
160 | unsigned int psc = 0, icpsc, scale; |
161 | u32 raw_prd = 0, raw_dty = 0; |
162 | int ret = 0; |
163 | |
164 | mutex_lock(&priv->lock); |
165 | |
166 | if (active_channels(dev: priv)) { |
167 | ret = -EBUSY; |
168 | goto unlock; |
169 | } |
170 | |
171 | ret = clk_enable(clk: priv->clk); |
172 | if (ret) { |
173 | dev_err(pwmchip_parent(chip), "failed to enable counter clock\n" ); |
174 | goto unlock; |
175 | } |
176 | |
177 | rate = clk_get_rate(clk: priv->clk); |
178 | if (!rate) { |
179 | ret = -EINVAL; |
180 | goto clk_dis; |
181 | } |
182 | |
183 | /* prescaler: fit timeout window provided by upper layer */ |
184 | div = (unsigned long long)rate * (unsigned long long)tmo_ms; |
185 | do_div(div, MSEC_PER_SEC); |
186 | prd = div; |
187 | while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) { |
188 | psc++; |
189 | div = prd; |
190 | do_div(div, psc + 1); |
191 | } |
192 | regmap_write(map: priv->regmap, TIM_ARR, val: priv->max_arr); |
193 | regmap_write(map: priv->regmap, TIM_PSC, val: psc); |
194 | |
195 | /* Reset input selector to its default input and disable slave mode */ |
196 | regmap_write(map: priv->regmap, TIM_TISEL, val: 0x0); |
197 | regmap_write(map: priv->regmap, TIM_SMCR, val: 0x0); |
198 | |
199 | /* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */ |
200 | regmap_update_bits(map: priv->regmap, |
201 | reg: pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, |
202 | TIM_CCMR_CC1S | TIM_CCMR_CC2S, val: pwm->hwpwm & 0x1 ? |
203 | TIM_CCMR_CC1S_TI2 | TIM_CCMR_CC2S_TI2 : |
204 | TIM_CCMR_CC1S_TI1 | TIM_CCMR_CC2S_TI1); |
205 | |
206 | /* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */ |
207 | regmap_update_bits(map: priv->regmap, TIM_CCER, mask: pwm->hwpwm < 2 ? |
208 | TIM_CCER_CC12P : TIM_CCER_CC34P, val: pwm->hwpwm < 2 ? |
209 | TIM_CCER_CC2P : TIM_CCER_CC4P); |
210 | |
211 | ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, raw_prd: &raw_prd, raw_dty: &raw_dty); |
212 | if (ret) |
213 | goto stop; |
214 | |
215 | /* |
216 | * Got a capture. Try to improve accuracy at high rates: |
217 | * - decrease counter clock prescaler, scale up to max rate. |
218 | * - use input prescaler, capture once every /2 /4 or /8 edges. |
219 | */ |
220 | if (raw_prd) { |
221 | u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */ |
222 | |
223 | scale = max_arr / min(max_arr, raw_prd); |
224 | } else { |
225 | scale = priv->max_arr; /* bellow resolution, use max scale */ |
226 | } |
227 | |
228 | if (psc && scale > 1) { |
229 | /* 2nd measure with new scale */ |
230 | psc /= scale; |
231 | regmap_write(map: priv->regmap, TIM_PSC, val: psc); |
232 | ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, raw_prd: &raw_prd, |
233 | raw_dty: &raw_dty); |
234 | if (ret) |
235 | goto stop; |
236 | } |
237 | |
238 | /* Compute intermediate period not to exceed timeout at low rates */ |
239 | prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC; |
240 | do_div(prd, rate); |
241 | |
242 | for (icpsc = 0; icpsc < MAX_TIM_ICPSC ; icpsc++) { |
243 | /* input prescaler: also keep arbitrary margin */ |
244 | if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1)) |
245 | break; |
246 | if (prd >= (tmo_ms * NSEC_PER_MSEC) >> (icpsc + 2)) |
247 | break; |
248 | } |
249 | |
250 | if (!icpsc) |
251 | goto done; |
252 | |
253 | /* Last chance to improve period accuracy, using input prescaler */ |
254 | regmap_update_bits(map: priv->regmap, |
255 | reg: pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, |
256 | TIM_CCMR_IC1PSC | TIM_CCMR_IC2PSC, |
257 | FIELD_PREP(TIM_CCMR_IC1PSC, icpsc) | |
258 | FIELD_PREP(TIM_CCMR_IC2PSC, icpsc)); |
259 | |
260 | ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, raw_prd: &raw_prd, raw_dty: &raw_dty); |
261 | if (ret) |
262 | goto stop; |
263 | |
264 | if (raw_dty >= (raw_prd >> icpsc)) { |
265 | /* |
266 | * We may fall here using input prescaler, when input |
267 | * capture starts on high side (before falling edge). |
268 | * Example with icpsc to capture on each 4 events: |
269 | * |
270 | * start 1st capture 2nd capture |
271 | * v v v |
272 | * ___ _____ _____ _____ _____ ____ |
273 | * TI1..4 |__| |__| |__| |__| |__| |
274 | * v v . . . . . v v |
275 | * icpsc1/3: . 0 . 1 . 2 . 3 . 0 |
276 | * icpsc2/4: 0 1 2 3 0 |
277 | * v v v v |
278 | * CCR1/3 ......t0..............................t2 |
279 | * CCR2/4 ..t1..............................t1'... |
280 | * . . . |
281 | * Capture0: .<----------------------------->. |
282 | * Capture1: .<-------------------------->. . |
283 | * . . . |
284 | * Period: .<------> . . |
285 | * Low side: .<>. |
286 | * |
287 | * Result: |
288 | * - Period = Capture0 / icpsc |
289 | * - Duty = Period - Low side = Period - (Capture0 - Capture1) |
290 | */ |
291 | raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty); |
292 | } |
293 | |
294 | done: |
295 | prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC; |
296 | result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc); |
297 | dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC; |
298 | result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate); |
299 | stop: |
300 | regmap_write(map: priv->regmap, TIM_CCER, val: 0); |
301 | regmap_write(map: priv->regmap, reg: pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, val: 0); |
302 | regmap_write(map: priv->regmap, TIM_PSC, val: 0); |
303 | clk_dis: |
304 | clk_disable(clk: priv->clk); |
305 | unlock: |
306 | mutex_unlock(lock: &priv->lock); |
307 | |
308 | return ret; |
309 | } |
310 | |
311 | static int stm32_pwm_config(struct stm32_pwm *priv, unsigned int ch, |
312 | int duty_ns, int period_ns) |
313 | { |
314 | unsigned long long prd, div, dty; |
315 | unsigned int prescaler = 0; |
316 | u32 ccmr, mask, shift; |
317 | |
318 | /* Period and prescaler values depends on clock rate */ |
319 | div = (unsigned long long)clk_get_rate(clk: priv->clk) * period_ns; |
320 | |
321 | do_div(div, NSEC_PER_SEC); |
322 | prd = div; |
323 | |
324 | while (div > priv->max_arr) { |
325 | prescaler++; |
326 | div = prd; |
327 | do_div(div, prescaler + 1); |
328 | } |
329 | |
330 | prd = div; |
331 | |
332 | if (prescaler > MAX_TIM_PSC) |
333 | return -EINVAL; |
334 | |
335 | /* |
336 | * All channels share the same prescaler and counter so when two |
337 | * channels are active at the same time we can't change them |
338 | */ |
339 | if (active_channels(dev: priv) & ~(1 << ch * 4)) { |
340 | u32 psc, arr; |
341 | |
342 | regmap_read(map: priv->regmap, TIM_PSC, val: &psc); |
343 | regmap_read(map: priv->regmap, TIM_ARR, val: &arr); |
344 | |
345 | if ((psc != prescaler) || (arr != prd - 1)) |
346 | return -EBUSY; |
347 | } |
348 | |
349 | regmap_write(map: priv->regmap, TIM_PSC, val: prescaler); |
350 | regmap_write(map: priv->regmap, TIM_ARR, val: prd - 1); |
351 | regmap_set_bits(map: priv->regmap, TIM_CR1, TIM_CR1_ARPE); |
352 | |
353 | /* Calculate the duty cycles */ |
354 | dty = prd * duty_ns; |
355 | do_div(dty, period_ns); |
356 | |
357 | regmap_write(map: priv->regmap, TIM_CCR1 + 4 * ch, val: dty); |
358 | |
359 | /* Configure output mode */ |
360 | shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT; |
361 | ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift; |
362 | mask = CCMR_CHANNEL_MASK << shift; |
363 | |
364 | if (ch < 2) |
365 | regmap_update_bits(map: priv->regmap, TIM_CCMR1, mask, val: ccmr); |
366 | else |
367 | regmap_update_bits(map: priv->regmap, TIM_CCMR2, mask, val: ccmr); |
368 | |
369 | regmap_set_bits(map: priv->regmap, TIM_BDTR, TIM_BDTR_MOE); |
370 | |
371 | return 0; |
372 | } |
373 | |
374 | static int stm32_pwm_set_polarity(struct stm32_pwm *priv, unsigned int ch, |
375 | enum pwm_polarity polarity) |
376 | { |
377 | u32 mask; |
378 | |
379 | mask = TIM_CCER_CC1P << (ch * 4); |
380 | if (priv->have_complementary_output) |
381 | mask |= TIM_CCER_CC1NP << (ch * 4); |
382 | |
383 | regmap_update_bits(map: priv->regmap, TIM_CCER, mask, |
384 | val: polarity == PWM_POLARITY_NORMAL ? 0 : mask); |
385 | |
386 | return 0; |
387 | } |
388 | |
389 | static int stm32_pwm_enable(struct stm32_pwm *priv, unsigned int ch) |
390 | { |
391 | u32 mask; |
392 | int ret; |
393 | |
394 | ret = clk_enable(clk: priv->clk); |
395 | if (ret) |
396 | return ret; |
397 | |
398 | /* Enable channel */ |
399 | mask = TIM_CCER_CC1E << (ch * 4); |
400 | if (priv->have_complementary_output) |
401 | mask |= TIM_CCER_CC1NE << (ch * 4); |
402 | |
403 | regmap_set_bits(map: priv->regmap, TIM_CCER, bits: mask); |
404 | |
405 | /* Make sure that registers are updated */ |
406 | regmap_set_bits(map: priv->regmap, TIM_EGR, TIM_EGR_UG); |
407 | |
408 | /* Enable controller */ |
409 | regmap_set_bits(map: priv->regmap, TIM_CR1, TIM_CR1_CEN); |
410 | |
411 | return 0; |
412 | } |
413 | |
414 | static void stm32_pwm_disable(struct stm32_pwm *priv, unsigned int ch) |
415 | { |
416 | u32 mask; |
417 | |
418 | /* Disable channel */ |
419 | mask = TIM_CCER_CC1E << (ch * 4); |
420 | if (priv->have_complementary_output) |
421 | mask |= TIM_CCER_CC1NE << (ch * 4); |
422 | |
423 | regmap_clear_bits(map: priv->regmap, TIM_CCER, bits: mask); |
424 | |
425 | /* When all channels are disabled, we can disable the controller */ |
426 | if (!active_channels(dev: priv)) |
427 | regmap_clear_bits(map: priv->regmap, TIM_CR1, TIM_CR1_CEN); |
428 | |
429 | clk_disable(clk: priv->clk); |
430 | } |
431 | |
432 | static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
433 | const struct pwm_state *state) |
434 | { |
435 | bool enabled; |
436 | struct stm32_pwm *priv = to_stm32_pwm_dev(chip); |
437 | int ret; |
438 | |
439 | enabled = pwm->state.enabled; |
440 | |
441 | if (enabled && !state->enabled) { |
442 | stm32_pwm_disable(priv, ch: pwm->hwpwm); |
443 | return 0; |
444 | } |
445 | |
446 | if (state->polarity != pwm->state.polarity) |
447 | stm32_pwm_set_polarity(priv, ch: pwm->hwpwm, polarity: state->polarity); |
448 | |
449 | ret = stm32_pwm_config(priv, ch: pwm->hwpwm, |
450 | duty_ns: state->duty_cycle, period_ns: state->period); |
451 | if (ret) |
452 | return ret; |
453 | |
454 | if (!enabled && state->enabled) |
455 | ret = stm32_pwm_enable(priv, ch: pwm->hwpwm); |
456 | |
457 | return ret; |
458 | } |
459 | |
460 | static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm, |
461 | const struct pwm_state *state) |
462 | { |
463 | struct stm32_pwm *priv = to_stm32_pwm_dev(chip); |
464 | int ret; |
465 | |
466 | /* protect common prescaler for all active channels */ |
467 | mutex_lock(&priv->lock); |
468 | ret = stm32_pwm_apply(chip, pwm, state); |
469 | mutex_unlock(lock: &priv->lock); |
470 | |
471 | return ret; |
472 | } |
473 | |
474 | static int stm32_pwm_get_state(struct pwm_chip *chip, |
475 | struct pwm_device *pwm, struct pwm_state *state) |
476 | { |
477 | struct stm32_pwm *priv = to_stm32_pwm_dev(chip); |
478 | int ch = pwm->hwpwm; |
479 | unsigned long rate; |
480 | u32 ccer, psc, arr, ccr; |
481 | u64 dty, prd; |
482 | int ret; |
483 | |
484 | mutex_lock(&priv->lock); |
485 | |
486 | ret = regmap_read(map: priv->regmap, TIM_CCER, val: &ccer); |
487 | if (ret) |
488 | goto out; |
489 | |
490 | state->enabled = ccer & (TIM_CCER_CC1E << (ch * 4)); |
491 | state->polarity = (ccer & (TIM_CCER_CC1P << (ch * 4))) ? |
492 | PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL; |
493 | ret = regmap_read(map: priv->regmap, TIM_PSC, val: &psc); |
494 | if (ret) |
495 | goto out; |
496 | ret = regmap_read(map: priv->regmap, TIM_ARR, val: &arr); |
497 | if (ret) |
498 | goto out; |
499 | ret = regmap_read(map: priv->regmap, TIM_CCR1 + 4 * ch, val: &ccr); |
500 | if (ret) |
501 | goto out; |
502 | |
503 | rate = clk_get_rate(clk: priv->clk); |
504 | |
505 | prd = (u64)NSEC_PER_SEC * (psc + 1) * (arr + 1); |
506 | state->period = DIV_ROUND_UP_ULL(prd, rate); |
507 | dty = (u64)NSEC_PER_SEC * (psc + 1) * ccr; |
508 | state->duty_cycle = DIV_ROUND_UP_ULL(dty, rate); |
509 | |
510 | out: |
511 | mutex_unlock(lock: &priv->lock); |
512 | return ret; |
513 | } |
514 | |
515 | static const struct pwm_ops stm32pwm_ops = { |
516 | .apply = stm32_pwm_apply_locked, |
517 | .get_state = stm32_pwm_get_state, |
518 | .capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL, |
519 | }; |
520 | |
521 | static int stm32_pwm_set_breakinput(struct stm32_pwm *priv, |
522 | const struct stm32_breakinput *bi) |
523 | { |
524 | u32 shift = TIM_BDTR_BKF_SHIFT(bi->index); |
525 | u32 bke = TIM_BDTR_BKE(bi->index); |
526 | u32 bkp = TIM_BDTR_BKP(bi->index); |
527 | u32 bkf = TIM_BDTR_BKF(bi->index); |
528 | u32 mask = bkf | bkp | bke; |
529 | u32 bdtr; |
530 | |
531 | bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke; |
532 | |
533 | if (bi->level) |
534 | bdtr |= bkp; |
535 | |
536 | regmap_update_bits(map: priv->regmap, TIM_BDTR, mask, val: bdtr); |
537 | |
538 | regmap_read(map: priv->regmap, TIM_BDTR, val: &bdtr); |
539 | |
540 | return (bdtr & bke) ? 0 : -EINVAL; |
541 | } |
542 | |
543 | static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv) |
544 | { |
545 | unsigned int i; |
546 | int ret; |
547 | |
548 | for (i = 0; i < priv->num_breakinputs; i++) { |
549 | ret = stm32_pwm_set_breakinput(priv, bi: &priv->breakinputs[i]); |
550 | if (ret < 0) |
551 | return ret; |
552 | } |
553 | |
554 | return 0; |
555 | } |
556 | |
557 | static int stm32_pwm_probe_breakinputs(struct stm32_pwm *priv, |
558 | struct device_node *np) |
559 | { |
560 | int nb, ret, array_size; |
561 | unsigned int i; |
562 | |
563 | nb = of_property_count_elems_of_size(np, propname: "st,breakinput" , |
564 | elem_size: sizeof(struct stm32_breakinput)); |
565 | |
566 | /* |
567 | * Because "st,breakinput" parameter is optional do not make probe |
568 | * failed if it doesn't exist. |
569 | */ |
570 | if (nb <= 0) |
571 | return 0; |
572 | |
573 | if (nb > MAX_BREAKINPUT) |
574 | return -EINVAL; |
575 | |
576 | priv->num_breakinputs = nb; |
577 | array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32); |
578 | ret = of_property_read_u32_array(np, propname: "st,breakinput" , |
579 | out_values: (u32 *)priv->breakinputs, sz: array_size); |
580 | if (ret) |
581 | return ret; |
582 | |
583 | for (i = 0; i < priv->num_breakinputs; i++) { |
584 | if (priv->breakinputs[i].index > 1 || |
585 | priv->breakinputs[i].level > 1 || |
586 | priv->breakinputs[i].filter > 15) |
587 | return -EINVAL; |
588 | } |
589 | |
590 | return stm32_pwm_apply_breakinputs(priv); |
591 | } |
592 | |
593 | static void stm32_pwm_detect_complementary(struct stm32_pwm *priv) |
594 | { |
595 | u32 ccer; |
596 | |
597 | /* |
598 | * If complementary bit doesn't exist writing 1 will have no |
599 | * effect so we can detect it. |
600 | */ |
601 | regmap_set_bits(map: priv->regmap, TIM_CCER, TIM_CCER_CC1NE); |
602 | regmap_read(map: priv->regmap, TIM_CCER, val: &ccer); |
603 | regmap_clear_bits(map: priv->regmap, TIM_CCER, TIM_CCER_CC1NE); |
604 | |
605 | priv->have_complementary_output = (ccer != 0); |
606 | } |
607 | |
608 | static unsigned int stm32_pwm_detect_channels(struct regmap *regmap, |
609 | unsigned int *num_enabled) |
610 | { |
611 | u32 ccer, ccer_backup; |
612 | |
613 | /* |
614 | * If channels enable bits don't exist writing 1 will have no |
615 | * effect so we can detect and count them. |
616 | */ |
617 | regmap_read(map: regmap, TIM_CCER, val: &ccer_backup); |
618 | regmap_set_bits(map: regmap, TIM_CCER, TIM_CCER_CCXE); |
619 | regmap_read(map: regmap, TIM_CCER, val: &ccer); |
620 | regmap_write(map: regmap, TIM_CCER, val: ccer_backup); |
621 | |
622 | *num_enabled = hweight32(ccer_backup & TIM_CCER_CCXE); |
623 | |
624 | return hweight32(ccer & TIM_CCER_CCXE); |
625 | } |
626 | |
627 | static int stm32_pwm_probe(struct platform_device *pdev) |
628 | { |
629 | struct device *dev = &pdev->dev; |
630 | struct device_node *np = dev->of_node; |
631 | struct stm32_timers *ddata = dev_get_drvdata(dev: pdev->dev.parent); |
632 | struct pwm_chip *chip; |
633 | struct stm32_pwm *priv; |
634 | unsigned int npwm, num_enabled; |
635 | unsigned int i; |
636 | int ret; |
637 | |
638 | npwm = stm32_pwm_detect_channels(regmap: ddata->regmap, num_enabled: &num_enabled); |
639 | |
640 | chip = devm_pwmchip_alloc(parent: dev, npwm, sizeof_priv: sizeof(*priv)); |
641 | if (IS_ERR(ptr: chip)) |
642 | return PTR_ERR(ptr: chip); |
643 | priv = to_stm32_pwm_dev(chip); |
644 | |
645 | mutex_init(&priv->lock); |
646 | priv->regmap = ddata->regmap; |
647 | priv->clk = ddata->clk; |
648 | priv->max_arr = ddata->max_arr; |
649 | |
650 | if (!priv->regmap || !priv->clk) |
651 | return -EINVAL; |
652 | |
653 | ret = stm32_pwm_probe_breakinputs(priv, np); |
654 | if (ret) |
655 | return ret; |
656 | |
657 | stm32_pwm_detect_complementary(priv); |
658 | |
659 | chip->ops = &stm32pwm_ops; |
660 | |
661 | /* Initialize clock refcount to number of enabled PWM channels. */ |
662 | for (i = 0; i < num_enabled; i++) |
663 | clk_enable(clk: priv->clk); |
664 | |
665 | ret = devm_pwmchip_add(dev, chip); |
666 | if (ret < 0) |
667 | return ret; |
668 | |
669 | platform_set_drvdata(pdev, data: chip); |
670 | |
671 | return 0; |
672 | } |
673 | |
674 | static int stm32_pwm_suspend(struct device *dev) |
675 | { |
676 | struct pwm_chip *chip = dev_get_drvdata(dev); |
677 | struct stm32_pwm *priv = to_stm32_pwm_dev(chip); |
678 | unsigned int i; |
679 | u32 ccer, mask; |
680 | |
681 | /* Look for active channels */ |
682 | ccer = active_channels(dev: priv); |
683 | |
684 | for (i = 0; i < chip->npwm; i++) { |
685 | mask = TIM_CCER_CC1E << (i * 4); |
686 | if (ccer & mask) { |
687 | dev_err(dev, "PWM %u still in use by consumer %s\n" , |
688 | i, chip->pwms[i].label); |
689 | return -EBUSY; |
690 | } |
691 | } |
692 | |
693 | return pinctrl_pm_select_sleep_state(dev); |
694 | } |
695 | |
696 | static int stm32_pwm_resume(struct device *dev) |
697 | { |
698 | struct pwm_chip *chip = dev_get_drvdata(dev); |
699 | struct stm32_pwm *priv = to_stm32_pwm_dev(chip); |
700 | int ret; |
701 | |
702 | ret = pinctrl_pm_select_default_state(dev); |
703 | if (ret) |
704 | return ret; |
705 | |
706 | /* restore breakinput registers that may have been lost in low power */ |
707 | return stm32_pwm_apply_breakinputs(priv); |
708 | } |
709 | |
710 | static DEFINE_SIMPLE_DEV_PM_OPS(stm32_pwm_pm_ops, stm32_pwm_suspend, stm32_pwm_resume); |
711 | |
712 | static const struct of_device_id stm32_pwm_of_match[] = { |
713 | { .compatible = "st,stm32-pwm" , }, |
714 | { /* end node */ }, |
715 | }; |
716 | MODULE_DEVICE_TABLE(of, stm32_pwm_of_match); |
717 | |
718 | static struct platform_driver stm32_pwm_driver = { |
719 | .probe = stm32_pwm_probe, |
720 | .driver = { |
721 | .name = "stm32-pwm" , |
722 | .of_match_table = stm32_pwm_of_match, |
723 | .pm = pm_ptr(&stm32_pwm_pm_ops), |
724 | }, |
725 | }; |
726 | module_platform_driver(stm32_pwm_driver); |
727 | |
728 | MODULE_ALIAS("platform:stm32-pwm" ); |
729 | MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver" ); |
730 | MODULE_LICENSE("GPL v2" ); |
731 | |