1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * rtc-twl.c -- TWL Real Time Clock interface |
4 | * |
5 | * Copyright (C) 2007 MontaVista Software, Inc |
6 | * Author: Alexandre Rusev <source@mvista.com> |
7 | * |
8 | * Based on original TI driver twl4030-rtc.c |
9 | * Copyright (C) 2006 Texas Instruments, Inc. |
10 | * |
11 | * Based on rtc-omap.c |
12 | * Copyright (C) 2003 MontaVista Software, Inc. |
13 | * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com> |
14 | * Copyright (C) 2006 David Brownell |
15 | */ |
16 | |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | |
19 | #include <linux/kernel.h> |
20 | #include <linux/errno.h> |
21 | #include <linux/init.h> |
22 | #include <linux/module.h> |
23 | #include <linux/types.h> |
24 | #include <linux/rtc.h> |
25 | #include <linux/bcd.h> |
26 | #include <linux/platform_device.h> |
27 | #include <linux/interrupt.h> |
28 | #include <linux/of.h> |
29 | |
30 | #include <linux/mfd/twl.h> |
31 | |
32 | enum twl_class { |
33 | TWL_4030 = 0, |
34 | TWL_6030, |
35 | }; |
36 | |
37 | /* |
38 | * RTC block register offsets (use TWL_MODULE_RTC) |
39 | */ |
40 | enum { |
41 | REG_SECONDS_REG = 0, |
42 | REG_MINUTES_REG, |
43 | REG_HOURS_REG, |
44 | REG_DAYS_REG, |
45 | REG_MONTHS_REG, |
46 | REG_YEARS_REG, |
47 | REG_WEEKS_REG, |
48 | |
49 | REG_ALARM_SECONDS_REG, |
50 | REG_ALARM_MINUTES_REG, |
51 | REG_ALARM_HOURS_REG, |
52 | REG_ALARM_DAYS_REG, |
53 | REG_ALARM_MONTHS_REG, |
54 | REG_ALARM_YEARS_REG, |
55 | |
56 | REG_RTC_CTRL_REG, |
57 | REG_RTC_STATUS_REG, |
58 | REG_RTC_INTERRUPTS_REG, |
59 | |
60 | REG_RTC_COMP_LSB_REG, |
61 | REG_RTC_COMP_MSB_REG, |
62 | }; |
63 | static const u8 twl4030_rtc_reg_map[] = { |
64 | [REG_SECONDS_REG] = 0x00, |
65 | [REG_MINUTES_REG] = 0x01, |
66 | [REG_HOURS_REG] = 0x02, |
67 | [REG_DAYS_REG] = 0x03, |
68 | [REG_MONTHS_REG] = 0x04, |
69 | [REG_YEARS_REG] = 0x05, |
70 | [REG_WEEKS_REG] = 0x06, |
71 | |
72 | [REG_ALARM_SECONDS_REG] = 0x07, |
73 | [REG_ALARM_MINUTES_REG] = 0x08, |
74 | [REG_ALARM_HOURS_REG] = 0x09, |
75 | [REG_ALARM_DAYS_REG] = 0x0A, |
76 | [REG_ALARM_MONTHS_REG] = 0x0B, |
77 | [REG_ALARM_YEARS_REG] = 0x0C, |
78 | |
79 | [REG_RTC_CTRL_REG] = 0x0D, |
80 | [REG_RTC_STATUS_REG] = 0x0E, |
81 | [REG_RTC_INTERRUPTS_REG] = 0x0F, |
82 | |
83 | [REG_RTC_COMP_LSB_REG] = 0x10, |
84 | [REG_RTC_COMP_MSB_REG] = 0x11, |
85 | }; |
86 | static const u8 twl6030_rtc_reg_map[] = { |
87 | [REG_SECONDS_REG] = 0x00, |
88 | [REG_MINUTES_REG] = 0x01, |
89 | [REG_HOURS_REG] = 0x02, |
90 | [REG_DAYS_REG] = 0x03, |
91 | [REG_MONTHS_REG] = 0x04, |
92 | [REG_YEARS_REG] = 0x05, |
93 | [REG_WEEKS_REG] = 0x06, |
94 | |
95 | [REG_ALARM_SECONDS_REG] = 0x08, |
96 | [REG_ALARM_MINUTES_REG] = 0x09, |
97 | [REG_ALARM_HOURS_REG] = 0x0A, |
98 | [REG_ALARM_DAYS_REG] = 0x0B, |
99 | [REG_ALARM_MONTHS_REG] = 0x0C, |
100 | [REG_ALARM_YEARS_REG] = 0x0D, |
101 | |
102 | [REG_RTC_CTRL_REG] = 0x10, |
103 | [REG_RTC_STATUS_REG] = 0x11, |
104 | [REG_RTC_INTERRUPTS_REG] = 0x12, |
105 | |
106 | [REG_RTC_COMP_LSB_REG] = 0x13, |
107 | [REG_RTC_COMP_MSB_REG] = 0x14, |
108 | }; |
109 | |
110 | /* RTC_CTRL_REG bitfields */ |
111 | #define BIT_RTC_CTRL_REG_STOP_RTC_M 0x01 |
112 | #define BIT_RTC_CTRL_REG_ROUND_30S_M 0x02 |
113 | #define BIT_RTC_CTRL_REG_AUTO_COMP_M 0x04 |
114 | #define BIT_RTC_CTRL_REG_MODE_12_24_M 0x08 |
115 | #define BIT_RTC_CTRL_REG_TEST_MODE_M 0x10 |
116 | #define BIT_RTC_CTRL_REG_SET_32_COUNTER_M 0x20 |
117 | #define BIT_RTC_CTRL_REG_GET_TIME_M 0x40 |
118 | #define BIT_RTC_CTRL_REG_RTC_V_OPT 0x80 |
119 | |
120 | /* RTC_STATUS_REG bitfields */ |
121 | #define BIT_RTC_STATUS_REG_RUN_M 0x02 |
122 | #define BIT_RTC_STATUS_REG_1S_EVENT_M 0x04 |
123 | #define BIT_RTC_STATUS_REG_1M_EVENT_M 0x08 |
124 | #define BIT_RTC_STATUS_REG_1H_EVENT_M 0x10 |
125 | #define BIT_RTC_STATUS_REG_1D_EVENT_M 0x20 |
126 | #define BIT_RTC_STATUS_REG_ALARM_M 0x40 |
127 | #define BIT_RTC_STATUS_REG_POWER_UP_M 0x80 |
128 | |
129 | /* RTC_INTERRUPTS_REG bitfields */ |
130 | #define BIT_RTC_INTERRUPTS_REG_EVERY_M 0x03 |
131 | #define BIT_RTC_INTERRUPTS_REG_IT_TIMER_M 0x04 |
132 | #define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M 0x08 |
133 | |
134 | |
135 | /* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */ |
136 | #define ALL_TIME_REGS 6 |
137 | |
138 | /*----------------------------------------------------------------------*/ |
139 | struct twl_rtc { |
140 | struct device *dev; |
141 | struct rtc_device *rtc; |
142 | u8 *reg_map; |
143 | /* |
144 | * Cache the value for timer/alarm interrupts register; this is |
145 | * only changed by callers holding rtc ops lock (or resume). |
146 | */ |
147 | unsigned char rtc_irq_bits; |
148 | bool wake_enabled; |
149 | #ifdef CONFIG_PM_SLEEP |
150 | unsigned char irqstat; |
151 | #endif |
152 | enum twl_class class; |
153 | }; |
154 | |
155 | /* |
156 | * Supports 1 byte read from TWL RTC register. |
157 | */ |
158 | static int twl_rtc_read_u8(struct twl_rtc *twl_rtc, u8 *data, u8 reg) |
159 | { |
160 | int ret; |
161 | |
162 | ret = twl_i2c_read_u8(mod_no: TWL_MODULE_RTC, val: data, reg: (twl_rtc->reg_map[reg])); |
163 | if (ret < 0) |
164 | pr_err("Could not read TWL register %X - error %d\n" , reg, ret); |
165 | return ret; |
166 | } |
167 | |
168 | /* |
169 | * Supports 1 byte write to TWL RTC registers. |
170 | */ |
171 | static int twl_rtc_write_u8(struct twl_rtc *twl_rtc, u8 data, u8 reg) |
172 | { |
173 | int ret; |
174 | |
175 | ret = twl_i2c_write_u8(mod_no: TWL_MODULE_RTC, val: data, reg: (twl_rtc->reg_map[reg])); |
176 | if (ret < 0) |
177 | pr_err("Could not write TWL register %X - error %d\n" , |
178 | reg, ret); |
179 | return ret; |
180 | } |
181 | |
182 | /* |
183 | * Enable 1/second update and/or alarm interrupts. |
184 | */ |
185 | static int set_rtc_irq_bit(struct twl_rtc *twl_rtc, unsigned char bit) |
186 | { |
187 | unsigned char val; |
188 | int ret; |
189 | |
190 | /* if the bit is set, return from here */ |
191 | if (twl_rtc->rtc_irq_bits & bit) |
192 | return 0; |
193 | |
194 | val = twl_rtc->rtc_irq_bits | bit; |
195 | val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M; |
196 | ret = twl_rtc_write_u8(twl_rtc, data: val, reg: REG_RTC_INTERRUPTS_REG); |
197 | if (ret == 0) |
198 | twl_rtc->rtc_irq_bits = val; |
199 | |
200 | return ret; |
201 | } |
202 | |
203 | /* |
204 | * Disable update and/or alarm interrupts. |
205 | */ |
206 | static int mask_rtc_irq_bit(struct twl_rtc *twl_rtc, unsigned char bit) |
207 | { |
208 | unsigned char val; |
209 | int ret; |
210 | |
211 | /* if the bit is clear, return from here */ |
212 | if (!(twl_rtc->rtc_irq_bits & bit)) |
213 | return 0; |
214 | |
215 | val = twl_rtc->rtc_irq_bits & ~bit; |
216 | ret = twl_rtc_write_u8(twl_rtc, data: val, reg: REG_RTC_INTERRUPTS_REG); |
217 | if (ret == 0) |
218 | twl_rtc->rtc_irq_bits = val; |
219 | |
220 | return ret; |
221 | } |
222 | |
223 | static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled) |
224 | { |
225 | struct platform_device *pdev = to_platform_device(dev); |
226 | struct twl_rtc *twl_rtc = dev_get_drvdata(dev); |
227 | int irq = platform_get_irq(pdev, 0); |
228 | int ret; |
229 | |
230 | if (enabled) { |
231 | ret = set_rtc_irq_bit(twl_rtc, |
232 | BIT_RTC_INTERRUPTS_REG_IT_ALARM_M); |
233 | if (device_can_wakeup(dev) && !twl_rtc->wake_enabled) { |
234 | enable_irq_wake(irq); |
235 | twl_rtc->wake_enabled = true; |
236 | } |
237 | } else { |
238 | ret = mask_rtc_irq_bit(twl_rtc, |
239 | BIT_RTC_INTERRUPTS_REG_IT_ALARM_M); |
240 | if (twl_rtc->wake_enabled) { |
241 | disable_irq_wake(irq); |
242 | twl_rtc->wake_enabled = false; |
243 | } |
244 | } |
245 | |
246 | return ret; |
247 | } |
248 | |
249 | /* |
250 | * Gets current TWL RTC time and date parameters. |
251 | * |
252 | * The RTC's time/alarm representation is not what gmtime(3) requires |
253 | * Linux to use: |
254 | * |
255 | * - Months are 1..12 vs Linux 0-11 |
256 | * - Years are 0..99 vs Linux 1900..N (we assume 21st century) |
257 | */ |
258 | static int twl_rtc_read_time(struct device *dev, struct rtc_time *tm) |
259 | { |
260 | struct twl_rtc *twl_rtc = dev_get_drvdata(dev); |
261 | unsigned char rtc_data[ALL_TIME_REGS]; |
262 | int ret; |
263 | u8 save_control; |
264 | u8 rtc_control; |
265 | |
266 | ret = twl_rtc_read_u8(twl_rtc, data: &save_control, reg: REG_RTC_CTRL_REG); |
267 | if (ret < 0) { |
268 | dev_err(dev, "%s: reading CTRL_REG, error %d\n" , __func__, ret); |
269 | return ret; |
270 | } |
271 | /* for twl6030/32 make sure BIT_RTC_CTRL_REG_GET_TIME_M is clear */ |
272 | if (twl_rtc->class == TWL_6030) { |
273 | if (save_control & BIT_RTC_CTRL_REG_GET_TIME_M) { |
274 | save_control &= ~BIT_RTC_CTRL_REG_GET_TIME_M; |
275 | ret = twl_rtc_write_u8(twl_rtc, data: save_control, |
276 | reg: REG_RTC_CTRL_REG); |
277 | if (ret < 0) { |
278 | dev_err(dev, "%s clr GET_TIME, error %d\n" , |
279 | __func__, ret); |
280 | return ret; |
281 | } |
282 | } |
283 | } |
284 | |
285 | /* Copy RTC counting registers to static registers or latches */ |
286 | rtc_control = save_control | BIT_RTC_CTRL_REG_GET_TIME_M; |
287 | |
288 | /* for twl6030/32 enable read access to static shadowed registers */ |
289 | if (twl_rtc->class == TWL_6030) |
290 | rtc_control |= BIT_RTC_CTRL_REG_RTC_V_OPT; |
291 | |
292 | ret = twl_rtc_write_u8(twl_rtc, data: rtc_control, reg: REG_RTC_CTRL_REG); |
293 | if (ret < 0) { |
294 | dev_err(dev, "%s: writing CTRL_REG, error %d\n" , __func__, ret); |
295 | return ret; |
296 | } |
297 | |
298 | ret = twl_i2c_read(mod_no: TWL_MODULE_RTC, value: rtc_data, |
299 | reg: (twl_rtc->reg_map[REG_SECONDS_REG]), ALL_TIME_REGS); |
300 | |
301 | if (ret < 0) { |
302 | dev_err(dev, "%s: reading data, error %d\n" , __func__, ret); |
303 | return ret; |
304 | } |
305 | |
306 | /* for twl6030 restore original state of rtc control register */ |
307 | if (twl_rtc->class == TWL_6030) { |
308 | ret = twl_rtc_write_u8(twl_rtc, data: save_control, reg: REG_RTC_CTRL_REG); |
309 | if (ret < 0) { |
310 | dev_err(dev, "%s: restore CTRL_REG, error %d\n" , |
311 | __func__, ret); |
312 | return ret; |
313 | } |
314 | } |
315 | |
316 | tm->tm_sec = bcd2bin(rtc_data[0]); |
317 | tm->tm_min = bcd2bin(rtc_data[1]); |
318 | tm->tm_hour = bcd2bin(rtc_data[2]); |
319 | tm->tm_mday = bcd2bin(rtc_data[3]); |
320 | tm->tm_mon = bcd2bin(rtc_data[4]) - 1; |
321 | tm->tm_year = bcd2bin(rtc_data[5]) + 100; |
322 | |
323 | return ret; |
324 | } |
325 | |
326 | static int twl_rtc_set_time(struct device *dev, struct rtc_time *tm) |
327 | { |
328 | struct twl_rtc *twl_rtc = dev_get_drvdata(dev); |
329 | unsigned char save_control; |
330 | unsigned char rtc_data[ALL_TIME_REGS]; |
331 | int ret; |
332 | |
333 | rtc_data[0] = bin2bcd(tm->tm_sec); |
334 | rtc_data[1] = bin2bcd(tm->tm_min); |
335 | rtc_data[2] = bin2bcd(tm->tm_hour); |
336 | rtc_data[3] = bin2bcd(tm->tm_mday); |
337 | rtc_data[4] = bin2bcd(tm->tm_mon + 1); |
338 | rtc_data[5] = bin2bcd(tm->tm_year - 100); |
339 | |
340 | /* Stop RTC while updating the TC registers */ |
341 | ret = twl_rtc_read_u8(twl_rtc, data: &save_control, reg: REG_RTC_CTRL_REG); |
342 | if (ret < 0) |
343 | goto out; |
344 | |
345 | save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M; |
346 | ret = twl_rtc_write_u8(twl_rtc, data: save_control, reg: REG_RTC_CTRL_REG); |
347 | if (ret < 0) |
348 | goto out; |
349 | |
350 | /* update all the time registers in one shot */ |
351 | ret = twl_i2c_write(mod_no: TWL_MODULE_RTC, value: rtc_data, |
352 | reg: (twl_rtc->reg_map[REG_SECONDS_REG]), ALL_TIME_REGS); |
353 | if (ret < 0) { |
354 | dev_err(dev, "rtc_set_time error %d\n" , ret); |
355 | goto out; |
356 | } |
357 | |
358 | /* Start back RTC */ |
359 | save_control |= BIT_RTC_CTRL_REG_STOP_RTC_M; |
360 | ret = twl_rtc_write_u8(twl_rtc, data: save_control, reg: REG_RTC_CTRL_REG); |
361 | |
362 | out: |
363 | return ret; |
364 | } |
365 | |
366 | /* |
367 | * Gets current TWL RTC alarm time. |
368 | */ |
369 | static int twl_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm) |
370 | { |
371 | struct twl_rtc *twl_rtc = dev_get_drvdata(dev); |
372 | unsigned char rtc_data[ALL_TIME_REGS]; |
373 | int ret; |
374 | |
375 | ret = twl_i2c_read(mod_no: TWL_MODULE_RTC, value: rtc_data, |
376 | reg: twl_rtc->reg_map[REG_ALARM_SECONDS_REG], ALL_TIME_REGS); |
377 | if (ret < 0) { |
378 | dev_err(dev, "rtc_read_alarm error %d\n" , ret); |
379 | return ret; |
380 | } |
381 | |
382 | /* some of these fields may be wildcard/"match all" */ |
383 | alm->time.tm_sec = bcd2bin(rtc_data[0]); |
384 | alm->time.tm_min = bcd2bin(rtc_data[1]); |
385 | alm->time.tm_hour = bcd2bin(rtc_data[2]); |
386 | alm->time.tm_mday = bcd2bin(rtc_data[3]); |
387 | alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1; |
388 | alm->time.tm_year = bcd2bin(rtc_data[5]) + 100; |
389 | |
390 | /* report cached alarm enable state */ |
391 | if (twl_rtc->rtc_irq_bits & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M) |
392 | alm->enabled = 1; |
393 | |
394 | return ret; |
395 | } |
396 | |
397 | static int twl_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) |
398 | { |
399 | struct twl_rtc *twl_rtc = dev_get_drvdata(dev); |
400 | |
401 | unsigned char alarm_data[ALL_TIME_REGS]; |
402 | int ret; |
403 | |
404 | ret = twl_rtc_alarm_irq_enable(dev, enabled: 0); |
405 | if (ret) |
406 | goto out; |
407 | |
408 | alarm_data[0] = bin2bcd(alm->time.tm_sec); |
409 | alarm_data[1] = bin2bcd(alm->time.tm_min); |
410 | alarm_data[2] = bin2bcd(alm->time.tm_hour); |
411 | alarm_data[3] = bin2bcd(alm->time.tm_mday); |
412 | alarm_data[4] = bin2bcd(alm->time.tm_mon + 1); |
413 | alarm_data[5] = bin2bcd(alm->time.tm_year - 100); |
414 | |
415 | /* update all the alarm registers in one shot */ |
416 | ret = twl_i2c_write(mod_no: TWL_MODULE_RTC, value: alarm_data, |
417 | reg: twl_rtc->reg_map[REG_ALARM_SECONDS_REG], ALL_TIME_REGS); |
418 | if (ret) { |
419 | dev_err(dev, "rtc_set_alarm error %d\n" , ret); |
420 | goto out; |
421 | } |
422 | |
423 | if (alm->enabled) |
424 | ret = twl_rtc_alarm_irq_enable(dev, enabled: 1); |
425 | out: |
426 | return ret; |
427 | } |
428 | |
429 | static irqreturn_t twl_rtc_interrupt(int irq, void *data) |
430 | { |
431 | struct twl_rtc *twl_rtc = data; |
432 | unsigned long events; |
433 | int ret = IRQ_NONE; |
434 | int res; |
435 | u8 rd_reg; |
436 | |
437 | res = twl_rtc_read_u8(twl_rtc, data: &rd_reg, reg: REG_RTC_STATUS_REG); |
438 | if (res) |
439 | goto out; |
440 | /* |
441 | * Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG. |
442 | * only one (ALARM or RTC) interrupt source may be enabled |
443 | * at time, we also could check our results |
444 | * by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM] |
445 | */ |
446 | if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M) |
447 | events = RTC_IRQF | RTC_AF; |
448 | else |
449 | events = RTC_IRQF | RTC_PF; |
450 | |
451 | res = twl_rtc_write_u8(twl_rtc, BIT_RTC_STATUS_REG_ALARM_M, |
452 | reg: REG_RTC_STATUS_REG); |
453 | if (res) |
454 | goto out; |
455 | |
456 | if (twl_rtc->class == TWL_4030) { |
457 | /* Clear on Read enabled. RTC_IT bit of TWL4030_INT_PWR_ISR1 |
458 | * needs 2 reads to clear the interrupt. One read is done in |
459 | * do_twl_pwrirq(). Doing the second read, to clear |
460 | * the bit. |
461 | * |
462 | * FIXME the reason PWR_ISR1 needs an extra read is that |
463 | * RTC_IF retriggered until we cleared REG_ALARM_M above. |
464 | * But re-reading like this is a bad hack; by doing so we |
465 | * risk wrongly clearing status for some other IRQ (losing |
466 | * the interrupt). Be smarter about handling RTC_UF ... |
467 | */ |
468 | res = twl_i2c_read_u8(mod_no: TWL4030_MODULE_INT, |
469 | val: &rd_reg, TWL4030_INT_PWR_ISR1); |
470 | if (res) |
471 | goto out; |
472 | } |
473 | |
474 | /* Notify RTC core on event */ |
475 | rtc_update_irq(rtc: twl_rtc->rtc, num: 1, events); |
476 | |
477 | ret = IRQ_HANDLED; |
478 | out: |
479 | return ret; |
480 | } |
481 | |
482 | static const struct rtc_class_ops twl_rtc_ops = { |
483 | .read_time = twl_rtc_read_time, |
484 | .set_time = twl_rtc_set_time, |
485 | .read_alarm = twl_rtc_read_alarm, |
486 | .set_alarm = twl_rtc_set_alarm, |
487 | .alarm_irq_enable = twl_rtc_alarm_irq_enable, |
488 | }; |
489 | |
490 | static int twl_nvram_read(void *priv, unsigned int offset, void *val, |
491 | size_t bytes) |
492 | { |
493 | return twl_i2c_read(mod_no: (long)priv, value: val, reg: offset, num_bytes: bytes); |
494 | } |
495 | |
496 | static int twl_nvram_write(void *priv, unsigned int offset, void *val, |
497 | size_t bytes) |
498 | { |
499 | return twl_i2c_write(mod_no: (long)priv, value: val, reg: offset, num_bytes: bytes); |
500 | } |
501 | |
502 | /*----------------------------------------------------------------------*/ |
503 | |
504 | static int twl_rtc_probe(struct platform_device *pdev) |
505 | { |
506 | struct twl_rtc *twl_rtc; |
507 | struct nvmem_config nvmem_cfg; |
508 | struct device_node *np = pdev->dev.of_node; |
509 | int ret = -EINVAL; |
510 | int irq = platform_get_irq(pdev, 0); |
511 | u8 rd_reg; |
512 | |
513 | if (!np) { |
514 | dev_err(&pdev->dev, "no DT info\n" ); |
515 | return -EINVAL; |
516 | } |
517 | |
518 | if (irq <= 0) |
519 | return ret; |
520 | |
521 | twl_rtc = devm_kzalloc(dev: &pdev->dev, size: sizeof(*twl_rtc), GFP_KERNEL); |
522 | if (!twl_rtc) |
523 | return -ENOMEM; |
524 | |
525 | if (twl_class_is_4030()) { |
526 | twl_rtc->class = TWL_4030; |
527 | twl_rtc->reg_map = (u8 *)twl4030_rtc_reg_map; |
528 | } else if (twl_class_is_6030()) { |
529 | twl_rtc->class = TWL_6030; |
530 | twl_rtc->reg_map = (u8 *)twl6030_rtc_reg_map; |
531 | } else { |
532 | dev_err(&pdev->dev, "TWL Class not supported.\n" ); |
533 | return -EINVAL; |
534 | } |
535 | |
536 | ret = twl_rtc_read_u8(twl_rtc, data: &rd_reg, reg: REG_RTC_STATUS_REG); |
537 | if (ret < 0) |
538 | return ret; |
539 | |
540 | if (rd_reg & BIT_RTC_STATUS_REG_POWER_UP_M) |
541 | dev_warn(&pdev->dev, "Power up reset detected.\n" ); |
542 | |
543 | if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M) |
544 | dev_warn(&pdev->dev, "Pending Alarm interrupt detected.\n" ); |
545 | |
546 | /* Clear RTC Power up reset and pending alarm interrupts */ |
547 | ret = twl_rtc_write_u8(twl_rtc, data: rd_reg, reg: REG_RTC_STATUS_REG); |
548 | if (ret < 0) |
549 | return ret; |
550 | |
551 | if (twl_rtc->class == TWL_6030) { |
552 | twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK, |
553 | REG_INT_MSK_LINE_A); |
554 | twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK, |
555 | REG_INT_MSK_STS_A); |
556 | } |
557 | |
558 | ret = twl_rtc_write_u8(twl_rtc, BIT_RTC_CTRL_REG_STOP_RTC_M, |
559 | reg: REG_RTC_CTRL_REG); |
560 | if (ret < 0) |
561 | return ret; |
562 | |
563 | /* ensure interrupts are disabled, bootloaders can be strange */ |
564 | ret = twl_rtc_write_u8(twl_rtc, data: 0, reg: REG_RTC_INTERRUPTS_REG); |
565 | if (ret < 0) |
566 | dev_warn(&pdev->dev, "unable to disable interrupt\n" ); |
567 | |
568 | /* init cached IRQ enable bits */ |
569 | ret = twl_rtc_read_u8(twl_rtc, data: &twl_rtc->rtc_irq_bits, |
570 | reg: REG_RTC_INTERRUPTS_REG); |
571 | if (ret < 0) |
572 | return ret; |
573 | |
574 | platform_set_drvdata(pdev, data: twl_rtc); |
575 | device_init_wakeup(dev: &pdev->dev, enable: 1); |
576 | |
577 | twl_rtc->rtc = devm_rtc_device_register(dev: &pdev->dev, name: pdev->name, |
578 | ops: &twl_rtc_ops, THIS_MODULE); |
579 | if (IS_ERR(ptr: twl_rtc->rtc)) |
580 | return PTR_ERR(ptr: twl_rtc->rtc); |
581 | |
582 | ret = devm_request_threaded_irq(dev: &pdev->dev, irq, NULL, |
583 | thread_fn: twl_rtc_interrupt, |
584 | IRQF_TRIGGER_RISING | IRQF_ONESHOT, |
585 | devname: dev_name(dev: &twl_rtc->rtc->dev), dev_id: twl_rtc); |
586 | if (ret < 0) { |
587 | dev_err(&pdev->dev, "IRQ is not free.\n" ); |
588 | return ret; |
589 | } |
590 | |
591 | memset(&nvmem_cfg, 0, sizeof(nvmem_cfg)); |
592 | nvmem_cfg.name = "twl-secured-" ; |
593 | nvmem_cfg.type = NVMEM_TYPE_BATTERY_BACKED; |
594 | nvmem_cfg.reg_read = twl_nvram_read, |
595 | nvmem_cfg.reg_write = twl_nvram_write, |
596 | nvmem_cfg.word_size = 1; |
597 | nvmem_cfg.stride = 1; |
598 | if (twl_class_is_4030()) { |
599 | /* 20 bytes SECURED_REG area */ |
600 | nvmem_cfg.size = 20; |
601 | nvmem_cfg.priv = (void *)TWL_MODULE_SECURED_REG; |
602 | devm_rtc_nvmem_register(rtc: twl_rtc->rtc, nvmem_config: &nvmem_cfg); |
603 | /* 8 bytes BACKUP area */ |
604 | nvmem_cfg.name = "twl-backup-" ; |
605 | nvmem_cfg.size = 8; |
606 | nvmem_cfg.priv = (void *)TWL4030_MODULE_BACKUP; |
607 | devm_rtc_nvmem_register(rtc: twl_rtc->rtc, nvmem_config: &nvmem_cfg); |
608 | } else { |
609 | /* 8 bytes SECURED_REG area */ |
610 | nvmem_cfg.size = 8; |
611 | nvmem_cfg.priv = (void *)TWL_MODULE_SECURED_REG; |
612 | devm_rtc_nvmem_register(rtc: twl_rtc->rtc, nvmem_config: &nvmem_cfg); |
613 | } |
614 | |
615 | return 0; |
616 | } |
617 | |
618 | /* |
619 | * Disable all TWL RTC module interrupts. |
620 | * Sets status flag to free. |
621 | */ |
622 | static void twl_rtc_remove(struct platform_device *pdev) |
623 | { |
624 | struct twl_rtc *twl_rtc = platform_get_drvdata(pdev); |
625 | |
626 | /* leave rtc running, but disable irqs */ |
627 | mask_rtc_irq_bit(twl_rtc, BIT_RTC_INTERRUPTS_REG_IT_ALARM_M); |
628 | mask_rtc_irq_bit(twl_rtc, BIT_RTC_INTERRUPTS_REG_IT_TIMER_M); |
629 | if (twl_rtc->class == TWL_6030) { |
630 | twl6030_interrupt_mask(TWL6030_RTC_INT_MASK, |
631 | REG_INT_MSK_LINE_A); |
632 | twl6030_interrupt_mask(TWL6030_RTC_INT_MASK, |
633 | REG_INT_MSK_STS_A); |
634 | } |
635 | } |
636 | |
637 | static void twl_rtc_shutdown(struct platform_device *pdev) |
638 | { |
639 | struct twl_rtc *twl_rtc = platform_get_drvdata(pdev); |
640 | |
641 | /* mask timer interrupts, but leave alarm interrupts on to enable |
642 | power-on when alarm is triggered */ |
643 | mask_rtc_irq_bit(twl_rtc, BIT_RTC_INTERRUPTS_REG_IT_TIMER_M); |
644 | } |
645 | |
646 | #ifdef CONFIG_PM_SLEEP |
647 | static int twl_rtc_suspend(struct device *dev) |
648 | { |
649 | struct twl_rtc *twl_rtc = dev_get_drvdata(dev); |
650 | |
651 | twl_rtc->irqstat = twl_rtc->rtc_irq_bits; |
652 | |
653 | mask_rtc_irq_bit(twl_rtc, BIT_RTC_INTERRUPTS_REG_IT_TIMER_M); |
654 | return 0; |
655 | } |
656 | |
657 | static int twl_rtc_resume(struct device *dev) |
658 | { |
659 | struct twl_rtc *twl_rtc = dev_get_drvdata(dev); |
660 | |
661 | set_rtc_irq_bit(twl_rtc, bit: twl_rtc->irqstat); |
662 | return 0; |
663 | } |
664 | #endif |
665 | |
666 | static SIMPLE_DEV_PM_OPS(twl_rtc_pm_ops, twl_rtc_suspend, twl_rtc_resume); |
667 | |
668 | static const struct of_device_id twl_rtc_of_match[] = { |
669 | {.compatible = "ti,twl4030-rtc" , }, |
670 | { }, |
671 | }; |
672 | MODULE_DEVICE_TABLE(of, twl_rtc_of_match); |
673 | |
674 | static struct platform_driver twl4030rtc_driver = { |
675 | .probe = twl_rtc_probe, |
676 | .remove_new = twl_rtc_remove, |
677 | .shutdown = twl_rtc_shutdown, |
678 | .driver = { |
679 | .name = "twl_rtc" , |
680 | .pm = &twl_rtc_pm_ops, |
681 | .of_match_table = twl_rtc_of_match, |
682 | }, |
683 | }; |
684 | |
685 | module_platform_driver(twl4030rtc_driver); |
686 | |
687 | MODULE_AUTHOR("Texas Instruments, MontaVista Software" ); |
688 | MODULE_LICENSE("GPL" ); |
689 | |