1 | /* |
2 | * Disk Array driver for HP Smart Array SAS controllers |
3 | * Copyright (c) 2019-2020 Microchip Technology Inc. and its subsidiaries |
4 | * Copyright 2016 Microsemi Corporation |
5 | * Copyright 2014-2015 PMC-Sierra, Inc. |
6 | * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P. |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License as published by |
10 | * the Free Software Foundation; version 2 of the License. |
11 | * |
12 | * This program is distributed in the hope that it will be useful, |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
14 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or |
15 | * NON INFRINGEMENT. See the GNU General Public License for more details. |
16 | * |
17 | * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com |
18 | * |
19 | */ |
20 | #ifndef HPSA_CMD_H |
21 | #define HPSA_CMD_H |
22 | |
23 | #include <linux/compiler.h> |
24 | |
25 | #include <linux/build_bug.h> /* static_assert */ |
26 | #include <linux/stddef.h> /* offsetof */ |
27 | |
28 | /* general boundary defintions */ |
29 | #define SENSEINFOBYTES 32 /* may vary between hbas */ |
30 | #define SG_ENTRIES_IN_CMD 32 /* Max SG entries excluding chain blocks */ |
31 | #define HPSA_SG_CHAIN 0x80000000 |
32 | #define HPSA_SG_LAST 0x40000000 |
33 | #define MAXREPLYQS 256 |
34 | |
35 | /* Command Status value */ |
36 | #define CMD_SUCCESS 0x0000 |
37 | #define CMD_TARGET_STATUS 0x0001 |
38 | #define CMD_DATA_UNDERRUN 0x0002 |
39 | #define CMD_DATA_OVERRUN 0x0003 |
40 | #define CMD_INVALID 0x0004 |
41 | #define CMD_PROTOCOL_ERR 0x0005 |
42 | #define CMD_HARDWARE_ERR 0x0006 |
43 | #define CMD_CONNECTION_LOST 0x0007 |
44 | #define CMD_ABORTED 0x0008 |
45 | #define CMD_ABORT_FAILED 0x0009 |
46 | #define CMD_UNSOLICITED_ABORT 0x000A |
47 | #define CMD_TIMEOUT 0x000B |
48 | #define CMD_UNABORTABLE 0x000C |
49 | #define CMD_TMF_STATUS 0x000D |
50 | #define CMD_IOACCEL_DISABLED 0x000E |
51 | #define CMD_CTLR_LOCKUP 0xffff |
52 | /* Note: CMD_CTLR_LOCKUP is not a value defined by the CISS spec |
53 | * it is a value defined by the driver that commands can be marked |
54 | * with when a controller lockup has been detected by the driver |
55 | */ |
56 | |
57 | /* TMF function status values */ |
58 | #define CISS_TMF_COMPLETE 0x00 |
59 | #define CISS_TMF_INVALID_FRAME 0x02 |
60 | #define CISS_TMF_NOT_SUPPORTED 0x04 |
61 | #define CISS_TMF_FAILED 0x05 |
62 | #define CISS_TMF_SUCCESS 0x08 |
63 | #define CISS_TMF_WRONG_LUN 0x09 |
64 | #define CISS_TMF_OVERLAPPED_TAG 0x0a |
65 | |
66 | /* Unit Attentions ASC's as defined for the MSA2012sa */ |
67 | #define POWER_OR_RESET 0x29 |
68 | #define STATE_CHANGED 0x2a |
69 | #define UNIT_ATTENTION_CLEARED 0x2f |
70 | #define LUN_FAILED 0x3e |
71 | #define REPORT_LUNS_CHANGED 0x3f |
72 | |
73 | /* Unit Attentions ASCQ's as defined for the MSA2012sa */ |
74 | |
75 | /* These ASCQ's defined for ASC = POWER_OR_RESET */ |
76 | #define POWER_ON_RESET 0x00 |
77 | #define POWER_ON_REBOOT 0x01 |
78 | #define SCSI_BUS_RESET 0x02 |
79 | #define MSA_TARGET_RESET 0x03 |
80 | #define CONTROLLER_FAILOVER 0x04 |
81 | #define TRANSCEIVER_SE 0x05 |
82 | #define TRANSCEIVER_LVD 0x06 |
83 | |
84 | /* These ASCQ's defined for ASC = STATE_CHANGED */ |
85 | #define RESERVATION_PREEMPTED 0x03 |
86 | #define ASYM_ACCESS_CHANGED 0x06 |
87 | #define LUN_CAPACITY_CHANGED 0x09 |
88 | |
89 | /* transfer direction */ |
90 | #define XFER_NONE 0x00 |
91 | #define XFER_WRITE 0x01 |
92 | #define XFER_READ 0x02 |
93 | #define XFER_RSVD 0x03 |
94 | |
95 | /* task attribute */ |
96 | #define ATTR_UNTAGGED 0x00 |
97 | #define ATTR_SIMPLE 0x04 |
98 | #define ATTR_HEADOFQUEUE 0x05 |
99 | #define ATTR_ORDERED 0x06 |
100 | #define ATTR_ACA 0x07 |
101 | |
102 | /* cdb type */ |
103 | #define TYPE_CMD 0x00 |
104 | #define TYPE_MSG 0x01 |
105 | #define TYPE_IOACCEL2_CMD 0x81 /* 0x81 is not used by hardware */ |
106 | |
107 | /* Message Types */ |
108 | #define HPSA_TASK_MANAGEMENT 0x00 |
109 | #define HPSA_RESET 0x01 |
110 | #define HPSA_SCAN 0x02 |
111 | #define HPSA_NOOP 0x03 |
112 | |
113 | #define HPSA_CTLR_RESET_TYPE 0x00 |
114 | #define HPSA_BUS_RESET_TYPE 0x01 |
115 | #define HPSA_TARGET_RESET_TYPE 0x03 |
116 | #define HPSA_LUN_RESET_TYPE 0x04 |
117 | #define HPSA_NEXUS_RESET_TYPE 0x05 |
118 | |
119 | /* Task Management Functions */ |
120 | #define HPSA_TMF_ABORT_TASK 0x00 |
121 | #define HPSA_TMF_ABORT_TASK_SET 0x01 |
122 | #define HPSA_TMF_CLEAR_ACA 0x02 |
123 | #define HPSA_TMF_CLEAR_TASK_SET 0x03 |
124 | #define HPSA_TMF_QUERY_TASK 0x04 |
125 | #define HPSA_TMF_QUERY_TASK_SET 0x05 |
126 | #define HPSA_TMF_QUERY_ASYNCEVENT 0x06 |
127 | |
128 | |
129 | |
130 | /* config space register offsets */ |
131 | #define CFG_VENDORID 0x00 |
132 | #define CFG_DEVICEID 0x02 |
133 | #define CFG_I2OBAR 0x10 |
134 | #define CFG_MEM1BAR 0x14 |
135 | |
136 | /* i2o space register offsets */ |
137 | #define I2O_IBDB_SET 0x20 |
138 | #define I2O_IBDB_CLEAR 0x70 |
139 | #define I2O_INT_STATUS 0x30 |
140 | #define I2O_INT_MASK 0x34 |
141 | #define I2O_IBPOST_Q 0x40 |
142 | #define I2O_OBPOST_Q 0x44 |
143 | #define I2O_DMA1_CFG 0x214 |
144 | |
145 | /* Configuration Table */ |
146 | #define CFGTBL_ChangeReq 0x00000001l |
147 | #define CFGTBL_AccCmds 0x00000001l |
148 | #define DOORBELL_CTLR_RESET 0x00000004l |
149 | #define DOORBELL_CTLR_RESET2 0x00000020l |
150 | #define DOORBELL_CLEAR_EVENTS 0x00000040l |
151 | #define DOORBELL_GENERATE_CHKPT 0x00000080l |
152 | |
153 | #define CFGTBL_Trans_Simple 0x00000002l |
154 | #define CFGTBL_Trans_Performant 0x00000004l |
155 | #define CFGTBL_Trans_io_accel1 0x00000080l |
156 | #define CFGTBL_Trans_io_accel2 0x00000100l |
157 | #define CFGTBL_Trans_use_short_tags 0x20000000l |
158 | #define CFGTBL_Trans_enable_directed_msix (1 << 30) |
159 | |
160 | #define CFGTBL_BusType_Ultra2 0x00000001l |
161 | #define CFGTBL_BusType_Ultra3 0x00000002l |
162 | #define CFGTBL_BusType_Fibre1G 0x00000100l |
163 | #define CFGTBL_BusType_Fibre2G 0x00000200l |
164 | |
165 | /* VPD Inquiry types */ |
166 | #define HPSA_INQUIRY_FAILED 0x02 |
167 | #define HPSA_VPD_SUPPORTED_PAGES 0x00 |
168 | #define HPSA_VPD_LV_DEVICE_ID 0x83 |
169 | #define HPSA_VPD_LV_DEVICE_GEOMETRY 0xC1 |
170 | #define HPSA_VPD_LV_IOACCEL_STATUS 0xC2 |
171 | #define HPSA_VPD_LV_STATUS 0xC3 |
172 | #define 4 |
173 | |
174 | /* Logical volume states */ |
175 | #define HPSA_VPD_LV_STATUS_UNSUPPORTED 0xff |
176 | #define HPSA_LV_OK 0x0 |
177 | #define HPSA_LV_FAILED 0x01 |
178 | #define HPSA_LV_NOT_AVAILABLE 0x0b |
179 | #define HPSA_LV_UNDERGOING_ERASE 0x0F |
180 | #define HPSA_LV_UNDERGOING_RPI 0x12 |
181 | #define HPSA_LV_PENDING_RPI 0x13 |
182 | #define HPSA_LV_ENCRYPTED_NO_KEY 0x14 |
183 | #define HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER 0x15 |
184 | #define HPSA_LV_UNDERGOING_ENCRYPTION 0x16 |
185 | #define HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING 0x17 |
186 | #define HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER 0x18 |
187 | #define HPSA_LV_PENDING_ENCRYPTION 0x19 |
188 | #define HPSA_LV_PENDING_ENCRYPTION_REKEYING 0x1A |
189 | |
190 | struct vals32 { |
191 | u32 lower; |
192 | u32 upper; |
193 | }; |
194 | |
195 | union u64bit { |
196 | struct vals32 val32; |
197 | u64 val; |
198 | }; |
199 | |
200 | /* FIXME this is a per controller value (barf!) */ |
201 | #define HPSA_MAX_LUN 1024 |
202 | #define HPSA_MAX_PHYS_LUN 1024 |
203 | #define MAX_EXT_TARGETS 32 |
204 | #define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \ |
205 | MAX_EXT_TARGETS + 1) /* + 1 is for the controller itself */ |
206 | |
207 | /* SCSI-3 Commands */ |
208 | #define HPSA_INQUIRY 0x12 |
209 | struct InquiryData { |
210 | u8 data_byte[36]; |
211 | } __packed; |
212 | |
213 | #define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */ |
214 | #define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */ |
215 | #define HPSA_REPORT_PHYS_EXTENDED 0x02 |
216 | #define HPSA_CISS_READ 0xc0 /* CISS Read */ |
217 | #define HPSA_GET_RAID_MAP 0xc8 /* CISS Get RAID Layout Map */ |
218 | |
219 | #define RAID_MAP_MAX_ENTRIES 256 |
220 | |
221 | struct raid_map_disk_data { |
222 | u32 ioaccel_handle; /**< Handle to access this disk via the |
223 | * I/O accelerator */ |
224 | u8 xor_mult[2]; /**< XOR multipliers for this position, |
225 | * valid for data disks only */ |
226 | u8 reserved[2]; |
227 | } __packed; |
228 | |
229 | struct raid_map_data { |
230 | __le32 structure_size; /* Size of entire structure in bytes */ |
231 | __le32 volume_blk_size; /* bytes / block in the volume */ |
232 | __le64 volume_blk_cnt; /* logical blocks on the volume */ |
233 | u8 phys_blk_shift; /* Shift factor to convert between |
234 | * units of logical blocks and physical |
235 | * disk blocks */ |
236 | u8 parity_rotation_shift; /* Shift factor to convert between units |
237 | * of logical stripes and physical |
238 | * stripes */ |
239 | __le16 strip_size; /* blocks used on each disk / stripe */ |
240 | __le64 disk_starting_blk; /* First disk block used in volume */ |
241 | __le64 disk_blk_cnt; /* disk blocks used by volume / disk */ |
242 | __le16 data_disks_per_row; /* data disk entries / row in the map */ |
243 | __le16 metadata_disks_per_row;/* mirror/parity disk entries / row |
244 | * in the map */ |
245 | __le16 row_cnt; /* rows in each layout map */ |
246 | __le16 layout_map_count; /* layout maps (1 map per mirror/parity |
247 | * group) */ |
248 | __le16 flags; /* Bit 0 set if encryption enabled */ |
249 | #define RAID_MAP_FLAG_ENCRYPT_ON 0x01 |
250 | __le16 dekindex; /* Data encryption key index. */ |
251 | u8 reserved[16]; |
252 | struct raid_map_disk_data data[RAID_MAP_MAX_ENTRIES]; |
253 | } __packed; |
254 | |
255 | struct ReportLUNdata { |
256 | u8 LUNListLength[4]; |
257 | u8 extended_response_flag; |
258 | u8 reserved[3]; |
259 | u8 LUN[HPSA_MAX_LUN][8]; |
260 | } __packed; |
261 | |
262 | struct ext_report_lun_entry { |
263 | u8 lunid[8]; |
264 | #define MASKED_DEVICE(x) ((x)[3] & 0xC0) |
265 | #define GET_BMIC_BUS(lunid) ((lunid)[7] & 0x3F) |
266 | #define GET_BMIC_LEVEL_TWO_TARGET(lunid) ((lunid)[6]) |
267 | #define GET_BMIC_DRIVE_NUMBER(lunid) (((GET_BMIC_BUS((lunid)) - 1) << 8) + \ |
268 | GET_BMIC_LEVEL_TWO_TARGET((lunid))) |
269 | u8 wwid[8]; |
270 | u8 device_type; |
271 | u8 device_flags; |
272 | u8 lun_count; /* multi-lun device, how many luns */ |
273 | u8 redundant_paths; |
274 | u32 ioaccel_handle; /* ioaccel1 only uses lower 16 bits */ |
275 | } __packed; |
276 | |
277 | struct ReportExtendedLUNdata { |
278 | u8 LUNListLength[4]; |
279 | u8 extended_response_flag; |
280 | u8 reserved[3]; |
281 | struct ext_report_lun_entry LUN[HPSA_MAX_PHYS_LUN]; |
282 | } __packed; |
283 | |
284 | struct SenseSubsystem_info { |
285 | u8 reserved[36]; |
286 | u8 portname[8]; |
287 | u8 reserved1[1108]; |
288 | } __packed; |
289 | |
290 | /* BMIC commands */ |
291 | #define BMIC_READ 0x26 |
292 | #define BMIC_WRITE 0x27 |
293 | #define BMIC_CACHE_FLUSH 0xc2 |
294 | #define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */ |
295 | #define BMIC_FLASH_FIRMWARE 0xF7 |
296 | #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64 |
297 | #define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15 |
298 | #define BMIC_IDENTIFY_CONTROLLER 0x11 |
299 | #define BMIC_SET_DIAG_OPTIONS 0xF4 |
300 | #define BMIC_SENSE_DIAG_OPTIONS 0xF5 |
301 | #define HPSA_DIAG_OPTS_DISABLE_RLD_CACHING 0x80000000 |
302 | #define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66 |
303 | #define BMIC_SENSE_STORAGE_BOX_PARAMS 0x65 |
304 | |
305 | /* Command List Structure */ |
306 | union SCSI3Addr { |
307 | struct { |
308 | u8 Dev; |
309 | u8 Bus:6; |
310 | u8 Mode:2; /* b00 */ |
311 | } PeripDev; |
312 | struct { |
313 | u8 DevLSB; |
314 | u8 DevMSB:6; |
315 | u8 Mode:2; /* b01 */ |
316 | } LogDev; |
317 | struct { |
318 | u8 Dev:5; |
319 | u8 Bus:3; |
320 | u8 Targ:6; |
321 | u8 Mode:2; /* b10 */ |
322 | } LogUnit; |
323 | } __packed; |
324 | |
325 | struct PhysDevAddr { |
326 | u32 TargetId:24; |
327 | u32 Bus:6; |
328 | u32 Mode:2; |
329 | /* 2 level target device addr */ |
330 | union SCSI3Addr Target[2]; |
331 | } __packed; |
332 | |
333 | struct LogDevAddr { |
334 | u32 VolId:30; |
335 | u32 Mode:2; |
336 | u8 reserved[4]; |
337 | } __packed; |
338 | |
339 | union LUNAddr { |
340 | u8 LunAddrBytes[8]; |
341 | union SCSI3Addr SCSI3Lun[4]; |
342 | struct PhysDevAddr PhysDev; |
343 | struct LogDevAddr LogDev; |
344 | } __packed; |
345 | |
346 | struct CommandListHeader { |
347 | u8 ReplyQueue; |
348 | u8 SGList; |
349 | __le16 SGTotal; |
350 | __le64 tag; |
351 | union LUNAddr LUN; |
352 | } __packed; |
353 | |
354 | struct RequestBlock { |
355 | u8 CDBLen; |
356 | /* |
357 | * type_attr_dir: |
358 | * type: low 3 bits |
359 | * attr: middle 3 bits |
360 | * dir: high 2 bits |
361 | */ |
362 | u8 type_attr_dir; |
363 | #define TYPE_ATTR_DIR(t, a, d) ((((d) & 0x03) << 6) |\ |
364 | (((a) & 0x07) << 3) |\ |
365 | ((t) & 0x07)) |
366 | #define GET_TYPE(tad) ((tad) & 0x07) |
367 | #define GET_ATTR(tad) (((tad) >> 3) & 0x07) |
368 | #define GET_DIR(tad) (((tad) >> 6) & 0x03) |
369 | u16 Timeout; |
370 | u8 CDB[16]; |
371 | } __packed; |
372 | |
373 | struct ErrDescriptor { |
374 | __le64 Addr; |
375 | __le32 Len; |
376 | } __packed; |
377 | |
378 | struct SGDescriptor { |
379 | __le64 Addr; |
380 | __le32 Len; |
381 | __le32 Ext; |
382 | } __packed; |
383 | |
384 | union MoreErrInfo { |
385 | struct { |
386 | u8 Reserved[3]; |
387 | u8 Type; |
388 | u32 ErrorInfo; |
389 | } Common_Info; |
390 | struct { |
391 | u8 Reserved[2]; |
392 | u8 offense_size; /* size of offending entry */ |
393 | u8 offense_num; /* byte # of offense 0-base */ |
394 | u32 offense_value; |
395 | } Invalid_Cmd; |
396 | } __packed; |
397 | |
398 | struct ErrorInfo { |
399 | u8 ScsiStatus; |
400 | u8 SenseLen; |
401 | u16 CommandStatus; |
402 | u32 ResidualCnt; |
403 | union MoreErrInfo MoreErrInfo; |
404 | u8 SenseInfo[SENSEINFOBYTES]; |
405 | } __packed; |
406 | /* Command types */ |
407 | #define CMD_IOCTL_PEND 0x01 |
408 | #define CMD_SCSI 0x03 |
409 | #define CMD_IOACCEL1 0x04 |
410 | #define CMD_IOACCEL2 0x05 |
411 | #define IOACCEL2_TMF 0x06 |
412 | |
413 | #define DIRECT_LOOKUP_SHIFT 4 |
414 | #define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1)) |
415 | |
416 | #define HPSA_ERROR_BIT 0x02 |
417 | struct ctlr_info; /* defined in hpsa.h */ |
418 | /* The size of this structure needs to be divisible by 128 |
419 | * on all architectures. The low 4 bits of the addresses |
420 | * are used as follows: |
421 | * |
422 | * bit 0: to device, used to indicate "performant mode" command |
423 | * from device, indidcates error status. |
424 | * bit 1-3: to device, indicates block fetch table entry for |
425 | * reducing DMA in fetching commands from host memory. |
426 | */ |
427 | |
428 | #define COMMANDLIST_ALIGNMENT 128 |
429 | struct CommandList { |
430 | struct CommandListHeader Header; |
431 | struct RequestBlock Request; |
432 | struct ErrDescriptor ErrDesc; |
433 | struct SGDescriptor SG[SG_ENTRIES_IN_CMD]; |
434 | /* information associated with the command */ |
435 | u32 busaddr; /* physical addr of this record */ |
436 | struct ErrorInfo *err_info; /* pointer to the allocated mem */ |
437 | struct ctlr_info *h; |
438 | int cmd_type; |
439 | long cmdindex; |
440 | struct completion *waiting; |
441 | struct scsi_cmnd *scsi_cmd; |
442 | struct work_struct work; |
443 | |
444 | /* |
445 | * For commands using either of the two "ioaccel" paths to |
446 | * bypass the RAID stack and go directly to the physical disk |
447 | * phys_disk is a pointer to the hpsa_scsi_dev_t to which the |
448 | * i/o is destined. We need to store that here because the command |
449 | * may potentially encounter TASK SET FULL and need to be resubmitted |
450 | * For "normal" i/o's not using the "ioaccel" paths, phys_disk is |
451 | * not used. |
452 | */ |
453 | struct hpsa_scsi_dev_t *phys_disk; |
454 | |
455 | bool retry_pending; |
456 | struct hpsa_scsi_dev_t *device; |
457 | atomic_t refcount; /* Must be last to avoid memset in hpsa_cmd_init() */ |
458 | } __aligned(COMMANDLIST_ALIGNMENT); |
459 | |
460 | /* |
461 | * Make sure our embedded atomic variable is aligned. Otherwise we break atomic |
462 | * operations on architectures that don't support unaligned atomics like IA64. |
463 | * |
464 | * The assert guards against reintroductin against unwanted __packed to |
465 | * the struct CommandList. |
466 | */ |
467 | static_assert(offsetof(struct CommandList, refcount) % __alignof__(atomic_t) == 0); |
468 | |
469 | /* Max S/G elements in I/O accelerator command */ |
470 | #define IOACCEL1_MAXSGENTRIES 24 |
471 | #define IOACCEL2_MAXSGENTRIES 28 |
472 | |
473 | /* |
474 | * Structure for I/O accelerator (mode 1) commands. |
475 | * Note that this structure must be 128-byte aligned in size. |
476 | */ |
477 | #define IOACCEL1_COMMANDLIST_ALIGNMENT 128 |
478 | struct io_accel1_cmd { |
479 | __le16 dev_handle; /* 0x00 - 0x01 */ |
480 | u8 reserved1; /* 0x02 */ |
481 | u8 function; /* 0x03 */ |
482 | u8 reserved2[8]; /* 0x04 - 0x0B */ |
483 | u32 err_info; /* 0x0C - 0x0F */ |
484 | u8 reserved3[2]; /* 0x10 - 0x11 */ |
485 | u8 err_info_len; /* 0x12 */ |
486 | u8 reserved4; /* 0x13 */ |
487 | u8 sgl_offset; /* 0x14 */ |
488 | u8 reserved5[7]; /* 0x15 - 0x1B */ |
489 | __le32 transfer_len; /* 0x1C - 0x1F */ |
490 | u8 reserved6[4]; /* 0x20 - 0x23 */ |
491 | __le16 io_flags; /* 0x24 - 0x25 */ |
492 | u8 reserved7[14]; /* 0x26 - 0x33 */ |
493 | u8 LUN[8]; /* 0x34 - 0x3B */ |
494 | __le32 control; /* 0x3C - 0x3F */ |
495 | u8 CDB[16]; /* 0x40 - 0x4F */ |
496 | u8 reserved8[16]; /* 0x50 - 0x5F */ |
497 | __le16 host_context_flags; /* 0x60 - 0x61 */ |
498 | __le16 timeout_sec; /* 0x62 - 0x63 */ |
499 | u8 ReplyQueue; /* 0x64 */ |
500 | u8 reserved9[3]; /* 0x65 - 0x67 */ |
501 | __le64 tag; /* 0x68 - 0x6F */ |
502 | __le64 host_addr; /* 0x70 - 0x77 */ |
503 | u8 CISS_LUN[8]; /* 0x78 - 0x7F */ |
504 | struct SGDescriptor SG[IOACCEL1_MAXSGENTRIES]; |
505 | } __packed __aligned(IOACCEL1_COMMANDLIST_ALIGNMENT); |
506 | |
507 | #define IOACCEL1_FUNCTION_SCSIIO 0x00 |
508 | #define IOACCEL1_SGLOFFSET 32 |
509 | |
510 | #define IOACCEL1_IOFLAGS_IO_REQ 0x4000 |
511 | #define IOACCEL1_IOFLAGS_CDBLEN_MASK 0x001F |
512 | #define IOACCEL1_IOFLAGS_CDBLEN_MAX 16 |
513 | |
514 | #define IOACCEL1_CONTROL_NODATAXFER 0x00000000 |
515 | #define IOACCEL1_CONTROL_DATA_OUT 0x01000000 |
516 | #define IOACCEL1_CONTROL_DATA_IN 0x02000000 |
517 | #define IOACCEL1_CONTROL_TASKPRIO_MASK 0x00007800 |
518 | #define IOACCEL1_CONTROL_TASKPRIO_SHIFT 11 |
519 | #define IOACCEL1_CONTROL_SIMPLEQUEUE 0x00000000 |
520 | #define IOACCEL1_CONTROL_HEADOFQUEUE 0x00000100 |
521 | #define IOACCEL1_CONTROL_ORDEREDQUEUE 0x00000200 |
522 | #define IOACCEL1_CONTROL_ACA 0x00000400 |
523 | |
524 | #define IOACCEL1_HCFLAGS_CISS_FORMAT 0x0013 |
525 | |
526 | #define IOACCEL1_BUSADDR_CMDTYPE 0x00000060 |
527 | |
528 | struct ioaccel2_sg_element { |
529 | __le64 address; |
530 | __le32 length; |
531 | u8 reserved[3]; |
532 | u8 chain_indicator; |
533 | #define IOACCEL2_CHAIN 0x80 |
534 | #define IOACCEL2_LAST_SG 0x40 |
535 | } __packed; |
536 | |
537 | /* |
538 | * SCSI Response Format structure for IO Accelerator Mode 2 |
539 | */ |
540 | struct io_accel2_scsi_response { |
541 | u8 IU_type; |
542 | #define IOACCEL2_IU_TYPE_SRF 0x60 |
543 | u8 reserved1[3]; |
544 | u8 req_id[4]; /* request identifier */ |
545 | u8 reserved2[4]; |
546 | u8 serv_response; /* service response */ |
547 | #define IOACCEL2_SERV_RESPONSE_COMPLETE 0x000 |
548 | #define IOACCEL2_SERV_RESPONSE_FAILURE 0x001 |
549 | #define IOACCEL2_SERV_RESPONSE_TMF_COMPLETE 0x002 |
550 | #define IOACCEL2_SERV_RESPONSE_TMF_SUCCESS 0x003 |
551 | #define IOACCEL2_SERV_RESPONSE_TMF_REJECTED 0x004 |
552 | #define IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN 0x005 |
553 | u8 status; /* status */ |
554 | #define IOACCEL2_STATUS_SR_TASK_COMP_GOOD 0x00 |
555 | #define IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND 0x02 |
556 | #define IOACCEL2_STATUS_SR_TASK_COMP_BUSY 0x08 |
557 | #define IOACCEL2_STATUS_SR_TASK_COMP_RES_CON 0x18 |
558 | #define IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL 0x28 |
559 | #define IOACCEL2_STATUS_SR_TASK_COMP_ABORTED 0x40 |
560 | #define IOACCEL2_STATUS_SR_IOACCEL_DISABLED 0x0E |
561 | #define IOACCEL2_STATUS_SR_IO_ERROR 0x01 |
562 | #define IOACCEL2_STATUS_SR_IO_ABORTED 0x02 |
563 | #define IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE 0x03 |
564 | #define IOACCEL2_STATUS_SR_INVALID_DEVICE 0x04 |
565 | #define IOACCEL2_STATUS_SR_UNDERRUN 0x51 |
566 | #define IOACCEL2_STATUS_SR_OVERRUN 0x75 |
567 | u8 data_present; /* low 2 bits */ |
568 | #define IOACCEL2_NO_DATAPRESENT 0x000 |
569 | #define IOACCEL2_RESPONSE_DATAPRESENT 0x001 |
570 | #define IOACCEL2_SENSE_DATA_PRESENT 0x002 |
571 | #define IOACCEL2_RESERVED 0x003 |
572 | u8 sense_data_len; /* sense/response data length */ |
573 | u8 resid_cnt[4]; /* residual count */ |
574 | u8 sense_data_buff[32]; /* sense/response data buffer */ |
575 | } __packed; |
576 | |
577 | /* |
578 | * Structure for I/O accelerator (mode 2 or m2) commands. |
579 | * Note that this structure must be 128-byte aligned in size. |
580 | */ |
581 | #define IOACCEL2_COMMANDLIST_ALIGNMENT 128 |
582 | struct io_accel2_cmd { |
583 | u8 IU_type; /* IU Type */ |
584 | u8 direction; /* direction, memtype, and encryption */ |
585 | #define IOACCEL2_DIRECTION_MASK 0x03 /* bits 0,1: direction */ |
586 | #define IOACCEL2_DIRECTION_MEMTYPE_MASK 0x04 /* bit 2: memtype source/dest */ |
587 | /* 0b=PCIe, 1b=DDR */ |
588 | #define IOACCEL2_DIRECTION_ENCRYPT_MASK 0x08 /* bit 3: encryption flag */ |
589 | /* 0=off, 1=on */ |
590 | u8 reply_queue; /* Reply Queue ID */ |
591 | u8 reserved1; /* Reserved */ |
592 | __le32 scsi_nexus; /* Device Handle */ |
593 | __le32 Tag; /* cciss tag, lower 4 bytes only */ |
594 | __le32 tweak_lower; /* Encryption tweak, lower 4 bytes */ |
595 | u8 cdb[16]; /* SCSI Command Descriptor Block */ |
596 | u8 cciss_lun[8]; /* 8 byte SCSI address */ |
597 | __le32 data_len; /* Total bytes to transfer */ |
598 | u8 cmd_priority_task_attr; /* priority and task attrs */ |
599 | #define IOACCEL2_PRIORITY_MASK 0x78 |
600 | #define IOACCEL2_ATTR_MASK 0x07 |
601 | u8 sg_count; /* Number of sg elements */ |
602 | __le16 dekindex; /* Data encryption key index */ |
603 | __le64 err_ptr; /* Error Pointer */ |
604 | __le32 err_len; /* Error Length*/ |
605 | __le32 tweak_upper; /* Encryption tweak, upper 4 bytes */ |
606 | struct ioaccel2_sg_element sg[IOACCEL2_MAXSGENTRIES]; |
607 | struct io_accel2_scsi_response error_data; |
608 | } __packed __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT); |
609 | |
610 | /* |
611 | * defines for Mode 2 command struct |
612 | * FIXME: this can't be all I need mfm |
613 | */ |
614 | #define IOACCEL2_IU_TYPE 0x40 |
615 | #define IOACCEL2_IU_TMF_TYPE 0x41 |
616 | #define IOACCEL2_DIR_NO_DATA 0x00 |
617 | #define IOACCEL2_DIR_DATA_IN 0x01 |
618 | #define IOACCEL2_DIR_DATA_OUT 0x02 |
619 | #define IOACCEL2_TMF_ABORT 0x01 |
620 | /* |
621 | * SCSI Task Management Request format for Accelerator Mode 2 |
622 | */ |
623 | struct hpsa_tmf_struct { |
624 | u8 iu_type; /* Information Unit Type */ |
625 | u8 reply_queue; /* Reply Queue ID */ |
626 | u8 tmf; /* Task Management Function */ |
627 | u8 reserved1; /* byte 3 Reserved */ |
628 | __le32 it_nexus; /* SCSI I-T Nexus */ |
629 | u8 lun_id[8]; /* LUN ID for TMF request */ |
630 | __le64 tag; /* cciss tag associated w/ request */ |
631 | __le64 abort_tag; /* cciss tag of SCSI cmd or TMF to abort */ |
632 | __le64 error_ptr; /* Error Pointer */ |
633 | __le32 error_len; /* Error Length */ |
634 | } __packed __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT); |
635 | |
636 | /* Configuration Table Structure */ |
637 | struct HostWrite { |
638 | __le32 TransportRequest; |
639 | __le32 command_pool_addr_hi; |
640 | __le32 CoalIntDelay; |
641 | __le32 CoalIntCount; |
642 | } __packed; |
643 | |
644 | #define SIMPLE_MODE 0x02 |
645 | #define PERFORMANT_MODE 0x04 |
646 | #define MEMQ_MODE 0x08 |
647 | #define IOACCEL_MODE_1 0x80 |
648 | |
649 | #define DRIVER_SUPPORT_UA_ENABLE 0x00000001 |
650 | |
651 | struct CfgTable { |
652 | u8 Signature[4]; |
653 | __le32 SpecValence; |
654 | __le32 TransportSupport; |
655 | __le32 TransportActive; |
656 | struct HostWrite HostWrite; |
657 | __le32 CmdsOutMax; |
658 | __le32 BusTypes; |
659 | __le32 TransMethodOffset; |
660 | u8 ServerName[16]; |
661 | __le32 HeartBeat; |
662 | __le32 driver_support; |
663 | #define ENABLE_SCSI_PREFETCH 0x100 |
664 | #define ENABLE_UNIT_ATTN 0x01 |
665 | __le32 MaxScatterGatherElements; |
666 | __le32 MaxLogicalUnits; |
667 | __le32 MaxPhysicalDevices; |
668 | __le32 MaxPhysicalDrivesPerLogicalUnit; |
669 | __le32 MaxPerformantModeCommands; |
670 | __le32 MaxBlockFetch; |
671 | __le32 PowerConservationSupport; |
672 | __le32 PowerConservationEnable; |
673 | __le32 TMFSupportFlags; |
674 | u8 TMFTagMask[8]; |
675 | u8 reserved[0x78 - 0x70]; |
676 | __le32 misc_fw_support; /* offset 0x78 */ |
677 | #define MISC_FW_DOORBELL_RESET 0x02 |
678 | #define MISC_FW_DOORBELL_RESET2 0x010 |
679 | #define MISC_FW_RAID_OFFLOAD_BASIC 0x020 |
680 | #define MISC_FW_EVENT_NOTIFY 0x080 |
681 | u8 driver_version[32]; |
682 | __le32 max_cached_write_size; |
683 | u8 driver_scratchpad[16]; |
684 | __le32 max_error_info_length; |
685 | __le32 io_accel_max_embedded_sg_count; |
686 | __le32 io_accel_request_size_offset; |
687 | __le32 event_notify; |
688 | #define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE (1 << 30) |
689 | #define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE (1 << 31) |
690 | __le32 clear_event_notify; |
691 | } __packed; |
692 | |
693 | #define NUM_BLOCKFETCH_ENTRIES 8 |
694 | struct TransTable_struct { |
695 | __le32 BlockFetch[NUM_BLOCKFETCH_ENTRIES]; |
696 | __le32 RepQSize; |
697 | __le32 RepQCount; |
698 | __le32 RepQCtrAddrLow32; |
699 | __le32 RepQCtrAddrHigh32; |
700 | #define MAX_REPLY_QUEUES 64 |
701 | struct vals32 RepQAddr[MAX_REPLY_QUEUES]; |
702 | } __packed; |
703 | |
704 | struct hpsa_pci_info { |
705 | unsigned char bus; |
706 | unsigned char dev_fn; |
707 | unsigned short domain; |
708 | u32 board_id; |
709 | } __packed; |
710 | |
711 | struct bmic_identify_controller { |
712 | u8 configured_logical_drive_count; /* offset 0 */ |
713 | u8 pad1[153]; |
714 | __le16 extended_logical_unit_count; /* offset 154 */ |
715 | u8 pad2[136]; |
716 | u8 controller_mode; /* offset 292 */ |
717 | u8 pad3[32]; |
718 | } __packed; |
719 | |
720 | |
721 | struct bmic_identify_physical_device { |
722 | u8 scsi_bus; /* SCSI Bus number on controller */ |
723 | u8 scsi_id; /* SCSI ID on this bus */ |
724 | __le16 block_size; /* sector size in bytes */ |
725 | __le32 total_blocks; /* number for sectors on drive */ |
726 | __le32 reserved_blocks; /* controller reserved (RIS) */ |
727 | u8 model[40]; /* Physical Drive Model */ |
728 | u8 serial_number[40]; /* Drive Serial Number */ |
729 | u8 firmware_revision[8]; /* drive firmware revision */ |
730 | u8 scsi_inquiry_bits; /* inquiry byte 7 bits */ |
731 | u8 compaq_drive_stamp; /* 0 means drive not stamped */ |
732 | u8 last_failure_reason; |
733 | #define BMIC_LAST_FAILURE_TOO_SMALL_IN_LOAD_CONFIG 0x01 |
734 | #define BMIC_LAST_FAILURE_ERROR_ERASING_RIS 0x02 |
735 | #define BMIC_LAST_FAILURE_ERROR_SAVING_RIS 0x03 |
736 | #define BMIC_LAST_FAILURE_FAIL_DRIVE_COMMAND 0x04 |
737 | #define BMIC_LAST_FAILURE_MARK_BAD_FAILED 0x05 |
738 | #define BMIC_LAST_FAILURE_MARK_BAD_FAILED_IN_FINISH_REMAP 0x06 |
739 | #define BMIC_LAST_FAILURE_TIMEOUT 0x07 |
740 | #define BMIC_LAST_FAILURE_AUTOSENSE_FAILED 0x08 |
741 | #define BMIC_LAST_FAILURE_MEDIUM_ERROR_1 0x09 |
742 | #define BMIC_LAST_FAILURE_MEDIUM_ERROR_2 0x0a |
743 | #define BMIC_LAST_FAILURE_NOT_READY_BAD_SENSE 0x0b |
744 | #define BMIC_LAST_FAILURE_NOT_READY 0x0c |
745 | #define BMIC_LAST_FAILURE_HARDWARE_ERROR 0x0d |
746 | #define BMIC_LAST_FAILURE_ABORTED_COMMAND 0x0e |
747 | #define BMIC_LAST_FAILURE_WRITE_PROTECTED 0x0f |
748 | #define BMIC_LAST_FAILURE_SPIN_UP_FAILURE_IN_RECOVER 0x10 |
749 | #define BMIC_LAST_FAILURE_REBUILD_WRITE_ERROR 0x11 |
750 | #define BMIC_LAST_FAILURE_TOO_SMALL_IN_HOT_PLUG 0x12 |
751 | #define BMIC_LAST_FAILURE_BUS_RESET_RECOVERY_ABORTED 0x13 |
752 | #define BMIC_LAST_FAILURE_REMOVED_IN_HOT_PLUG 0x14 |
753 | #define BMIC_LAST_FAILURE_INIT_REQUEST_SENSE_FAILED 0x15 |
754 | #define BMIC_LAST_FAILURE_INIT_START_UNIT_FAILED 0x16 |
755 | #define BMIC_LAST_FAILURE_INQUIRY_FAILED 0x17 |
756 | #define BMIC_LAST_FAILURE_NON_DISK_DEVICE 0x18 |
757 | #define BMIC_LAST_FAILURE_READ_CAPACITY_FAILED 0x19 |
758 | #define BMIC_LAST_FAILURE_INVALID_BLOCK_SIZE 0x1a |
759 | #define BMIC_LAST_FAILURE_HOT_PLUG_REQUEST_SENSE_FAILED 0x1b |
760 | #define BMIC_LAST_FAILURE_HOT_PLUG_START_UNIT_FAILED 0x1c |
761 | #define BMIC_LAST_FAILURE_WRITE_ERROR_AFTER_REMAP 0x1d |
762 | #define BMIC_LAST_FAILURE_INIT_RESET_RECOVERY_ABORTED 0x1e |
763 | #define BMIC_LAST_FAILURE_DEFERRED_WRITE_ERROR 0x1f |
764 | #define BMIC_LAST_FAILURE_MISSING_IN_SAVE_RIS 0x20 |
765 | #define BMIC_LAST_FAILURE_WRONG_REPLACE 0x21 |
766 | #define BMIC_LAST_FAILURE_GDP_VPD_INQUIRY_FAILED 0x22 |
767 | #define BMIC_LAST_FAILURE_GDP_MODE_SENSE_FAILED 0x23 |
768 | #define BMIC_LAST_FAILURE_DRIVE_NOT_IN_48BIT_MODE 0x24 |
769 | #define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_HOT_PLUG 0x25 |
770 | #define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_LOAD_CFG 0x26 |
771 | #define BMIC_LAST_FAILURE_PROTOCOL_ADAPTER_FAILED 0x27 |
772 | #define BMIC_LAST_FAILURE_FAULTY_ID_BAY_EMPTY 0x28 |
773 | #define BMIC_LAST_FAILURE_FAULTY_ID_BAY_OCCUPIED 0x29 |
774 | #define BMIC_LAST_FAILURE_FAULTY_ID_INVALID_BAY 0x2a |
775 | #define BMIC_LAST_FAILURE_WRITE_RETRIES_FAILED 0x2b |
776 | |
777 | #define BMIC_LAST_FAILURE_SMART_ERROR_REPORTED 0x37 |
778 | #define BMIC_LAST_FAILURE_PHY_RESET_FAILED 0x38 |
779 | #define BMIC_LAST_FAILURE_ONLY_ONE_CTLR_CAN_SEE_DRIVE 0x40 |
780 | #define BMIC_LAST_FAILURE_KC_VOLUME_FAILED 0x41 |
781 | #define BMIC_LAST_FAILURE_UNEXPECTED_REPLACEMENT 0x42 |
782 | #define BMIC_LAST_FAILURE_OFFLINE_ERASE 0x80 |
783 | #define BMIC_LAST_FAILURE_OFFLINE_TOO_SMALL 0x81 |
784 | #define BMIC_LAST_FAILURE_OFFLINE_DRIVE_TYPE_MIX 0x82 |
785 | #define BMIC_LAST_FAILURE_OFFLINE_ERASE_COMPLETE 0x83 |
786 | |
787 | u8 flags; |
788 | u8 more_flags; |
789 | u8 scsi_lun; /* SCSI LUN for phys drive */ |
790 | u8 yet_more_flags; |
791 | u8 even_more_flags; |
792 | __le32 spi_speed_rules;/* SPI Speed data:Ultra disable diagnose */ |
793 | u8 phys_connector[2]; /* connector number on controller */ |
794 | u8 phys_box_on_bus; /* phys enclosure this drive resides */ |
795 | u8 phys_bay_in_box; /* phys drv bay this drive resides */ |
796 | __le32 rpm; /* Drive rotational speed in rpm */ |
797 | u8 device_type; /* type of drive */ |
798 | #define BMIC_DEVICE_TYPE_CONTROLLER 0x07 |
799 | |
800 | u8 sata_version; /* only valid when drive_type is SATA */ |
801 | __le64 big_total_block_count; |
802 | __le64 ris_starting_lba; |
803 | __le32 ris_size; |
804 | u8 wwid[20]; |
805 | u8 controller_phy_map[32]; |
806 | __le16 phy_count; |
807 | u8 phy_connected_dev_type[256]; |
808 | u8 phy_to_drive_bay_num[256]; |
809 | __le16 phy_to_attached_dev_index[256]; |
810 | u8 box_index; |
811 | u8 reserved; |
812 | __le16 ; |
813 | #define BMIC_PHYS_DRIVE_SUPPORTS_GAS_GAUGE(idphydrv) \ |
814 | (idphydrv->extra_physical_drive_flags & (1 << 10)) |
815 | u8 negotiated_link_rate[256]; |
816 | u8 phy_to_phy_map[256]; |
817 | u8 redundant_path_present_map; |
818 | u8 redundant_path_failure_map; |
819 | u8 active_path_number; |
820 | __le16 alternate_paths_phys_connector[8]; |
821 | u8 alternate_paths_phys_box_on_port[8]; |
822 | u8 multi_lun_device_lun_count; |
823 | u8 minimum_good_fw_revision[8]; |
824 | u8 unique_inquiry_bytes[20]; |
825 | u8 current_temperature_degreesC; |
826 | u8 temperature_threshold_degreesC; |
827 | u8 max_temperature_degreesC; |
828 | u8 logical_blocks_per_phys_block_exp; /* phyblocksize = 512*2^exp */ |
829 | __le16 current_queue_depth_limit; |
830 | u8 reserved_switch_stuff[60]; |
831 | __le16 power_on_hours; /* valid only if gas gauge supported */ |
832 | __le16 percent_endurance_used; /* valid only if gas gauge supported. */ |
833 | #define BMIC_PHYS_DRIVE_SSD_WEAROUT(idphydrv) \ |
834 | ((idphydrv->percent_endurance_used & 0x80) || \ |
835 | (idphydrv->percent_endurance_used > 10000)) |
836 | u8 drive_authentication; |
837 | #define BMIC_PHYS_DRIVE_AUTHENTICATED(idphydrv) \ |
838 | (idphydrv->drive_authentication == 0x80) |
839 | u8 smart_carrier_authentication; |
840 | #define BMIC_SMART_CARRIER_AUTHENTICATION_SUPPORTED(idphydrv) \ |
841 | (idphydrv->smart_carrier_authentication != 0x0) |
842 | #define BMIC_SMART_CARRIER_AUTHENTICATED(idphydrv) \ |
843 | (idphydrv->smart_carrier_authentication == 0x01) |
844 | u8 smart_carrier_app_fw_version; |
845 | u8 smart_carrier_bootloader_fw_version; |
846 | u8 sanitize_support_flags; |
847 | u8 drive_key_flags; |
848 | u8 encryption_key_name[64]; |
849 | __le32 misc_drive_flags; |
850 | __le16 dek_index; |
851 | __le16 hba_drive_encryption_flags; |
852 | __le16 max_overwrite_time; |
853 | __le16 max_block_erase_time; |
854 | __le16 max_crypto_erase_time; |
855 | u8 device_connector_info[5]; |
856 | u8 connector_name[8][8]; |
857 | u8 page_83_id[16]; |
858 | u8 max_link_rate[256]; |
859 | u8 neg_phys_link_rate[256]; |
860 | u8 box_conn_name[8]; |
861 | } __packed __attribute((aligned(512))); |
862 | |
863 | struct bmic_sense_subsystem_info { |
864 | u8 primary_slot_number; |
865 | u8 reserved[3]; |
866 | u8 chasis_serial_number[32]; |
867 | u8 primary_world_wide_id[8]; |
868 | u8 primary_array_serial_number[32]; /* NULL terminated */ |
869 | u8 primary_cache_serial_number[32]; /* NULL terminated */ |
870 | u8 reserved_2[8]; |
871 | u8 secondary_array_serial_number[32]; |
872 | u8 secondary_cache_serial_number[32]; |
873 | u8 pad[332]; |
874 | } __packed; |
875 | |
876 | struct bmic_sense_storage_box_params { |
877 | u8 reserved[36]; |
878 | u8 inquiry_valid; |
879 | u8 reserved_1[68]; |
880 | u8 phys_box_on_port; |
881 | u8 reserved_2[22]; |
882 | u16 connection_info; |
883 | u8 reserver_3[84]; |
884 | u8 phys_connector[2]; |
885 | u8 reserved_4[296]; |
886 | } __packed; |
887 | |
888 | #endif /* HPSA_CMD_H */ |
889 | |