1 | /*****************************************************************************/ |
2 | /* ips.c -- driver for the Adaptec / IBM ServeRAID controller */ |
3 | /* */ |
4 | /* Written By: Keith Mitchell, IBM Corporation */ |
5 | /* Jack Hammer, Adaptec, Inc. */ |
6 | /* David Jeffery, Adaptec, Inc. */ |
7 | /* */ |
8 | /* Copyright (C) 2000 IBM Corporation */ |
9 | /* Copyright (C) 2002,2003 Adaptec, Inc. */ |
10 | /* */ |
11 | /* This program is free software; you can redistribute it and/or modify */ |
12 | /* it under the terms of the GNU General Public License as published by */ |
13 | /* the Free Software Foundation; either version 2 of the License, or */ |
14 | /* (at your option) any later version. */ |
15 | /* */ |
16 | /* This program is distributed in the hope that it will be useful, */ |
17 | /* but WITHOUT ANY WARRANTY; without even the implied warranty of */ |
18 | /* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ |
19 | /* GNU General Public License for more details. */ |
20 | /* */ |
21 | /* NO WARRANTY */ |
22 | /* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */ |
23 | /* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */ |
24 | /* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */ |
25 | /* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */ |
26 | /* solely responsible for determining the appropriateness of using and */ |
27 | /* distributing the Program and assumes all risks associated with its */ |
28 | /* exercise of rights under this Agreement, including but not limited to */ |
29 | /* the risks and costs of program errors, damage to or loss of data, */ |
30 | /* programs or equipment, and unavailability or interruption of operations. */ |
31 | /* */ |
32 | /* DISCLAIMER OF LIABILITY */ |
33 | /* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */ |
34 | /* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */ |
35 | /* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */ |
36 | /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */ |
37 | /* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */ |
38 | /* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */ |
39 | /* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */ |
40 | /* */ |
41 | /* You should have received a copy of the GNU General Public License */ |
42 | /* along with this program; if not, write to the Free Software */ |
43 | /* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ |
44 | /* */ |
45 | /* Bugs/Comments/Suggestions about this driver should be mailed to: */ |
46 | /* ipslinux@adaptec.com */ |
47 | /* */ |
48 | /* For system support issues, contact your local IBM Customer support. */ |
49 | /* Directions to find IBM Customer Support for each country can be found at: */ |
50 | /* http://www.ibm.com/planetwide/ */ |
51 | /* */ |
52 | /*****************************************************************************/ |
53 | |
54 | /*****************************************************************************/ |
55 | /* Change Log */ |
56 | /* */ |
57 | /* 0.99.02 - Breakup commands that are bigger than 8 * the stripe size */ |
58 | /* 0.99.03 - Make interrupt routine handle all completed request on the */ |
59 | /* adapter not just the first one */ |
60 | /* - Make sure passthru commands get woken up if we run out of */ |
61 | /* SCBs */ |
62 | /* - Send all of the commands on the queue at once rather than */ |
63 | /* one at a time since the card will support it. */ |
64 | /* 0.99.04 - Fix race condition in the passthru mechanism -- this required */ |
65 | /* the interface to the utilities to change */ |
66 | /* - Fix error recovery code */ |
67 | /* 0.99.05 - Fix an oops when we get certain passthru commands */ |
68 | /* 1.00.00 - Initial Public Release */ |
69 | /* Functionally equivalent to 0.99.05 */ |
70 | /* 3.60.00 - Bump max commands to 128 for use with firmware 3.60 */ |
71 | /* - Change version to 3.60 to coincide with release numbering. */ |
72 | /* 3.60.01 - Remove bogus error check in passthru routine */ |
73 | /* 3.60.02 - Make DCDB direction based on lookup table */ |
74 | /* - Only allow one DCDB command to a SCSI ID at a time */ |
75 | /* 4.00.00 - Add support for ServeRAID 4 */ |
76 | /* 4.00.01 - Add support for First Failure Data Capture */ |
77 | /* 4.00.02 - Fix problem with PT DCDB with no buffer */ |
78 | /* 4.00.03 - Add alternative passthru interface */ |
79 | /* - Add ability to flash BIOS */ |
80 | /* 4.00.04 - Rename structures/constants to be prefixed with IPS_ */ |
81 | /* 4.00.05 - Remove wish_block from init routine */ |
82 | /* - Use linux/spinlock.h instead of asm/spinlock.h for kernels */ |
83 | /* 2.3.18 and later */ |
84 | /* - Sync with other changes from the 2.3 kernels */ |
85 | /* 4.00.06 - Fix timeout with initial FFDC command */ |
86 | /* 4.00.06a - Port to 2.4 (trivial) -- Christoph Hellwig <hch@infradead.org> */ |
87 | /* 4.10.00 - Add support for ServeRAID 4M/4L */ |
88 | /* 4.10.13 - Fix for dynamic unload and proc file system */ |
89 | /* 4.20.03 - Rename version to coincide with new release schedules */ |
90 | /* Performance fixes */ |
91 | /* Fix truncation of /proc files with cat */ |
92 | /* Merge in changes through kernel 2.4.0test1ac21 */ |
93 | /* 4.20.13 - Fix some failure cases / reset code */ |
94 | /* - Hook into the reboot_notifier to flush the controller cache */ |
95 | /* 4.50.01 - Fix problem when there is a hole in logical drive numbering */ |
96 | /* 4.70.09 - Use a Common ( Large Buffer ) for Flashing from the JCRM CD */ |
97 | /* - Add IPSSEND Flash Support */ |
98 | /* - Set Sense Data for Unknown SCSI Command */ |
99 | /* - Use Slot Number from NVRAM Page 5 */ |
100 | /* - Restore caller's DCDB Structure */ |
101 | /* 4.70.12 - Corrective actions for bad controller ( during initialization )*/ |
102 | /* 4.70.13 - Don't Send CDB's if we already know the device is not present */ |
103 | /* - Don't release HA Lock in ips_next() until SC taken off queue */ |
104 | /* - Unregister SCSI device in ips_release() */ |
105 | /* 4.70.15 - Fix Breakup for very large ( non-SG ) requests in ips_done() */ |
106 | /* 4.71.00 - Change all memory allocations to not use GFP_DMA flag */ |
107 | /* Code Clean-Up for 2.4.x kernel */ |
108 | /* 4.72.00 - Allow for a Scatter-Gather Element to exceed MAX_XFER Size */ |
109 | /* 4.72.01 - I/O Mapped Memory release ( so "insmod ips" does not Fail ) */ |
110 | /* - Don't Issue Internal FFDC Command if there are Active Commands */ |
111 | /* - Close Window for getting too many IOCTL's active */ |
112 | /* 4.80.00 - Make ia64 Safe */ |
113 | /* 4.80.04 - Eliminate calls to strtok() if 2.4.x or greater */ |
114 | /* - Adjustments to Device Queue Depth */ |
115 | /* 4.80.14 - Take all semaphores off stack */ |
116 | /* - Clean Up New_IOCTL path */ |
117 | /* 4.80.20 - Set max_sectors in Scsi_Host structure ( if >= 2.4.7 kernel ) */ |
118 | /* - 5 second delay needed after resetting an i960 adapter */ |
119 | /* 4.80.26 - Clean up potential code problems ( Arjan's recommendations ) */ |
120 | /* 4.90.01 - Version Matching for FirmWare, BIOS, and Driver */ |
121 | /* 4.90.05 - Use New PCI Architecture to facilitate Hot Plug Development */ |
122 | /* 4.90.08 - Increase Delays in Flashing ( Trombone Only - 4H ) */ |
123 | /* 4.90.08 - Data Corruption if First Scatter Gather Element is > 64K */ |
124 | /* 4.90.11 - Don't actually RESET unless it's physically required */ |
125 | /* - Remove unused compile options */ |
126 | /* 5.00.01 - Sarasota ( 5i ) adapters must always be scanned first */ |
127 | /* - Get rid on IOCTL_NEW_COMMAND code */ |
128 | /* - Add Extended DCDB Commands for Tape Support in 5I */ |
129 | /* 5.10.12 - use pci_dma interfaces, update for 2.5 kernel changes */ |
130 | /* 5.10.15 - remove unused code (sem, macros, etc.) */ |
131 | /* 5.30.00 - use __devexit_p() */ |
132 | /* 6.00.00 - Add 6x Adapters and Battery Flash */ |
133 | /* 6.10.00 - Remove 1G Addressing Limitations */ |
134 | /* 6.11.xx - Get VersionInfo buffer off the stack ! DDTS 60401 */ |
135 | /* 6.11.xx - Make Logical Drive Info structure safe for DMA DDTS 60639 */ |
136 | /* 7.10.18 - Add highmem_io flag in SCSI Templete for 2.4 kernels */ |
137 | /* - Fix path/name for scsi_hosts.h include for 2.6 kernels */ |
138 | /* - Fix sort order of 7k */ |
139 | /* - Remove 3 unused "inline" functions */ |
140 | /* 7.12.xx - Use STATIC functions wherever possible */ |
141 | /* - Clean up deprecated MODULE_PARM calls */ |
142 | /* 7.12.05 - Remove Version Matching per IBM request */ |
143 | /*****************************************************************************/ |
144 | |
145 | /* |
146 | * Conditional Compilation directives for this driver: |
147 | * |
148 | * IPS_DEBUG - Turn on debugging info |
149 | * |
150 | * Parameters: |
151 | * |
152 | * debug:<number> - Set debug level to <number> |
153 | * NOTE: only works when IPS_DEBUG compile directive is used. |
154 | * 1 - Normal debug messages |
155 | * 2 - Verbose debug messages |
156 | * 11 - Method trace (non interrupt) |
157 | * 12 - Method trace (includes interrupt) |
158 | * |
159 | * noi2o - Don't use I2O Queues (ServeRAID 4 only) |
160 | * nommap - Don't use memory mapped I/O |
161 | * ioctlsize - Initial size of the IOCTL buffer |
162 | */ |
163 | |
164 | #include <asm/io.h> |
165 | #include <asm/byteorder.h> |
166 | #include <asm/page.h> |
167 | #include <linux/stddef.h> |
168 | #include <linux/string.h> |
169 | #include <linux/errno.h> |
170 | #include <linux/kernel.h> |
171 | #include <linux/ioport.h> |
172 | #include <linux/slab.h> |
173 | #include <linux/delay.h> |
174 | #include <linux/pci.h> |
175 | #include <linux/proc_fs.h> |
176 | #include <linux/reboot.h> |
177 | #include <linux/interrupt.h> |
178 | |
179 | #include <linux/blkdev.h> |
180 | #include <linux/types.h> |
181 | #include <linux/dma-mapping.h> |
182 | |
183 | #include <scsi/scsi.h> |
184 | #include <scsi/scsi_cmnd.h> |
185 | #include <scsi/scsi_device.h> |
186 | #include <scsi/scsi_eh.h> |
187 | #include <scsi/scsi_host.h> |
188 | #include <scsi/scsi_tcq.h> |
189 | #include <scsi/sg.h> |
190 | |
191 | #include "ips.h" |
192 | |
193 | #include <linux/module.h> |
194 | |
195 | #include <linux/stat.h> |
196 | |
197 | #include <linux/spinlock.h> |
198 | #include <linux/init.h> |
199 | |
200 | #include <linux/smp.h> |
201 | |
202 | #ifdef MODULE |
203 | static char *ips = NULL; |
204 | module_param(ips, charp, 0); |
205 | #endif |
206 | |
207 | /* |
208 | * DRIVER_VER |
209 | */ |
210 | #define IPS_VERSION_HIGH IPS_VER_MAJOR_STRING "." IPS_VER_MINOR_STRING |
211 | #define IPS_VERSION_LOW "." IPS_VER_BUILD_STRING " " |
212 | |
213 | #define IPS_DMA_DIR(scb) ((!scb->scsi_cmd || ips_is_passthru(scb->scsi_cmd) || \ |
214 | DMA_NONE == scb->scsi_cmd->sc_data_direction) ? \ |
215 | DMA_BIDIRECTIONAL : \ |
216 | scb->scsi_cmd->sc_data_direction) |
217 | |
218 | #ifdef IPS_DEBUG |
219 | #define METHOD_TRACE(s, i) if (ips_debug >= (i+10)) printk(KERN_NOTICE s "\n"); |
220 | #define DEBUG(i, s) if (ips_debug >= i) printk(KERN_NOTICE s "\n"); |
221 | #define DEBUG_VAR(i, s, v...) if (ips_debug >= i) printk(KERN_NOTICE s "\n", v); |
222 | #else |
223 | #define METHOD_TRACE(s, i) |
224 | #define DEBUG(i, s) |
225 | #define DEBUG_VAR(i, s, v...) |
226 | #endif |
227 | |
228 | /* |
229 | * Function prototypes |
230 | */ |
231 | static int ips_eh_abort(struct scsi_cmnd *); |
232 | static int ips_eh_reset(struct scsi_cmnd *); |
233 | static int ips_queue(struct Scsi_Host *, struct scsi_cmnd *); |
234 | static const char *ips_info(struct Scsi_Host *); |
235 | static irqreturn_t do_ipsintr(int, void *); |
236 | static int ips_hainit(ips_ha_t *); |
237 | static int ips_map_status(ips_ha_t *, ips_scb_t *, ips_stat_t *); |
238 | static int ips_send_wait(ips_ha_t *, ips_scb_t *, int, int); |
239 | static int ips_send_cmd(ips_ha_t *, ips_scb_t *); |
240 | static int ips_online(ips_ha_t *, ips_scb_t *); |
241 | static int ips_inquiry(ips_ha_t *, ips_scb_t *); |
242 | static int ips_rdcap(ips_ha_t *, ips_scb_t *); |
243 | static int ips_msense(ips_ha_t *, ips_scb_t *); |
244 | static int ips_reqsen(ips_ha_t *, ips_scb_t *); |
245 | static int ips_deallocatescbs(ips_ha_t *, int); |
246 | static int ips_allocatescbs(ips_ha_t *); |
247 | static int ips_reset_copperhead(ips_ha_t *); |
248 | static int ips_reset_copperhead_memio(ips_ha_t *); |
249 | static int ips_reset_morpheus(ips_ha_t *); |
250 | static int ips_issue_copperhead(ips_ha_t *, ips_scb_t *); |
251 | static int ips_issue_copperhead_memio(ips_ha_t *, ips_scb_t *); |
252 | static int ips_issue_i2o(ips_ha_t *, ips_scb_t *); |
253 | static int ips_issue_i2o_memio(ips_ha_t *, ips_scb_t *); |
254 | static int ips_isintr_copperhead(ips_ha_t *); |
255 | static int ips_isintr_copperhead_memio(ips_ha_t *); |
256 | static int ips_isintr_morpheus(ips_ha_t *); |
257 | static int ips_wait(ips_ha_t *, int, int); |
258 | static int ips_write_driver_status(ips_ha_t *, int); |
259 | static int ips_read_adapter_status(ips_ha_t *, int); |
260 | static int ips_read_subsystem_parameters(ips_ha_t *, int); |
261 | static int ips_read_config(ips_ha_t *, int); |
262 | static int ips_clear_adapter(ips_ha_t *, int); |
263 | static int ips_readwrite_page5(ips_ha_t *, int, int); |
264 | static int ips_init_copperhead(ips_ha_t *); |
265 | static int ips_init_copperhead_memio(ips_ha_t *); |
266 | static int ips_init_morpheus(ips_ha_t *); |
267 | static int ips_isinit_copperhead(ips_ha_t *); |
268 | static int ips_isinit_copperhead_memio(ips_ha_t *); |
269 | static int ips_isinit_morpheus(ips_ha_t *); |
270 | static int ips_erase_bios(ips_ha_t *); |
271 | static int ips_program_bios(ips_ha_t *, char *, uint32_t, uint32_t); |
272 | static int ips_verify_bios(ips_ha_t *, char *, uint32_t, uint32_t); |
273 | static int ips_erase_bios_memio(ips_ha_t *); |
274 | static int ips_program_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t); |
275 | static int ips_verify_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t); |
276 | static int ips_flash_copperhead(ips_ha_t *, ips_passthru_t *, ips_scb_t *); |
277 | static int ips_flash_bios(ips_ha_t *, ips_passthru_t *, ips_scb_t *); |
278 | static int ips_flash_firmware(ips_ha_t *, ips_passthru_t *, ips_scb_t *); |
279 | static void ips_free_flash_copperhead(ips_ha_t * ha); |
280 | static void ips_get_bios_version(ips_ha_t *, int); |
281 | static void ips_identify_controller(ips_ha_t *); |
282 | static void ips_chkstatus(ips_ha_t *, IPS_STATUS *); |
283 | static void ips_enable_int_copperhead(ips_ha_t *); |
284 | static void ips_enable_int_copperhead_memio(ips_ha_t *); |
285 | static void ips_enable_int_morpheus(ips_ha_t *); |
286 | static int ips_intr_copperhead(ips_ha_t *); |
287 | static int ips_intr_morpheus(ips_ha_t *); |
288 | static void ips_next(ips_ha_t *, int); |
289 | static void ipsintr_blocking(ips_ha_t *, struct ips_scb *); |
290 | static void ipsintr_done(ips_ha_t *, struct ips_scb *); |
291 | static void ips_done(ips_ha_t *, ips_scb_t *); |
292 | static void ips_free(ips_ha_t *); |
293 | static void ips_init_scb(ips_ha_t *, ips_scb_t *); |
294 | static void ips_freescb(ips_ha_t *, ips_scb_t *); |
295 | static void ips_setup_funclist(ips_ha_t *); |
296 | static void ips_statinit(ips_ha_t *); |
297 | static void ips_statinit_memio(ips_ha_t *); |
298 | static void ips_fix_ffdc_time(ips_ha_t *, ips_scb_t *, time64_t); |
299 | static void ips_ffdc_reset(ips_ha_t *, int); |
300 | static void ips_ffdc_time(ips_ha_t *); |
301 | static uint32_t ips_statupd_copperhead(ips_ha_t *); |
302 | static uint32_t ips_statupd_copperhead_memio(ips_ha_t *); |
303 | static uint32_t ips_statupd_morpheus(ips_ha_t *); |
304 | static ips_scb_t *ips_getscb(ips_ha_t *); |
305 | static void ips_putq_scb_head(ips_scb_queue_t *, ips_scb_t *); |
306 | static void ips_putq_wait_tail(ips_wait_queue_entry_t *, struct scsi_cmnd *); |
307 | static void ips_putq_copp_tail(ips_copp_queue_t *, |
308 | ips_copp_wait_item_t *); |
309 | static ips_scb_t *ips_removeq_scb_head(ips_scb_queue_t *); |
310 | static ips_scb_t *ips_removeq_scb(ips_scb_queue_t *, ips_scb_t *); |
311 | static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_entry_t *); |
312 | static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_entry_t *, |
313 | struct scsi_cmnd *); |
314 | static ips_copp_wait_item_t *ips_removeq_copp(ips_copp_queue_t *, |
315 | ips_copp_wait_item_t *); |
316 | static ips_copp_wait_item_t *ips_removeq_copp_head(ips_copp_queue_t *); |
317 | |
318 | static int ips_is_passthru(struct scsi_cmnd *); |
319 | static int ips_make_passthru(ips_ha_t *, struct scsi_cmnd *, ips_scb_t *, int); |
320 | static int ips_usrcmd(ips_ha_t *, ips_passthru_t *, ips_scb_t *); |
321 | static void ips_cleanup_passthru(ips_ha_t *, ips_scb_t *); |
322 | static void ips_scmd_buf_write(struct scsi_cmnd * scmd, void *data, |
323 | unsigned int count); |
324 | static void ips_scmd_buf_read(struct scsi_cmnd * scmd, void *data, |
325 | unsigned int count); |
326 | |
327 | static int ips_write_info(struct Scsi_Host *, char *, int); |
328 | static int ips_show_info(struct seq_file *, struct Scsi_Host *); |
329 | static int ips_host_info(ips_ha_t *, struct seq_file *); |
330 | static int ips_abort_init(ips_ha_t * ha, int index); |
331 | static int ips_init_phase2(int index); |
332 | |
333 | static int ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr); |
334 | static int ips_register_scsi(int index); |
335 | |
336 | static int ips_poll_for_flush_complete(ips_ha_t * ha); |
337 | static void ips_flush_and_reset(ips_ha_t *ha); |
338 | |
339 | /* |
340 | * global variables |
341 | */ |
342 | static const char ips_name[] = "ips" ; |
343 | static struct Scsi_Host *ips_sh[IPS_MAX_ADAPTERS]; /* Array of host controller structures */ |
344 | static ips_ha_t *ips_ha[IPS_MAX_ADAPTERS]; /* Array of HA structures */ |
345 | static unsigned int ips_next_controller; |
346 | static unsigned int ips_num_controllers; |
347 | static unsigned int ips_released_controllers; |
348 | static int ips_hotplug; |
349 | static int ips_cmd_timeout = 60; |
350 | static int ips_reset_timeout = 60 * 5; |
351 | static int ips_force_memio = 1; /* Always use Memory Mapped I/O */ |
352 | static int ips_force_i2o = 1; /* Always use I2O command delivery */ |
353 | static int ips_ioctlsize = IPS_IOCTL_SIZE; /* Size of the ioctl buffer */ |
354 | static int ips_cd_boot; /* Booting from Manager CD */ |
355 | static char *ips_FlashData = NULL; /* CD Boot - Flash Data Buffer */ |
356 | static dma_addr_t ips_flashbusaddr; |
357 | static long ips_FlashDataInUse; /* CD Boot - Flash Data In Use Flag */ |
358 | static uint32_t MaxLiteCmds = 32; /* Max Active Cmds for a Lite Adapter */ |
359 | static struct scsi_host_template ips_driver_template = { |
360 | .info = ips_info, |
361 | .queuecommand = ips_queue, |
362 | .eh_abort_handler = ips_eh_abort, |
363 | .eh_host_reset_handler = ips_eh_reset, |
364 | .proc_name = "ips" , |
365 | .show_info = ips_show_info, |
366 | .write_info = ips_write_info, |
367 | .slave_configure = ips_slave_configure, |
368 | .bios_param = ips_biosparam, |
369 | .this_id = -1, |
370 | .sg_tablesize = IPS_MAX_SG, |
371 | .cmd_per_lun = 3, |
372 | .no_write_same = 1, |
373 | }; |
374 | |
375 | |
376 | /* This table describes all ServeRAID Adapters */ |
377 | static struct pci_device_id ips_pci_table[] = { |
378 | { 0x1014, 0x002E, PCI_ANY_ID, PCI_ANY_ID, 0, 0 }, |
379 | { 0x1014, 0x01BD, PCI_ANY_ID, PCI_ANY_ID, 0, 0 }, |
380 | { 0x9005, 0x0250, PCI_ANY_ID, PCI_ANY_ID, 0, 0 }, |
381 | { 0, } |
382 | }; |
383 | |
384 | MODULE_DEVICE_TABLE( pci, ips_pci_table ); |
385 | |
386 | static char ips_hot_plug_name[] = "ips" ; |
387 | |
388 | static int ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent); |
389 | static void ips_remove_device(struct pci_dev *pci_dev); |
390 | |
391 | static struct pci_driver ips_pci_driver = { |
392 | .name = ips_hot_plug_name, |
393 | .id_table = ips_pci_table, |
394 | .probe = ips_insert_device, |
395 | .remove = ips_remove_device, |
396 | }; |
397 | |
398 | |
399 | /* |
400 | * Necessary forward function protoypes |
401 | */ |
402 | static int ips_halt(struct notifier_block *nb, ulong event, void *buf); |
403 | |
404 | #define MAX_ADAPTER_NAME 15 |
405 | |
406 | static char ips_adapter_name[][30] = { |
407 | "ServeRAID" , |
408 | "ServeRAID II" , |
409 | "ServeRAID on motherboard" , |
410 | "ServeRAID on motherboard" , |
411 | "ServeRAID 3H" , |
412 | "ServeRAID 3L" , |
413 | "ServeRAID 4H" , |
414 | "ServeRAID 4M" , |
415 | "ServeRAID 4L" , |
416 | "ServeRAID 4Mx" , |
417 | "ServeRAID 4Lx" , |
418 | "ServeRAID 5i" , |
419 | "ServeRAID 5i" , |
420 | "ServeRAID 6M" , |
421 | "ServeRAID 6i" , |
422 | "ServeRAID 7t" , |
423 | "ServeRAID 7k" , |
424 | "ServeRAID 7M" |
425 | }; |
426 | |
427 | static struct notifier_block ips_notifier = { |
428 | ips_halt, NULL, 0 |
429 | }; |
430 | |
431 | /* |
432 | * Direction table |
433 | */ |
434 | static char ips_command_direction[] = { |
435 | IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, |
436 | IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, |
437 | IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
438 | IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT, |
439 | IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_OUT, |
440 | IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT, |
441 | IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_IN, |
442 | IPS_DATA_UNK, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, |
443 | IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_UNK, |
444 | IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, |
445 | IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, |
446 | IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, |
447 | IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, |
448 | IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_NONE, |
449 | IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, |
450 | IPS_DATA_NONE, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, |
451 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
452 | IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
453 | IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
454 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
455 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
456 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
457 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
458 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
459 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
460 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
461 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
462 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
463 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
464 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
465 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
466 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
467 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
468 | IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_NONE, |
469 | IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_OUT, |
470 | IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_NONE, |
471 | IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, |
472 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
473 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
474 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
475 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
476 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
477 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
478 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
479 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
480 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
481 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_OUT, |
482 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
483 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
484 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, |
485 | IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK |
486 | }; |
487 | |
488 | |
489 | /****************************************************************************/ |
490 | /* */ |
491 | /* Routine Name: ips_setup */ |
492 | /* */ |
493 | /* Routine Description: */ |
494 | /* */ |
495 | /* setup parameters to the driver */ |
496 | /* */ |
497 | /****************************************************************************/ |
498 | static int |
499 | ips_setup(char *ips_str) |
500 | { |
501 | |
502 | int i; |
503 | char *key; |
504 | char *value; |
505 | static const IPS_OPTION options[] = { |
506 | {"noi2o" , &ips_force_i2o, 0}, |
507 | {"nommap" , &ips_force_memio, 0}, |
508 | {"ioctlsize" , &ips_ioctlsize, IPS_IOCTL_SIZE}, |
509 | {"cdboot" , &ips_cd_boot, 0}, |
510 | {"maxcmds" , &MaxLiteCmds, 32}, |
511 | }; |
512 | |
513 | /* Don't use strtok() anymore ( if 2.4 Kernel or beyond ) */ |
514 | /* Search for value */ |
515 | while ((key = strsep(&ips_str, ",." ))) { |
516 | if (!*key) |
517 | continue; |
518 | value = strchr(key, ':'); |
519 | if (value) |
520 | *value++ = '\0'; |
521 | /* |
522 | * We now have key/value pairs. |
523 | * Update the variables |
524 | */ |
525 | for (i = 0; i < ARRAY_SIZE(options); i++) { |
526 | if (strncasecmp |
527 | (s1: key, s2: options[i].option_name, |
528 | strlen(options[i].option_name)) == 0) { |
529 | if (value) |
530 | *options[i].option_flag = |
531 | simple_strtoul(value, NULL, 0); |
532 | else |
533 | *options[i].option_flag = |
534 | options[i].option_value; |
535 | break; |
536 | } |
537 | } |
538 | } |
539 | |
540 | return (1); |
541 | } |
542 | |
543 | __setup("ips=" , ips_setup); |
544 | |
545 | /****************************************************************************/ |
546 | /* */ |
547 | /* Routine Name: ips_detect */ |
548 | /* */ |
549 | /* Routine Description: */ |
550 | /* */ |
551 | /* Detect and initialize the driver */ |
552 | /* */ |
553 | /* NOTE: this routine is called under the io_request_lock spinlock */ |
554 | /* */ |
555 | /****************************************************************************/ |
556 | static int |
557 | ips_detect(struct scsi_host_template * SHT) |
558 | { |
559 | int i; |
560 | |
561 | METHOD_TRACE("ips_detect" , 1); |
562 | |
563 | #ifdef MODULE |
564 | if (ips) |
565 | ips_setup(ips); |
566 | #endif |
567 | |
568 | for (i = 0; i < ips_num_controllers; i++) { |
569 | if (ips_register_scsi(index: i)) |
570 | ips_free(ips_ha[i]); |
571 | ips_released_controllers++; |
572 | } |
573 | ips_hotplug = 1; |
574 | return (ips_num_controllers); |
575 | } |
576 | |
577 | /****************************************************************************/ |
578 | /* configure the function pointers to use the functions that will work */ |
579 | /* with the found version of the adapter */ |
580 | /****************************************************************************/ |
581 | static void |
582 | ips_setup_funclist(ips_ha_t * ha) |
583 | { |
584 | |
585 | /* |
586 | * Setup Functions |
587 | */ |
588 | if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) { |
589 | /* morpheus / marco / sebring */ |
590 | ha->func.isintr = ips_isintr_morpheus; |
591 | ha->func.isinit = ips_isinit_morpheus; |
592 | ha->func.issue = ips_issue_i2o_memio; |
593 | ha->func.init = ips_init_morpheus; |
594 | ha->func.statupd = ips_statupd_morpheus; |
595 | ha->func.reset = ips_reset_morpheus; |
596 | ha->func.intr = ips_intr_morpheus; |
597 | ha->func.enableint = ips_enable_int_morpheus; |
598 | } else if (IPS_USE_MEMIO(ha)) { |
599 | /* copperhead w/MEMIO */ |
600 | ha->func.isintr = ips_isintr_copperhead_memio; |
601 | ha->func.isinit = ips_isinit_copperhead_memio; |
602 | ha->func.init = ips_init_copperhead_memio; |
603 | ha->func.statupd = ips_statupd_copperhead_memio; |
604 | ha->func.statinit = ips_statinit_memio; |
605 | ha->func.reset = ips_reset_copperhead_memio; |
606 | ha->func.intr = ips_intr_copperhead; |
607 | ha->func.erasebios = ips_erase_bios_memio; |
608 | ha->func.programbios = ips_program_bios_memio; |
609 | ha->func.verifybios = ips_verify_bios_memio; |
610 | ha->func.enableint = ips_enable_int_copperhead_memio; |
611 | if (IPS_USE_I2O_DELIVER(ha)) |
612 | ha->func.issue = ips_issue_i2o_memio; |
613 | else |
614 | ha->func.issue = ips_issue_copperhead_memio; |
615 | } else { |
616 | /* copperhead */ |
617 | ha->func.isintr = ips_isintr_copperhead; |
618 | ha->func.isinit = ips_isinit_copperhead; |
619 | ha->func.init = ips_init_copperhead; |
620 | ha->func.statupd = ips_statupd_copperhead; |
621 | ha->func.statinit = ips_statinit; |
622 | ha->func.reset = ips_reset_copperhead; |
623 | ha->func.intr = ips_intr_copperhead; |
624 | ha->func.erasebios = ips_erase_bios; |
625 | ha->func.programbios = ips_program_bios; |
626 | ha->func.verifybios = ips_verify_bios; |
627 | ha->func.enableint = ips_enable_int_copperhead; |
628 | |
629 | if (IPS_USE_I2O_DELIVER(ha)) |
630 | ha->func.issue = ips_issue_i2o; |
631 | else |
632 | ha->func.issue = ips_issue_copperhead; |
633 | } |
634 | } |
635 | |
636 | /****************************************************************************/ |
637 | /* */ |
638 | /* Routine Name: ips_release */ |
639 | /* */ |
640 | /* Routine Description: */ |
641 | /* */ |
642 | /* Remove a driver */ |
643 | /* */ |
644 | /****************************************************************************/ |
645 | static void ips_release(struct Scsi_Host *sh) |
646 | { |
647 | ips_scb_t *scb; |
648 | ips_ha_t *ha; |
649 | int i; |
650 | |
651 | METHOD_TRACE("ips_release" , 1); |
652 | |
653 | scsi_remove_host(sh); |
654 | |
655 | for (i = 0; i < IPS_MAX_ADAPTERS && ips_sh[i] != sh; i++) ; |
656 | |
657 | if (i == IPS_MAX_ADAPTERS) { |
658 | printk(KERN_WARNING |
659 | "(%s) release, invalid Scsi_Host pointer.\n" , ips_name); |
660 | BUG(); |
661 | } |
662 | |
663 | ha = IPS_HA(sh); |
664 | |
665 | if (!ha) |
666 | return; |
667 | |
668 | /* flush the cache on the controller */ |
669 | scb = &ha->scbs[ha->max_cmds - 1]; |
670 | |
671 | ips_init_scb(ha, scb); |
672 | |
673 | scb->timeout = ips_cmd_timeout; |
674 | scb->cdb[0] = IPS_CMD_FLUSH; |
675 | |
676 | scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH; |
677 | scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb); |
678 | scb->cmd.flush_cache.state = IPS_NORM_STATE; |
679 | scb->cmd.flush_cache.reserved = 0; |
680 | scb->cmd.flush_cache.reserved2 = 0; |
681 | scb->cmd.flush_cache.reserved3 = 0; |
682 | scb->cmd.flush_cache.reserved4 = 0; |
683 | |
684 | IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n" ); |
685 | |
686 | /* send command */ |
687 | if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE) |
688 | IPS_PRINTK(KERN_WARNING, ha->pcidev, "Incomplete Flush.\n" ); |
689 | |
690 | IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Complete.\n" ); |
691 | |
692 | ips_sh[i] = NULL; |
693 | ips_ha[i] = NULL; |
694 | |
695 | /* free extra memory */ |
696 | ips_free(ha); |
697 | |
698 | /* free IRQ */ |
699 | free_irq(ha->pcidev->irq, ha); |
700 | |
701 | scsi_host_put(t: sh); |
702 | |
703 | ips_released_controllers++; |
704 | } |
705 | |
706 | /****************************************************************************/ |
707 | /* */ |
708 | /* Routine Name: ips_halt */ |
709 | /* */ |
710 | /* Routine Description: */ |
711 | /* */ |
712 | /* Perform cleanup when the system reboots */ |
713 | /* */ |
714 | /****************************************************************************/ |
715 | static int |
716 | ips_halt(struct notifier_block *nb, ulong event, void *buf) |
717 | { |
718 | ips_scb_t *scb; |
719 | ips_ha_t *ha; |
720 | int i; |
721 | |
722 | if ((event != SYS_RESTART) && (event != SYS_HALT) && |
723 | (event != SYS_POWER_OFF)) |
724 | return (NOTIFY_DONE); |
725 | |
726 | for (i = 0; i < ips_next_controller; i++) { |
727 | ha = (ips_ha_t *) ips_ha[i]; |
728 | |
729 | if (!ha) |
730 | continue; |
731 | |
732 | if (!ha->active) |
733 | continue; |
734 | |
735 | /* flush the cache on the controller */ |
736 | scb = &ha->scbs[ha->max_cmds - 1]; |
737 | |
738 | ips_init_scb(ha, scb); |
739 | |
740 | scb->timeout = ips_cmd_timeout; |
741 | scb->cdb[0] = IPS_CMD_FLUSH; |
742 | |
743 | scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH; |
744 | scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb); |
745 | scb->cmd.flush_cache.state = IPS_NORM_STATE; |
746 | scb->cmd.flush_cache.reserved = 0; |
747 | scb->cmd.flush_cache.reserved2 = 0; |
748 | scb->cmd.flush_cache.reserved3 = 0; |
749 | scb->cmd.flush_cache.reserved4 = 0; |
750 | |
751 | IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n" ); |
752 | |
753 | /* send command */ |
754 | if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == |
755 | IPS_FAILURE) |
756 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
757 | "Incomplete Flush.\n" ); |
758 | else |
759 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
760 | "Flushing Complete.\n" ); |
761 | } |
762 | |
763 | return (NOTIFY_OK); |
764 | } |
765 | |
766 | /****************************************************************************/ |
767 | /* */ |
768 | /* Routine Name: ips_eh_abort */ |
769 | /* */ |
770 | /* Routine Description: */ |
771 | /* */ |
772 | /* Abort a command (using the new error code stuff) */ |
773 | /* Note: this routine is called under the io_request_lock */ |
774 | /****************************************************************************/ |
775 | int ips_eh_abort(struct scsi_cmnd *SC) |
776 | { |
777 | ips_ha_t *ha; |
778 | ips_copp_wait_item_t *item; |
779 | int ret; |
780 | struct Scsi_Host *host; |
781 | |
782 | METHOD_TRACE("ips_eh_abort" , 1); |
783 | |
784 | if (!SC) |
785 | return (FAILED); |
786 | |
787 | host = SC->device->host; |
788 | ha = (ips_ha_t *) SC->device->host->hostdata; |
789 | |
790 | if (!ha) |
791 | return (FAILED); |
792 | |
793 | if (!ha->active) |
794 | return (FAILED); |
795 | |
796 | spin_lock(lock: host->host_lock); |
797 | |
798 | /* See if the command is on the copp queue */ |
799 | item = ha->copp_waitlist.head; |
800 | while ((item) && (item->scsi_cmd != SC)) |
801 | item = item->next; |
802 | |
803 | if (item) { |
804 | /* Found it */ |
805 | ips_removeq_copp(&ha->copp_waitlist, item); |
806 | ret = (SUCCESS); |
807 | |
808 | /* See if the command is on the wait queue */ |
809 | } else if (ips_removeq_wait(&ha->scb_waitlist, SC)) { |
810 | /* command not sent yet */ |
811 | ret = (SUCCESS); |
812 | } else { |
813 | /* command must have already been sent */ |
814 | ret = (FAILED); |
815 | } |
816 | |
817 | spin_unlock(lock: host->host_lock); |
818 | return ret; |
819 | } |
820 | |
821 | /****************************************************************************/ |
822 | /* */ |
823 | /* Routine Name: ips_eh_reset */ |
824 | /* */ |
825 | /* Routine Description: */ |
826 | /* */ |
827 | /* Reset the controller (with new eh error code) */ |
828 | /* */ |
829 | /* NOTE: this routine is called under the io_request_lock spinlock */ |
830 | /* */ |
831 | /****************************************************************************/ |
832 | static int __ips_eh_reset(struct scsi_cmnd *SC) |
833 | { |
834 | int ret; |
835 | int i; |
836 | ips_ha_t *ha; |
837 | ips_scb_t *scb; |
838 | |
839 | METHOD_TRACE("ips_eh_reset" , 1); |
840 | |
841 | #ifdef NO_IPS_RESET |
842 | return (FAILED); |
843 | #else |
844 | |
845 | if (!SC) { |
846 | DEBUG(1, "Reset called with NULL scsi command" ); |
847 | |
848 | return (FAILED); |
849 | } |
850 | |
851 | ha = (ips_ha_t *) SC->device->host->hostdata; |
852 | |
853 | if (!ha) { |
854 | DEBUG(1, "Reset called with NULL ha struct" ); |
855 | |
856 | return (FAILED); |
857 | } |
858 | |
859 | if (!ha->active) |
860 | return (FAILED); |
861 | |
862 | /* An explanation for the casual observer: */ |
863 | /* Part of the function of a RAID controller is automatic error */ |
864 | /* detection and recovery. As such, the only problem that physically */ |
865 | /* resetting an adapter will ever fix is when, for some reason, */ |
866 | /* the driver is not successfully communicating with the adapter. */ |
867 | /* Therefore, we will attempt to flush this adapter. If that succeeds, */ |
868 | /* then there's no real purpose in a physical reset. This will complete */ |
869 | /* much faster and avoids any problems that might be caused by a */ |
870 | /* physical reset ( such as having to fail all the outstanding I/O's ). */ |
871 | |
872 | if (ha->ioctl_reset == 0) { /* IF Not an IOCTL Requested Reset */ |
873 | scb = &ha->scbs[ha->max_cmds - 1]; |
874 | |
875 | ips_init_scb(ha, scb); |
876 | |
877 | scb->timeout = ips_cmd_timeout; |
878 | scb->cdb[0] = IPS_CMD_FLUSH; |
879 | |
880 | scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH; |
881 | scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb); |
882 | scb->cmd.flush_cache.state = IPS_NORM_STATE; |
883 | scb->cmd.flush_cache.reserved = 0; |
884 | scb->cmd.flush_cache.reserved2 = 0; |
885 | scb->cmd.flush_cache.reserved3 = 0; |
886 | scb->cmd.flush_cache.reserved4 = 0; |
887 | |
888 | /* Attempt the flush command */ |
889 | ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL); |
890 | if (ret == IPS_SUCCESS) { |
891 | IPS_PRINTK(KERN_NOTICE, ha->pcidev, |
892 | "Reset Request - Flushed Cache\n" ); |
893 | return (SUCCESS); |
894 | } |
895 | } |
896 | |
897 | /* Either we can't communicate with the adapter or it's an IOCTL request */ |
898 | /* from a utility. A physical reset is needed at this point. */ |
899 | |
900 | ha->ioctl_reset = 0; /* Reset the IOCTL Requested Reset Flag */ |
901 | |
902 | /* |
903 | * command must have already been sent |
904 | * reset the controller |
905 | */ |
906 | IPS_PRINTK(KERN_NOTICE, ha->pcidev, "Resetting controller.\n" ); |
907 | ret = (*ha->func.reset) (ha); |
908 | |
909 | if (!ret) { |
910 | struct scsi_cmnd *scsi_cmd; |
911 | |
912 | IPS_PRINTK(KERN_NOTICE, ha->pcidev, |
913 | "Controller reset failed - controller now offline.\n" ); |
914 | |
915 | /* Now fail all of the active commands */ |
916 | DEBUG_VAR(1, "(%s%d) Failing active commands" , |
917 | ips_name, ha->host_num); |
918 | |
919 | while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) { |
920 | scb->scsi_cmd->result = DID_ERROR << 16; |
921 | scsi_done(cmd: scb->scsi_cmd); |
922 | ips_freescb(ha, scb); |
923 | } |
924 | |
925 | /* Now fail all of the pending commands */ |
926 | DEBUG_VAR(1, "(%s%d) Failing pending commands" , |
927 | ips_name, ha->host_num); |
928 | |
929 | while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) { |
930 | scsi_cmd->result = DID_ERROR; |
931 | scsi_done(cmd: scsi_cmd); |
932 | } |
933 | |
934 | ha->active = false; |
935 | return (FAILED); |
936 | } |
937 | |
938 | if (!ips_clear_adapter(ha, IPS_INTR_IORL)) { |
939 | struct scsi_cmnd *scsi_cmd; |
940 | |
941 | IPS_PRINTK(KERN_NOTICE, ha->pcidev, |
942 | "Controller reset failed - controller now offline.\n" ); |
943 | |
944 | /* Now fail all of the active commands */ |
945 | DEBUG_VAR(1, "(%s%d) Failing active commands" , |
946 | ips_name, ha->host_num); |
947 | |
948 | while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) { |
949 | scb->scsi_cmd->result = DID_ERROR << 16; |
950 | scsi_done(cmd: scb->scsi_cmd); |
951 | ips_freescb(ha, scb); |
952 | } |
953 | |
954 | /* Now fail all of the pending commands */ |
955 | DEBUG_VAR(1, "(%s%d) Failing pending commands" , |
956 | ips_name, ha->host_num); |
957 | |
958 | while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) { |
959 | scsi_cmd->result = DID_ERROR << 16; |
960 | scsi_done(cmd: scsi_cmd); |
961 | } |
962 | |
963 | ha->active = false; |
964 | return (FAILED); |
965 | } |
966 | |
967 | /* FFDC */ |
968 | if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) { |
969 | ha->last_ffdc = ktime_get_real_seconds(); |
970 | ha->reset_count++; |
971 | ips_ffdc_reset(ha, IPS_INTR_IORL); |
972 | } |
973 | |
974 | /* Now fail all of the active commands */ |
975 | DEBUG_VAR(1, "(%s%d) Failing active commands" , ips_name, ha->host_num); |
976 | |
977 | while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) { |
978 | scb->scsi_cmd->result = DID_RESET << 16; |
979 | scsi_done(cmd: scb->scsi_cmd); |
980 | ips_freescb(ha, scb); |
981 | } |
982 | |
983 | /* Reset DCDB active command bits */ |
984 | for (i = 1; i < ha->nbus; i++) |
985 | ha->dcdb_active[i - 1] = 0; |
986 | |
987 | /* Reset the number of active IOCTLs */ |
988 | ha->num_ioctl = 0; |
989 | |
990 | ips_next(ha, IPS_INTR_IORL); |
991 | |
992 | return (SUCCESS); |
993 | #endif /* NO_IPS_RESET */ |
994 | |
995 | } |
996 | |
997 | static int ips_eh_reset(struct scsi_cmnd *SC) |
998 | { |
999 | int rc; |
1000 | |
1001 | spin_lock_irq(lock: SC->device->host->host_lock); |
1002 | rc = __ips_eh_reset(SC); |
1003 | spin_unlock_irq(lock: SC->device->host->host_lock); |
1004 | |
1005 | return rc; |
1006 | } |
1007 | |
1008 | /****************************************************************************/ |
1009 | /* */ |
1010 | /* Routine Name: ips_queue */ |
1011 | /* */ |
1012 | /* Routine Description: */ |
1013 | /* */ |
1014 | /* Send a command to the controller */ |
1015 | /* */ |
1016 | /* NOTE: */ |
1017 | /* Linux obtains io_request_lock before calling this function */ |
1018 | /* */ |
1019 | /****************************************************************************/ |
1020 | static int ips_queue_lck(struct scsi_cmnd *SC) |
1021 | { |
1022 | void (*done)(struct scsi_cmnd *) = scsi_done; |
1023 | ips_ha_t *ha; |
1024 | ips_passthru_t *pt; |
1025 | |
1026 | METHOD_TRACE("ips_queue" , 1); |
1027 | |
1028 | ha = (ips_ha_t *) SC->device->host->hostdata; |
1029 | |
1030 | if (!ha) |
1031 | goto out_error; |
1032 | |
1033 | if (!ha->active) |
1034 | goto out_error; |
1035 | |
1036 | if (ips_is_passthru(SC)) { |
1037 | if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) { |
1038 | SC->result = DID_BUS_BUSY << 16; |
1039 | done(SC); |
1040 | |
1041 | return (0); |
1042 | } |
1043 | } else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) { |
1044 | SC->result = DID_BUS_BUSY << 16; |
1045 | done(SC); |
1046 | |
1047 | return (0); |
1048 | } |
1049 | |
1050 | DEBUG_VAR(2, "(%s%d): ips_queue: cmd 0x%X (%d %d %d)" , |
1051 | ips_name, |
1052 | ha->host_num, |
1053 | SC->cmnd[0], |
1054 | SC->device->channel, SC->device->id, SC->device->lun); |
1055 | |
1056 | /* Check for command to initiator IDs */ |
1057 | if ((scmd_channel(SC) > 0) |
1058 | && (scmd_id(SC) == ha->ha_id[scmd_channel(SC)])) { |
1059 | SC->result = DID_NO_CONNECT << 16; |
1060 | done(SC); |
1061 | |
1062 | return (0); |
1063 | } |
1064 | |
1065 | if (ips_is_passthru(SC)) { |
1066 | |
1067 | ips_copp_wait_item_t *scratch; |
1068 | |
1069 | /* A Reset IOCTL is only sent by the boot CD in extreme cases. */ |
1070 | /* There can never be any system activity ( network or disk ), but check */ |
1071 | /* anyway just as a good practice. */ |
1072 | pt = (ips_passthru_t *) scsi_sglist(cmd: SC); |
1073 | if ((pt->CoppCP.cmd.reset.op_code == IPS_CMD_RESET_CHANNEL) && |
1074 | (pt->CoppCP.cmd.reset.adapter_flag == 1)) { |
1075 | if (ha->scb_activelist.count != 0) { |
1076 | SC->result = DID_BUS_BUSY << 16; |
1077 | done(SC); |
1078 | return (0); |
1079 | } |
1080 | ha->ioctl_reset = 1; /* This reset request is from an IOCTL */ |
1081 | __ips_eh_reset(SC); |
1082 | SC->result = DID_OK << 16; |
1083 | scsi_done(cmd: SC); |
1084 | return (0); |
1085 | } |
1086 | |
1087 | /* allocate space for the scribble */ |
1088 | scratch = kmalloc(size: sizeof (ips_copp_wait_item_t), GFP_ATOMIC); |
1089 | |
1090 | if (!scratch) { |
1091 | SC->result = DID_ERROR << 16; |
1092 | done(SC); |
1093 | |
1094 | return (0); |
1095 | } |
1096 | |
1097 | scratch->scsi_cmd = SC; |
1098 | scratch->next = NULL; |
1099 | |
1100 | ips_putq_copp_tail(&ha->copp_waitlist, scratch); |
1101 | } else { |
1102 | ips_putq_wait_tail(&ha->scb_waitlist, SC); |
1103 | } |
1104 | |
1105 | ips_next(ha, IPS_INTR_IORL); |
1106 | |
1107 | return (0); |
1108 | out_error: |
1109 | SC->result = DID_ERROR << 16; |
1110 | done(SC); |
1111 | |
1112 | return (0); |
1113 | } |
1114 | |
1115 | static DEF_SCSI_QCMD(ips_queue) |
1116 | |
1117 | /****************************************************************************/ |
1118 | /* */ |
1119 | /* Routine Name: ips_biosparam */ |
1120 | /* */ |
1121 | /* Routine Description: */ |
1122 | /* */ |
1123 | /* Set bios geometry for the controller */ |
1124 | /* */ |
1125 | /****************************************************************************/ |
1126 | static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev, |
1127 | sector_t capacity, int geom[]) |
1128 | { |
1129 | ips_ha_t *ha = (ips_ha_t *) sdev->host->hostdata; |
1130 | int heads; |
1131 | int sectors; |
1132 | int cylinders; |
1133 | |
1134 | METHOD_TRACE("ips_biosparam" , 1); |
1135 | |
1136 | if (!ha) |
1137 | /* ?!?! host adater info invalid */ |
1138 | return (0); |
1139 | |
1140 | if (!ha->active) |
1141 | return (0); |
1142 | |
1143 | if (!ips_read_adapter_status(ha, IPS_INTR_ON)) |
1144 | /* ?!?! Enquiry command failed */ |
1145 | return (0); |
1146 | |
1147 | if ((capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) { |
1148 | heads = IPS_NORM_HEADS; |
1149 | sectors = IPS_NORM_SECTORS; |
1150 | } else { |
1151 | heads = IPS_COMP_HEADS; |
1152 | sectors = IPS_COMP_SECTORS; |
1153 | } |
1154 | |
1155 | cylinders = (unsigned long) capacity / (heads * sectors); |
1156 | |
1157 | DEBUG_VAR(2, "Geometry: heads: %d, sectors: %d, cylinders: %d" , |
1158 | heads, sectors, cylinders); |
1159 | |
1160 | geom[0] = heads; |
1161 | geom[1] = sectors; |
1162 | geom[2] = cylinders; |
1163 | |
1164 | return (0); |
1165 | } |
1166 | |
1167 | /****************************************************************************/ |
1168 | /* */ |
1169 | /* Routine Name: ips_slave_configure */ |
1170 | /* */ |
1171 | /* Routine Description: */ |
1172 | /* */ |
1173 | /* Set queue depths on devices once scan is complete */ |
1174 | /* */ |
1175 | /****************************************************************************/ |
1176 | static int |
1177 | ips_slave_configure(struct scsi_device * SDptr) |
1178 | { |
1179 | ips_ha_t *ha; |
1180 | int min; |
1181 | |
1182 | ha = IPS_HA(SDptr->host); |
1183 | if (SDptr->tagged_supported && SDptr->type == TYPE_DISK) { |
1184 | min = ha->max_cmds / 2; |
1185 | if (ha->enq->ucLogDriveCount <= 2) |
1186 | min = ha->max_cmds - 1; |
1187 | scsi_change_queue_depth(SDptr, min); |
1188 | } |
1189 | |
1190 | SDptr->skip_ms_page_8 = 1; |
1191 | SDptr->skip_ms_page_3f = 1; |
1192 | return 0; |
1193 | } |
1194 | |
1195 | /****************************************************************************/ |
1196 | /* */ |
1197 | /* Routine Name: do_ipsintr */ |
1198 | /* */ |
1199 | /* Routine Description: */ |
1200 | /* */ |
1201 | /* Wrapper for the interrupt handler */ |
1202 | /* */ |
1203 | /****************************************************************************/ |
1204 | static irqreturn_t |
1205 | do_ipsintr(int irq, void *dev_id) |
1206 | { |
1207 | ips_ha_t *ha; |
1208 | struct Scsi_Host *host; |
1209 | int irqstatus; |
1210 | |
1211 | METHOD_TRACE("do_ipsintr" , 2); |
1212 | |
1213 | ha = (ips_ha_t *) dev_id; |
1214 | if (!ha) |
1215 | return IRQ_NONE; |
1216 | host = ips_sh[ha->host_num]; |
1217 | /* interrupt during initialization */ |
1218 | if (!host) { |
1219 | (*ha->func.intr) (ha); |
1220 | return IRQ_HANDLED; |
1221 | } |
1222 | |
1223 | spin_lock(lock: host->host_lock); |
1224 | |
1225 | if (!ha->active) { |
1226 | spin_unlock(lock: host->host_lock); |
1227 | return IRQ_HANDLED; |
1228 | } |
1229 | |
1230 | irqstatus = (*ha->func.intr) (ha); |
1231 | |
1232 | spin_unlock(lock: host->host_lock); |
1233 | |
1234 | /* start the next command */ |
1235 | ips_next(ha, IPS_INTR_ON); |
1236 | return IRQ_RETVAL(irqstatus); |
1237 | } |
1238 | |
1239 | /****************************************************************************/ |
1240 | /* */ |
1241 | /* Routine Name: ips_intr_copperhead */ |
1242 | /* */ |
1243 | /* Routine Description: */ |
1244 | /* */ |
1245 | /* Polling interrupt handler */ |
1246 | /* */ |
1247 | /* ASSUMES interrupts are disabled */ |
1248 | /* */ |
1249 | /****************************************************************************/ |
1250 | int |
1251 | ips_intr_copperhead(ips_ha_t * ha) |
1252 | { |
1253 | ips_stat_t *sp; |
1254 | ips_scb_t *scb; |
1255 | IPS_STATUS cstatus; |
1256 | int intrstatus; |
1257 | |
1258 | METHOD_TRACE("ips_intr" , 2); |
1259 | |
1260 | if (!ha) |
1261 | return 0; |
1262 | |
1263 | if (!ha->active) |
1264 | return 0; |
1265 | |
1266 | intrstatus = (*ha->func.isintr) (ha); |
1267 | |
1268 | if (!intrstatus) { |
1269 | /* |
1270 | * Unexpected/Shared interrupt |
1271 | */ |
1272 | |
1273 | return 0; |
1274 | } |
1275 | |
1276 | while (true) { |
1277 | sp = &ha->sp; |
1278 | |
1279 | intrstatus = (*ha->func.isintr) (ha); |
1280 | |
1281 | if (!intrstatus) |
1282 | break; |
1283 | else |
1284 | cstatus.value = (*ha->func.statupd) (ha); |
1285 | |
1286 | if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) { |
1287 | /* Spurious Interrupt ? */ |
1288 | continue; |
1289 | } |
1290 | |
1291 | ips_chkstatus(ha, &cstatus); |
1292 | scb = (ips_scb_t *) sp->scb_addr; |
1293 | |
1294 | /* |
1295 | * use the callback function to finish things up |
1296 | * NOTE: interrupts are OFF for this |
1297 | */ |
1298 | (*scb->callback) (ha, scb); |
1299 | } /* end while */ |
1300 | return 1; |
1301 | } |
1302 | |
1303 | /****************************************************************************/ |
1304 | /* */ |
1305 | /* Routine Name: ips_intr_morpheus */ |
1306 | /* */ |
1307 | /* Routine Description: */ |
1308 | /* */ |
1309 | /* Polling interrupt handler */ |
1310 | /* */ |
1311 | /* ASSUMES interrupts are disabled */ |
1312 | /* */ |
1313 | /****************************************************************************/ |
1314 | int |
1315 | ips_intr_morpheus(ips_ha_t * ha) |
1316 | { |
1317 | ips_stat_t *sp; |
1318 | ips_scb_t *scb; |
1319 | IPS_STATUS cstatus; |
1320 | int intrstatus; |
1321 | |
1322 | METHOD_TRACE("ips_intr_morpheus" , 2); |
1323 | |
1324 | if (!ha) |
1325 | return 0; |
1326 | |
1327 | if (!ha->active) |
1328 | return 0; |
1329 | |
1330 | intrstatus = (*ha->func.isintr) (ha); |
1331 | |
1332 | if (!intrstatus) { |
1333 | /* |
1334 | * Unexpected/Shared interrupt |
1335 | */ |
1336 | |
1337 | return 0; |
1338 | } |
1339 | |
1340 | while (true) { |
1341 | sp = &ha->sp; |
1342 | |
1343 | intrstatus = (*ha->func.isintr) (ha); |
1344 | |
1345 | if (!intrstatus) |
1346 | break; |
1347 | else |
1348 | cstatus.value = (*ha->func.statupd) (ha); |
1349 | |
1350 | if (cstatus.value == 0xffffffff) |
1351 | /* No more to process */ |
1352 | break; |
1353 | |
1354 | if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) { |
1355 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
1356 | "Spurious interrupt; no ccb.\n" ); |
1357 | |
1358 | continue; |
1359 | } |
1360 | |
1361 | ips_chkstatus(ha, &cstatus); |
1362 | scb = (ips_scb_t *) sp->scb_addr; |
1363 | |
1364 | /* |
1365 | * use the callback function to finish things up |
1366 | * NOTE: interrupts are OFF for this |
1367 | */ |
1368 | (*scb->callback) (ha, scb); |
1369 | } /* end while */ |
1370 | return 1; |
1371 | } |
1372 | |
1373 | /****************************************************************************/ |
1374 | /* */ |
1375 | /* Routine Name: ips_info */ |
1376 | /* */ |
1377 | /* Routine Description: */ |
1378 | /* */ |
1379 | /* Return info about the driver */ |
1380 | /* */ |
1381 | /****************************************************************************/ |
1382 | static const char * |
1383 | ips_info(struct Scsi_Host *SH) |
1384 | { |
1385 | static char buffer[256]; |
1386 | char *bp; |
1387 | ips_ha_t *ha; |
1388 | |
1389 | METHOD_TRACE("ips_info" , 1); |
1390 | |
1391 | ha = IPS_HA(SH); |
1392 | |
1393 | if (!ha) |
1394 | return (NULL); |
1395 | |
1396 | bp = &buffer[0]; |
1397 | memset(bp, 0, sizeof (buffer)); |
1398 | |
1399 | sprintf(buf: bp, fmt: "%s%s%s Build %d" , "IBM PCI ServeRAID " , |
1400 | IPS_VERSION_HIGH, IPS_VERSION_LOW, IPS_BUILD_IDENT); |
1401 | |
1402 | if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) { |
1403 | strcat(p: bp, q: " <" ); |
1404 | strcat(p: bp, q: ips_adapter_name[ha->ad_type - 1]); |
1405 | strcat(p: bp, q: ">" ); |
1406 | } |
1407 | |
1408 | return (bp); |
1409 | } |
1410 | |
1411 | static int |
1412 | ips_write_info(struct Scsi_Host *host, char *buffer, int length) |
1413 | { |
1414 | int i; |
1415 | ips_ha_t *ha = NULL; |
1416 | |
1417 | /* Find our host structure */ |
1418 | for (i = 0; i < ips_next_controller; i++) { |
1419 | if (ips_sh[i]) { |
1420 | if (ips_sh[i] == host) { |
1421 | ha = (ips_ha_t *) ips_sh[i]->hostdata; |
1422 | break; |
1423 | } |
1424 | } |
1425 | } |
1426 | |
1427 | if (!ha) |
1428 | return (-EINVAL); |
1429 | |
1430 | return 0; |
1431 | } |
1432 | |
1433 | static int |
1434 | ips_show_info(struct seq_file *m, struct Scsi_Host *host) |
1435 | { |
1436 | int i; |
1437 | ips_ha_t *ha = NULL; |
1438 | |
1439 | /* Find our host structure */ |
1440 | for (i = 0; i < ips_next_controller; i++) { |
1441 | if (ips_sh[i]) { |
1442 | if (ips_sh[i] == host) { |
1443 | ha = (ips_ha_t *) ips_sh[i]->hostdata; |
1444 | break; |
1445 | } |
1446 | } |
1447 | } |
1448 | |
1449 | if (!ha) |
1450 | return (-EINVAL); |
1451 | |
1452 | return ips_host_info(ha, m); |
1453 | } |
1454 | |
1455 | /*--------------------------------------------------------------------------*/ |
1456 | /* Helper Functions */ |
1457 | /*--------------------------------------------------------------------------*/ |
1458 | |
1459 | /****************************************************************************/ |
1460 | /* */ |
1461 | /* Routine Name: ips_is_passthru */ |
1462 | /* */ |
1463 | /* Routine Description: */ |
1464 | /* */ |
1465 | /* Determine if the specified SCSI command is really a passthru command */ |
1466 | /* */ |
1467 | /****************************************************************************/ |
1468 | static int ips_is_passthru(struct scsi_cmnd *SC) |
1469 | { |
1470 | unsigned long flags; |
1471 | |
1472 | METHOD_TRACE("ips_is_passthru" , 1); |
1473 | |
1474 | if (!SC) |
1475 | return (0); |
1476 | |
1477 | if ((SC->cmnd[0] == IPS_IOCTL_COMMAND) && |
1478 | (SC->device->channel == 0) && |
1479 | (SC->device->id == IPS_ADAPTER_ID) && |
1480 | (SC->device->lun == 0) && scsi_sglist(cmd: SC)) { |
1481 | struct scatterlist *sg = scsi_sglist(cmd: SC); |
1482 | char *buffer; |
1483 | |
1484 | /* local_irq_save() protects the KM_IRQ0 address slot. */ |
1485 | local_irq_save(flags); |
1486 | buffer = kmap_local_page(page: sg_page(sg)) + sg->offset; |
1487 | if (buffer && buffer[0] == 'C' && buffer[1] == 'O' && |
1488 | buffer[2] == 'P' && buffer[3] == 'P') { |
1489 | kunmap_local(buffer); |
1490 | local_irq_restore(flags); |
1491 | return 1; |
1492 | } |
1493 | kunmap_local(buffer); |
1494 | local_irq_restore(flags); |
1495 | } |
1496 | return 0; |
1497 | } |
1498 | |
1499 | /****************************************************************************/ |
1500 | /* */ |
1501 | /* Routine Name: ips_alloc_passthru_buffer */ |
1502 | /* */ |
1503 | /* Routine Description: */ |
1504 | /* allocate a buffer large enough for the ioctl data if the ioctl buffer */ |
1505 | /* is too small or doesn't exist */ |
1506 | /****************************************************************************/ |
1507 | static int |
1508 | ips_alloc_passthru_buffer(ips_ha_t * ha, int length) |
1509 | { |
1510 | void *bigger_buf; |
1511 | dma_addr_t dma_busaddr; |
1512 | |
1513 | if (ha->ioctl_data && length <= ha->ioctl_len) |
1514 | return 0; |
1515 | /* there is no buffer or it's not big enough, allocate a new one */ |
1516 | bigger_buf = dma_alloc_coherent(dev: &ha->pcidev->dev, size: length, dma_handle: &dma_busaddr, |
1517 | GFP_KERNEL); |
1518 | if (bigger_buf) { |
1519 | /* free the old memory */ |
1520 | dma_free_coherent(dev: &ha->pcidev->dev, size: ha->ioctl_len, |
1521 | cpu_addr: ha->ioctl_data, dma_handle: ha->ioctl_busaddr); |
1522 | /* use the new memory */ |
1523 | ha->ioctl_data = (char *) bigger_buf; |
1524 | ha->ioctl_len = length; |
1525 | ha->ioctl_busaddr = dma_busaddr; |
1526 | } else { |
1527 | return -1; |
1528 | } |
1529 | return 0; |
1530 | } |
1531 | |
1532 | /****************************************************************************/ |
1533 | /* */ |
1534 | /* Routine Name: ips_make_passthru */ |
1535 | /* */ |
1536 | /* Routine Description: */ |
1537 | /* */ |
1538 | /* Make a passthru command out of the info in the Scsi block */ |
1539 | /* */ |
1540 | /****************************************************************************/ |
1541 | static int |
1542 | ips_make_passthru(ips_ha_t *ha, struct scsi_cmnd *SC, ips_scb_t *scb, int intr) |
1543 | { |
1544 | ips_passthru_t *pt; |
1545 | int length = 0; |
1546 | int i, ret; |
1547 | struct scatterlist *sg = scsi_sglist(cmd: SC); |
1548 | |
1549 | METHOD_TRACE("ips_make_passthru" , 1); |
1550 | |
1551 | scsi_for_each_sg(SC, sg, scsi_sg_count(SC), i) |
1552 | length += sg->length; |
1553 | |
1554 | if (length < sizeof (ips_passthru_t)) { |
1555 | /* wrong size */ |
1556 | DEBUG_VAR(1, "(%s%d) Passthru structure wrong size" , |
1557 | ips_name, ha->host_num); |
1558 | return (IPS_FAILURE); |
1559 | } |
1560 | if (ips_alloc_passthru_buffer(ha, length)) { |
1561 | /* allocation failure! If ha->ioctl_data exists, use it to return |
1562 | some error codes. Return a failed command to the scsi layer. */ |
1563 | if (ha->ioctl_data) { |
1564 | pt = (ips_passthru_t *) ha->ioctl_data; |
1565 | ips_scmd_buf_read(scmd: SC, data: pt, count: sizeof (ips_passthru_t)); |
1566 | pt->BasicStatus = 0x0B; |
1567 | pt->ExtendedStatus = 0x00; |
1568 | ips_scmd_buf_write(scmd: SC, data: pt, count: sizeof (ips_passthru_t)); |
1569 | } |
1570 | return IPS_FAILURE; |
1571 | } |
1572 | ha->ioctl_datasize = length; |
1573 | |
1574 | ips_scmd_buf_read(scmd: SC, data: ha->ioctl_data, count: ha->ioctl_datasize); |
1575 | pt = (ips_passthru_t *) ha->ioctl_data; |
1576 | |
1577 | /* |
1578 | * Some notes about the passthru interface used |
1579 | * |
1580 | * IF the scsi op_code == 0x0d then we assume |
1581 | * that the data came along with/goes with the |
1582 | * packet we received from the sg driver. In this |
1583 | * case the CmdBSize field of the pt structure is |
1584 | * used for the size of the buffer. |
1585 | */ |
1586 | |
1587 | switch (pt->CoppCmd) { |
1588 | case IPS_NUMCTRLS: |
1589 | memcpy(ha->ioctl_data + sizeof (ips_passthru_t), |
1590 | &ips_num_controllers, sizeof (int)); |
1591 | ips_scmd_buf_write(scmd: SC, data: ha->ioctl_data, |
1592 | count: sizeof (ips_passthru_t) + sizeof (int)); |
1593 | SC->result = DID_OK << 16; |
1594 | |
1595 | return (IPS_SUCCESS_IMM); |
1596 | |
1597 | case IPS_COPPUSRCMD: |
1598 | case IPS_COPPIOCCMD: |
1599 | if (SC->cmnd[0] == IPS_IOCTL_COMMAND) { |
1600 | if (length < (sizeof (ips_passthru_t) + pt->CmdBSize)) { |
1601 | /* wrong size */ |
1602 | DEBUG_VAR(1, |
1603 | "(%s%d) Passthru structure wrong size" , |
1604 | ips_name, ha->host_num); |
1605 | |
1606 | return (IPS_FAILURE); |
1607 | } |
1608 | |
1609 | if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD && |
1610 | pt->CoppCP.cmd.flashfw.op_code == |
1611 | IPS_CMD_RW_BIOSFW) { |
1612 | ret = ips_flash_copperhead(ha, pt, scb); |
1613 | ips_scmd_buf_write(scmd: SC, data: ha->ioctl_data, |
1614 | count: sizeof (ips_passthru_t)); |
1615 | return ret; |
1616 | } |
1617 | if (ips_usrcmd(ha, pt, scb)) |
1618 | return (IPS_SUCCESS); |
1619 | else |
1620 | return (IPS_FAILURE); |
1621 | } |
1622 | |
1623 | break; |
1624 | |
1625 | } /* end switch */ |
1626 | |
1627 | return (IPS_FAILURE); |
1628 | } |
1629 | |
1630 | /****************************************************************************/ |
1631 | /* Routine Name: ips_flash_copperhead */ |
1632 | /* Routine Description: */ |
1633 | /* Flash the BIOS/FW on a Copperhead style controller */ |
1634 | /****************************************************************************/ |
1635 | static int |
1636 | ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb) |
1637 | { |
1638 | int datasize; |
1639 | |
1640 | /* Trombone is the only copperhead that can do packet flash, but only |
1641 | * for firmware. No one said it had to make sense. */ |
1642 | if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) { |
1643 | if (ips_usrcmd(ha, pt, scb)) |
1644 | return IPS_SUCCESS; |
1645 | else |
1646 | return IPS_FAILURE; |
1647 | } |
1648 | pt->BasicStatus = 0x0B; |
1649 | pt->ExtendedStatus = 0; |
1650 | scb->scsi_cmd->result = DID_OK << 16; |
1651 | /* IF it's OK to Use the "CD BOOT" Flash Buffer, then you can */ |
1652 | /* avoid allocating a huge buffer per adapter ( which can fail ). */ |
1653 | if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE && |
1654 | pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) { |
1655 | pt->BasicStatus = 0; |
1656 | return ips_flash_bios(ha, pt, scb); |
1657 | } else if (pt->CoppCP.cmd.flashfw.packet_num == 0) { |
1658 | if (ips_FlashData && !test_and_set_bit(nr: 0, addr: &ips_FlashDataInUse)){ |
1659 | ha->flash_data = ips_FlashData; |
1660 | ha->flash_busaddr = ips_flashbusaddr; |
1661 | ha->flash_len = PAGE_SIZE << 7; |
1662 | ha->flash_datasize = 0; |
1663 | } else if (!ha->flash_data) { |
1664 | datasize = pt->CoppCP.cmd.flashfw.total_packets * |
1665 | pt->CoppCP.cmd.flashfw.count; |
1666 | ha->flash_data = dma_alloc_coherent(dev: &ha->pcidev->dev, |
1667 | size: datasize, dma_handle: &ha->flash_busaddr, GFP_KERNEL); |
1668 | if (!ha->flash_data){ |
1669 | printk(KERN_WARNING "Unable to allocate a flash buffer\n" ); |
1670 | return IPS_FAILURE; |
1671 | } |
1672 | ha->flash_datasize = 0; |
1673 | ha->flash_len = datasize; |
1674 | } else |
1675 | return IPS_FAILURE; |
1676 | } else { |
1677 | if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize > |
1678 | ha->flash_len) { |
1679 | ips_free_flash_copperhead(ha); |
1680 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
1681 | "failed size sanity check\n" ); |
1682 | return IPS_FAILURE; |
1683 | } |
1684 | } |
1685 | if (!ha->flash_data) |
1686 | return IPS_FAILURE; |
1687 | pt->BasicStatus = 0; |
1688 | memcpy(&ha->flash_data[ha->flash_datasize], pt + 1, |
1689 | pt->CoppCP.cmd.flashfw.count); |
1690 | ha->flash_datasize += pt->CoppCP.cmd.flashfw.count; |
1691 | if (pt->CoppCP.cmd.flashfw.packet_num == |
1692 | pt->CoppCP.cmd.flashfw.total_packets - 1) { |
1693 | if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE) |
1694 | return ips_flash_bios(ha, pt, scb); |
1695 | else if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) |
1696 | return ips_flash_firmware(ha, pt, scb); |
1697 | } |
1698 | return IPS_SUCCESS_IMM; |
1699 | } |
1700 | |
1701 | /****************************************************************************/ |
1702 | /* Routine Name: ips_flash_bios */ |
1703 | /* Routine Description: */ |
1704 | /* flashes the bios of a copperhead adapter */ |
1705 | /****************************************************************************/ |
1706 | static int |
1707 | ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb) |
1708 | { |
1709 | |
1710 | if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE && |
1711 | pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_BIOS) { |
1712 | if ((!ha->func.programbios) || (!ha->func.erasebios) || |
1713 | (!ha->func.verifybios)) |
1714 | goto error; |
1715 | if ((*ha->func.erasebios) (ha)) { |
1716 | DEBUG_VAR(1, |
1717 | "(%s%d) flash bios failed - unable to erase flash" , |
1718 | ips_name, ha->host_num); |
1719 | goto error; |
1720 | } else |
1721 | if ((*ha->func.programbios) (ha, |
1722 | ha->flash_data + |
1723 | IPS_BIOS_HEADER, |
1724 | ha->flash_datasize - |
1725 | IPS_BIOS_HEADER, 0)) { |
1726 | DEBUG_VAR(1, |
1727 | "(%s%d) flash bios failed - unable to flash" , |
1728 | ips_name, ha->host_num); |
1729 | goto error; |
1730 | } else |
1731 | if ((*ha->func.verifybios) (ha, |
1732 | ha->flash_data + |
1733 | IPS_BIOS_HEADER, |
1734 | ha->flash_datasize - |
1735 | IPS_BIOS_HEADER, 0)) { |
1736 | DEBUG_VAR(1, |
1737 | "(%s%d) flash bios failed - unable to verify flash" , |
1738 | ips_name, ha->host_num); |
1739 | goto error; |
1740 | } |
1741 | ips_free_flash_copperhead(ha); |
1742 | return IPS_SUCCESS_IMM; |
1743 | } else if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE && |
1744 | pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) { |
1745 | if (!ha->func.erasebios) |
1746 | goto error; |
1747 | if ((*ha->func.erasebios) (ha)) { |
1748 | DEBUG_VAR(1, |
1749 | "(%s%d) flash bios failed - unable to erase flash" , |
1750 | ips_name, ha->host_num); |
1751 | goto error; |
1752 | } |
1753 | return IPS_SUCCESS_IMM; |
1754 | } |
1755 | error: |
1756 | pt->BasicStatus = 0x0B; |
1757 | pt->ExtendedStatus = 0x00; |
1758 | ips_free_flash_copperhead(ha); |
1759 | return IPS_FAILURE; |
1760 | } |
1761 | |
1762 | /****************************************************************************/ |
1763 | /* */ |
1764 | /* Routine Name: ips_fill_scb_sg_single */ |
1765 | /* */ |
1766 | /* Routine Description: */ |
1767 | /* Fill in a single scb sg_list element from an address */ |
1768 | /* return a -1 if a breakup occurred */ |
1769 | /****************************************************************************/ |
1770 | static int |
1771 | ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr, |
1772 | ips_scb_t * scb, int indx, unsigned int e_len) |
1773 | { |
1774 | |
1775 | int ret_val = 0; |
1776 | |
1777 | if ((scb->data_len + e_len) > ha->max_xfer) { |
1778 | e_len = ha->max_xfer - scb->data_len; |
1779 | scb->breakup = indx; |
1780 | ++scb->sg_break; |
1781 | ret_val = -1; |
1782 | } else { |
1783 | scb->breakup = 0; |
1784 | scb->sg_break = 0; |
1785 | } |
1786 | if (IPS_USE_ENH_SGLIST(ha)) { |
1787 | scb->sg_list.enh_list[indx].address_lo = |
1788 | cpu_to_le32(lower_32_bits(busaddr)); |
1789 | scb->sg_list.enh_list[indx].address_hi = |
1790 | cpu_to_le32(upper_32_bits(busaddr)); |
1791 | scb->sg_list.enh_list[indx].length = cpu_to_le32(e_len); |
1792 | } else { |
1793 | scb->sg_list.std_list[indx].address = |
1794 | cpu_to_le32(lower_32_bits(busaddr)); |
1795 | scb->sg_list.std_list[indx].length = cpu_to_le32(e_len); |
1796 | } |
1797 | |
1798 | ++scb->sg_len; |
1799 | scb->data_len += e_len; |
1800 | return ret_val; |
1801 | } |
1802 | |
1803 | /****************************************************************************/ |
1804 | /* Routine Name: ips_flash_firmware */ |
1805 | /* Routine Description: */ |
1806 | /* flashes the firmware of a copperhead adapter */ |
1807 | /****************************************************************************/ |
1808 | static int |
1809 | ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb) |
1810 | { |
1811 | IPS_SG_LIST sg_list; |
1812 | uint32_t cmd_busaddr; |
1813 | |
1814 | if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE && |
1815 | pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_FW) { |
1816 | memset(&pt->CoppCP.cmd, 0, sizeof (IPS_HOST_COMMAND)); |
1817 | pt->CoppCP.cmd.flashfw.op_code = IPS_CMD_DOWNLOAD; |
1818 | pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize); |
1819 | } else { |
1820 | pt->BasicStatus = 0x0B; |
1821 | pt->ExtendedStatus = 0x00; |
1822 | ips_free_flash_copperhead(ha); |
1823 | return IPS_FAILURE; |
1824 | } |
1825 | /* Save the S/G list pointer so it doesn't get clobbered */ |
1826 | sg_list.list = scb->sg_list.list; |
1827 | cmd_busaddr = scb->scb_busaddr; |
1828 | /* copy in the CP */ |
1829 | memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD)); |
1830 | /* FIX stuff that might be wrong */ |
1831 | scb->sg_list.list = sg_list.list; |
1832 | scb->scb_busaddr = cmd_busaddr; |
1833 | scb->bus = scb->scsi_cmd->device->channel; |
1834 | scb->target_id = scb->scsi_cmd->device->id; |
1835 | scb->lun = scb->scsi_cmd->device->lun; |
1836 | scb->sg_len = 0; |
1837 | scb->data_len = 0; |
1838 | scb->flags = 0; |
1839 | scb->op_code = 0; |
1840 | scb->callback = ipsintr_done; |
1841 | scb->timeout = ips_cmd_timeout; |
1842 | |
1843 | scb->data_len = ha->flash_datasize; |
1844 | scb->data_busaddr = |
1845 | dma_map_single(&ha->pcidev->dev, ha->flash_data, scb->data_len, |
1846 | IPS_DMA_DIR(scb)); |
1847 | scb->flags |= IPS_SCB_MAP_SINGLE; |
1848 | scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb); |
1849 | scb->cmd.flashfw.buffer_addr = cpu_to_le32(scb->data_busaddr); |
1850 | if (pt->TimeOut) |
1851 | scb->timeout = pt->TimeOut; |
1852 | scb->scsi_cmd->result = DID_OK << 16; |
1853 | return IPS_SUCCESS; |
1854 | } |
1855 | |
1856 | /****************************************************************************/ |
1857 | /* Routine Name: ips_free_flash_copperhead */ |
1858 | /* Routine Description: */ |
1859 | /* release the memory resources used to hold the flash image */ |
1860 | /****************************************************************************/ |
1861 | static void |
1862 | ips_free_flash_copperhead(ips_ha_t * ha) |
1863 | { |
1864 | if (ha->flash_data == ips_FlashData) |
1865 | test_and_clear_bit(nr: 0, addr: &ips_FlashDataInUse); |
1866 | else if (ha->flash_data) |
1867 | dma_free_coherent(dev: &ha->pcidev->dev, size: ha->flash_len, |
1868 | cpu_addr: ha->flash_data, dma_handle: ha->flash_busaddr); |
1869 | ha->flash_data = NULL; |
1870 | } |
1871 | |
1872 | /****************************************************************************/ |
1873 | /* */ |
1874 | /* Routine Name: ips_usrcmd */ |
1875 | /* */ |
1876 | /* Routine Description: */ |
1877 | /* */ |
1878 | /* Process a user command and make it ready to send */ |
1879 | /* */ |
1880 | /****************************************************************************/ |
1881 | static int |
1882 | ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb) |
1883 | { |
1884 | IPS_SG_LIST sg_list; |
1885 | uint32_t cmd_busaddr; |
1886 | |
1887 | METHOD_TRACE("ips_usrcmd" , 1); |
1888 | |
1889 | if ((!scb) || (!pt) || (!ha)) |
1890 | return (0); |
1891 | |
1892 | /* Save the S/G list pointer so it doesn't get clobbered */ |
1893 | sg_list.list = scb->sg_list.list; |
1894 | cmd_busaddr = scb->scb_busaddr; |
1895 | /* copy in the CP */ |
1896 | memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD)); |
1897 | memcpy(&scb->dcdb, &pt->CoppCP.dcdb, sizeof (IPS_DCDB_TABLE)); |
1898 | |
1899 | /* FIX stuff that might be wrong */ |
1900 | scb->sg_list.list = sg_list.list; |
1901 | scb->scb_busaddr = cmd_busaddr; |
1902 | scb->bus = scb->scsi_cmd->device->channel; |
1903 | scb->target_id = scb->scsi_cmd->device->id; |
1904 | scb->lun = scb->scsi_cmd->device->lun; |
1905 | scb->sg_len = 0; |
1906 | scb->data_len = 0; |
1907 | scb->flags = 0; |
1908 | scb->op_code = 0; |
1909 | scb->callback = ipsintr_done; |
1910 | scb->timeout = ips_cmd_timeout; |
1911 | scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); |
1912 | |
1913 | /* we don't support DCDB/READ/WRITE Scatter Gather */ |
1914 | if ((scb->cmd.basic_io.op_code == IPS_CMD_READ_SG) || |
1915 | (scb->cmd.basic_io.op_code == IPS_CMD_WRITE_SG) || |
1916 | (scb->cmd.basic_io.op_code == IPS_CMD_DCDB_SG)) |
1917 | return (0); |
1918 | |
1919 | if (pt->CmdBSize) { |
1920 | scb->data_len = pt->CmdBSize; |
1921 | scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t); |
1922 | } else { |
1923 | scb->data_busaddr = 0L; |
1924 | } |
1925 | |
1926 | if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) |
1927 | scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr + |
1928 | (unsigned long) &scb-> |
1929 | dcdb - |
1930 | (unsigned long) scb); |
1931 | |
1932 | if (pt->CmdBSize) { |
1933 | if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) |
1934 | scb->dcdb.buffer_pointer = |
1935 | cpu_to_le32(scb->data_busaddr); |
1936 | else |
1937 | scb->cmd.basic_io.sg_addr = |
1938 | cpu_to_le32(scb->data_busaddr); |
1939 | } |
1940 | |
1941 | /* set timeouts */ |
1942 | if (pt->TimeOut) { |
1943 | scb->timeout = pt->TimeOut; |
1944 | |
1945 | if (pt->TimeOut <= 10) |
1946 | scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; |
1947 | else if (pt->TimeOut <= 60) |
1948 | scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; |
1949 | else |
1950 | scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; |
1951 | } |
1952 | |
1953 | /* assume success */ |
1954 | scb->scsi_cmd->result = DID_OK << 16; |
1955 | |
1956 | /* success */ |
1957 | return (1); |
1958 | } |
1959 | |
1960 | /****************************************************************************/ |
1961 | /* */ |
1962 | /* Routine Name: ips_cleanup_passthru */ |
1963 | /* */ |
1964 | /* Routine Description: */ |
1965 | /* */ |
1966 | /* Cleanup after a passthru command */ |
1967 | /* */ |
1968 | /****************************************************************************/ |
1969 | static void |
1970 | ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb) |
1971 | { |
1972 | ips_passthru_t *pt; |
1973 | |
1974 | METHOD_TRACE("ips_cleanup_passthru" , 1); |
1975 | |
1976 | if ((!scb) || (!scb->scsi_cmd) || (!scsi_sglist(cmd: scb->scsi_cmd))) { |
1977 | DEBUG_VAR(1, "(%s%d) couldn't cleanup after passthru" , |
1978 | ips_name, ha->host_num); |
1979 | |
1980 | return; |
1981 | } |
1982 | pt = (ips_passthru_t *) ha->ioctl_data; |
1983 | |
1984 | /* Copy data back to the user */ |
1985 | if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) /* Copy DCDB Back to Caller's Area */ |
1986 | memcpy(&pt->CoppCP.dcdb, &scb->dcdb, sizeof (IPS_DCDB_TABLE)); |
1987 | |
1988 | pt->BasicStatus = scb->basic_status; |
1989 | pt->ExtendedStatus = scb->extended_status; |
1990 | pt->AdapterType = ha->ad_type; |
1991 | |
1992 | if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD && |
1993 | (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD || |
1994 | scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW)) |
1995 | ips_free_flash_copperhead(ha); |
1996 | |
1997 | ips_scmd_buf_write(scmd: scb->scsi_cmd, data: ha->ioctl_data, count: ha->ioctl_datasize); |
1998 | } |
1999 | |
2000 | /****************************************************************************/ |
2001 | /* */ |
2002 | /* Routine Name: ips_host_info */ |
2003 | /* */ |
2004 | /* Routine Description: */ |
2005 | /* */ |
2006 | /* The passthru interface for the driver */ |
2007 | /* */ |
2008 | /****************************************************************************/ |
2009 | static int |
2010 | ips_host_info(ips_ha_t *ha, struct seq_file *m) |
2011 | { |
2012 | METHOD_TRACE("ips_host_info" , 1); |
2013 | |
2014 | seq_puts(m, s: "\nIBM ServeRAID General Information:\n\n" ); |
2015 | |
2016 | if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) && |
2017 | (le16_to_cpu(ha->nvram->adapter_type) != 0)) |
2018 | seq_printf(m, fmt: "\tController Type : %s\n" , |
2019 | ips_adapter_name[ha->ad_type - 1]); |
2020 | else |
2021 | seq_puts(m, s: "\tController Type : Unknown\n" ); |
2022 | |
2023 | if (ha->io_addr) |
2024 | seq_printf(m, |
2025 | fmt: "\tIO region : 0x%x (%d bytes)\n" , |
2026 | ha->io_addr, ha->io_len); |
2027 | |
2028 | if (ha->mem_addr) { |
2029 | seq_printf(m, |
2030 | fmt: "\tMemory region : 0x%x (%d bytes)\n" , |
2031 | ha->mem_addr, ha->mem_len); |
2032 | seq_printf(m, |
2033 | fmt: "\tShared memory address : 0x%lx\n" , |
2034 | (unsigned long)ha->mem_ptr); |
2035 | } |
2036 | |
2037 | seq_printf(m, fmt: "\tIRQ number : %d\n" , ha->pcidev->irq); |
2038 | |
2039 | /* For the Next 3 lines Check for Binary 0 at the end and don't include it if it's there. */ |
2040 | /* That keeps everything happy for "text" operations on the proc file. */ |
2041 | |
2042 | if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) { |
2043 | if (ha->nvram->bios_low[3] == 0) { |
2044 | seq_printf(m, |
2045 | fmt: "\tBIOS Version : %c%c%c%c%c%c%c\n" , |
2046 | ha->nvram->bios_high[0], ha->nvram->bios_high[1], |
2047 | ha->nvram->bios_high[2], ha->nvram->bios_high[3], |
2048 | ha->nvram->bios_low[0], ha->nvram->bios_low[1], |
2049 | ha->nvram->bios_low[2]); |
2050 | |
2051 | } else { |
2052 | seq_printf(m, |
2053 | fmt: "\tBIOS Version : %c%c%c%c%c%c%c%c\n" , |
2054 | ha->nvram->bios_high[0], ha->nvram->bios_high[1], |
2055 | ha->nvram->bios_high[2], ha->nvram->bios_high[3], |
2056 | ha->nvram->bios_low[0], ha->nvram->bios_low[1], |
2057 | ha->nvram->bios_low[2], ha->nvram->bios_low[3]); |
2058 | } |
2059 | |
2060 | } |
2061 | |
2062 | if (ha->enq->CodeBlkVersion[7] == 0) { |
2063 | seq_printf(m, |
2064 | fmt: "\tFirmware Version : %c%c%c%c%c%c%c\n" , |
2065 | ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1], |
2066 | ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3], |
2067 | ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5], |
2068 | ha->enq->CodeBlkVersion[6]); |
2069 | } else { |
2070 | seq_printf(m, |
2071 | fmt: "\tFirmware Version : %c%c%c%c%c%c%c%c\n" , |
2072 | ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1], |
2073 | ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3], |
2074 | ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5], |
2075 | ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]); |
2076 | } |
2077 | |
2078 | if (ha->enq->BootBlkVersion[7] == 0) { |
2079 | seq_printf(m, |
2080 | fmt: "\tBoot Block Version : %c%c%c%c%c%c%c\n" , |
2081 | ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1], |
2082 | ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3], |
2083 | ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5], |
2084 | ha->enq->BootBlkVersion[6]); |
2085 | } else { |
2086 | seq_printf(m, |
2087 | fmt: "\tBoot Block Version : %c%c%c%c%c%c%c%c\n" , |
2088 | ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1], |
2089 | ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3], |
2090 | ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5], |
2091 | ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]); |
2092 | } |
2093 | |
2094 | seq_printf(m, fmt: "\tDriver Version : %s%s\n" , |
2095 | IPS_VERSION_HIGH, IPS_VERSION_LOW); |
2096 | |
2097 | seq_printf(m, fmt: "\tDriver Build : %d\n" , |
2098 | IPS_BUILD_IDENT); |
2099 | |
2100 | seq_printf(m, fmt: "\tMax Physical Devices : %d\n" , |
2101 | ha->enq->ucMaxPhysicalDevices); |
2102 | seq_printf(m, fmt: "\tMax Active Commands : %d\n" , |
2103 | ha->max_cmds); |
2104 | seq_printf(m, fmt: "\tCurrent Queued Commands : %d\n" , |
2105 | ha->scb_waitlist.count); |
2106 | seq_printf(m, fmt: "\tCurrent Active Commands : %d\n" , |
2107 | ha->scb_activelist.count - ha->num_ioctl); |
2108 | seq_printf(m, fmt: "\tCurrent Queued PT Commands : %d\n" , |
2109 | ha->copp_waitlist.count); |
2110 | seq_printf(m, fmt: "\tCurrent Active PT Commands : %d\n" , |
2111 | ha->num_ioctl); |
2112 | |
2113 | seq_putc(m, c: '\n'); |
2114 | |
2115 | return 0; |
2116 | } |
2117 | |
2118 | /****************************************************************************/ |
2119 | /* */ |
2120 | /* Routine Name: ips_identify_controller */ |
2121 | /* */ |
2122 | /* Routine Description: */ |
2123 | /* */ |
2124 | /* Identify this controller */ |
2125 | /* */ |
2126 | /****************************************************************************/ |
2127 | static void |
2128 | ips_identify_controller(ips_ha_t * ha) |
2129 | { |
2130 | METHOD_TRACE("ips_identify_controller" , 1); |
2131 | |
2132 | switch (ha->pcidev->device) { |
2133 | case IPS_DEVICEID_COPPERHEAD: |
2134 | if (ha->pcidev->revision <= IPS_REVID_SERVERAID) { |
2135 | ha->ad_type = IPS_ADTYPE_SERVERAID; |
2136 | } else if (ha->pcidev->revision == IPS_REVID_SERVERAID2) { |
2137 | ha->ad_type = IPS_ADTYPE_SERVERAID2; |
2138 | } else if (ha->pcidev->revision == IPS_REVID_NAVAJO) { |
2139 | ha->ad_type = IPS_ADTYPE_NAVAJO; |
2140 | } else if ((ha->pcidev->revision == IPS_REVID_SERVERAID2) |
2141 | && (ha->slot_num == 0)) { |
2142 | ha->ad_type = IPS_ADTYPE_KIOWA; |
2143 | } else if ((ha->pcidev->revision >= IPS_REVID_CLARINETP1) && |
2144 | (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) { |
2145 | if (ha->enq->ucMaxPhysicalDevices == 15) |
2146 | ha->ad_type = IPS_ADTYPE_SERVERAID3L; |
2147 | else |
2148 | ha->ad_type = IPS_ADTYPE_SERVERAID3; |
2149 | } else if ((ha->pcidev->revision >= IPS_REVID_TROMBONE32) && |
2150 | (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) { |
2151 | ha->ad_type = IPS_ADTYPE_SERVERAID4H; |
2152 | } |
2153 | break; |
2154 | |
2155 | case IPS_DEVICEID_MORPHEUS: |
2156 | switch (ha->pcidev->subsystem_device) { |
2157 | case IPS_SUBDEVICEID_4L: |
2158 | ha->ad_type = IPS_ADTYPE_SERVERAID4L; |
2159 | break; |
2160 | |
2161 | case IPS_SUBDEVICEID_4M: |
2162 | ha->ad_type = IPS_ADTYPE_SERVERAID4M; |
2163 | break; |
2164 | |
2165 | case IPS_SUBDEVICEID_4MX: |
2166 | ha->ad_type = IPS_ADTYPE_SERVERAID4MX; |
2167 | break; |
2168 | |
2169 | case IPS_SUBDEVICEID_4LX: |
2170 | ha->ad_type = IPS_ADTYPE_SERVERAID4LX; |
2171 | break; |
2172 | |
2173 | case IPS_SUBDEVICEID_5I2: |
2174 | ha->ad_type = IPS_ADTYPE_SERVERAID5I2; |
2175 | break; |
2176 | |
2177 | case IPS_SUBDEVICEID_5I1: |
2178 | ha->ad_type = IPS_ADTYPE_SERVERAID5I1; |
2179 | break; |
2180 | } |
2181 | |
2182 | break; |
2183 | |
2184 | case IPS_DEVICEID_MARCO: |
2185 | switch (ha->pcidev->subsystem_device) { |
2186 | case IPS_SUBDEVICEID_6M: |
2187 | ha->ad_type = IPS_ADTYPE_SERVERAID6M; |
2188 | break; |
2189 | case IPS_SUBDEVICEID_6I: |
2190 | ha->ad_type = IPS_ADTYPE_SERVERAID6I; |
2191 | break; |
2192 | case IPS_SUBDEVICEID_7k: |
2193 | ha->ad_type = IPS_ADTYPE_SERVERAID7k; |
2194 | break; |
2195 | case IPS_SUBDEVICEID_7M: |
2196 | ha->ad_type = IPS_ADTYPE_SERVERAID7M; |
2197 | break; |
2198 | } |
2199 | break; |
2200 | } |
2201 | } |
2202 | |
2203 | /****************************************************************************/ |
2204 | /* */ |
2205 | /* Routine Name: ips_get_bios_version */ |
2206 | /* */ |
2207 | /* Routine Description: */ |
2208 | /* */ |
2209 | /* Get the BIOS revision number */ |
2210 | /* */ |
2211 | /****************************************************************************/ |
2212 | static void |
2213 | ips_get_bios_version(ips_ha_t * ha, int intr) |
2214 | { |
2215 | ips_scb_t *scb; |
2216 | int ret; |
2217 | uint8_t major; |
2218 | uint8_t minor; |
2219 | uint8_t subminor; |
2220 | uint8_t *buffer; |
2221 | |
2222 | METHOD_TRACE("ips_get_bios_version" , 1); |
2223 | |
2224 | major = 0; |
2225 | minor = 0; |
2226 | |
2227 | memcpy(ha->bios_version, " ?" , 8); |
2228 | |
2229 | if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) { |
2230 | if (IPS_USE_MEMIO(ha)) { |
2231 | /* Memory Mapped I/O */ |
2232 | |
2233 | /* test 1st byte */ |
2234 | writel(val: 0, addr: ha->mem_ptr + IPS_REG_FLAP); |
2235 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
2236 | udelay(25); /* 25 us */ |
2237 | |
2238 | if (readb(addr: ha->mem_ptr + IPS_REG_FLDP) != 0x55) |
2239 | return; |
2240 | |
2241 | writel(val: 1, addr: ha->mem_ptr + IPS_REG_FLAP); |
2242 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
2243 | udelay(25); /* 25 us */ |
2244 | |
2245 | if (readb(addr: ha->mem_ptr + IPS_REG_FLDP) != 0xAA) |
2246 | return; |
2247 | |
2248 | /* Get Major version */ |
2249 | writel(val: 0x1FF, addr: ha->mem_ptr + IPS_REG_FLAP); |
2250 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
2251 | udelay(25); /* 25 us */ |
2252 | |
2253 | major = readb(addr: ha->mem_ptr + IPS_REG_FLDP); |
2254 | |
2255 | /* Get Minor version */ |
2256 | writel(val: 0x1FE, addr: ha->mem_ptr + IPS_REG_FLAP); |
2257 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
2258 | udelay(25); /* 25 us */ |
2259 | minor = readb(addr: ha->mem_ptr + IPS_REG_FLDP); |
2260 | |
2261 | /* Get SubMinor version */ |
2262 | writel(val: 0x1FD, addr: ha->mem_ptr + IPS_REG_FLAP); |
2263 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
2264 | udelay(25); /* 25 us */ |
2265 | subminor = readb(addr: ha->mem_ptr + IPS_REG_FLDP); |
2266 | |
2267 | } else { |
2268 | /* Programmed I/O */ |
2269 | |
2270 | /* test 1st byte */ |
2271 | outl(value: 0, port: ha->io_addr + IPS_REG_FLAP); |
2272 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
2273 | udelay(25); /* 25 us */ |
2274 | |
2275 | if (inb(port: ha->io_addr + IPS_REG_FLDP) != 0x55) |
2276 | return; |
2277 | |
2278 | outl(value: 1, port: ha->io_addr + IPS_REG_FLAP); |
2279 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
2280 | udelay(25); /* 25 us */ |
2281 | |
2282 | if (inb(port: ha->io_addr + IPS_REG_FLDP) != 0xAA) |
2283 | return; |
2284 | |
2285 | /* Get Major version */ |
2286 | outl(value: 0x1FF, port: ha->io_addr + IPS_REG_FLAP); |
2287 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
2288 | udelay(25); /* 25 us */ |
2289 | |
2290 | major = inb(port: ha->io_addr + IPS_REG_FLDP); |
2291 | |
2292 | /* Get Minor version */ |
2293 | outl(value: 0x1FE, port: ha->io_addr + IPS_REG_FLAP); |
2294 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
2295 | udelay(25); /* 25 us */ |
2296 | |
2297 | minor = inb(port: ha->io_addr + IPS_REG_FLDP); |
2298 | |
2299 | /* Get SubMinor version */ |
2300 | outl(value: 0x1FD, port: ha->io_addr + IPS_REG_FLAP); |
2301 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
2302 | udelay(25); /* 25 us */ |
2303 | |
2304 | subminor = inb(port: ha->io_addr + IPS_REG_FLDP); |
2305 | |
2306 | } |
2307 | } else { |
2308 | /* Morpheus Family - Send Command to the card */ |
2309 | |
2310 | buffer = ha->ioctl_data; |
2311 | |
2312 | memset(buffer, 0, 0x1000); |
2313 | |
2314 | scb = &ha->scbs[ha->max_cmds - 1]; |
2315 | |
2316 | ips_init_scb(ha, scb); |
2317 | |
2318 | scb->timeout = ips_cmd_timeout; |
2319 | scb->cdb[0] = IPS_CMD_RW_BIOSFW; |
2320 | |
2321 | scb->cmd.flashfw.op_code = IPS_CMD_RW_BIOSFW; |
2322 | scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb); |
2323 | scb->cmd.flashfw.type = 1; |
2324 | scb->cmd.flashfw.direction = 0; |
2325 | scb->cmd.flashfw.count = cpu_to_le32(0x800); |
2326 | scb->cmd.flashfw.total_packets = 1; |
2327 | scb->cmd.flashfw.packet_num = 0; |
2328 | scb->data_len = 0x1000; |
2329 | scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr; |
2330 | |
2331 | /* issue the command */ |
2332 | if (((ret = |
2333 | ips_send_wait(ha, scb, ips_cmd_timeout, |
2334 | intr)) == IPS_FAILURE) |
2335 | || (ret == IPS_SUCCESS_IMM) |
2336 | || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) { |
2337 | /* Error occurred */ |
2338 | |
2339 | return; |
2340 | } |
2341 | |
2342 | if ((buffer[0xC0] == 0x55) && (buffer[0xC1] == 0xAA)) { |
2343 | major = buffer[0x1ff + 0xC0]; /* Offset 0x1ff after the header (0xc0) */ |
2344 | minor = buffer[0x1fe + 0xC0]; /* Offset 0x1fe after the header (0xc0) */ |
2345 | subminor = buffer[0x1fd + 0xC0]; /* Offset 0x1fd after the header (0xc0) */ |
2346 | } else { |
2347 | return; |
2348 | } |
2349 | } |
2350 | |
2351 | ha->bios_version[0] = hex_asc_upper_hi(major); |
2352 | ha->bios_version[1] = '.'; |
2353 | ha->bios_version[2] = hex_asc_upper_lo(major); |
2354 | ha->bios_version[3] = hex_asc_upper_lo(subminor); |
2355 | ha->bios_version[4] = '.'; |
2356 | ha->bios_version[5] = hex_asc_upper_hi(minor); |
2357 | ha->bios_version[6] = hex_asc_upper_lo(minor); |
2358 | ha->bios_version[7] = 0; |
2359 | } |
2360 | |
2361 | /****************************************************************************/ |
2362 | /* */ |
2363 | /* Routine Name: ips_hainit */ |
2364 | /* */ |
2365 | /* Routine Description: */ |
2366 | /* */ |
2367 | /* Initialize the controller */ |
2368 | /* */ |
2369 | /* NOTE: Assumes to be called from with a lock */ |
2370 | /* */ |
2371 | /****************************************************************************/ |
2372 | static int |
2373 | ips_hainit(ips_ha_t * ha) |
2374 | { |
2375 | int i; |
2376 | |
2377 | METHOD_TRACE("ips_hainit" , 1); |
2378 | |
2379 | if (!ha) |
2380 | return (0); |
2381 | |
2382 | if (ha->func.statinit) |
2383 | (*ha->func.statinit) (ha); |
2384 | |
2385 | if (ha->func.enableint) |
2386 | (*ha->func.enableint) (ha); |
2387 | |
2388 | /* Send FFDC */ |
2389 | ha->reset_count = 1; |
2390 | ha->last_ffdc = ktime_get_real_seconds(); |
2391 | ips_ffdc_reset(ha, IPS_INTR_IORL); |
2392 | |
2393 | if (!ips_read_config(ha, IPS_INTR_IORL)) { |
2394 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
2395 | "unable to read config from controller.\n" ); |
2396 | |
2397 | return (0); |
2398 | } |
2399 | /* end if */ |
2400 | if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) { |
2401 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
2402 | "unable to read controller status.\n" ); |
2403 | |
2404 | return (0); |
2405 | } |
2406 | |
2407 | /* Identify this controller */ |
2408 | ips_identify_controller(ha); |
2409 | |
2410 | if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) { |
2411 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
2412 | "unable to read subsystem parameters.\n" ); |
2413 | |
2414 | return (0); |
2415 | } |
2416 | |
2417 | /* write nvram user page 5 */ |
2418 | if (!ips_write_driver_status(ha, IPS_INTR_IORL)) { |
2419 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
2420 | "unable to write driver info to controller.\n" ); |
2421 | |
2422 | return (0); |
2423 | } |
2424 | |
2425 | /* If there are Logical Drives and a Reset Occurred, then an EraseStripeLock is Needed */ |
2426 | if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1)) |
2427 | ips_clear_adapter(ha, IPS_INTR_IORL); |
2428 | |
2429 | /* set limits on SID, LUN, BUS */ |
2430 | ha->ntargets = IPS_MAX_TARGETS + 1; |
2431 | ha->nlun = 1; |
2432 | ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1; |
2433 | |
2434 | switch (ha->conf->logical_drive[0].ucStripeSize) { |
2435 | case 4: |
2436 | ha->max_xfer = 0x10000; |
2437 | break; |
2438 | |
2439 | case 5: |
2440 | ha->max_xfer = 0x20000; |
2441 | break; |
2442 | |
2443 | case 6: |
2444 | ha->max_xfer = 0x40000; |
2445 | break; |
2446 | |
2447 | case 7: |
2448 | default: |
2449 | ha->max_xfer = 0x80000; |
2450 | break; |
2451 | } |
2452 | |
2453 | /* setup max concurrent commands */ |
2454 | if (le32_to_cpu(ha->subsys->param[4]) & 0x1) { |
2455 | /* Use the new method */ |
2456 | ha->max_cmds = ha->enq->ucConcurrentCmdCount; |
2457 | } else { |
2458 | /* use the old method */ |
2459 | switch (ha->conf->logical_drive[0].ucStripeSize) { |
2460 | case 4: |
2461 | ha->max_cmds = 32; |
2462 | break; |
2463 | |
2464 | case 5: |
2465 | ha->max_cmds = 16; |
2466 | break; |
2467 | |
2468 | case 6: |
2469 | ha->max_cmds = 8; |
2470 | break; |
2471 | |
2472 | case 7: |
2473 | default: |
2474 | ha->max_cmds = 4; |
2475 | break; |
2476 | } |
2477 | } |
2478 | |
2479 | /* Limit the Active Commands on a Lite Adapter */ |
2480 | if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) || |
2481 | (ha->ad_type == IPS_ADTYPE_SERVERAID4L) || |
2482 | (ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) { |
2483 | if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds)) |
2484 | ha->max_cmds = MaxLiteCmds; |
2485 | } |
2486 | |
2487 | /* set controller IDs */ |
2488 | ha->ha_id[0] = IPS_ADAPTER_ID; |
2489 | for (i = 1; i < ha->nbus; i++) { |
2490 | ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f; |
2491 | ha->dcdb_active[i - 1] = 0; |
2492 | } |
2493 | |
2494 | return (1); |
2495 | } |
2496 | |
2497 | /****************************************************************************/ |
2498 | /* */ |
2499 | /* Routine Name: ips_next */ |
2500 | /* */ |
2501 | /* Routine Description: */ |
2502 | /* */ |
2503 | /* Take the next command off the queue and send it to the controller */ |
2504 | /* */ |
2505 | /****************************************************************************/ |
2506 | static void |
2507 | ips_next(ips_ha_t * ha, int intr) |
2508 | { |
2509 | ips_scb_t *scb; |
2510 | struct scsi_cmnd *SC; |
2511 | struct scsi_cmnd *p; |
2512 | struct scsi_cmnd *q; |
2513 | ips_copp_wait_item_t *item; |
2514 | int ret; |
2515 | struct Scsi_Host *host; |
2516 | METHOD_TRACE("ips_next" , 1); |
2517 | |
2518 | if (!ha) |
2519 | return; |
2520 | host = ips_sh[ha->host_num]; |
2521 | /* |
2522 | * Block access to the queue function so |
2523 | * this command won't time out |
2524 | */ |
2525 | if (intr == IPS_INTR_ON) |
2526 | spin_lock(lock: host->host_lock); |
2527 | |
2528 | if ((ha->subsys->param[3] & 0x300000) |
2529 | && (ha->scb_activelist.count == 0)) { |
2530 | time64_t now = ktime_get_real_seconds(); |
2531 | if (now - ha->last_ffdc > IPS_SECS_8HOURS) { |
2532 | ha->last_ffdc = now; |
2533 | ips_ffdc_time(ha); |
2534 | } |
2535 | } |
2536 | |
2537 | /* |
2538 | * Send passthru commands |
2539 | * These have priority over normal I/O |
2540 | * but shouldn't affect performance too much |
2541 | * since we limit the number that can be active |
2542 | * on the card at any one time |
2543 | */ |
2544 | while ((ha->num_ioctl < IPS_MAX_IOCTL) && |
2545 | (ha->copp_waitlist.head) && (scb = ips_getscb(ha))) { |
2546 | |
2547 | item = ips_removeq_copp_head(&ha->copp_waitlist); |
2548 | ha->num_ioctl++; |
2549 | if (intr == IPS_INTR_ON) |
2550 | spin_unlock(lock: host->host_lock); |
2551 | scb->scsi_cmd = item->scsi_cmd; |
2552 | kfree(objp: item); |
2553 | |
2554 | ret = ips_make_passthru(ha, SC: scb->scsi_cmd, scb, intr); |
2555 | |
2556 | if (intr == IPS_INTR_ON) |
2557 | spin_lock(lock: host->host_lock); |
2558 | switch (ret) { |
2559 | case IPS_FAILURE: |
2560 | if (scb->scsi_cmd) { |
2561 | scb->scsi_cmd->result = DID_ERROR << 16; |
2562 | scsi_done(cmd: scb->scsi_cmd); |
2563 | } |
2564 | |
2565 | ips_freescb(ha, scb); |
2566 | break; |
2567 | case IPS_SUCCESS_IMM: |
2568 | if (scb->scsi_cmd) { |
2569 | scb->scsi_cmd->result = DID_OK << 16; |
2570 | scsi_done(cmd: scb->scsi_cmd); |
2571 | } |
2572 | |
2573 | ips_freescb(ha, scb); |
2574 | break; |
2575 | default: |
2576 | break; |
2577 | } /* end case */ |
2578 | |
2579 | if (ret != IPS_SUCCESS) { |
2580 | ha->num_ioctl--; |
2581 | continue; |
2582 | } |
2583 | |
2584 | ret = ips_send_cmd(ha, scb); |
2585 | |
2586 | if (ret == IPS_SUCCESS) |
2587 | ips_putq_scb_head(&ha->scb_activelist, scb); |
2588 | else |
2589 | ha->num_ioctl--; |
2590 | |
2591 | switch (ret) { |
2592 | case IPS_FAILURE: |
2593 | if (scb->scsi_cmd) { |
2594 | scb->scsi_cmd->result = DID_ERROR << 16; |
2595 | } |
2596 | |
2597 | ips_freescb(ha, scb); |
2598 | break; |
2599 | case IPS_SUCCESS_IMM: |
2600 | ips_freescb(ha, scb); |
2601 | break; |
2602 | default: |
2603 | break; |
2604 | } /* end case */ |
2605 | |
2606 | } |
2607 | |
2608 | /* |
2609 | * Send "Normal" I/O commands |
2610 | */ |
2611 | |
2612 | p = ha->scb_waitlist.head; |
2613 | while ((p) && (scb = ips_getscb(ha))) { |
2614 | if ((scmd_channel(p) > 0) |
2615 | && (ha-> |
2616 | dcdb_active[scmd_channel(p) - |
2617 | 1] & (1 << scmd_id(p)))) { |
2618 | ips_freescb(ha, scb); |
2619 | p = (struct scsi_cmnd *) p->host_scribble; |
2620 | continue; |
2621 | } |
2622 | |
2623 | q = p; |
2624 | SC = ips_removeq_wait(&ha->scb_waitlist, q); |
2625 | |
2626 | if (intr == IPS_INTR_ON) |
2627 | spin_unlock(lock: host->host_lock); /* Unlock HA after command is taken off queue */ |
2628 | |
2629 | SC->result = DID_OK; |
2630 | SC->host_scribble = NULL; |
2631 | |
2632 | scb->target_id = SC->device->id; |
2633 | scb->lun = SC->device->lun; |
2634 | scb->bus = SC->device->channel; |
2635 | scb->scsi_cmd = SC; |
2636 | scb->breakup = 0; |
2637 | scb->data_len = 0; |
2638 | scb->callback = ipsintr_done; |
2639 | scb->timeout = ips_cmd_timeout; |
2640 | memset(&scb->cmd, 0, 16); |
2641 | |
2642 | /* copy in the CDB */ |
2643 | memcpy(scb->cdb, SC->cmnd, SC->cmd_len); |
2644 | |
2645 | scb->sg_count = scsi_dma_map(cmd: SC); |
2646 | BUG_ON(scb->sg_count < 0); |
2647 | if (scb->sg_count) { |
2648 | struct scatterlist *sg; |
2649 | int i; |
2650 | |
2651 | scb->flags |= IPS_SCB_MAP_SG; |
2652 | |
2653 | scsi_for_each_sg(SC, sg, scb->sg_count, i) { |
2654 | if (ips_fill_scb_sg_single |
2655 | (ha, sg_dma_address(sg), scb, indx: i, |
2656 | sg_dma_len(sg)) < 0) |
2657 | break; |
2658 | } |
2659 | scb->dcdb.transfer_length = scb->data_len; |
2660 | } else { |
2661 | scb->data_busaddr = 0L; |
2662 | scb->sg_len = 0; |
2663 | scb->data_len = 0; |
2664 | scb->dcdb.transfer_length = 0; |
2665 | } |
2666 | |
2667 | scb->dcdb.cmd_attribute = |
2668 | ips_command_direction[scb->scsi_cmd->cmnd[0]]; |
2669 | |
2670 | /* Allow a WRITE BUFFER Command to Have no Data */ |
2671 | /* This is Used by Tape Flash Utilites */ |
2672 | if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) && |
2673 | (scb->data_len == 0)) |
2674 | scb->dcdb.cmd_attribute = 0; |
2675 | |
2676 | if (!(scb->dcdb.cmd_attribute & 0x3)) |
2677 | scb->dcdb.transfer_length = 0; |
2678 | |
2679 | if (scb->data_len >= IPS_MAX_XFER) { |
2680 | scb->dcdb.cmd_attribute |= IPS_TRANSFER64K; |
2681 | scb->dcdb.transfer_length = 0; |
2682 | } |
2683 | if (intr == IPS_INTR_ON) |
2684 | spin_lock(lock: host->host_lock); |
2685 | |
2686 | ret = ips_send_cmd(ha, scb); |
2687 | |
2688 | switch (ret) { |
2689 | case IPS_SUCCESS: |
2690 | ips_putq_scb_head(&ha->scb_activelist, scb); |
2691 | break; |
2692 | case IPS_FAILURE: |
2693 | if (scb->scsi_cmd) { |
2694 | scb->scsi_cmd->result = DID_ERROR << 16; |
2695 | scsi_done(cmd: scb->scsi_cmd); |
2696 | } |
2697 | |
2698 | if (scb->bus) |
2699 | ha->dcdb_active[scb->bus - 1] &= |
2700 | ~(1 << scb->target_id); |
2701 | |
2702 | ips_freescb(ha, scb); |
2703 | break; |
2704 | case IPS_SUCCESS_IMM: |
2705 | if (scb->scsi_cmd) |
2706 | scsi_done(cmd: scb->scsi_cmd); |
2707 | |
2708 | if (scb->bus) |
2709 | ha->dcdb_active[scb->bus - 1] &= |
2710 | ~(1 << scb->target_id); |
2711 | |
2712 | ips_freescb(ha, scb); |
2713 | break; |
2714 | default: |
2715 | break; |
2716 | } /* end case */ |
2717 | |
2718 | p = (struct scsi_cmnd *) p->host_scribble; |
2719 | |
2720 | } /* end while */ |
2721 | |
2722 | if (intr == IPS_INTR_ON) |
2723 | spin_unlock(lock: host->host_lock); |
2724 | } |
2725 | |
2726 | /****************************************************************************/ |
2727 | /* */ |
2728 | /* Routine Name: ips_putq_scb_head */ |
2729 | /* */ |
2730 | /* Routine Description: */ |
2731 | /* */ |
2732 | /* Add an item to the head of the queue */ |
2733 | /* */ |
2734 | /* ASSUMED to be called from within the HA lock */ |
2735 | /* */ |
2736 | /****************************************************************************/ |
2737 | static void |
2738 | ips_putq_scb_head(ips_scb_queue_t * queue, ips_scb_t * item) |
2739 | { |
2740 | METHOD_TRACE("ips_putq_scb_head" , 1); |
2741 | |
2742 | if (!item) |
2743 | return; |
2744 | |
2745 | item->q_next = queue->head; |
2746 | queue->head = item; |
2747 | |
2748 | if (!queue->tail) |
2749 | queue->tail = item; |
2750 | |
2751 | queue->count++; |
2752 | } |
2753 | |
2754 | /****************************************************************************/ |
2755 | /* */ |
2756 | /* Routine Name: ips_removeq_scb_head */ |
2757 | /* */ |
2758 | /* Routine Description: */ |
2759 | /* */ |
2760 | /* Remove the head of the queue */ |
2761 | /* */ |
2762 | /* ASSUMED to be called from within the HA lock */ |
2763 | /* */ |
2764 | /****************************************************************************/ |
2765 | static ips_scb_t * |
2766 | ips_removeq_scb_head(ips_scb_queue_t * queue) |
2767 | { |
2768 | ips_scb_t *item; |
2769 | |
2770 | METHOD_TRACE("ips_removeq_scb_head" , 1); |
2771 | |
2772 | item = queue->head; |
2773 | |
2774 | if (!item) { |
2775 | return (NULL); |
2776 | } |
2777 | |
2778 | queue->head = item->q_next; |
2779 | item->q_next = NULL; |
2780 | |
2781 | if (queue->tail == item) |
2782 | queue->tail = NULL; |
2783 | |
2784 | queue->count--; |
2785 | |
2786 | return (item); |
2787 | } |
2788 | |
2789 | /****************************************************************************/ |
2790 | /* */ |
2791 | /* Routine Name: ips_removeq_scb */ |
2792 | /* */ |
2793 | /* Routine Description: */ |
2794 | /* */ |
2795 | /* Remove an item from a queue */ |
2796 | /* */ |
2797 | /* ASSUMED to be called from within the HA lock */ |
2798 | /* */ |
2799 | /****************************************************************************/ |
2800 | static ips_scb_t * |
2801 | ips_removeq_scb(ips_scb_queue_t * queue, ips_scb_t * item) |
2802 | { |
2803 | ips_scb_t *p; |
2804 | |
2805 | METHOD_TRACE("ips_removeq_scb" , 1); |
2806 | |
2807 | if (!item) |
2808 | return (NULL); |
2809 | |
2810 | if (item == queue->head) { |
2811 | return (ips_removeq_scb_head(queue)); |
2812 | } |
2813 | |
2814 | p = queue->head; |
2815 | |
2816 | while ((p) && (item != p->q_next)) |
2817 | p = p->q_next; |
2818 | |
2819 | if (p) { |
2820 | /* found a match */ |
2821 | p->q_next = item->q_next; |
2822 | |
2823 | if (!item->q_next) |
2824 | queue->tail = p; |
2825 | |
2826 | item->q_next = NULL; |
2827 | queue->count--; |
2828 | |
2829 | return (item); |
2830 | } |
2831 | |
2832 | return (NULL); |
2833 | } |
2834 | |
2835 | /****************************************************************************/ |
2836 | /* */ |
2837 | /* Routine Name: ips_putq_wait_tail */ |
2838 | /* */ |
2839 | /* Routine Description: */ |
2840 | /* */ |
2841 | /* Add an item to the tail of the queue */ |
2842 | /* */ |
2843 | /* ASSUMED to be called from within the HA lock */ |
2844 | /* */ |
2845 | /****************************************************************************/ |
2846 | static void ips_putq_wait_tail(ips_wait_queue_entry_t *queue, struct scsi_cmnd *item) |
2847 | { |
2848 | METHOD_TRACE("ips_putq_wait_tail" , 1); |
2849 | |
2850 | if (!item) |
2851 | return; |
2852 | |
2853 | item->host_scribble = NULL; |
2854 | |
2855 | if (queue->tail) |
2856 | queue->tail->host_scribble = (char *) item; |
2857 | |
2858 | queue->tail = item; |
2859 | |
2860 | if (!queue->head) |
2861 | queue->head = item; |
2862 | |
2863 | queue->count++; |
2864 | } |
2865 | |
2866 | /****************************************************************************/ |
2867 | /* */ |
2868 | /* Routine Name: ips_removeq_wait_head */ |
2869 | /* */ |
2870 | /* Routine Description: */ |
2871 | /* */ |
2872 | /* Remove the head of the queue */ |
2873 | /* */ |
2874 | /* ASSUMED to be called from within the HA lock */ |
2875 | /* */ |
2876 | /****************************************************************************/ |
2877 | static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_entry_t *queue) |
2878 | { |
2879 | struct scsi_cmnd *item; |
2880 | |
2881 | METHOD_TRACE("ips_removeq_wait_head" , 1); |
2882 | |
2883 | item = queue->head; |
2884 | |
2885 | if (!item) { |
2886 | return (NULL); |
2887 | } |
2888 | |
2889 | queue->head = (struct scsi_cmnd *) item->host_scribble; |
2890 | item->host_scribble = NULL; |
2891 | |
2892 | if (queue->tail == item) |
2893 | queue->tail = NULL; |
2894 | |
2895 | queue->count--; |
2896 | |
2897 | return (item); |
2898 | } |
2899 | |
2900 | /****************************************************************************/ |
2901 | /* */ |
2902 | /* Routine Name: ips_removeq_wait */ |
2903 | /* */ |
2904 | /* Routine Description: */ |
2905 | /* */ |
2906 | /* Remove an item from a queue */ |
2907 | /* */ |
2908 | /* ASSUMED to be called from within the HA lock */ |
2909 | /* */ |
2910 | /****************************************************************************/ |
2911 | static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_entry_t *queue, |
2912 | struct scsi_cmnd *item) |
2913 | { |
2914 | struct scsi_cmnd *p; |
2915 | |
2916 | METHOD_TRACE("ips_removeq_wait" , 1); |
2917 | |
2918 | if (!item) |
2919 | return (NULL); |
2920 | |
2921 | if (item == queue->head) { |
2922 | return (ips_removeq_wait_head(queue)); |
2923 | } |
2924 | |
2925 | p = queue->head; |
2926 | |
2927 | while ((p) && (item != (struct scsi_cmnd *) p->host_scribble)) |
2928 | p = (struct scsi_cmnd *) p->host_scribble; |
2929 | |
2930 | if (p) { |
2931 | /* found a match */ |
2932 | p->host_scribble = item->host_scribble; |
2933 | |
2934 | if (!item->host_scribble) |
2935 | queue->tail = p; |
2936 | |
2937 | item->host_scribble = NULL; |
2938 | queue->count--; |
2939 | |
2940 | return (item); |
2941 | } |
2942 | |
2943 | return (NULL); |
2944 | } |
2945 | |
2946 | /****************************************************************************/ |
2947 | /* */ |
2948 | /* Routine Name: ips_putq_copp_tail */ |
2949 | /* */ |
2950 | /* Routine Description: */ |
2951 | /* */ |
2952 | /* Add an item to the tail of the queue */ |
2953 | /* */ |
2954 | /* ASSUMED to be called from within the HA lock */ |
2955 | /* */ |
2956 | /****************************************************************************/ |
2957 | static void |
2958 | ips_putq_copp_tail(ips_copp_queue_t * queue, ips_copp_wait_item_t * item) |
2959 | { |
2960 | METHOD_TRACE("ips_putq_copp_tail" , 1); |
2961 | |
2962 | if (!item) |
2963 | return; |
2964 | |
2965 | item->next = NULL; |
2966 | |
2967 | if (queue->tail) |
2968 | queue->tail->next = item; |
2969 | |
2970 | queue->tail = item; |
2971 | |
2972 | if (!queue->head) |
2973 | queue->head = item; |
2974 | |
2975 | queue->count++; |
2976 | } |
2977 | |
2978 | /****************************************************************************/ |
2979 | /* */ |
2980 | /* Routine Name: ips_removeq_copp_head */ |
2981 | /* */ |
2982 | /* Routine Description: */ |
2983 | /* */ |
2984 | /* Remove the head of the queue */ |
2985 | /* */ |
2986 | /* ASSUMED to be called from within the HA lock */ |
2987 | /* */ |
2988 | /****************************************************************************/ |
2989 | static ips_copp_wait_item_t * |
2990 | ips_removeq_copp_head(ips_copp_queue_t * queue) |
2991 | { |
2992 | ips_copp_wait_item_t *item; |
2993 | |
2994 | METHOD_TRACE("ips_removeq_copp_head" , 1); |
2995 | |
2996 | item = queue->head; |
2997 | |
2998 | if (!item) { |
2999 | return (NULL); |
3000 | } |
3001 | |
3002 | queue->head = item->next; |
3003 | item->next = NULL; |
3004 | |
3005 | if (queue->tail == item) |
3006 | queue->tail = NULL; |
3007 | |
3008 | queue->count--; |
3009 | |
3010 | return (item); |
3011 | } |
3012 | |
3013 | /****************************************************************************/ |
3014 | /* */ |
3015 | /* Routine Name: ips_removeq_copp */ |
3016 | /* */ |
3017 | /* Routine Description: */ |
3018 | /* */ |
3019 | /* Remove an item from a queue */ |
3020 | /* */ |
3021 | /* ASSUMED to be called from within the HA lock */ |
3022 | /* */ |
3023 | /****************************************************************************/ |
3024 | static ips_copp_wait_item_t * |
3025 | ips_removeq_copp(ips_copp_queue_t * queue, ips_copp_wait_item_t * item) |
3026 | { |
3027 | ips_copp_wait_item_t *p; |
3028 | |
3029 | METHOD_TRACE("ips_removeq_copp" , 1); |
3030 | |
3031 | if (!item) |
3032 | return (NULL); |
3033 | |
3034 | if (item == queue->head) { |
3035 | return (ips_removeq_copp_head(queue)); |
3036 | } |
3037 | |
3038 | p = queue->head; |
3039 | |
3040 | while ((p) && (item != p->next)) |
3041 | p = p->next; |
3042 | |
3043 | if (p) { |
3044 | /* found a match */ |
3045 | p->next = item->next; |
3046 | |
3047 | if (!item->next) |
3048 | queue->tail = p; |
3049 | |
3050 | item->next = NULL; |
3051 | queue->count--; |
3052 | |
3053 | return (item); |
3054 | } |
3055 | |
3056 | return (NULL); |
3057 | } |
3058 | |
3059 | /****************************************************************************/ |
3060 | /* */ |
3061 | /* Routine Name: ipsintr_blocking */ |
3062 | /* */ |
3063 | /* Routine Description: */ |
3064 | /* */ |
3065 | /* Finalize an interrupt for internal commands */ |
3066 | /* */ |
3067 | /****************************************************************************/ |
3068 | static void |
3069 | ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb) |
3070 | { |
3071 | METHOD_TRACE("ipsintr_blocking" , 2); |
3072 | |
3073 | ips_freescb(ha, scb); |
3074 | if (ha->waitflag && ha->cmd_in_progress == scb->cdb[0]) { |
3075 | ha->waitflag = false; |
3076 | |
3077 | return; |
3078 | } |
3079 | } |
3080 | |
3081 | /****************************************************************************/ |
3082 | /* */ |
3083 | /* Routine Name: ipsintr_done */ |
3084 | /* */ |
3085 | /* Routine Description: */ |
3086 | /* */ |
3087 | /* Finalize an interrupt for non-internal commands */ |
3088 | /* */ |
3089 | /****************************************************************************/ |
3090 | static void |
3091 | ipsintr_done(ips_ha_t * ha, ips_scb_t * scb) |
3092 | { |
3093 | METHOD_TRACE("ipsintr_done" , 2); |
3094 | |
3095 | if (!scb) { |
3096 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
3097 | "Spurious interrupt; scb NULL.\n" ); |
3098 | |
3099 | return; |
3100 | } |
3101 | |
3102 | if (scb->scsi_cmd == NULL) { |
3103 | /* unexpected interrupt */ |
3104 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
3105 | "Spurious interrupt; scsi_cmd not set.\n" ); |
3106 | |
3107 | return; |
3108 | } |
3109 | |
3110 | ips_done(ha, scb); |
3111 | } |
3112 | |
3113 | /****************************************************************************/ |
3114 | /* */ |
3115 | /* Routine Name: ips_done */ |
3116 | /* */ |
3117 | /* Routine Description: */ |
3118 | /* */ |
3119 | /* Do housekeeping on completed commands */ |
3120 | /* ASSUMED to be called form within the request lock */ |
3121 | /****************************************************************************/ |
3122 | static void |
3123 | ips_done(ips_ha_t * ha, ips_scb_t * scb) |
3124 | { |
3125 | int ret; |
3126 | |
3127 | METHOD_TRACE("ips_done" , 1); |
3128 | |
3129 | if (!scb) |
3130 | return; |
3131 | |
3132 | if ((scb->scsi_cmd) && (ips_is_passthru(SC: scb->scsi_cmd))) { |
3133 | ips_cleanup_passthru(ha, scb); |
3134 | ha->num_ioctl--; |
3135 | } else { |
3136 | /* |
3137 | * Check to see if this command had too much |
3138 | * data and had to be broke up. If so, queue |
3139 | * the rest of the data and continue. |
3140 | */ |
3141 | if ((scb->breakup) || (scb->sg_break)) { |
3142 | struct scatterlist *sg; |
3143 | int i, sg_dma_index, ips_sg_index = 0; |
3144 | |
3145 | /* we had a data breakup */ |
3146 | scb->data_len = 0; |
3147 | |
3148 | sg = scsi_sglist(cmd: scb->scsi_cmd); |
3149 | |
3150 | /* Spin forward to last dma chunk */ |
3151 | sg_dma_index = scb->breakup; |
3152 | for (i = 0; i < scb->breakup; i++) |
3153 | sg = sg_next(sg); |
3154 | |
3155 | /* Take care of possible partial on last chunk */ |
3156 | ips_fill_scb_sg_single(ha, |
3157 | sg_dma_address(sg), |
3158 | scb, indx: ips_sg_index++, |
3159 | sg_dma_len(sg)); |
3160 | |
3161 | for (; sg_dma_index < scsi_sg_count(cmd: scb->scsi_cmd); |
3162 | sg_dma_index++, sg = sg_next(sg)) { |
3163 | if (ips_fill_scb_sg_single |
3164 | (ha, |
3165 | sg_dma_address(sg), |
3166 | scb, indx: ips_sg_index++, |
3167 | sg_dma_len(sg)) < 0) |
3168 | break; |
3169 | } |
3170 | |
3171 | scb->dcdb.transfer_length = scb->data_len; |
3172 | scb->dcdb.cmd_attribute |= |
3173 | ips_command_direction[scb->scsi_cmd->cmnd[0]]; |
3174 | |
3175 | if (!(scb->dcdb.cmd_attribute & 0x3)) |
3176 | scb->dcdb.transfer_length = 0; |
3177 | |
3178 | if (scb->data_len >= IPS_MAX_XFER) { |
3179 | scb->dcdb.cmd_attribute |= IPS_TRANSFER64K; |
3180 | scb->dcdb.transfer_length = 0; |
3181 | } |
3182 | |
3183 | ret = ips_send_cmd(ha, scb); |
3184 | |
3185 | switch (ret) { |
3186 | case IPS_FAILURE: |
3187 | if (scb->scsi_cmd) { |
3188 | scb->scsi_cmd->result = DID_ERROR << 16; |
3189 | scsi_done(cmd: scb->scsi_cmd); |
3190 | } |
3191 | |
3192 | ips_freescb(ha, scb); |
3193 | break; |
3194 | case IPS_SUCCESS_IMM: |
3195 | if (scb->scsi_cmd) { |
3196 | scb->scsi_cmd->result = DID_ERROR << 16; |
3197 | scsi_done(cmd: scb->scsi_cmd); |
3198 | } |
3199 | |
3200 | ips_freescb(ha, scb); |
3201 | break; |
3202 | default: |
3203 | break; |
3204 | } /* end case */ |
3205 | |
3206 | return; |
3207 | } |
3208 | } /* end if passthru */ |
3209 | |
3210 | if (scb->bus) { |
3211 | ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id); |
3212 | } |
3213 | |
3214 | scsi_done(cmd: scb->scsi_cmd); |
3215 | |
3216 | ips_freescb(ha, scb); |
3217 | } |
3218 | |
3219 | /****************************************************************************/ |
3220 | /* */ |
3221 | /* Routine Name: ips_map_status */ |
3222 | /* */ |
3223 | /* Routine Description: */ |
3224 | /* */ |
3225 | /* Map Controller Error codes to Linux Error Codes */ |
3226 | /* */ |
3227 | /****************************************************************************/ |
3228 | static int |
3229 | ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp) |
3230 | { |
3231 | int errcode; |
3232 | int device_error; |
3233 | uint32_t transfer_len; |
3234 | IPS_DCDB_TABLE_TAPE *tapeDCDB; |
3235 | IPS_SCSI_INQ_DATA inquiryData; |
3236 | |
3237 | METHOD_TRACE("ips_map_status" , 1); |
3238 | |
3239 | if (scb->bus) { |
3240 | DEBUG_VAR(2, |
3241 | "(%s%d) Physical device error (%d %d %d): %x %x, Sense Key: %x, ASC: %x, ASCQ: %x" , |
3242 | ips_name, ha->host_num, |
3243 | scb->scsi_cmd->device->channel, |
3244 | scb->scsi_cmd->device->id, scb->scsi_cmd->device->lun, |
3245 | scb->basic_status, scb->extended_status, |
3246 | scb->extended_status == |
3247 | IPS_ERR_CKCOND ? scb->dcdb.sense_info[2] & 0xf : 0, |
3248 | scb->extended_status == |
3249 | IPS_ERR_CKCOND ? scb->dcdb.sense_info[12] : 0, |
3250 | scb->extended_status == |
3251 | IPS_ERR_CKCOND ? scb->dcdb.sense_info[13] : 0); |
3252 | } |
3253 | |
3254 | /* default driver error */ |
3255 | errcode = DID_ERROR; |
3256 | device_error = 0; |
3257 | |
3258 | switch (scb->basic_status & IPS_GSC_STATUS_MASK) { |
3259 | case IPS_CMD_TIMEOUT: |
3260 | errcode = DID_TIME_OUT; |
3261 | break; |
3262 | |
3263 | case IPS_INVAL_OPCO: |
3264 | case IPS_INVAL_CMD_BLK: |
3265 | case IPS_INVAL_PARM_BLK: |
3266 | case IPS_LD_ERROR: |
3267 | case IPS_CMD_CMPLT_WERROR: |
3268 | break; |
3269 | |
3270 | case IPS_PHYS_DRV_ERROR: |
3271 | switch (scb->extended_status) { |
3272 | case IPS_ERR_SEL_TO: |
3273 | if (scb->bus) |
3274 | errcode = DID_NO_CONNECT; |
3275 | |
3276 | break; |
3277 | |
3278 | case IPS_ERR_OU_RUN: |
3279 | if ((scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB) || |
3280 | (scb->cmd.dcdb.op_code == |
3281 | IPS_CMD_EXTENDED_DCDB_SG)) { |
3282 | tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; |
3283 | transfer_len = tapeDCDB->transfer_length; |
3284 | } else { |
3285 | transfer_len = |
3286 | (uint32_t) scb->dcdb.transfer_length; |
3287 | } |
3288 | |
3289 | if ((scb->bus) && (transfer_len < scb->data_len)) { |
3290 | /* Underrun - set default to no error */ |
3291 | errcode = DID_OK; |
3292 | |
3293 | /* Restrict access to physical DASD */ |
3294 | if (scb->scsi_cmd->cmnd[0] == INQUIRY) { |
3295 | ips_scmd_buf_read(scmd: scb->scsi_cmd, |
3296 | data: &inquiryData, count: sizeof (inquiryData)); |
3297 | if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) { |
3298 | errcode = DID_TIME_OUT; |
3299 | break; |
3300 | } |
3301 | } |
3302 | } else |
3303 | errcode = DID_ERROR; |
3304 | |
3305 | break; |
3306 | |
3307 | case IPS_ERR_RECOVERY: |
3308 | /* don't fail recovered errors */ |
3309 | if (scb->bus) |
3310 | errcode = DID_OK; |
3311 | |
3312 | break; |
3313 | |
3314 | case IPS_ERR_HOST_RESET: |
3315 | case IPS_ERR_DEV_RESET: |
3316 | errcode = DID_RESET; |
3317 | break; |
3318 | |
3319 | case IPS_ERR_CKCOND: |
3320 | if (scb->bus) { |
3321 | if ((scb->cmd.dcdb.op_code == |
3322 | IPS_CMD_EXTENDED_DCDB) |
3323 | || (scb->cmd.dcdb.op_code == |
3324 | IPS_CMD_EXTENDED_DCDB_SG)) { |
3325 | tapeDCDB = |
3326 | (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; |
3327 | memcpy_and_pad(dest: scb->scsi_cmd->sense_buffer, |
3328 | SCSI_SENSE_BUFFERSIZE, |
3329 | src: tapeDCDB->sense_info, |
3330 | count: sizeof(tapeDCDB->sense_info), pad: 0); |
3331 | } else { |
3332 | memcpy_and_pad(dest: scb->scsi_cmd->sense_buffer, |
3333 | SCSI_SENSE_BUFFERSIZE, |
3334 | src: scb->dcdb.sense_info, |
3335 | count: sizeof(scb->dcdb.sense_info), pad: 0); |
3336 | } |
3337 | device_error = 2; /* check condition */ |
3338 | } |
3339 | |
3340 | errcode = DID_OK; |
3341 | |
3342 | break; |
3343 | |
3344 | default: |
3345 | errcode = DID_ERROR; |
3346 | break; |
3347 | |
3348 | } /* end switch */ |
3349 | } /* end switch */ |
3350 | |
3351 | scb->scsi_cmd->result = device_error | (errcode << 16); |
3352 | |
3353 | return (1); |
3354 | } |
3355 | |
3356 | /****************************************************************************/ |
3357 | /* */ |
3358 | /* Routine Name: ips_send_wait */ |
3359 | /* */ |
3360 | /* Routine Description: */ |
3361 | /* */ |
3362 | /* Send a command to the controller and wait for it to return */ |
3363 | /* */ |
3364 | /* The FFDC Time Stamp use this function for the callback, but doesn't */ |
3365 | /* actually need to wait. */ |
3366 | /****************************************************************************/ |
3367 | static int |
3368 | ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr) |
3369 | { |
3370 | int ret; |
3371 | |
3372 | METHOD_TRACE("ips_send_wait" , 1); |
3373 | |
3374 | if (intr != IPS_FFDC) { /* Won't be Waiting if this is a Time Stamp */ |
3375 | ha->waitflag = true; |
3376 | ha->cmd_in_progress = scb->cdb[0]; |
3377 | } |
3378 | scb->callback = ipsintr_blocking; |
3379 | ret = ips_send_cmd(ha, scb); |
3380 | |
3381 | if ((ret == IPS_FAILURE) || (ret == IPS_SUCCESS_IMM)) |
3382 | return (ret); |
3383 | |
3384 | if (intr != IPS_FFDC) /* Don't Wait around if this is a Time Stamp */ |
3385 | ret = ips_wait(ha, timeout, intr); |
3386 | |
3387 | return (ret); |
3388 | } |
3389 | |
3390 | /****************************************************************************/ |
3391 | /* */ |
3392 | /* Routine Name: ips_scmd_buf_write */ |
3393 | /* */ |
3394 | /* Routine Description: */ |
3395 | /* Write data to struct scsi_cmnd request_buffer at proper offsets */ |
3396 | /****************************************************************************/ |
3397 | static void |
3398 | ips_scmd_buf_write(struct scsi_cmnd *scmd, void *data, unsigned int count) |
3399 | { |
3400 | unsigned long flags; |
3401 | |
3402 | local_irq_save(flags); |
3403 | scsi_sg_copy_from_buffer(cmd: scmd, buf: data, buflen: count); |
3404 | local_irq_restore(flags); |
3405 | } |
3406 | |
3407 | /****************************************************************************/ |
3408 | /* */ |
3409 | /* Routine Name: ips_scmd_buf_read */ |
3410 | /* */ |
3411 | /* Routine Description: */ |
3412 | /* Copy data from a struct scsi_cmnd to a new, linear buffer */ |
3413 | /****************************************************************************/ |
3414 | static void |
3415 | ips_scmd_buf_read(struct scsi_cmnd *scmd, void *data, unsigned int count) |
3416 | { |
3417 | unsigned long flags; |
3418 | |
3419 | local_irq_save(flags); |
3420 | scsi_sg_copy_to_buffer(cmd: scmd, buf: data, buflen: count); |
3421 | local_irq_restore(flags); |
3422 | } |
3423 | |
3424 | /****************************************************************************/ |
3425 | /* */ |
3426 | /* Routine Name: ips_send_cmd */ |
3427 | /* */ |
3428 | /* Routine Description: */ |
3429 | /* */ |
3430 | /* Map SCSI commands to ServeRAID commands for logical drives */ |
3431 | /* */ |
3432 | /****************************************************************************/ |
3433 | static int |
3434 | ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb) |
3435 | { |
3436 | int ret; |
3437 | char *sp; |
3438 | int device_error; |
3439 | IPS_DCDB_TABLE_TAPE *tapeDCDB; |
3440 | int TimeOut; |
3441 | |
3442 | METHOD_TRACE("ips_send_cmd" , 1); |
3443 | |
3444 | ret = IPS_SUCCESS; |
3445 | |
3446 | if (!scb->scsi_cmd) { |
3447 | /* internal command */ |
3448 | |
3449 | if (scb->bus > 0) { |
3450 | /* Controller commands can't be issued */ |
3451 | /* to real devices -- fail them */ |
3452 | if (ha->waitflag && ha->cmd_in_progress == scb->cdb[0]) |
3453 | ha->waitflag = false; |
3454 | |
3455 | return (1); |
3456 | } |
3457 | } else if ((scb->bus == 0) && (!ips_is_passthru(SC: scb->scsi_cmd))) { |
3458 | /* command to logical bus -- interpret */ |
3459 | ret = IPS_SUCCESS_IMM; |
3460 | |
3461 | switch (scb->scsi_cmd->cmnd[0]) { |
3462 | case ALLOW_MEDIUM_REMOVAL: |
3463 | case REZERO_UNIT: |
3464 | case ERASE: |
3465 | case WRITE_FILEMARKS: |
3466 | case SPACE: |
3467 | scb->scsi_cmd->result = DID_ERROR << 16; |
3468 | break; |
3469 | |
3470 | case START_STOP: |
3471 | scb->scsi_cmd->result = DID_OK << 16; |
3472 | break; |
3473 | |
3474 | case TEST_UNIT_READY: |
3475 | case INQUIRY: |
3476 | if (scb->target_id == IPS_ADAPTER_ID) { |
3477 | /* |
3478 | * Either we have a TUR |
3479 | * or we have a SCSI inquiry |
3480 | */ |
3481 | if (scb->scsi_cmd->cmnd[0] == TEST_UNIT_READY) |
3482 | scb->scsi_cmd->result = DID_OK << 16; |
3483 | |
3484 | if (scb->scsi_cmd->cmnd[0] == INQUIRY) { |
3485 | IPS_SCSI_INQ_DATA inquiry; |
3486 | |
3487 | memset(&inquiry, 0, |
3488 | sizeof (IPS_SCSI_INQ_DATA)); |
3489 | |
3490 | inquiry.DeviceType = |
3491 | IPS_SCSI_INQ_TYPE_PROCESSOR; |
3492 | inquiry.DeviceTypeQualifier = |
3493 | IPS_SCSI_INQ_LU_CONNECTED; |
3494 | inquiry.Version = IPS_SCSI_INQ_REV2; |
3495 | inquiry.ResponseDataFormat = |
3496 | IPS_SCSI_INQ_RD_REV2; |
3497 | inquiry.AdditionalLength = 31; |
3498 | inquiry.Flags[0] = |
3499 | IPS_SCSI_INQ_Address16; |
3500 | inquiry.Flags[1] = |
3501 | IPS_SCSI_INQ_WBus16 | |
3502 | IPS_SCSI_INQ_Sync; |
3503 | memcpy(inquiry.VendorId, "IBM " , |
3504 | 8); |
3505 | memcpy(inquiry.ProductId, |
3506 | "SERVERAID " , 16); |
3507 | memcpy(inquiry.ProductRevisionLevel, |
3508 | "1.00" , 4); |
3509 | |
3510 | ips_scmd_buf_write(scmd: scb->scsi_cmd, |
3511 | data: &inquiry, |
3512 | count: sizeof (inquiry)); |
3513 | |
3514 | scb->scsi_cmd->result = DID_OK << 16; |
3515 | } |
3516 | } else { |
3517 | scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO; |
3518 | scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb); |
3519 | scb->cmd.logical_info.reserved = 0; |
3520 | scb->cmd.logical_info.reserved2 = 0; |
3521 | scb->data_len = sizeof (IPS_LD_INFO); |
3522 | scb->data_busaddr = ha->logical_drive_info_dma_addr; |
3523 | scb->flags = 0; |
3524 | scb->cmd.logical_info.buffer_addr = scb->data_busaddr; |
3525 | ret = IPS_SUCCESS; |
3526 | } |
3527 | |
3528 | break; |
3529 | |
3530 | case REQUEST_SENSE: |
3531 | ips_reqsen(ha, scb); |
3532 | scb->scsi_cmd->result = DID_OK << 16; |
3533 | break; |
3534 | |
3535 | case READ_6: |
3536 | case WRITE_6: |
3537 | if (!scb->sg_len) { |
3538 | scb->cmd.basic_io.op_code = |
3539 | (scb->scsi_cmd->cmnd[0] == |
3540 | READ_6) ? IPS_CMD_READ : IPS_CMD_WRITE; |
3541 | scb->cmd.basic_io.enhanced_sg = 0; |
3542 | scb->cmd.basic_io.sg_addr = |
3543 | cpu_to_le32(scb->data_busaddr); |
3544 | } else { |
3545 | scb->cmd.basic_io.op_code = |
3546 | (scb->scsi_cmd->cmnd[0] == |
3547 | READ_6) ? IPS_CMD_READ_SG : |
3548 | IPS_CMD_WRITE_SG; |
3549 | scb->cmd.basic_io.enhanced_sg = |
3550 | IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0; |
3551 | scb->cmd.basic_io.sg_addr = |
3552 | cpu_to_le32(scb->sg_busaddr); |
3553 | } |
3554 | |
3555 | scb->cmd.basic_io.segment_4G = 0; |
3556 | scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); |
3557 | scb->cmd.basic_io.log_drv = scb->target_id; |
3558 | scb->cmd.basic_io.sg_count = scb->sg_len; |
3559 | |
3560 | if (scb->cmd.basic_io.lba) |
3561 | le32_add_cpu(var: &scb->cmd.basic_io.lba, |
3562 | le16_to_cpu(scb->cmd.basic_io. |
3563 | sector_count)); |
3564 | else |
3565 | scb->cmd.basic_io.lba = |
3566 | (((scb->scsi_cmd-> |
3567 | cmnd[1] & 0x1f) << 16) | (scb->scsi_cmd-> |
3568 | cmnd[2] << 8) | |
3569 | (scb->scsi_cmd->cmnd[3])); |
3570 | |
3571 | scb->cmd.basic_io.sector_count = |
3572 | cpu_to_le16(scb->data_len / IPS_BLKSIZE); |
3573 | |
3574 | if (le16_to_cpu(scb->cmd.basic_io.sector_count) == 0) |
3575 | scb->cmd.basic_io.sector_count = |
3576 | cpu_to_le16(256); |
3577 | |
3578 | ret = IPS_SUCCESS; |
3579 | break; |
3580 | |
3581 | case READ_10: |
3582 | case WRITE_10: |
3583 | if (!scb->sg_len) { |
3584 | scb->cmd.basic_io.op_code = |
3585 | (scb->scsi_cmd->cmnd[0] == |
3586 | READ_10) ? IPS_CMD_READ : IPS_CMD_WRITE; |
3587 | scb->cmd.basic_io.enhanced_sg = 0; |
3588 | scb->cmd.basic_io.sg_addr = |
3589 | cpu_to_le32(scb->data_busaddr); |
3590 | } else { |
3591 | scb->cmd.basic_io.op_code = |
3592 | (scb->scsi_cmd->cmnd[0] == |
3593 | READ_10) ? IPS_CMD_READ_SG : |
3594 | IPS_CMD_WRITE_SG; |
3595 | scb->cmd.basic_io.enhanced_sg = |
3596 | IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0; |
3597 | scb->cmd.basic_io.sg_addr = |
3598 | cpu_to_le32(scb->sg_busaddr); |
3599 | } |
3600 | |
3601 | scb->cmd.basic_io.segment_4G = 0; |
3602 | scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); |
3603 | scb->cmd.basic_io.log_drv = scb->target_id; |
3604 | scb->cmd.basic_io.sg_count = scb->sg_len; |
3605 | |
3606 | if (scb->cmd.basic_io.lba) |
3607 | le32_add_cpu(var: &scb->cmd.basic_io.lba, |
3608 | le16_to_cpu(scb->cmd.basic_io. |
3609 | sector_count)); |
3610 | else |
3611 | scb->cmd.basic_io.lba = |
3612 | ((scb->scsi_cmd->cmnd[2] << 24) | (scb-> |
3613 | scsi_cmd-> |
3614 | cmnd[3] |
3615 | << 16) | |
3616 | (scb->scsi_cmd->cmnd[4] << 8) | scb-> |
3617 | scsi_cmd->cmnd[5]); |
3618 | |
3619 | scb->cmd.basic_io.sector_count = |
3620 | cpu_to_le16(scb->data_len / IPS_BLKSIZE); |
3621 | |
3622 | if (cpu_to_le16(scb->cmd.basic_io.sector_count) == 0) { |
3623 | /* |
3624 | * This is a null condition |
3625 | * we don't have to do anything |
3626 | * so just return |
3627 | */ |
3628 | scb->scsi_cmd->result = DID_OK << 16; |
3629 | } else |
3630 | ret = IPS_SUCCESS; |
3631 | |
3632 | break; |
3633 | |
3634 | case RESERVE: |
3635 | case RELEASE: |
3636 | scb->scsi_cmd->result = DID_OK << 16; |
3637 | break; |
3638 | |
3639 | case MODE_SENSE: |
3640 | scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY; |
3641 | scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); |
3642 | scb->cmd.basic_io.segment_4G = 0; |
3643 | scb->cmd.basic_io.enhanced_sg = 0; |
3644 | scb->data_len = sizeof (*ha->enq); |
3645 | scb->cmd.basic_io.sg_addr = ha->enq_busaddr; |
3646 | ret = IPS_SUCCESS; |
3647 | break; |
3648 | |
3649 | case READ_CAPACITY: |
3650 | scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO; |
3651 | scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb); |
3652 | scb->cmd.logical_info.reserved = 0; |
3653 | scb->cmd.logical_info.reserved2 = 0; |
3654 | scb->cmd.logical_info.reserved3 = 0; |
3655 | scb->data_len = sizeof (IPS_LD_INFO); |
3656 | scb->data_busaddr = ha->logical_drive_info_dma_addr; |
3657 | scb->flags = 0; |
3658 | scb->cmd.logical_info.buffer_addr = scb->data_busaddr; |
3659 | ret = IPS_SUCCESS; |
3660 | break; |
3661 | |
3662 | case SEND_DIAGNOSTIC: |
3663 | case REASSIGN_BLOCKS: |
3664 | case FORMAT_UNIT: |
3665 | case SEEK_10: |
3666 | case VERIFY: |
3667 | case READ_DEFECT_DATA: |
3668 | case READ_BUFFER: |
3669 | case WRITE_BUFFER: |
3670 | scb->scsi_cmd->result = DID_OK << 16; |
3671 | break; |
3672 | |
3673 | default: |
3674 | /* Set the Return Info to appear like the Command was */ |
3675 | /* attempted, a Check Condition occurred, and Sense */ |
3676 | /* Data indicating an Invalid CDB OpCode is returned. */ |
3677 | sp = (char *) scb->scsi_cmd->sense_buffer; |
3678 | |
3679 | sp[0] = 0x70; /* Error Code */ |
3680 | sp[2] = ILLEGAL_REQUEST; /* Sense Key 5 Illegal Req. */ |
3681 | sp[7] = 0x0A; /* Additional Sense Length */ |
3682 | sp[12] = 0x20; /* ASC = Invalid OpCode */ |
3683 | sp[13] = 0x00; /* ASCQ */ |
3684 | |
3685 | device_error = 2; /* Indicate Check Condition */ |
3686 | scb->scsi_cmd->result = device_error | (DID_OK << 16); |
3687 | break; |
3688 | } /* end switch */ |
3689 | } |
3690 | /* end if */ |
3691 | if (ret == IPS_SUCCESS_IMM) |
3692 | return (ret); |
3693 | |
3694 | /* setup DCDB */ |
3695 | if (scb->bus > 0) { |
3696 | |
3697 | /* If we already know the Device is Not there, no need to attempt a Command */ |
3698 | /* This also protects an NT FailOver Controller from getting CDB's sent to it */ |
3699 | if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) { |
3700 | scb->scsi_cmd->result = DID_NO_CONNECT << 16; |
3701 | return (IPS_SUCCESS_IMM); |
3702 | } |
3703 | |
3704 | ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id); |
3705 | scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb); |
3706 | scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr + |
3707 | (unsigned long) &scb-> |
3708 | dcdb - |
3709 | (unsigned long) scb); |
3710 | scb->cmd.dcdb.reserved = 0; |
3711 | scb->cmd.dcdb.reserved2 = 0; |
3712 | scb->cmd.dcdb.reserved3 = 0; |
3713 | scb->cmd.dcdb.segment_4G = 0; |
3714 | scb->cmd.dcdb.enhanced_sg = 0; |
3715 | |
3716 | TimeOut = scsi_cmd_to_rq(scmd: scb->scsi_cmd)->timeout; |
3717 | |
3718 | if (ha->subsys->param[4] & 0x00100000) { /* If NEW Tape DCDB is Supported */ |
3719 | if (!scb->sg_len) { |
3720 | scb->cmd.dcdb.op_code = IPS_CMD_EXTENDED_DCDB; |
3721 | } else { |
3722 | scb->cmd.dcdb.op_code = |
3723 | IPS_CMD_EXTENDED_DCDB_SG; |
3724 | scb->cmd.dcdb.enhanced_sg = |
3725 | IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0; |
3726 | } |
3727 | |
3728 | tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; /* Use Same Data Area as Old DCDB Struct */ |
3729 | tapeDCDB->device_address = |
3730 | ((scb->bus - 1) << 4) | scb->target_id; |
3731 | tapeDCDB->cmd_attribute |= IPS_DISCONNECT_ALLOWED; |
3732 | tapeDCDB->cmd_attribute &= ~IPS_TRANSFER64K; /* Always Turn OFF 64K Size Flag */ |
3733 | |
3734 | if (TimeOut) { |
3735 | if (TimeOut < (10 * HZ)) |
3736 | tapeDCDB->cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */ |
3737 | else if (TimeOut < (60 * HZ)) |
3738 | tapeDCDB->cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */ |
3739 | else if (TimeOut < (1200 * HZ)) |
3740 | tapeDCDB->cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */ |
3741 | } |
3742 | |
3743 | tapeDCDB->cdb_length = scb->scsi_cmd->cmd_len; |
3744 | tapeDCDB->reserved_for_LUN = 0; |
3745 | tapeDCDB->transfer_length = scb->data_len; |
3746 | if (scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB_SG) |
3747 | tapeDCDB->buffer_pointer = |
3748 | cpu_to_le32(scb->sg_busaddr); |
3749 | else |
3750 | tapeDCDB->buffer_pointer = |
3751 | cpu_to_le32(scb->data_busaddr); |
3752 | tapeDCDB->sg_count = scb->sg_len; |
3753 | tapeDCDB->sense_length = sizeof (tapeDCDB->sense_info); |
3754 | tapeDCDB->scsi_status = 0; |
3755 | tapeDCDB->reserved = 0; |
3756 | memcpy(tapeDCDB->scsi_cdb, scb->scsi_cmd->cmnd, |
3757 | scb->scsi_cmd->cmd_len); |
3758 | } else { |
3759 | if (!scb->sg_len) { |
3760 | scb->cmd.dcdb.op_code = IPS_CMD_DCDB; |
3761 | } else { |
3762 | scb->cmd.dcdb.op_code = IPS_CMD_DCDB_SG; |
3763 | scb->cmd.dcdb.enhanced_sg = |
3764 | IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0; |
3765 | } |
3766 | |
3767 | scb->dcdb.device_address = |
3768 | ((scb->bus - 1) << 4) | scb->target_id; |
3769 | scb->dcdb.cmd_attribute |= IPS_DISCONNECT_ALLOWED; |
3770 | |
3771 | if (TimeOut) { |
3772 | if (TimeOut < (10 * HZ)) |
3773 | scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */ |
3774 | else if (TimeOut < (60 * HZ)) |
3775 | scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */ |
3776 | else if (TimeOut < (1200 * HZ)) |
3777 | scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */ |
3778 | } |
3779 | |
3780 | scb->dcdb.transfer_length = scb->data_len; |
3781 | if (scb->dcdb.cmd_attribute & IPS_TRANSFER64K) |
3782 | scb->dcdb.transfer_length = 0; |
3783 | if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB_SG) |
3784 | scb->dcdb.buffer_pointer = |
3785 | cpu_to_le32(scb->sg_busaddr); |
3786 | else |
3787 | scb->dcdb.buffer_pointer = |
3788 | cpu_to_le32(scb->data_busaddr); |
3789 | scb->dcdb.cdb_length = scb->scsi_cmd->cmd_len; |
3790 | scb->dcdb.sense_length = sizeof (scb->dcdb.sense_info); |
3791 | scb->dcdb.sg_count = scb->sg_len; |
3792 | scb->dcdb.reserved = 0; |
3793 | memcpy(scb->dcdb.scsi_cdb, scb->scsi_cmd->cmnd, |
3794 | scb->scsi_cmd->cmd_len); |
3795 | scb->dcdb.scsi_status = 0; |
3796 | scb->dcdb.reserved2[0] = 0; |
3797 | scb->dcdb.reserved2[1] = 0; |
3798 | scb->dcdb.reserved2[2] = 0; |
3799 | } |
3800 | } |
3801 | |
3802 | return ((*ha->func.issue) (ha, scb)); |
3803 | } |
3804 | |
3805 | /****************************************************************************/ |
3806 | /* */ |
3807 | /* Routine Name: ips_chk_status */ |
3808 | /* */ |
3809 | /* Routine Description: */ |
3810 | /* */ |
3811 | /* Check the status of commands to logical drives */ |
3812 | /* Assumed to be called with the HA lock */ |
3813 | /****************************************************************************/ |
3814 | static void |
3815 | ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus) |
3816 | { |
3817 | ips_scb_t *scb; |
3818 | ips_stat_t *sp; |
3819 | uint8_t basic_status; |
3820 | uint8_t ext_status; |
3821 | int errcode; |
3822 | IPS_SCSI_INQ_DATA inquiryData; |
3823 | |
3824 | METHOD_TRACE("ips_chkstatus" , 1); |
3825 | |
3826 | scb = &ha->scbs[pstatus->fields.command_id]; |
3827 | scb->basic_status = basic_status = |
3828 | pstatus->fields.basic_status & IPS_BASIC_STATUS_MASK; |
3829 | scb->extended_status = ext_status = pstatus->fields.extended_status; |
3830 | |
3831 | sp = &ha->sp; |
3832 | sp->residue_len = 0; |
3833 | sp->scb_addr = (void *) scb; |
3834 | |
3835 | /* Remove the item from the active queue */ |
3836 | ips_removeq_scb(queue: &ha->scb_activelist, item: scb); |
3837 | |
3838 | if (!scb->scsi_cmd) |
3839 | /* internal commands are handled in do_ipsintr */ |
3840 | return; |
3841 | |
3842 | DEBUG_VAR(2, "(%s%d) ips_chkstatus: cmd 0x%X id %d (%d %d %d)" , |
3843 | ips_name, |
3844 | ha->host_num, |
3845 | scb->cdb[0], |
3846 | scb->cmd.basic_io.command_id, |
3847 | scb->bus, scb->target_id, scb->lun); |
3848 | |
3849 | if ((scb->scsi_cmd) && (ips_is_passthru(SC: scb->scsi_cmd))) |
3850 | /* passthru - just returns the raw result */ |
3851 | return; |
3852 | |
3853 | errcode = DID_OK; |
3854 | |
3855 | if (((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_SUCCESS) || |
3856 | ((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_RECOVERED_ERROR)) { |
3857 | |
3858 | if (scb->bus == 0) { |
3859 | if ((basic_status & IPS_GSC_STATUS_MASK) == |
3860 | IPS_CMD_RECOVERED_ERROR) { |
3861 | DEBUG_VAR(1, |
3862 | "(%s%d) Recovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x" , |
3863 | ips_name, ha->host_num, |
3864 | scb->cmd.basic_io.op_code, |
3865 | basic_status, ext_status); |
3866 | } |
3867 | |
3868 | switch (scb->scsi_cmd->cmnd[0]) { |
3869 | case ALLOW_MEDIUM_REMOVAL: |
3870 | case REZERO_UNIT: |
3871 | case ERASE: |
3872 | case WRITE_FILEMARKS: |
3873 | case SPACE: |
3874 | errcode = DID_ERROR; |
3875 | break; |
3876 | |
3877 | case START_STOP: |
3878 | break; |
3879 | |
3880 | case TEST_UNIT_READY: |
3881 | if (!ips_online(ha, scb)) { |
3882 | errcode = DID_TIME_OUT; |
3883 | } |
3884 | break; |
3885 | |
3886 | case INQUIRY: |
3887 | if (ips_online(ha, scb)) { |
3888 | ips_inquiry(ha, scb); |
3889 | } else { |
3890 | errcode = DID_TIME_OUT; |
3891 | } |
3892 | break; |
3893 | |
3894 | case REQUEST_SENSE: |
3895 | ips_reqsen(ha, scb); |
3896 | break; |
3897 | |
3898 | case READ_6: |
3899 | case WRITE_6: |
3900 | case READ_10: |
3901 | case WRITE_10: |
3902 | case RESERVE: |
3903 | case RELEASE: |
3904 | break; |
3905 | |
3906 | case MODE_SENSE: |
3907 | if (!ips_online(ha, scb) |
3908 | || !ips_msense(ha, scb)) { |
3909 | errcode = DID_ERROR; |
3910 | } |
3911 | break; |
3912 | |
3913 | case READ_CAPACITY: |
3914 | if (ips_online(ha, scb)) |
3915 | ips_rdcap(ha, scb); |
3916 | else { |
3917 | errcode = DID_TIME_OUT; |
3918 | } |
3919 | break; |
3920 | |
3921 | case SEND_DIAGNOSTIC: |
3922 | case REASSIGN_BLOCKS: |
3923 | break; |
3924 | |
3925 | case FORMAT_UNIT: |
3926 | errcode = DID_ERROR; |
3927 | break; |
3928 | |
3929 | case SEEK_10: |
3930 | case VERIFY: |
3931 | case READ_DEFECT_DATA: |
3932 | case READ_BUFFER: |
3933 | case WRITE_BUFFER: |
3934 | break; |
3935 | |
3936 | default: |
3937 | errcode = DID_ERROR; |
3938 | } /* end switch */ |
3939 | |
3940 | scb->scsi_cmd->result = errcode << 16; |
3941 | } else { /* bus == 0 */ |
3942 | /* restrict access to physical drives */ |
3943 | if (scb->scsi_cmd->cmnd[0] == INQUIRY) { |
3944 | ips_scmd_buf_read(scmd: scb->scsi_cmd, |
3945 | data: &inquiryData, count: sizeof (inquiryData)); |
3946 | if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) |
3947 | scb->scsi_cmd->result = DID_TIME_OUT << 16; |
3948 | } |
3949 | } /* else */ |
3950 | } else { /* recovered error / success */ |
3951 | if (scb->bus == 0) { |
3952 | DEBUG_VAR(1, |
3953 | "(%s%d) Unrecovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x" , |
3954 | ips_name, ha->host_num, |
3955 | scb->cmd.basic_io.op_code, basic_status, |
3956 | ext_status); |
3957 | } |
3958 | |
3959 | ips_map_status(ha, scb, sp); |
3960 | } /* else */ |
3961 | } |
3962 | |
3963 | /****************************************************************************/ |
3964 | /* */ |
3965 | /* Routine Name: ips_online */ |
3966 | /* */ |
3967 | /* Routine Description: */ |
3968 | /* */ |
3969 | /* Determine if a logical drive is online */ |
3970 | /* */ |
3971 | /****************************************************************************/ |
3972 | static int |
3973 | ips_online(ips_ha_t * ha, ips_scb_t * scb) |
3974 | { |
3975 | METHOD_TRACE("ips_online" , 1); |
3976 | |
3977 | if (scb->target_id >= IPS_MAX_LD) |
3978 | return (0); |
3979 | |
3980 | if ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1) { |
3981 | memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO)); |
3982 | return (0); |
3983 | } |
3984 | |
3985 | if (ha->logical_drive_info->drive_info[scb->target_id].state != |
3986 | IPS_LD_OFFLINE |
3987 | && ha->logical_drive_info->drive_info[scb->target_id].state != |
3988 | IPS_LD_FREE |
3989 | && ha->logical_drive_info->drive_info[scb->target_id].state != |
3990 | IPS_LD_CRS |
3991 | && ha->logical_drive_info->drive_info[scb->target_id].state != |
3992 | IPS_LD_SYS) |
3993 | return (1); |
3994 | else |
3995 | return (0); |
3996 | } |
3997 | |
3998 | /****************************************************************************/ |
3999 | /* */ |
4000 | /* Routine Name: ips_inquiry */ |
4001 | /* */ |
4002 | /* Routine Description: */ |
4003 | /* */ |
4004 | /* Simulate an inquiry command to a logical drive */ |
4005 | /* */ |
4006 | /****************************************************************************/ |
4007 | static int |
4008 | ips_inquiry(ips_ha_t * ha, ips_scb_t * scb) |
4009 | { |
4010 | IPS_SCSI_INQ_DATA inquiry; |
4011 | |
4012 | METHOD_TRACE("ips_inquiry" , 1); |
4013 | |
4014 | memset(&inquiry, 0, sizeof (IPS_SCSI_INQ_DATA)); |
4015 | |
4016 | inquiry.DeviceType = IPS_SCSI_INQ_TYPE_DASD; |
4017 | inquiry.DeviceTypeQualifier = IPS_SCSI_INQ_LU_CONNECTED; |
4018 | inquiry.Version = IPS_SCSI_INQ_REV2; |
4019 | inquiry.ResponseDataFormat = IPS_SCSI_INQ_RD_REV2; |
4020 | inquiry.AdditionalLength = 31; |
4021 | inquiry.Flags[0] = IPS_SCSI_INQ_Address16; |
4022 | inquiry.Flags[1] = |
4023 | IPS_SCSI_INQ_WBus16 | IPS_SCSI_INQ_Sync | IPS_SCSI_INQ_CmdQue; |
4024 | memcpy(inquiry.VendorId, "IBM " , 8); |
4025 | memcpy(inquiry.ProductId, "SERVERAID " , 16); |
4026 | memcpy(inquiry.ProductRevisionLevel, "1.00" , 4); |
4027 | |
4028 | ips_scmd_buf_write(scmd: scb->scsi_cmd, data: &inquiry, count: sizeof (inquiry)); |
4029 | |
4030 | return (1); |
4031 | } |
4032 | |
4033 | /****************************************************************************/ |
4034 | /* */ |
4035 | /* Routine Name: ips_rdcap */ |
4036 | /* */ |
4037 | /* Routine Description: */ |
4038 | /* */ |
4039 | /* Simulate a read capacity command to a logical drive */ |
4040 | /* */ |
4041 | /****************************************************************************/ |
4042 | static int |
4043 | ips_rdcap(ips_ha_t * ha, ips_scb_t * scb) |
4044 | { |
4045 | IPS_SCSI_CAPACITY cap; |
4046 | |
4047 | METHOD_TRACE("ips_rdcap" , 1); |
4048 | |
4049 | if (scsi_bufflen(cmd: scb->scsi_cmd) < 8) |
4050 | return (0); |
4051 | |
4052 | cap.lba = |
4053 | cpu_to_be32(le32_to_cpu |
4054 | (ha->logical_drive_info-> |
4055 | drive_info[scb->target_id].sector_count) - 1); |
4056 | cap.len = cpu_to_be32((uint32_t) IPS_BLKSIZE); |
4057 | |
4058 | ips_scmd_buf_write(scmd: scb->scsi_cmd, data: &cap, count: sizeof (cap)); |
4059 | |
4060 | return (1); |
4061 | } |
4062 | |
4063 | /****************************************************************************/ |
4064 | /* */ |
4065 | /* Routine Name: ips_msense */ |
4066 | /* */ |
4067 | /* Routine Description: */ |
4068 | /* */ |
4069 | /* Simulate a mode sense command to a logical drive */ |
4070 | /* */ |
4071 | /****************************************************************************/ |
4072 | static int |
4073 | ips_msense(ips_ha_t * ha, ips_scb_t * scb) |
4074 | { |
4075 | uint16_t heads; |
4076 | uint16_t sectors; |
4077 | uint32_t cylinders; |
4078 | IPS_SCSI_MODE_PAGE_DATA mdata; |
4079 | |
4080 | METHOD_TRACE("ips_msense" , 1); |
4081 | |
4082 | if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 && |
4083 | (ha->enq->ucMiscFlag & 0x8) == 0) { |
4084 | heads = IPS_NORM_HEADS; |
4085 | sectors = IPS_NORM_SECTORS; |
4086 | } else { |
4087 | heads = IPS_COMP_HEADS; |
4088 | sectors = IPS_COMP_SECTORS; |
4089 | } |
4090 | |
4091 | cylinders = |
4092 | (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) - |
4093 | 1) / (heads * sectors); |
4094 | |
4095 | memset(&mdata, 0, sizeof (IPS_SCSI_MODE_PAGE_DATA)); |
4096 | |
4097 | mdata.hdr.BlockDescLength = 8; |
4098 | |
4099 | switch (scb->scsi_cmd->cmnd[2] & 0x3f) { |
4100 | case 0x03: /* page 3 */ |
4101 | mdata.pdata.pg3.PageCode = 3; |
4102 | mdata.pdata.pg3.PageLength = sizeof (IPS_SCSI_MODE_PAGE3); |
4103 | mdata.hdr.DataLength = |
4104 | 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg3.PageLength; |
4105 | mdata.pdata.pg3.TracksPerZone = 0; |
4106 | mdata.pdata.pg3.AltSectorsPerZone = 0; |
4107 | mdata.pdata.pg3.AltTracksPerZone = 0; |
4108 | mdata.pdata.pg3.AltTracksPerVolume = 0; |
4109 | mdata.pdata.pg3.SectorsPerTrack = cpu_to_be16(sectors); |
4110 | mdata.pdata.pg3.BytesPerSector = cpu_to_be16(IPS_BLKSIZE); |
4111 | mdata.pdata.pg3.Interleave = cpu_to_be16(1); |
4112 | mdata.pdata.pg3.TrackSkew = 0; |
4113 | mdata.pdata.pg3.CylinderSkew = 0; |
4114 | mdata.pdata.pg3.flags = IPS_SCSI_MP3_SoftSector; |
4115 | break; |
4116 | |
4117 | case 0x4: |
4118 | mdata.pdata.pg4.PageCode = 4; |
4119 | mdata.pdata.pg4.PageLength = sizeof (IPS_SCSI_MODE_PAGE4); |
4120 | mdata.hdr.DataLength = |
4121 | 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg4.PageLength; |
4122 | mdata.pdata.pg4.CylindersHigh = |
4123 | cpu_to_be16((cylinders >> 8) & 0xFFFF); |
4124 | mdata.pdata.pg4.CylindersLow = (cylinders & 0xFF); |
4125 | mdata.pdata.pg4.Heads = heads; |
4126 | mdata.pdata.pg4.WritePrecompHigh = 0; |
4127 | mdata.pdata.pg4.WritePrecompLow = 0; |
4128 | mdata.pdata.pg4.ReducedWriteCurrentHigh = 0; |
4129 | mdata.pdata.pg4.ReducedWriteCurrentLow = 0; |
4130 | mdata.pdata.pg4.StepRate = cpu_to_be16(1); |
4131 | mdata.pdata.pg4.LandingZoneHigh = 0; |
4132 | mdata.pdata.pg4.LandingZoneLow = 0; |
4133 | mdata.pdata.pg4.flags = 0; |
4134 | mdata.pdata.pg4.RotationalOffset = 0; |
4135 | mdata.pdata.pg4.MediumRotationRate = 0; |
4136 | break; |
4137 | case 0x8: |
4138 | mdata.pdata.pg8.PageCode = 8; |
4139 | mdata.pdata.pg8.PageLength = sizeof (IPS_SCSI_MODE_PAGE8); |
4140 | mdata.hdr.DataLength = |
4141 | 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg8.PageLength; |
4142 | /* everything else is left set to 0 */ |
4143 | break; |
4144 | |
4145 | default: |
4146 | return (0); |
4147 | } /* end switch */ |
4148 | |
4149 | ips_scmd_buf_write(scmd: scb->scsi_cmd, data: &mdata, count: sizeof (mdata)); |
4150 | |
4151 | return (1); |
4152 | } |
4153 | |
4154 | /****************************************************************************/ |
4155 | /* */ |
4156 | /* Routine Name: ips_reqsen */ |
4157 | /* */ |
4158 | /* Routine Description: */ |
4159 | /* */ |
4160 | /* Simulate a request sense command to a logical drive */ |
4161 | /* */ |
4162 | /****************************************************************************/ |
4163 | static int |
4164 | ips_reqsen(ips_ha_t * ha, ips_scb_t * scb) |
4165 | { |
4166 | IPS_SCSI_REQSEN reqsen; |
4167 | |
4168 | METHOD_TRACE("ips_reqsen" , 1); |
4169 | |
4170 | memset(&reqsen, 0, sizeof (IPS_SCSI_REQSEN)); |
4171 | |
4172 | reqsen.ResponseCode = |
4173 | IPS_SCSI_REQSEN_VALID | IPS_SCSI_REQSEN_CURRENT_ERR; |
4174 | reqsen.AdditionalLength = 10; |
4175 | reqsen.AdditionalSenseCode = IPS_SCSI_REQSEN_NO_SENSE; |
4176 | reqsen.AdditionalSenseCodeQual = IPS_SCSI_REQSEN_NO_SENSE; |
4177 | |
4178 | ips_scmd_buf_write(scmd: scb->scsi_cmd, data: &reqsen, count: sizeof (reqsen)); |
4179 | |
4180 | return (1); |
4181 | } |
4182 | |
4183 | /****************************************************************************/ |
4184 | /* */ |
4185 | /* Routine Name: ips_free */ |
4186 | /* */ |
4187 | /* Routine Description: */ |
4188 | /* */ |
4189 | /* Free any allocated space for this controller */ |
4190 | /* */ |
4191 | /****************************************************************************/ |
4192 | static void |
4193 | ips_free(ips_ha_t * ha) |
4194 | { |
4195 | |
4196 | METHOD_TRACE("ips_free" , 1); |
4197 | |
4198 | if (ha) { |
4199 | if (ha->enq) { |
4200 | dma_free_coherent(dev: &ha->pcidev->dev, size: sizeof(IPS_ENQ), |
4201 | cpu_addr: ha->enq, dma_handle: ha->enq_busaddr); |
4202 | ha->enq = NULL; |
4203 | } |
4204 | |
4205 | kfree(objp: ha->conf); |
4206 | ha->conf = NULL; |
4207 | |
4208 | if (ha->adapt) { |
4209 | dma_free_coherent(dev: &ha->pcidev->dev, |
4210 | size: sizeof (IPS_ADAPTER) + |
4211 | sizeof (IPS_IO_CMD), cpu_addr: ha->adapt, |
4212 | dma_handle: ha->adapt->hw_status_start); |
4213 | ha->adapt = NULL; |
4214 | } |
4215 | |
4216 | if (ha->logical_drive_info) { |
4217 | dma_free_coherent(dev: &ha->pcidev->dev, |
4218 | size: sizeof (IPS_LD_INFO), |
4219 | cpu_addr: ha->logical_drive_info, |
4220 | dma_handle: ha->logical_drive_info_dma_addr); |
4221 | ha->logical_drive_info = NULL; |
4222 | } |
4223 | |
4224 | kfree(objp: ha->nvram); |
4225 | ha->nvram = NULL; |
4226 | |
4227 | kfree(objp: ha->subsys); |
4228 | ha->subsys = NULL; |
4229 | |
4230 | if (ha->ioctl_data) { |
4231 | dma_free_coherent(dev: &ha->pcidev->dev, size: ha->ioctl_len, |
4232 | cpu_addr: ha->ioctl_data, dma_handle: ha->ioctl_busaddr); |
4233 | ha->ioctl_data = NULL; |
4234 | ha->ioctl_datasize = 0; |
4235 | ha->ioctl_len = 0; |
4236 | } |
4237 | ips_deallocatescbs(ha, ha->max_cmds); |
4238 | |
4239 | /* free memory mapped (if applicable) */ |
4240 | if (ha->mem_ptr) { |
4241 | iounmap(addr: ha->ioremap_ptr); |
4242 | ha->ioremap_ptr = NULL; |
4243 | ha->mem_ptr = NULL; |
4244 | } |
4245 | |
4246 | ha->mem_addr = 0; |
4247 | |
4248 | } |
4249 | } |
4250 | |
4251 | /****************************************************************************/ |
4252 | /* */ |
4253 | /* Routine Name: ips_deallocatescbs */ |
4254 | /* */ |
4255 | /* Routine Description: */ |
4256 | /* */ |
4257 | /* Free the command blocks */ |
4258 | /* */ |
4259 | /****************************************************************************/ |
4260 | static int |
4261 | ips_deallocatescbs(ips_ha_t * ha, int cmds) |
4262 | { |
4263 | if (ha->scbs) { |
4264 | dma_free_coherent(dev: &ha->pcidev->dev, |
4265 | IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds, |
4266 | cpu_addr: ha->scbs->sg_list.list, |
4267 | dma_handle: ha->scbs->sg_busaddr); |
4268 | dma_free_coherent(dev: &ha->pcidev->dev, size: sizeof (ips_scb_t) * cmds, |
4269 | cpu_addr: ha->scbs, dma_handle: ha->scbs->scb_busaddr); |
4270 | ha->scbs = NULL; |
4271 | } /* end if */ |
4272 | return 1; |
4273 | } |
4274 | |
4275 | /****************************************************************************/ |
4276 | /* */ |
4277 | /* Routine Name: ips_allocatescbs */ |
4278 | /* */ |
4279 | /* Routine Description: */ |
4280 | /* */ |
4281 | /* Allocate the command blocks */ |
4282 | /* */ |
4283 | /****************************************************************************/ |
4284 | static int |
4285 | ips_allocatescbs(ips_ha_t * ha) |
4286 | { |
4287 | ips_scb_t *scb_p; |
4288 | IPS_SG_LIST ips_sg; |
4289 | int i; |
4290 | dma_addr_t command_dma, sg_dma; |
4291 | |
4292 | METHOD_TRACE("ips_allocatescbs" , 1); |
4293 | |
4294 | /* Allocate memory for the SCBs */ |
4295 | ha->scbs = dma_alloc_coherent(dev: &ha->pcidev->dev, |
4296 | size: ha->max_cmds * sizeof (ips_scb_t), |
4297 | dma_handle: &command_dma, GFP_KERNEL); |
4298 | if (ha->scbs == NULL) |
4299 | return 0; |
4300 | ips_sg.list = dma_alloc_coherent(dev: &ha->pcidev->dev, |
4301 | IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * ha->max_cmds, |
4302 | dma_handle: &sg_dma, GFP_KERNEL); |
4303 | if (ips_sg.list == NULL) { |
4304 | dma_free_coherent(dev: &ha->pcidev->dev, |
4305 | size: ha->max_cmds * sizeof (ips_scb_t), cpu_addr: ha->scbs, |
4306 | dma_handle: command_dma); |
4307 | return 0; |
4308 | } |
4309 | |
4310 | memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t)); |
4311 | |
4312 | for (i = 0; i < ha->max_cmds; i++) { |
4313 | scb_p = &ha->scbs[i]; |
4314 | scb_p->scb_busaddr = command_dma + sizeof (ips_scb_t) * i; |
4315 | /* set up S/G list */ |
4316 | if (IPS_USE_ENH_SGLIST(ha)) { |
4317 | scb_p->sg_list.enh_list = |
4318 | ips_sg.enh_list + i * IPS_MAX_SG; |
4319 | scb_p->sg_busaddr = |
4320 | sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i; |
4321 | } else { |
4322 | scb_p->sg_list.std_list = |
4323 | ips_sg.std_list + i * IPS_MAX_SG; |
4324 | scb_p->sg_busaddr = |
4325 | sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i; |
4326 | } |
4327 | |
4328 | /* add to the free list */ |
4329 | if (i < ha->max_cmds - 1) { |
4330 | scb_p->q_next = ha->scb_freelist; |
4331 | ha->scb_freelist = scb_p; |
4332 | } |
4333 | } |
4334 | |
4335 | /* success */ |
4336 | return (1); |
4337 | } |
4338 | |
4339 | /****************************************************************************/ |
4340 | /* */ |
4341 | /* Routine Name: ips_init_scb */ |
4342 | /* */ |
4343 | /* Routine Description: */ |
4344 | /* */ |
4345 | /* Initialize a CCB to default values */ |
4346 | /* */ |
4347 | /****************************************************************************/ |
4348 | static void |
4349 | ips_init_scb(ips_ha_t * ha, ips_scb_t * scb) |
4350 | { |
4351 | IPS_SG_LIST sg_list; |
4352 | uint32_t cmd_busaddr, sg_busaddr; |
4353 | METHOD_TRACE("ips_init_scb" , 1); |
4354 | |
4355 | if (scb == NULL) |
4356 | return; |
4357 | |
4358 | sg_list.list = scb->sg_list.list; |
4359 | cmd_busaddr = scb->scb_busaddr; |
4360 | sg_busaddr = scb->sg_busaddr; |
4361 | /* zero fill */ |
4362 | memset(scb, 0, sizeof (ips_scb_t)); |
4363 | memset(ha->dummy, 0, sizeof (IPS_IO_CMD)); |
4364 | |
4365 | /* Initialize dummy command bucket */ |
4366 | ha->dummy->op_code = 0xFF; |
4367 | ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start |
4368 | + sizeof (IPS_ADAPTER)); |
4369 | ha->dummy->command_id = IPS_MAX_CMDS; |
4370 | |
4371 | /* set bus address of scb */ |
4372 | scb->scb_busaddr = cmd_busaddr; |
4373 | scb->sg_busaddr = sg_busaddr; |
4374 | scb->sg_list.list = sg_list.list; |
4375 | |
4376 | /* Neptune Fix */ |
4377 | scb->cmd.basic_io.cccr = cpu_to_le32((uint32_t) IPS_BIT_ILE); |
4378 | scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start |
4379 | + sizeof (IPS_ADAPTER)); |
4380 | } |
4381 | |
4382 | /****************************************************************************/ |
4383 | /* */ |
4384 | /* Routine Name: ips_get_scb */ |
4385 | /* */ |
4386 | /* Routine Description: */ |
4387 | /* */ |
4388 | /* Initialize a CCB to default values */ |
4389 | /* */ |
4390 | /* ASSUMED to be called from within a lock */ |
4391 | /* */ |
4392 | /****************************************************************************/ |
4393 | static ips_scb_t * |
4394 | ips_getscb(ips_ha_t * ha) |
4395 | { |
4396 | ips_scb_t *scb; |
4397 | |
4398 | METHOD_TRACE("ips_getscb" , 1); |
4399 | |
4400 | if ((scb = ha->scb_freelist) == NULL) { |
4401 | |
4402 | return (NULL); |
4403 | } |
4404 | |
4405 | ha->scb_freelist = scb->q_next; |
4406 | scb->flags = 0; |
4407 | scb->q_next = NULL; |
4408 | |
4409 | ips_init_scb(ha, scb); |
4410 | |
4411 | return (scb); |
4412 | } |
4413 | |
4414 | /****************************************************************************/ |
4415 | /* */ |
4416 | /* Routine Name: ips_free_scb */ |
4417 | /* */ |
4418 | /* Routine Description: */ |
4419 | /* */ |
4420 | /* Return an unused CCB back to the free list */ |
4421 | /* */ |
4422 | /* ASSUMED to be called from within a lock */ |
4423 | /* */ |
4424 | /****************************************************************************/ |
4425 | static void |
4426 | ips_freescb(ips_ha_t * ha, ips_scb_t * scb) |
4427 | { |
4428 | |
4429 | METHOD_TRACE("ips_freescb" , 1); |
4430 | if (scb->flags & IPS_SCB_MAP_SG) |
4431 | scsi_dma_unmap(cmd: scb->scsi_cmd); |
4432 | else if (scb->flags & IPS_SCB_MAP_SINGLE) |
4433 | dma_unmap_single(&ha->pcidev->dev, scb->data_busaddr, |
4434 | scb->data_len, IPS_DMA_DIR(scb)); |
4435 | |
4436 | /* check to make sure this is not our "special" scb */ |
4437 | if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) { |
4438 | scb->q_next = ha->scb_freelist; |
4439 | ha->scb_freelist = scb; |
4440 | } |
4441 | } |
4442 | |
4443 | /****************************************************************************/ |
4444 | /* */ |
4445 | /* Routine Name: ips_isinit_copperhead */ |
4446 | /* */ |
4447 | /* Routine Description: */ |
4448 | /* */ |
4449 | /* Is controller initialized ? */ |
4450 | /* */ |
4451 | /****************************************************************************/ |
4452 | static int |
4453 | ips_isinit_copperhead(ips_ha_t * ha) |
4454 | { |
4455 | uint8_t scpr; |
4456 | uint8_t isr; |
4457 | |
4458 | METHOD_TRACE("ips_isinit_copperhead" , 1); |
4459 | |
4460 | isr = inb(port: ha->io_addr + IPS_REG_HISR); |
4461 | scpr = inb(port: ha->io_addr + IPS_REG_SCPR); |
4462 | |
4463 | if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0)) |
4464 | return (0); |
4465 | else |
4466 | return (1); |
4467 | } |
4468 | |
4469 | /****************************************************************************/ |
4470 | /* */ |
4471 | /* Routine Name: ips_isinit_copperhead_memio */ |
4472 | /* */ |
4473 | /* Routine Description: */ |
4474 | /* */ |
4475 | /* Is controller initialized ? */ |
4476 | /* */ |
4477 | /****************************************************************************/ |
4478 | static int |
4479 | ips_isinit_copperhead_memio(ips_ha_t * ha) |
4480 | { |
4481 | uint8_t isr = 0; |
4482 | uint8_t scpr; |
4483 | |
4484 | METHOD_TRACE("ips_is_init_copperhead_memio" , 1); |
4485 | |
4486 | isr = readb(addr: ha->mem_ptr + IPS_REG_HISR); |
4487 | scpr = readb(addr: ha->mem_ptr + IPS_REG_SCPR); |
4488 | |
4489 | if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0)) |
4490 | return (0); |
4491 | else |
4492 | return (1); |
4493 | } |
4494 | |
4495 | /****************************************************************************/ |
4496 | /* */ |
4497 | /* Routine Name: ips_isinit_morpheus */ |
4498 | /* */ |
4499 | /* Routine Description: */ |
4500 | /* */ |
4501 | /* Is controller initialized ? */ |
4502 | /* */ |
4503 | /****************************************************************************/ |
4504 | static int |
4505 | ips_isinit_morpheus(ips_ha_t * ha) |
4506 | { |
4507 | uint32_t post; |
4508 | uint32_t bits; |
4509 | |
4510 | METHOD_TRACE("ips_is_init_morpheus" , 1); |
4511 | |
4512 | if (ips_isintr_morpheus(ha)) |
4513 | ips_flush_and_reset(ha); |
4514 | |
4515 | post = readl(addr: ha->mem_ptr + IPS_REG_I960_MSG0); |
4516 | bits = readl(addr: ha->mem_ptr + IPS_REG_I2O_HIR); |
4517 | |
4518 | if (post == 0) |
4519 | return (0); |
4520 | else if (bits & 0x3) |
4521 | return (0); |
4522 | else |
4523 | return (1); |
4524 | } |
4525 | |
4526 | /****************************************************************************/ |
4527 | /* */ |
4528 | /* Routine Name: ips_flush_and_reset */ |
4529 | /* */ |
4530 | /* Routine Description: */ |
4531 | /* */ |
4532 | /* Perform cleanup ( FLUSH and RESET ) when the adapter is in an unknown */ |
4533 | /* state ( was trying to INIT and an interrupt was already pending ) ... */ |
4534 | /* */ |
4535 | /****************************************************************************/ |
4536 | static void |
4537 | ips_flush_and_reset(ips_ha_t *ha) |
4538 | { |
4539 | ips_scb_t *scb; |
4540 | int ret; |
4541 | int time; |
4542 | int done; |
4543 | dma_addr_t command_dma; |
4544 | |
4545 | /* Create a usuable SCB */ |
4546 | scb = dma_alloc_coherent(dev: &ha->pcidev->dev, size: sizeof(ips_scb_t), |
4547 | dma_handle: &command_dma, GFP_KERNEL); |
4548 | if (scb) { |
4549 | memset(scb, 0, sizeof(ips_scb_t)); |
4550 | ips_init_scb(ha, scb); |
4551 | scb->scb_busaddr = command_dma; |
4552 | |
4553 | scb->timeout = ips_cmd_timeout; |
4554 | scb->cdb[0] = IPS_CMD_FLUSH; |
4555 | |
4556 | scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH; |
4557 | scb->cmd.flush_cache.command_id = IPS_MAX_CMDS; /* Use an ID that would otherwise not exist */ |
4558 | scb->cmd.flush_cache.state = IPS_NORM_STATE; |
4559 | scb->cmd.flush_cache.reserved = 0; |
4560 | scb->cmd.flush_cache.reserved2 = 0; |
4561 | scb->cmd.flush_cache.reserved3 = 0; |
4562 | scb->cmd.flush_cache.reserved4 = 0; |
4563 | |
4564 | ret = ips_send_cmd(ha, scb); /* Send the Flush Command */ |
4565 | |
4566 | if (ret == IPS_SUCCESS) { |
4567 | time = 60 * IPS_ONE_SEC; /* Max Wait time is 60 seconds */ |
4568 | done = 0; |
4569 | |
4570 | while ((time > 0) && (!done)) { |
4571 | done = ips_poll_for_flush_complete(ha); |
4572 | /* This may look evil, but it's only done during extremely rare start-up conditions ! */ |
4573 | udelay(1000); |
4574 | time--; |
4575 | } |
4576 | } |
4577 | } |
4578 | |
4579 | /* Now RESET and INIT the adapter */ |
4580 | (*ha->func.reset) (ha); |
4581 | |
4582 | dma_free_coherent(dev: &ha->pcidev->dev, size: sizeof(ips_scb_t), cpu_addr: scb, dma_handle: command_dma); |
4583 | return; |
4584 | } |
4585 | |
4586 | /****************************************************************************/ |
4587 | /* */ |
4588 | /* Routine Name: ips_poll_for_flush_complete */ |
4589 | /* */ |
4590 | /* Routine Description: */ |
4591 | /* */ |
4592 | /* Poll for the Flush Command issued by ips_flush_and_reset() to complete */ |
4593 | /* All other responses are just taken off the queue and ignored */ |
4594 | /* */ |
4595 | /****************************************************************************/ |
4596 | static int |
4597 | ips_poll_for_flush_complete(ips_ha_t * ha) |
4598 | { |
4599 | IPS_STATUS cstatus; |
4600 | |
4601 | while (true) { |
4602 | cstatus.value = (*ha->func.statupd) (ha); |
4603 | |
4604 | if (cstatus.value == 0xffffffff) /* If No Interrupt to process */ |
4605 | break; |
4606 | |
4607 | /* Success is when we see the Flush Command ID */ |
4608 | if (cstatus.fields.command_id == IPS_MAX_CMDS) |
4609 | return 1; |
4610 | } |
4611 | |
4612 | return 0; |
4613 | } |
4614 | |
4615 | /****************************************************************************/ |
4616 | /* */ |
4617 | /* Routine Name: ips_enable_int_copperhead */ |
4618 | /* */ |
4619 | /* Routine Description: */ |
4620 | /* Turn on interrupts */ |
4621 | /* */ |
4622 | /****************************************************************************/ |
4623 | static void |
4624 | ips_enable_int_copperhead(ips_ha_t * ha) |
4625 | { |
4626 | METHOD_TRACE("ips_enable_int_copperhead" , 1); |
4627 | |
4628 | outb(value: ha->io_addr + IPS_REG_HISR, IPS_BIT_EI); |
4629 | inb(port: ha->io_addr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/ |
4630 | } |
4631 | |
4632 | /****************************************************************************/ |
4633 | /* */ |
4634 | /* Routine Name: ips_enable_int_copperhead_memio */ |
4635 | /* */ |
4636 | /* Routine Description: */ |
4637 | /* Turn on interrupts */ |
4638 | /* */ |
4639 | /****************************************************************************/ |
4640 | static void |
4641 | ips_enable_int_copperhead_memio(ips_ha_t * ha) |
4642 | { |
4643 | METHOD_TRACE("ips_enable_int_copperhead_memio" , 1); |
4644 | |
4645 | writeb(IPS_BIT_EI, addr: ha->mem_ptr + IPS_REG_HISR); |
4646 | readb(addr: ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/ |
4647 | } |
4648 | |
4649 | /****************************************************************************/ |
4650 | /* */ |
4651 | /* Routine Name: ips_enable_int_morpheus */ |
4652 | /* */ |
4653 | /* Routine Description: */ |
4654 | /* Turn on interrupts */ |
4655 | /* */ |
4656 | /****************************************************************************/ |
4657 | static void |
4658 | ips_enable_int_morpheus(ips_ha_t * ha) |
4659 | { |
4660 | uint32_t Oimr; |
4661 | |
4662 | METHOD_TRACE("ips_enable_int_morpheus" , 1); |
4663 | |
4664 | Oimr = readl(addr: ha->mem_ptr + IPS_REG_I960_OIMR); |
4665 | Oimr &= ~0x08; |
4666 | writel(val: Oimr, addr: ha->mem_ptr + IPS_REG_I960_OIMR); |
4667 | readl(addr: ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/ |
4668 | } |
4669 | |
4670 | /****************************************************************************/ |
4671 | /* */ |
4672 | /* Routine Name: ips_init_copperhead */ |
4673 | /* */ |
4674 | /* Routine Description: */ |
4675 | /* */ |
4676 | /* Initialize a copperhead controller */ |
4677 | /* */ |
4678 | /****************************************************************************/ |
4679 | static int |
4680 | ips_init_copperhead(ips_ha_t * ha) |
4681 | { |
4682 | uint8_t Isr; |
4683 | uint8_t Cbsp; |
4684 | uint8_t PostByte[IPS_MAX_POST_BYTES]; |
4685 | int i, j; |
4686 | |
4687 | METHOD_TRACE("ips_init_copperhead" , 1); |
4688 | |
4689 | for (i = 0; i < IPS_MAX_POST_BYTES; i++) { |
4690 | for (j = 0; j < 45; j++) { |
4691 | Isr = inb(port: ha->io_addr + IPS_REG_HISR); |
4692 | if (Isr & IPS_BIT_GHI) |
4693 | break; |
4694 | |
4695 | /* Delay for 1 Second */ |
4696 | MDELAY(IPS_ONE_SEC); |
4697 | } |
4698 | |
4699 | if (j >= 45) |
4700 | /* error occurred */ |
4701 | return (0); |
4702 | |
4703 | PostByte[i] = inb(port: ha->io_addr + IPS_REG_ISPR); |
4704 | outb(value: Isr, port: ha->io_addr + IPS_REG_HISR); |
4705 | } |
4706 | |
4707 | if (PostByte[0] < IPS_GOOD_POST_STATUS) { |
4708 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
4709 | "reset controller fails (post status %x %x).\n" , |
4710 | PostByte[0], PostByte[1]); |
4711 | |
4712 | return (0); |
4713 | } |
4714 | |
4715 | for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) { |
4716 | for (j = 0; j < 240; j++) { |
4717 | Isr = inb(port: ha->io_addr + IPS_REG_HISR); |
4718 | if (Isr & IPS_BIT_GHI) |
4719 | break; |
4720 | |
4721 | /* Delay for 1 Second */ |
4722 | MDELAY(IPS_ONE_SEC); |
4723 | } |
4724 | |
4725 | if (j >= 240) |
4726 | /* error occurred */ |
4727 | return (0); |
4728 | |
4729 | inb(port: ha->io_addr + IPS_REG_ISPR); |
4730 | outb(value: Isr, port: ha->io_addr + IPS_REG_HISR); |
4731 | } |
4732 | |
4733 | for (i = 0; i < 240; i++) { |
4734 | Cbsp = inb(port: ha->io_addr + IPS_REG_CBSP); |
4735 | |
4736 | if ((Cbsp & IPS_BIT_OP) == 0) |
4737 | break; |
4738 | |
4739 | /* Delay for 1 Second */ |
4740 | MDELAY(IPS_ONE_SEC); |
4741 | } |
4742 | |
4743 | if (i >= 240) |
4744 | /* reset failed */ |
4745 | return (0); |
4746 | |
4747 | /* setup CCCR */ |
4748 | outl(value: 0x1010, port: ha->io_addr + IPS_REG_CCCR); |
4749 | |
4750 | /* Enable busmastering */ |
4751 | outb(IPS_BIT_EBM, port: ha->io_addr + IPS_REG_SCPR); |
4752 | |
4753 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
4754 | /* fix for anaconda64 */ |
4755 | outl(value: 0, port: ha->io_addr + IPS_REG_NDAE); |
4756 | |
4757 | /* Enable interrupts */ |
4758 | outb(IPS_BIT_EI, port: ha->io_addr + IPS_REG_HISR); |
4759 | |
4760 | return (1); |
4761 | } |
4762 | |
4763 | /****************************************************************************/ |
4764 | /* */ |
4765 | /* Routine Name: ips_init_copperhead_memio */ |
4766 | /* */ |
4767 | /* Routine Description: */ |
4768 | /* */ |
4769 | /* Initialize a copperhead controller with memory mapped I/O */ |
4770 | /* */ |
4771 | /****************************************************************************/ |
4772 | static int |
4773 | ips_init_copperhead_memio(ips_ha_t * ha) |
4774 | { |
4775 | uint8_t Isr = 0; |
4776 | uint8_t Cbsp; |
4777 | uint8_t PostByte[IPS_MAX_POST_BYTES]; |
4778 | int i, j; |
4779 | |
4780 | METHOD_TRACE("ips_init_copperhead_memio" , 1); |
4781 | |
4782 | for (i = 0; i < IPS_MAX_POST_BYTES; i++) { |
4783 | for (j = 0; j < 45; j++) { |
4784 | Isr = readb(addr: ha->mem_ptr + IPS_REG_HISR); |
4785 | if (Isr & IPS_BIT_GHI) |
4786 | break; |
4787 | |
4788 | /* Delay for 1 Second */ |
4789 | MDELAY(IPS_ONE_SEC); |
4790 | } |
4791 | |
4792 | if (j >= 45) |
4793 | /* error occurred */ |
4794 | return (0); |
4795 | |
4796 | PostByte[i] = readb(addr: ha->mem_ptr + IPS_REG_ISPR); |
4797 | writeb(val: Isr, addr: ha->mem_ptr + IPS_REG_HISR); |
4798 | } |
4799 | |
4800 | if (PostByte[0] < IPS_GOOD_POST_STATUS) { |
4801 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
4802 | "reset controller fails (post status %x %x).\n" , |
4803 | PostByte[0], PostByte[1]); |
4804 | |
4805 | return (0); |
4806 | } |
4807 | |
4808 | for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) { |
4809 | for (j = 0; j < 240; j++) { |
4810 | Isr = readb(addr: ha->mem_ptr + IPS_REG_HISR); |
4811 | if (Isr & IPS_BIT_GHI) |
4812 | break; |
4813 | |
4814 | /* Delay for 1 Second */ |
4815 | MDELAY(IPS_ONE_SEC); |
4816 | } |
4817 | |
4818 | if (j >= 240) |
4819 | /* error occurred */ |
4820 | return (0); |
4821 | |
4822 | readb(addr: ha->mem_ptr + IPS_REG_ISPR); |
4823 | writeb(val: Isr, addr: ha->mem_ptr + IPS_REG_HISR); |
4824 | } |
4825 | |
4826 | for (i = 0; i < 240; i++) { |
4827 | Cbsp = readb(addr: ha->mem_ptr + IPS_REG_CBSP); |
4828 | |
4829 | if ((Cbsp & IPS_BIT_OP) == 0) |
4830 | break; |
4831 | |
4832 | /* Delay for 1 Second */ |
4833 | MDELAY(IPS_ONE_SEC); |
4834 | } |
4835 | |
4836 | if (i >= 240) |
4837 | /* error occurred */ |
4838 | return (0); |
4839 | |
4840 | /* setup CCCR */ |
4841 | writel(val: 0x1010, addr: ha->mem_ptr + IPS_REG_CCCR); |
4842 | |
4843 | /* Enable busmastering */ |
4844 | writeb(IPS_BIT_EBM, addr: ha->mem_ptr + IPS_REG_SCPR); |
4845 | |
4846 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
4847 | /* fix for anaconda64 */ |
4848 | writel(val: 0, addr: ha->mem_ptr + IPS_REG_NDAE); |
4849 | |
4850 | /* Enable interrupts */ |
4851 | writeb(IPS_BIT_EI, addr: ha->mem_ptr + IPS_REG_HISR); |
4852 | |
4853 | /* if we get here then everything went OK */ |
4854 | return (1); |
4855 | } |
4856 | |
4857 | /****************************************************************************/ |
4858 | /* */ |
4859 | /* Routine Name: ips_init_morpheus */ |
4860 | /* */ |
4861 | /* Routine Description: */ |
4862 | /* */ |
4863 | /* Initialize a morpheus controller */ |
4864 | /* */ |
4865 | /****************************************************************************/ |
4866 | static int |
4867 | ips_init_morpheus(ips_ha_t * ha) |
4868 | { |
4869 | uint32_t Post; |
4870 | uint32_t Config; |
4871 | uint32_t Isr; |
4872 | uint32_t Oimr; |
4873 | int i; |
4874 | |
4875 | METHOD_TRACE("ips_init_morpheus" , 1); |
4876 | |
4877 | /* Wait up to 45 secs for Post */ |
4878 | for (i = 0; i < 45; i++) { |
4879 | Isr = readl(addr: ha->mem_ptr + IPS_REG_I2O_HIR); |
4880 | |
4881 | if (Isr & IPS_BIT_I960_MSG0I) |
4882 | break; |
4883 | |
4884 | /* Delay for 1 Second */ |
4885 | MDELAY(IPS_ONE_SEC); |
4886 | } |
4887 | |
4888 | if (i >= 45) { |
4889 | /* error occurred */ |
4890 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
4891 | "timeout waiting for post.\n" ); |
4892 | |
4893 | return (0); |
4894 | } |
4895 | |
4896 | Post = readl(addr: ha->mem_ptr + IPS_REG_I960_MSG0); |
4897 | |
4898 | if (Post == 0x4F00) { /* If Flashing the Battery PIC */ |
4899 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
4900 | "Flashing Battery PIC, Please wait ...\n" ); |
4901 | |
4902 | /* Clear the interrupt bit */ |
4903 | Isr = (uint32_t) IPS_BIT_I960_MSG0I; |
4904 | writel(val: Isr, addr: ha->mem_ptr + IPS_REG_I2O_HIR); |
4905 | |
4906 | for (i = 0; i < 120; i++) { /* Wait Up to 2 Min. for Completion */ |
4907 | Post = readl(addr: ha->mem_ptr + IPS_REG_I960_MSG0); |
4908 | if (Post != 0x4F00) |
4909 | break; |
4910 | /* Delay for 1 Second */ |
4911 | MDELAY(IPS_ONE_SEC); |
4912 | } |
4913 | |
4914 | if (i >= 120) { |
4915 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
4916 | "timeout waiting for Battery PIC Flash\n" ); |
4917 | return (0); |
4918 | } |
4919 | |
4920 | } |
4921 | |
4922 | /* Clear the interrupt bit */ |
4923 | Isr = (uint32_t) IPS_BIT_I960_MSG0I; |
4924 | writel(val: Isr, addr: ha->mem_ptr + IPS_REG_I2O_HIR); |
4925 | |
4926 | if (Post < (IPS_GOOD_POST_STATUS << 8)) { |
4927 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
4928 | "reset controller fails (post status %x).\n" , Post); |
4929 | |
4930 | return (0); |
4931 | } |
4932 | |
4933 | /* Wait up to 240 secs for config bytes */ |
4934 | for (i = 0; i < 240; i++) { |
4935 | Isr = readl(addr: ha->mem_ptr + IPS_REG_I2O_HIR); |
4936 | |
4937 | if (Isr & IPS_BIT_I960_MSG1I) |
4938 | break; |
4939 | |
4940 | /* Delay for 1 Second */ |
4941 | MDELAY(IPS_ONE_SEC); |
4942 | } |
4943 | |
4944 | if (i >= 240) { |
4945 | /* error occurred */ |
4946 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
4947 | "timeout waiting for config.\n" ); |
4948 | |
4949 | return (0); |
4950 | } |
4951 | |
4952 | Config = readl(addr: ha->mem_ptr + IPS_REG_I960_MSG1); |
4953 | |
4954 | /* Clear interrupt bit */ |
4955 | Isr = (uint32_t) IPS_BIT_I960_MSG1I; |
4956 | writel(val: Isr, addr: ha->mem_ptr + IPS_REG_I2O_HIR); |
4957 | |
4958 | /* Turn on the interrupts */ |
4959 | Oimr = readl(addr: ha->mem_ptr + IPS_REG_I960_OIMR); |
4960 | Oimr &= ~0x8; |
4961 | writel(val: Oimr, addr: ha->mem_ptr + IPS_REG_I960_OIMR); |
4962 | |
4963 | /* if we get here then everything went OK */ |
4964 | |
4965 | /* Since we did a RESET, an EraseStripeLock may be needed */ |
4966 | if (Post == 0xEF10) { |
4967 | if ((Config == 0x000F) || (Config == 0x0009)) |
4968 | ha->requires_esl = 1; |
4969 | } |
4970 | |
4971 | return (1); |
4972 | } |
4973 | |
4974 | /****************************************************************************/ |
4975 | /* */ |
4976 | /* Routine Name: ips_reset_copperhead */ |
4977 | /* */ |
4978 | /* Routine Description: */ |
4979 | /* */ |
4980 | /* Reset the controller */ |
4981 | /* */ |
4982 | /****************************************************************************/ |
4983 | static int |
4984 | ips_reset_copperhead(ips_ha_t * ha) |
4985 | { |
4986 | int reset_counter; |
4987 | |
4988 | METHOD_TRACE("ips_reset_copperhead" , 1); |
4989 | |
4990 | DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d" , |
4991 | ips_name, ha->host_num, ha->io_addr, ha->pcidev->irq); |
4992 | |
4993 | reset_counter = 0; |
4994 | |
4995 | while (reset_counter < 2) { |
4996 | reset_counter++; |
4997 | |
4998 | outb(IPS_BIT_RST, port: ha->io_addr + IPS_REG_SCPR); |
4999 | |
5000 | /* Delay for 1 Second */ |
5001 | MDELAY(IPS_ONE_SEC); |
5002 | |
5003 | outb(value: 0, port: ha->io_addr + IPS_REG_SCPR); |
5004 | |
5005 | /* Delay for 1 Second */ |
5006 | MDELAY(IPS_ONE_SEC); |
5007 | |
5008 | if ((*ha->func.init) (ha)) |
5009 | break; |
5010 | else if (reset_counter >= 2) { |
5011 | |
5012 | return (0); |
5013 | } |
5014 | } |
5015 | |
5016 | return (1); |
5017 | } |
5018 | |
5019 | /****************************************************************************/ |
5020 | /* */ |
5021 | /* Routine Name: ips_reset_copperhead_memio */ |
5022 | /* */ |
5023 | /* Routine Description: */ |
5024 | /* */ |
5025 | /* Reset the controller */ |
5026 | /* */ |
5027 | /****************************************************************************/ |
5028 | static int |
5029 | ips_reset_copperhead_memio(ips_ha_t * ha) |
5030 | { |
5031 | int reset_counter; |
5032 | |
5033 | METHOD_TRACE("ips_reset_copperhead_memio" , 1); |
5034 | |
5035 | DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d" , |
5036 | ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq); |
5037 | |
5038 | reset_counter = 0; |
5039 | |
5040 | while (reset_counter < 2) { |
5041 | reset_counter++; |
5042 | |
5043 | writeb(IPS_BIT_RST, addr: ha->mem_ptr + IPS_REG_SCPR); |
5044 | |
5045 | /* Delay for 1 Second */ |
5046 | MDELAY(IPS_ONE_SEC); |
5047 | |
5048 | writeb(val: 0, addr: ha->mem_ptr + IPS_REG_SCPR); |
5049 | |
5050 | /* Delay for 1 Second */ |
5051 | MDELAY(IPS_ONE_SEC); |
5052 | |
5053 | if ((*ha->func.init) (ha)) |
5054 | break; |
5055 | else if (reset_counter >= 2) { |
5056 | |
5057 | return (0); |
5058 | } |
5059 | } |
5060 | |
5061 | return (1); |
5062 | } |
5063 | |
5064 | /****************************************************************************/ |
5065 | /* */ |
5066 | /* Routine Name: ips_reset_morpheus */ |
5067 | /* */ |
5068 | /* Routine Description: */ |
5069 | /* */ |
5070 | /* Reset the controller */ |
5071 | /* */ |
5072 | /****************************************************************************/ |
5073 | static int |
5074 | ips_reset_morpheus(ips_ha_t * ha) |
5075 | { |
5076 | int reset_counter; |
5077 | uint8_t junk; |
5078 | |
5079 | METHOD_TRACE("ips_reset_morpheus" , 1); |
5080 | |
5081 | DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d" , |
5082 | ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq); |
5083 | |
5084 | reset_counter = 0; |
5085 | |
5086 | while (reset_counter < 2) { |
5087 | reset_counter++; |
5088 | |
5089 | writel(val: 0x80000000, addr: ha->mem_ptr + IPS_REG_I960_IDR); |
5090 | |
5091 | /* Delay for 5 Seconds */ |
5092 | MDELAY(5 * IPS_ONE_SEC); |
5093 | |
5094 | /* Do a PCI config read to wait for adapter */ |
5095 | pci_read_config_byte(dev: ha->pcidev, where: 4, val: &junk); |
5096 | |
5097 | if ((*ha->func.init) (ha)) |
5098 | break; |
5099 | else if (reset_counter >= 2) { |
5100 | |
5101 | return (0); |
5102 | } |
5103 | } |
5104 | |
5105 | return (1); |
5106 | } |
5107 | |
5108 | /****************************************************************************/ |
5109 | /* */ |
5110 | /* Routine Name: ips_statinit */ |
5111 | /* */ |
5112 | /* Routine Description: */ |
5113 | /* */ |
5114 | /* Initialize the status queues on the controller */ |
5115 | /* */ |
5116 | /****************************************************************************/ |
5117 | static void |
5118 | ips_statinit(ips_ha_t * ha) |
5119 | { |
5120 | uint32_t phys_status_start; |
5121 | |
5122 | METHOD_TRACE("ips_statinit" , 1); |
5123 | |
5124 | ha->adapt->p_status_start = ha->adapt->status; |
5125 | ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS; |
5126 | ha->adapt->p_status_tail = ha->adapt->status; |
5127 | |
5128 | phys_status_start = ha->adapt->hw_status_start; |
5129 | outl(value: phys_status_start, port: ha->io_addr + IPS_REG_SQSR); |
5130 | outl(value: phys_status_start + IPS_STATUS_Q_SIZE, |
5131 | port: ha->io_addr + IPS_REG_SQER); |
5132 | outl(value: phys_status_start + IPS_STATUS_SIZE, |
5133 | port: ha->io_addr + IPS_REG_SQHR); |
5134 | outl(value: phys_status_start, port: ha->io_addr + IPS_REG_SQTR); |
5135 | |
5136 | ha->adapt->hw_status_tail = phys_status_start; |
5137 | } |
5138 | |
5139 | /****************************************************************************/ |
5140 | /* */ |
5141 | /* Routine Name: ips_statinit_memio */ |
5142 | /* */ |
5143 | /* Routine Description: */ |
5144 | /* */ |
5145 | /* Initialize the status queues on the controller */ |
5146 | /* */ |
5147 | /****************************************************************************/ |
5148 | static void |
5149 | ips_statinit_memio(ips_ha_t * ha) |
5150 | { |
5151 | uint32_t phys_status_start; |
5152 | |
5153 | METHOD_TRACE("ips_statinit_memio" , 1); |
5154 | |
5155 | ha->adapt->p_status_start = ha->adapt->status; |
5156 | ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS; |
5157 | ha->adapt->p_status_tail = ha->adapt->status; |
5158 | |
5159 | phys_status_start = ha->adapt->hw_status_start; |
5160 | writel(val: phys_status_start, addr: ha->mem_ptr + IPS_REG_SQSR); |
5161 | writel(val: phys_status_start + IPS_STATUS_Q_SIZE, |
5162 | addr: ha->mem_ptr + IPS_REG_SQER); |
5163 | writel(val: phys_status_start + IPS_STATUS_SIZE, addr: ha->mem_ptr + IPS_REG_SQHR); |
5164 | writel(val: phys_status_start, addr: ha->mem_ptr + IPS_REG_SQTR); |
5165 | |
5166 | ha->adapt->hw_status_tail = phys_status_start; |
5167 | } |
5168 | |
5169 | /****************************************************************************/ |
5170 | /* */ |
5171 | /* Routine Name: ips_statupd_copperhead */ |
5172 | /* */ |
5173 | /* Routine Description: */ |
5174 | /* */ |
5175 | /* Remove an element from the status queue */ |
5176 | /* */ |
5177 | /****************************************************************************/ |
5178 | static uint32_t |
5179 | ips_statupd_copperhead(ips_ha_t * ha) |
5180 | { |
5181 | METHOD_TRACE("ips_statupd_copperhead" , 1); |
5182 | |
5183 | if (ha->adapt->p_status_tail != ha->adapt->p_status_end) { |
5184 | ha->adapt->p_status_tail++; |
5185 | ha->adapt->hw_status_tail += sizeof (IPS_STATUS); |
5186 | } else { |
5187 | ha->adapt->p_status_tail = ha->adapt->p_status_start; |
5188 | ha->adapt->hw_status_tail = ha->adapt->hw_status_start; |
5189 | } |
5190 | |
5191 | outl(value: ha->adapt->hw_status_tail, |
5192 | port: ha->io_addr + IPS_REG_SQTR); |
5193 | |
5194 | return (ha->adapt->p_status_tail->value); |
5195 | } |
5196 | |
5197 | /****************************************************************************/ |
5198 | /* */ |
5199 | /* Routine Name: ips_statupd_copperhead_memio */ |
5200 | /* */ |
5201 | /* Routine Description: */ |
5202 | /* */ |
5203 | /* Remove an element from the status queue */ |
5204 | /* */ |
5205 | /****************************************************************************/ |
5206 | static uint32_t |
5207 | ips_statupd_copperhead_memio(ips_ha_t * ha) |
5208 | { |
5209 | METHOD_TRACE("ips_statupd_copperhead_memio" , 1); |
5210 | |
5211 | if (ha->adapt->p_status_tail != ha->adapt->p_status_end) { |
5212 | ha->adapt->p_status_tail++; |
5213 | ha->adapt->hw_status_tail += sizeof (IPS_STATUS); |
5214 | } else { |
5215 | ha->adapt->p_status_tail = ha->adapt->p_status_start; |
5216 | ha->adapt->hw_status_tail = ha->adapt->hw_status_start; |
5217 | } |
5218 | |
5219 | writel(val: ha->adapt->hw_status_tail, addr: ha->mem_ptr + IPS_REG_SQTR); |
5220 | |
5221 | return (ha->adapt->p_status_tail->value); |
5222 | } |
5223 | |
5224 | /****************************************************************************/ |
5225 | /* */ |
5226 | /* Routine Name: ips_statupd_morpheus */ |
5227 | /* */ |
5228 | /* Routine Description: */ |
5229 | /* */ |
5230 | /* Remove an element from the status queue */ |
5231 | /* */ |
5232 | /****************************************************************************/ |
5233 | static uint32_t |
5234 | ips_statupd_morpheus(ips_ha_t * ha) |
5235 | { |
5236 | uint32_t val; |
5237 | |
5238 | METHOD_TRACE("ips_statupd_morpheus" , 1); |
5239 | |
5240 | val = readl(addr: ha->mem_ptr + IPS_REG_I2O_OUTMSGQ); |
5241 | |
5242 | return (val); |
5243 | } |
5244 | |
5245 | /****************************************************************************/ |
5246 | /* */ |
5247 | /* Routine Name: ips_issue_copperhead */ |
5248 | /* */ |
5249 | /* Routine Description: */ |
5250 | /* */ |
5251 | /* Send a command down to the controller */ |
5252 | /* */ |
5253 | /****************************************************************************/ |
5254 | static int |
5255 | ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb) |
5256 | { |
5257 | uint32_t TimeOut; |
5258 | uint32_t val; |
5259 | |
5260 | METHOD_TRACE("ips_issue_copperhead" , 1); |
5261 | |
5262 | if (scb->scsi_cmd) { |
5263 | DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)" , |
5264 | ips_name, |
5265 | ha->host_num, |
5266 | scb->cdb[0], |
5267 | scb->cmd.basic_io.command_id, |
5268 | scb->bus, scb->target_id, scb->lun); |
5269 | } else { |
5270 | DEBUG_VAR(2, KERN_NOTICE "(%s%d) ips_issue: logical cmd id %d" , |
5271 | ips_name, ha->host_num, scb->cmd.basic_io.command_id); |
5272 | } |
5273 | |
5274 | TimeOut = 0; |
5275 | |
5276 | while ((val = |
5277 | le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) { |
5278 | udelay(1000); |
5279 | |
5280 | if (++TimeOut >= IPS_SEM_TIMEOUT) { |
5281 | if (!(val & IPS_BIT_START_STOP)) |
5282 | break; |
5283 | |
5284 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
5285 | "ips_issue val [0x%x].\n" , val); |
5286 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
5287 | "ips_issue semaphore chk timeout.\n" ); |
5288 | |
5289 | return (IPS_FAILURE); |
5290 | } /* end if */ |
5291 | } /* end while */ |
5292 | |
5293 | outl(value: scb->scb_busaddr, port: ha->io_addr + IPS_REG_CCSAR); |
5294 | outw(IPS_BIT_START_CMD, port: ha->io_addr + IPS_REG_CCCR); |
5295 | |
5296 | return (IPS_SUCCESS); |
5297 | } |
5298 | |
5299 | /****************************************************************************/ |
5300 | /* */ |
5301 | /* Routine Name: ips_issue_copperhead_memio */ |
5302 | /* */ |
5303 | /* Routine Description: */ |
5304 | /* */ |
5305 | /* Send a command down to the controller */ |
5306 | /* */ |
5307 | /****************************************************************************/ |
5308 | static int |
5309 | ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb) |
5310 | { |
5311 | uint32_t TimeOut; |
5312 | uint32_t val; |
5313 | |
5314 | METHOD_TRACE("ips_issue_copperhead_memio" , 1); |
5315 | |
5316 | if (scb->scsi_cmd) { |
5317 | DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)" , |
5318 | ips_name, |
5319 | ha->host_num, |
5320 | scb->cdb[0], |
5321 | scb->cmd.basic_io.command_id, |
5322 | scb->bus, scb->target_id, scb->lun); |
5323 | } else { |
5324 | DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d" , |
5325 | ips_name, ha->host_num, scb->cmd.basic_io.command_id); |
5326 | } |
5327 | |
5328 | TimeOut = 0; |
5329 | |
5330 | while ((val = readl(addr: ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) { |
5331 | udelay(1000); |
5332 | |
5333 | if (++TimeOut >= IPS_SEM_TIMEOUT) { |
5334 | if (!(val & IPS_BIT_START_STOP)) |
5335 | break; |
5336 | |
5337 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
5338 | "ips_issue val [0x%x].\n" , val); |
5339 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
5340 | "ips_issue semaphore chk timeout.\n" ); |
5341 | |
5342 | return (IPS_FAILURE); |
5343 | } /* end if */ |
5344 | } /* end while */ |
5345 | |
5346 | writel(val: scb->scb_busaddr, addr: ha->mem_ptr + IPS_REG_CCSAR); |
5347 | writel(IPS_BIT_START_CMD, addr: ha->mem_ptr + IPS_REG_CCCR); |
5348 | |
5349 | return (IPS_SUCCESS); |
5350 | } |
5351 | |
5352 | /****************************************************************************/ |
5353 | /* */ |
5354 | /* Routine Name: ips_issue_i2o */ |
5355 | /* */ |
5356 | /* Routine Description: */ |
5357 | /* */ |
5358 | /* Send a command down to the controller */ |
5359 | /* */ |
5360 | /****************************************************************************/ |
5361 | static int |
5362 | ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb) |
5363 | { |
5364 | |
5365 | METHOD_TRACE("ips_issue_i2o" , 1); |
5366 | |
5367 | if (scb->scsi_cmd) { |
5368 | DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)" , |
5369 | ips_name, |
5370 | ha->host_num, |
5371 | scb->cdb[0], |
5372 | scb->cmd.basic_io.command_id, |
5373 | scb->bus, scb->target_id, scb->lun); |
5374 | } else { |
5375 | DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d" , |
5376 | ips_name, ha->host_num, scb->cmd.basic_io.command_id); |
5377 | } |
5378 | |
5379 | outl(value: scb->scb_busaddr, port: ha->io_addr + IPS_REG_I2O_INMSGQ); |
5380 | |
5381 | return (IPS_SUCCESS); |
5382 | } |
5383 | |
5384 | /****************************************************************************/ |
5385 | /* */ |
5386 | /* Routine Name: ips_issue_i2o_memio */ |
5387 | /* */ |
5388 | /* Routine Description: */ |
5389 | /* */ |
5390 | /* Send a command down to the controller */ |
5391 | /* */ |
5392 | /****************************************************************************/ |
5393 | static int |
5394 | ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb) |
5395 | { |
5396 | |
5397 | METHOD_TRACE("ips_issue_i2o_memio" , 1); |
5398 | |
5399 | if (scb->scsi_cmd) { |
5400 | DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)" , |
5401 | ips_name, |
5402 | ha->host_num, |
5403 | scb->cdb[0], |
5404 | scb->cmd.basic_io.command_id, |
5405 | scb->bus, scb->target_id, scb->lun); |
5406 | } else { |
5407 | DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d" , |
5408 | ips_name, ha->host_num, scb->cmd.basic_io.command_id); |
5409 | } |
5410 | |
5411 | writel(val: scb->scb_busaddr, addr: ha->mem_ptr + IPS_REG_I2O_INMSGQ); |
5412 | |
5413 | return (IPS_SUCCESS); |
5414 | } |
5415 | |
5416 | /****************************************************************************/ |
5417 | /* */ |
5418 | /* Routine Name: ips_isintr_copperhead */ |
5419 | /* */ |
5420 | /* Routine Description: */ |
5421 | /* */ |
5422 | /* Test to see if an interrupt is for us */ |
5423 | /* */ |
5424 | /****************************************************************************/ |
5425 | static int |
5426 | ips_isintr_copperhead(ips_ha_t * ha) |
5427 | { |
5428 | uint8_t Isr; |
5429 | |
5430 | METHOD_TRACE("ips_isintr_copperhead" , 2); |
5431 | |
5432 | Isr = inb(port: ha->io_addr + IPS_REG_HISR); |
5433 | |
5434 | if (Isr == 0xFF) |
5435 | /* ?!?! Nothing really there */ |
5436 | return (0); |
5437 | |
5438 | if (Isr & IPS_BIT_SCE) |
5439 | return (1); |
5440 | else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) { |
5441 | /* status queue overflow or GHI */ |
5442 | /* just clear the interrupt */ |
5443 | outb(value: Isr, port: ha->io_addr + IPS_REG_HISR); |
5444 | } |
5445 | |
5446 | return (0); |
5447 | } |
5448 | |
5449 | /****************************************************************************/ |
5450 | /* */ |
5451 | /* Routine Name: ips_isintr_copperhead_memio */ |
5452 | /* */ |
5453 | /* Routine Description: */ |
5454 | /* */ |
5455 | /* Test to see if an interrupt is for us */ |
5456 | /* */ |
5457 | /****************************************************************************/ |
5458 | static int |
5459 | ips_isintr_copperhead_memio(ips_ha_t * ha) |
5460 | { |
5461 | uint8_t Isr; |
5462 | |
5463 | METHOD_TRACE("ips_isintr_memio" , 2); |
5464 | |
5465 | Isr = readb(addr: ha->mem_ptr + IPS_REG_HISR); |
5466 | |
5467 | if (Isr == 0xFF) |
5468 | /* ?!?! Nothing really there */ |
5469 | return (0); |
5470 | |
5471 | if (Isr & IPS_BIT_SCE) |
5472 | return (1); |
5473 | else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) { |
5474 | /* status queue overflow or GHI */ |
5475 | /* just clear the interrupt */ |
5476 | writeb(val: Isr, addr: ha->mem_ptr + IPS_REG_HISR); |
5477 | } |
5478 | |
5479 | return (0); |
5480 | } |
5481 | |
5482 | /****************************************************************************/ |
5483 | /* */ |
5484 | /* Routine Name: ips_isintr_morpheus */ |
5485 | /* */ |
5486 | /* Routine Description: */ |
5487 | /* */ |
5488 | /* Test to see if an interrupt is for us */ |
5489 | /* */ |
5490 | /****************************************************************************/ |
5491 | static int |
5492 | ips_isintr_morpheus(ips_ha_t * ha) |
5493 | { |
5494 | uint32_t Isr; |
5495 | |
5496 | METHOD_TRACE("ips_isintr_morpheus" , 2); |
5497 | |
5498 | Isr = readl(addr: ha->mem_ptr + IPS_REG_I2O_HIR); |
5499 | |
5500 | if (Isr & IPS_BIT_I2O_OPQI) |
5501 | return (1); |
5502 | else |
5503 | return (0); |
5504 | } |
5505 | |
5506 | /****************************************************************************/ |
5507 | /* */ |
5508 | /* Routine Name: ips_wait */ |
5509 | /* */ |
5510 | /* Routine Description: */ |
5511 | /* */ |
5512 | /* Wait for a command to complete */ |
5513 | /* */ |
5514 | /****************************************************************************/ |
5515 | static int |
5516 | ips_wait(ips_ha_t * ha, int time, int intr) |
5517 | { |
5518 | int ret; |
5519 | int done; |
5520 | |
5521 | METHOD_TRACE("ips_wait" , 1); |
5522 | |
5523 | ret = IPS_FAILURE; |
5524 | done = false; |
5525 | |
5526 | time *= IPS_ONE_SEC; /* convert seconds */ |
5527 | |
5528 | while ((time > 0) && (!done)) { |
5529 | if (intr == IPS_INTR_ON) { |
5530 | if (!ha->waitflag) { |
5531 | ret = IPS_SUCCESS; |
5532 | done = true; |
5533 | break; |
5534 | } |
5535 | } else if (intr == IPS_INTR_IORL) { |
5536 | if (!ha->waitflag) { |
5537 | /* |
5538 | * controller generated an interrupt to |
5539 | * acknowledge completion of the command |
5540 | * and ips_intr() has serviced the interrupt. |
5541 | */ |
5542 | ret = IPS_SUCCESS; |
5543 | done = true; |
5544 | break; |
5545 | } |
5546 | |
5547 | /* |
5548 | * NOTE: we already have the io_request_lock so |
5549 | * even if we get an interrupt it won't get serviced |
5550 | * until after we finish. |
5551 | */ |
5552 | |
5553 | (*ha->func.intr) (ha); |
5554 | } |
5555 | |
5556 | /* This looks like a very evil loop, but it only does this during start-up */ |
5557 | udelay(1000); |
5558 | time--; |
5559 | } |
5560 | |
5561 | return (ret); |
5562 | } |
5563 | |
5564 | /****************************************************************************/ |
5565 | /* */ |
5566 | /* Routine Name: ips_write_driver_status */ |
5567 | /* */ |
5568 | /* Routine Description: */ |
5569 | /* */ |
5570 | /* Write OS/Driver version to Page 5 of the nvram on the controller */ |
5571 | /* */ |
5572 | /****************************************************************************/ |
5573 | static int |
5574 | ips_write_driver_status(ips_ha_t * ha, int intr) |
5575 | { |
5576 | METHOD_TRACE("ips_write_driver_status" , 1); |
5577 | |
5578 | if (!ips_readwrite_page5(ha, false, intr)) { |
5579 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
5580 | "unable to read NVRAM page 5.\n" ); |
5581 | |
5582 | return (0); |
5583 | } |
5584 | |
5585 | /* check to make sure the page has a valid */ |
5586 | /* signature */ |
5587 | if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) { |
5588 | DEBUG_VAR(1, |
5589 | "(%s%d) NVRAM page 5 has an invalid signature: %X." , |
5590 | ips_name, ha->host_num, ha->nvram->signature); |
5591 | ha->nvram->signature = IPS_NVRAM_P5_SIG; |
5592 | } |
5593 | |
5594 | DEBUG_VAR(2, |
5595 | "(%s%d) Ad Type: %d, Ad Slot: %d, BIOS: %c%c%c%c %c%c%c%c." , |
5596 | ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type), |
5597 | ha->nvram->adapter_slot, ha->nvram->bios_high[0], |
5598 | ha->nvram->bios_high[1], ha->nvram->bios_high[2], |
5599 | ha->nvram->bios_high[3], ha->nvram->bios_low[0], |
5600 | ha->nvram->bios_low[1], ha->nvram->bios_low[2], |
5601 | ha->nvram->bios_low[3]); |
5602 | |
5603 | ips_get_bios_version(ha, intr); |
5604 | |
5605 | /* change values (as needed) */ |
5606 | ha->nvram->operating_system = IPS_OS_LINUX; |
5607 | ha->nvram->adapter_type = ha->ad_type; |
5608 | memcpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4); |
5609 | memcpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4); |
5610 | memcpy((char *) ha->nvram->bios_high, ha->bios_version, 4); |
5611 | memcpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4); |
5612 | |
5613 | ha->nvram->versioning = 0; /* Indicate the Driver Does Not Support Versioning */ |
5614 | |
5615 | /* now update the page */ |
5616 | if (!ips_readwrite_page5(ha, true, intr)) { |
5617 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
5618 | "unable to write NVRAM page 5.\n" ); |
5619 | |
5620 | return (0); |
5621 | } |
5622 | |
5623 | /* IF NVRAM Page 5 is OK, Use it for Slot Number Info Because Linux Doesn't Do Slots */ |
5624 | ha->slot_num = ha->nvram->adapter_slot; |
5625 | |
5626 | return (1); |
5627 | } |
5628 | |
5629 | /****************************************************************************/ |
5630 | /* */ |
5631 | /* Routine Name: ips_read_adapter_status */ |
5632 | /* */ |
5633 | /* Routine Description: */ |
5634 | /* */ |
5635 | /* Do an Inquiry command to the adapter */ |
5636 | /* */ |
5637 | /****************************************************************************/ |
5638 | static int |
5639 | ips_read_adapter_status(ips_ha_t * ha, int intr) |
5640 | { |
5641 | ips_scb_t *scb; |
5642 | int ret; |
5643 | |
5644 | METHOD_TRACE("ips_read_adapter_status" , 1); |
5645 | |
5646 | scb = &ha->scbs[ha->max_cmds - 1]; |
5647 | |
5648 | ips_init_scb(ha, scb); |
5649 | |
5650 | scb->timeout = ips_cmd_timeout; |
5651 | scb->cdb[0] = IPS_CMD_ENQUIRY; |
5652 | |
5653 | scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY; |
5654 | scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); |
5655 | scb->cmd.basic_io.sg_count = 0; |
5656 | scb->cmd.basic_io.lba = 0; |
5657 | scb->cmd.basic_io.sector_count = 0; |
5658 | scb->cmd.basic_io.log_drv = 0; |
5659 | scb->data_len = sizeof (*ha->enq); |
5660 | scb->cmd.basic_io.sg_addr = ha->enq_busaddr; |
5661 | |
5662 | /* send command */ |
5663 | if (((ret = |
5664 | ips_send_wait(ha, scb, timeout: ips_cmd_timeout, intr)) == IPS_FAILURE) |
5665 | || (ret == IPS_SUCCESS_IMM) |
5666 | || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) |
5667 | return (0); |
5668 | |
5669 | return (1); |
5670 | } |
5671 | |
5672 | /****************************************************************************/ |
5673 | /* */ |
5674 | /* Routine Name: ips_read_subsystem_parameters */ |
5675 | /* */ |
5676 | /* Routine Description: */ |
5677 | /* */ |
5678 | /* Read subsystem parameters from the adapter */ |
5679 | /* */ |
5680 | /****************************************************************************/ |
5681 | static int |
5682 | ips_read_subsystem_parameters(ips_ha_t * ha, int intr) |
5683 | { |
5684 | ips_scb_t *scb; |
5685 | int ret; |
5686 | |
5687 | METHOD_TRACE("ips_read_subsystem_parameters" , 1); |
5688 | |
5689 | scb = &ha->scbs[ha->max_cmds - 1]; |
5690 | |
5691 | ips_init_scb(ha, scb); |
5692 | |
5693 | scb->timeout = ips_cmd_timeout; |
5694 | scb->cdb[0] = IPS_CMD_GET_SUBSYS; |
5695 | |
5696 | scb->cmd.basic_io.op_code = IPS_CMD_GET_SUBSYS; |
5697 | scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); |
5698 | scb->cmd.basic_io.sg_count = 0; |
5699 | scb->cmd.basic_io.lba = 0; |
5700 | scb->cmd.basic_io.sector_count = 0; |
5701 | scb->cmd.basic_io.log_drv = 0; |
5702 | scb->data_len = sizeof (*ha->subsys); |
5703 | scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr; |
5704 | |
5705 | /* send command */ |
5706 | if (((ret = |
5707 | ips_send_wait(ha, scb, timeout: ips_cmd_timeout, intr)) == IPS_FAILURE) |
5708 | || (ret == IPS_SUCCESS_IMM) |
5709 | || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) |
5710 | return (0); |
5711 | |
5712 | memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys)); |
5713 | return (1); |
5714 | } |
5715 | |
5716 | /****************************************************************************/ |
5717 | /* */ |
5718 | /* Routine Name: ips_read_config */ |
5719 | /* */ |
5720 | /* Routine Description: */ |
5721 | /* */ |
5722 | /* Read the configuration on the adapter */ |
5723 | /* */ |
5724 | /****************************************************************************/ |
5725 | static int |
5726 | ips_read_config(ips_ha_t * ha, int intr) |
5727 | { |
5728 | ips_scb_t *scb; |
5729 | int i; |
5730 | int ret; |
5731 | |
5732 | METHOD_TRACE("ips_read_config" , 1); |
5733 | |
5734 | /* set defaults for initiator IDs */ |
5735 | for (i = 0; i < 4; i++) |
5736 | ha->conf->init_id[i] = 7; |
5737 | |
5738 | scb = &ha->scbs[ha->max_cmds - 1]; |
5739 | |
5740 | ips_init_scb(ha, scb); |
5741 | |
5742 | scb->timeout = ips_cmd_timeout; |
5743 | scb->cdb[0] = IPS_CMD_READ_CONF; |
5744 | |
5745 | scb->cmd.basic_io.op_code = IPS_CMD_READ_CONF; |
5746 | scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); |
5747 | scb->data_len = sizeof (*ha->conf); |
5748 | scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr; |
5749 | |
5750 | /* send command */ |
5751 | if (((ret = |
5752 | ips_send_wait(ha, scb, timeout: ips_cmd_timeout, intr)) == IPS_FAILURE) |
5753 | || (ret == IPS_SUCCESS_IMM) |
5754 | || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) { |
5755 | |
5756 | memset(ha->conf, 0, sizeof (IPS_CONF)); |
5757 | |
5758 | /* reset initiator IDs */ |
5759 | for (i = 0; i < 4; i++) |
5760 | ha->conf->init_id[i] = 7; |
5761 | |
5762 | /* Allow Completed with Errors, so JCRM can access the Adapter to fix the problems */ |
5763 | if ((scb->basic_status & IPS_GSC_STATUS_MASK) == |
5764 | IPS_CMD_CMPLT_WERROR) |
5765 | return (1); |
5766 | |
5767 | return (0); |
5768 | } |
5769 | |
5770 | memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf)); |
5771 | return (1); |
5772 | } |
5773 | |
5774 | /****************************************************************************/ |
5775 | /* */ |
5776 | /* Routine Name: ips_readwrite_page5 */ |
5777 | /* */ |
5778 | /* Routine Description: */ |
5779 | /* */ |
5780 | /* Read nvram page 5 from the adapter */ |
5781 | /* */ |
5782 | /****************************************************************************/ |
5783 | static int |
5784 | ips_readwrite_page5(ips_ha_t * ha, int write, int intr) |
5785 | { |
5786 | ips_scb_t *scb; |
5787 | int ret; |
5788 | |
5789 | METHOD_TRACE("ips_readwrite_page5" , 1); |
5790 | |
5791 | scb = &ha->scbs[ha->max_cmds - 1]; |
5792 | |
5793 | ips_init_scb(ha, scb); |
5794 | |
5795 | scb->timeout = ips_cmd_timeout; |
5796 | scb->cdb[0] = IPS_CMD_RW_NVRAM_PAGE; |
5797 | |
5798 | scb->cmd.nvram.op_code = IPS_CMD_RW_NVRAM_PAGE; |
5799 | scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb); |
5800 | scb->cmd.nvram.page = 5; |
5801 | scb->cmd.nvram.write = write; |
5802 | scb->cmd.nvram.reserved = 0; |
5803 | scb->cmd.nvram.reserved2 = 0; |
5804 | scb->data_len = sizeof (*ha->nvram); |
5805 | scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr; |
5806 | if (write) |
5807 | memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram)); |
5808 | |
5809 | /* issue the command */ |
5810 | if (((ret = |
5811 | ips_send_wait(ha, scb, timeout: ips_cmd_timeout, intr)) == IPS_FAILURE) |
5812 | || (ret == IPS_SUCCESS_IMM) |
5813 | || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) { |
5814 | |
5815 | memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5)); |
5816 | |
5817 | return (0); |
5818 | } |
5819 | if (!write) |
5820 | memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram)); |
5821 | return (1); |
5822 | } |
5823 | |
5824 | /****************************************************************************/ |
5825 | /* */ |
5826 | /* Routine Name: ips_clear_adapter */ |
5827 | /* */ |
5828 | /* Routine Description: */ |
5829 | /* */ |
5830 | /* Clear the stripe lock tables */ |
5831 | /* */ |
5832 | /****************************************************************************/ |
5833 | static int |
5834 | ips_clear_adapter(ips_ha_t * ha, int intr) |
5835 | { |
5836 | ips_scb_t *scb; |
5837 | int ret; |
5838 | |
5839 | METHOD_TRACE("ips_clear_adapter" , 1); |
5840 | |
5841 | scb = &ha->scbs[ha->max_cmds - 1]; |
5842 | |
5843 | ips_init_scb(ha, scb); |
5844 | |
5845 | scb->timeout = ips_reset_timeout; |
5846 | scb->cdb[0] = IPS_CMD_CONFIG_SYNC; |
5847 | |
5848 | scb->cmd.config_sync.op_code = IPS_CMD_CONFIG_SYNC; |
5849 | scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb); |
5850 | scb->cmd.config_sync.channel = 0; |
5851 | scb->cmd.config_sync.source_target = IPS_POCL; |
5852 | scb->cmd.config_sync.reserved = 0; |
5853 | scb->cmd.config_sync.reserved2 = 0; |
5854 | scb->cmd.config_sync.reserved3 = 0; |
5855 | |
5856 | /* issue command */ |
5857 | if (((ret = |
5858 | ips_send_wait(ha, scb, timeout: ips_reset_timeout, intr)) == IPS_FAILURE) |
5859 | || (ret == IPS_SUCCESS_IMM) |
5860 | || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) |
5861 | return (0); |
5862 | |
5863 | /* send unlock stripe command */ |
5864 | ips_init_scb(ha, scb); |
5865 | |
5866 | scb->cdb[0] = IPS_CMD_ERROR_TABLE; |
5867 | scb->timeout = ips_reset_timeout; |
5868 | |
5869 | scb->cmd.unlock_stripe.op_code = IPS_CMD_ERROR_TABLE; |
5870 | scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb); |
5871 | scb->cmd.unlock_stripe.log_drv = 0; |
5872 | scb->cmd.unlock_stripe.control = IPS_CSL; |
5873 | scb->cmd.unlock_stripe.reserved = 0; |
5874 | scb->cmd.unlock_stripe.reserved2 = 0; |
5875 | scb->cmd.unlock_stripe.reserved3 = 0; |
5876 | |
5877 | /* issue command */ |
5878 | if (((ret = |
5879 | ips_send_wait(ha, scb, timeout: ips_cmd_timeout, intr)) == IPS_FAILURE) |
5880 | || (ret == IPS_SUCCESS_IMM) |
5881 | || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) |
5882 | return (0); |
5883 | |
5884 | return (1); |
5885 | } |
5886 | |
5887 | /****************************************************************************/ |
5888 | /* */ |
5889 | /* Routine Name: ips_ffdc_reset */ |
5890 | /* */ |
5891 | /* Routine Description: */ |
5892 | /* */ |
5893 | /* FFDC: write reset info */ |
5894 | /* */ |
5895 | /****************************************************************************/ |
5896 | static void |
5897 | ips_ffdc_reset(ips_ha_t * ha, int intr) |
5898 | { |
5899 | ips_scb_t *scb; |
5900 | |
5901 | METHOD_TRACE("ips_ffdc_reset" , 1); |
5902 | |
5903 | scb = &ha->scbs[ha->max_cmds - 1]; |
5904 | |
5905 | ips_init_scb(ha, scb); |
5906 | |
5907 | scb->timeout = ips_cmd_timeout; |
5908 | scb->cdb[0] = IPS_CMD_FFDC; |
5909 | scb->cmd.ffdc.op_code = IPS_CMD_FFDC; |
5910 | scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb); |
5911 | scb->cmd.ffdc.reset_count = ha->reset_count; |
5912 | scb->cmd.ffdc.reset_type = 0x80; |
5913 | |
5914 | /* convert time to what the card wants */ |
5915 | ips_fix_ffdc_time(ha, scb, ha->last_ffdc); |
5916 | |
5917 | /* issue command */ |
5918 | ips_send_wait(ha, scb, timeout: ips_cmd_timeout, intr); |
5919 | } |
5920 | |
5921 | /****************************************************************************/ |
5922 | /* */ |
5923 | /* Routine Name: ips_ffdc_time */ |
5924 | /* */ |
5925 | /* Routine Description: */ |
5926 | /* */ |
5927 | /* FFDC: write time info */ |
5928 | /* */ |
5929 | /****************************************************************************/ |
5930 | static void |
5931 | ips_ffdc_time(ips_ha_t * ha) |
5932 | { |
5933 | ips_scb_t *scb; |
5934 | |
5935 | METHOD_TRACE("ips_ffdc_time" , 1); |
5936 | |
5937 | DEBUG_VAR(1, "(%s%d) Sending time update." , ips_name, ha->host_num); |
5938 | |
5939 | scb = &ha->scbs[ha->max_cmds - 1]; |
5940 | |
5941 | ips_init_scb(ha, scb); |
5942 | |
5943 | scb->timeout = ips_cmd_timeout; |
5944 | scb->cdb[0] = IPS_CMD_FFDC; |
5945 | scb->cmd.ffdc.op_code = IPS_CMD_FFDC; |
5946 | scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb); |
5947 | scb->cmd.ffdc.reset_count = 0; |
5948 | scb->cmd.ffdc.reset_type = 0; |
5949 | |
5950 | /* convert time to what the card wants */ |
5951 | ips_fix_ffdc_time(ha, scb, ha->last_ffdc); |
5952 | |
5953 | /* issue command */ |
5954 | ips_send_wait(ha, scb, timeout: ips_cmd_timeout, IPS_FFDC); |
5955 | } |
5956 | |
5957 | /****************************************************************************/ |
5958 | /* */ |
5959 | /* Routine Name: ips_fix_ffdc_time */ |
5960 | /* */ |
5961 | /* Routine Description: */ |
5962 | /* Adjust time_t to what the card wants */ |
5963 | /* */ |
5964 | /****************************************************************************/ |
5965 | static void |
5966 | ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time64_t current_time) |
5967 | { |
5968 | struct tm tm; |
5969 | |
5970 | METHOD_TRACE("ips_fix_ffdc_time" , 1); |
5971 | |
5972 | time64_to_tm(totalsecs: current_time, offset: 0, result: &tm); |
5973 | |
5974 | scb->cmd.ffdc.hour = tm.tm_hour; |
5975 | scb->cmd.ffdc.minute = tm.tm_min; |
5976 | scb->cmd.ffdc.second = tm.tm_sec; |
5977 | scb->cmd.ffdc.yearH = (tm.tm_year + 1900) / 100; |
5978 | scb->cmd.ffdc.yearL = tm.tm_year % 100; |
5979 | scb->cmd.ffdc.month = tm.tm_mon + 1; |
5980 | scb->cmd.ffdc.day = tm.tm_mday; |
5981 | } |
5982 | |
5983 | /**************************************************************************** |
5984 | * BIOS Flash Routines * |
5985 | ****************************************************************************/ |
5986 | |
5987 | /****************************************************************************/ |
5988 | /* */ |
5989 | /* Routine Name: ips_erase_bios */ |
5990 | /* */ |
5991 | /* Routine Description: */ |
5992 | /* Erase the BIOS on the adapter */ |
5993 | /* */ |
5994 | /****************************************************************************/ |
5995 | static int |
5996 | ips_erase_bios(ips_ha_t * ha) |
5997 | { |
5998 | int timeout; |
5999 | uint8_t status = 0; |
6000 | |
6001 | METHOD_TRACE("ips_erase_bios" , 1); |
6002 | |
6003 | status = 0; |
6004 | |
6005 | /* Clear the status register */ |
6006 | outl(value: 0, port: ha->io_addr + IPS_REG_FLAP); |
6007 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6008 | udelay(25); /* 25 us */ |
6009 | |
6010 | outb(value: 0x50, port: ha->io_addr + IPS_REG_FLDP); |
6011 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6012 | udelay(25); /* 25 us */ |
6013 | |
6014 | /* Erase Setup */ |
6015 | outb(value: 0x20, port: ha->io_addr + IPS_REG_FLDP); |
6016 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6017 | udelay(25); /* 25 us */ |
6018 | |
6019 | /* Erase Confirm */ |
6020 | outb(value: 0xD0, port: ha->io_addr + IPS_REG_FLDP); |
6021 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6022 | udelay(25); /* 25 us */ |
6023 | |
6024 | /* Erase Status */ |
6025 | outb(value: 0x70, port: ha->io_addr + IPS_REG_FLDP); |
6026 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6027 | udelay(25); /* 25 us */ |
6028 | |
6029 | timeout = 80000; /* 80 seconds */ |
6030 | |
6031 | while (timeout > 0) { |
6032 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { |
6033 | outl(value: 0, port: ha->io_addr + IPS_REG_FLAP); |
6034 | udelay(25); /* 25 us */ |
6035 | } |
6036 | |
6037 | status = inb(port: ha->io_addr + IPS_REG_FLDP); |
6038 | |
6039 | if (status & 0x80) |
6040 | break; |
6041 | |
6042 | MDELAY(1); |
6043 | timeout--; |
6044 | } |
6045 | |
6046 | /* check for timeout */ |
6047 | if (timeout <= 0) { |
6048 | /* timeout */ |
6049 | |
6050 | /* try to suspend the erase */ |
6051 | outb(value: 0xB0, port: ha->io_addr + IPS_REG_FLDP); |
6052 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6053 | udelay(25); /* 25 us */ |
6054 | |
6055 | /* wait for 10 seconds */ |
6056 | timeout = 10000; |
6057 | while (timeout > 0) { |
6058 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { |
6059 | outl(value: 0, port: ha->io_addr + IPS_REG_FLAP); |
6060 | udelay(25); /* 25 us */ |
6061 | } |
6062 | |
6063 | status = inb(port: ha->io_addr + IPS_REG_FLDP); |
6064 | |
6065 | if (status & 0xC0) |
6066 | break; |
6067 | |
6068 | MDELAY(1); |
6069 | timeout--; |
6070 | } |
6071 | |
6072 | return (1); |
6073 | } |
6074 | |
6075 | /* check for valid VPP */ |
6076 | if (status & 0x08) |
6077 | /* VPP failure */ |
6078 | return (1); |
6079 | |
6080 | /* check for successful flash */ |
6081 | if (status & 0x30) |
6082 | /* sequence error */ |
6083 | return (1); |
6084 | |
6085 | /* Otherwise, we were successful */ |
6086 | /* clear status */ |
6087 | outb(value: 0x50, port: ha->io_addr + IPS_REG_FLDP); |
6088 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6089 | udelay(25); /* 25 us */ |
6090 | |
6091 | /* enable reads */ |
6092 | outb(value: 0xFF, port: ha->io_addr + IPS_REG_FLDP); |
6093 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6094 | udelay(25); /* 25 us */ |
6095 | |
6096 | return (0); |
6097 | } |
6098 | |
6099 | /****************************************************************************/ |
6100 | /* */ |
6101 | /* Routine Name: ips_erase_bios_memio */ |
6102 | /* */ |
6103 | /* Routine Description: */ |
6104 | /* Erase the BIOS on the adapter */ |
6105 | /* */ |
6106 | /****************************************************************************/ |
6107 | static int |
6108 | ips_erase_bios_memio(ips_ha_t * ha) |
6109 | { |
6110 | int timeout; |
6111 | uint8_t status; |
6112 | |
6113 | METHOD_TRACE("ips_erase_bios_memio" , 1); |
6114 | |
6115 | status = 0; |
6116 | |
6117 | /* Clear the status register */ |
6118 | writel(val: 0, addr: ha->mem_ptr + IPS_REG_FLAP); |
6119 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6120 | udelay(25); /* 25 us */ |
6121 | |
6122 | writeb(val: 0x50, addr: ha->mem_ptr + IPS_REG_FLDP); |
6123 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6124 | udelay(25); /* 25 us */ |
6125 | |
6126 | /* Erase Setup */ |
6127 | writeb(val: 0x20, addr: ha->mem_ptr + IPS_REG_FLDP); |
6128 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6129 | udelay(25); /* 25 us */ |
6130 | |
6131 | /* Erase Confirm */ |
6132 | writeb(val: 0xD0, addr: ha->mem_ptr + IPS_REG_FLDP); |
6133 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6134 | udelay(25); /* 25 us */ |
6135 | |
6136 | /* Erase Status */ |
6137 | writeb(val: 0x70, addr: ha->mem_ptr + IPS_REG_FLDP); |
6138 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6139 | udelay(25); /* 25 us */ |
6140 | |
6141 | timeout = 80000; /* 80 seconds */ |
6142 | |
6143 | while (timeout > 0) { |
6144 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { |
6145 | writel(val: 0, addr: ha->mem_ptr + IPS_REG_FLAP); |
6146 | udelay(25); /* 25 us */ |
6147 | } |
6148 | |
6149 | status = readb(addr: ha->mem_ptr + IPS_REG_FLDP); |
6150 | |
6151 | if (status & 0x80) |
6152 | break; |
6153 | |
6154 | MDELAY(1); |
6155 | timeout--; |
6156 | } |
6157 | |
6158 | /* check for timeout */ |
6159 | if (timeout <= 0) { |
6160 | /* timeout */ |
6161 | |
6162 | /* try to suspend the erase */ |
6163 | writeb(val: 0xB0, addr: ha->mem_ptr + IPS_REG_FLDP); |
6164 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6165 | udelay(25); /* 25 us */ |
6166 | |
6167 | /* wait for 10 seconds */ |
6168 | timeout = 10000; |
6169 | while (timeout > 0) { |
6170 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { |
6171 | writel(val: 0, addr: ha->mem_ptr + IPS_REG_FLAP); |
6172 | udelay(25); /* 25 us */ |
6173 | } |
6174 | |
6175 | status = readb(addr: ha->mem_ptr + IPS_REG_FLDP); |
6176 | |
6177 | if (status & 0xC0) |
6178 | break; |
6179 | |
6180 | MDELAY(1); |
6181 | timeout--; |
6182 | } |
6183 | |
6184 | return (1); |
6185 | } |
6186 | |
6187 | /* check for valid VPP */ |
6188 | if (status & 0x08) |
6189 | /* VPP failure */ |
6190 | return (1); |
6191 | |
6192 | /* check for successful flash */ |
6193 | if (status & 0x30) |
6194 | /* sequence error */ |
6195 | return (1); |
6196 | |
6197 | /* Otherwise, we were successful */ |
6198 | /* clear status */ |
6199 | writeb(val: 0x50, addr: ha->mem_ptr + IPS_REG_FLDP); |
6200 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6201 | udelay(25); /* 25 us */ |
6202 | |
6203 | /* enable reads */ |
6204 | writeb(val: 0xFF, addr: ha->mem_ptr + IPS_REG_FLDP); |
6205 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6206 | udelay(25); /* 25 us */ |
6207 | |
6208 | return (0); |
6209 | } |
6210 | |
6211 | /****************************************************************************/ |
6212 | /* */ |
6213 | /* Routine Name: ips_program_bios */ |
6214 | /* */ |
6215 | /* Routine Description: */ |
6216 | /* Program the BIOS on the adapter */ |
6217 | /* */ |
6218 | /****************************************************************************/ |
6219 | static int |
6220 | ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize, |
6221 | uint32_t offset) |
6222 | { |
6223 | int i; |
6224 | int timeout; |
6225 | uint8_t status = 0; |
6226 | |
6227 | METHOD_TRACE("ips_program_bios" , 1); |
6228 | |
6229 | status = 0; |
6230 | |
6231 | for (i = 0; i < buffersize; i++) { |
6232 | /* write a byte */ |
6233 | outl(value: i + offset, port: ha->io_addr + IPS_REG_FLAP); |
6234 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6235 | udelay(25); /* 25 us */ |
6236 | |
6237 | outb(value: 0x40, port: ha->io_addr + IPS_REG_FLDP); |
6238 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6239 | udelay(25); /* 25 us */ |
6240 | |
6241 | outb(value: buffer[i], port: ha->io_addr + IPS_REG_FLDP); |
6242 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6243 | udelay(25); /* 25 us */ |
6244 | |
6245 | /* wait up to one second */ |
6246 | timeout = 1000; |
6247 | while (timeout > 0) { |
6248 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { |
6249 | outl(value: 0, port: ha->io_addr + IPS_REG_FLAP); |
6250 | udelay(25); /* 25 us */ |
6251 | } |
6252 | |
6253 | status = inb(port: ha->io_addr + IPS_REG_FLDP); |
6254 | |
6255 | if (status & 0x80) |
6256 | break; |
6257 | |
6258 | MDELAY(1); |
6259 | timeout--; |
6260 | } |
6261 | |
6262 | if (timeout == 0) { |
6263 | /* timeout error */ |
6264 | outl(value: 0, port: ha->io_addr + IPS_REG_FLAP); |
6265 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6266 | udelay(25); /* 25 us */ |
6267 | |
6268 | outb(value: 0xFF, port: ha->io_addr + IPS_REG_FLDP); |
6269 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6270 | udelay(25); /* 25 us */ |
6271 | |
6272 | return (1); |
6273 | } |
6274 | |
6275 | /* check the status */ |
6276 | if (status & 0x18) { |
6277 | /* programming error */ |
6278 | outl(value: 0, port: ha->io_addr + IPS_REG_FLAP); |
6279 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6280 | udelay(25); /* 25 us */ |
6281 | |
6282 | outb(value: 0xFF, port: ha->io_addr + IPS_REG_FLDP); |
6283 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6284 | udelay(25); /* 25 us */ |
6285 | |
6286 | return (1); |
6287 | } |
6288 | } /* end for */ |
6289 | |
6290 | /* Enable reading */ |
6291 | outl(value: 0, port: ha->io_addr + IPS_REG_FLAP); |
6292 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6293 | udelay(25); /* 25 us */ |
6294 | |
6295 | outb(value: 0xFF, port: ha->io_addr + IPS_REG_FLDP); |
6296 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6297 | udelay(25); /* 25 us */ |
6298 | |
6299 | return (0); |
6300 | } |
6301 | |
6302 | /****************************************************************************/ |
6303 | /* */ |
6304 | /* Routine Name: ips_program_bios_memio */ |
6305 | /* */ |
6306 | /* Routine Description: */ |
6307 | /* Program the BIOS on the adapter */ |
6308 | /* */ |
6309 | /****************************************************************************/ |
6310 | static int |
6311 | ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize, |
6312 | uint32_t offset) |
6313 | { |
6314 | int i; |
6315 | int timeout; |
6316 | uint8_t status = 0; |
6317 | |
6318 | METHOD_TRACE("ips_program_bios_memio" , 1); |
6319 | |
6320 | status = 0; |
6321 | |
6322 | for (i = 0; i < buffersize; i++) { |
6323 | /* write a byte */ |
6324 | writel(val: i + offset, addr: ha->mem_ptr + IPS_REG_FLAP); |
6325 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6326 | udelay(25); /* 25 us */ |
6327 | |
6328 | writeb(val: 0x40, addr: ha->mem_ptr + IPS_REG_FLDP); |
6329 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6330 | udelay(25); /* 25 us */ |
6331 | |
6332 | writeb(val: buffer[i], addr: ha->mem_ptr + IPS_REG_FLDP); |
6333 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6334 | udelay(25); /* 25 us */ |
6335 | |
6336 | /* wait up to one second */ |
6337 | timeout = 1000; |
6338 | while (timeout > 0) { |
6339 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { |
6340 | writel(val: 0, addr: ha->mem_ptr + IPS_REG_FLAP); |
6341 | udelay(25); /* 25 us */ |
6342 | } |
6343 | |
6344 | status = readb(addr: ha->mem_ptr + IPS_REG_FLDP); |
6345 | |
6346 | if (status & 0x80) |
6347 | break; |
6348 | |
6349 | MDELAY(1); |
6350 | timeout--; |
6351 | } |
6352 | |
6353 | if (timeout == 0) { |
6354 | /* timeout error */ |
6355 | writel(val: 0, addr: ha->mem_ptr + IPS_REG_FLAP); |
6356 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6357 | udelay(25); /* 25 us */ |
6358 | |
6359 | writeb(val: 0xFF, addr: ha->mem_ptr + IPS_REG_FLDP); |
6360 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6361 | udelay(25); /* 25 us */ |
6362 | |
6363 | return (1); |
6364 | } |
6365 | |
6366 | /* check the status */ |
6367 | if (status & 0x18) { |
6368 | /* programming error */ |
6369 | writel(val: 0, addr: ha->mem_ptr + IPS_REG_FLAP); |
6370 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6371 | udelay(25); /* 25 us */ |
6372 | |
6373 | writeb(val: 0xFF, addr: ha->mem_ptr + IPS_REG_FLDP); |
6374 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6375 | udelay(25); /* 25 us */ |
6376 | |
6377 | return (1); |
6378 | } |
6379 | } /* end for */ |
6380 | |
6381 | /* Enable reading */ |
6382 | writel(val: 0, addr: ha->mem_ptr + IPS_REG_FLAP); |
6383 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6384 | udelay(25); /* 25 us */ |
6385 | |
6386 | writeb(val: 0xFF, addr: ha->mem_ptr + IPS_REG_FLDP); |
6387 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6388 | udelay(25); /* 25 us */ |
6389 | |
6390 | return (0); |
6391 | } |
6392 | |
6393 | /****************************************************************************/ |
6394 | /* */ |
6395 | /* Routine Name: ips_verify_bios */ |
6396 | /* */ |
6397 | /* Routine Description: */ |
6398 | /* Verify the BIOS on the adapter */ |
6399 | /* */ |
6400 | /****************************************************************************/ |
6401 | static int |
6402 | ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize, |
6403 | uint32_t offset) |
6404 | { |
6405 | uint8_t checksum; |
6406 | int i; |
6407 | |
6408 | METHOD_TRACE("ips_verify_bios" , 1); |
6409 | |
6410 | /* test 1st byte */ |
6411 | outl(value: 0, port: ha->io_addr + IPS_REG_FLAP); |
6412 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6413 | udelay(25); /* 25 us */ |
6414 | |
6415 | if (inb(port: ha->io_addr + IPS_REG_FLDP) != 0x55) |
6416 | return (1); |
6417 | |
6418 | outl(value: 1, port: ha->io_addr + IPS_REG_FLAP); |
6419 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6420 | udelay(25); /* 25 us */ |
6421 | if (inb(port: ha->io_addr + IPS_REG_FLDP) != 0xAA) |
6422 | return (1); |
6423 | |
6424 | checksum = 0xff; |
6425 | for (i = 2; i < buffersize; i++) { |
6426 | |
6427 | outl(value: i + offset, port: ha->io_addr + IPS_REG_FLAP); |
6428 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6429 | udelay(25); /* 25 us */ |
6430 | |
6431 | checksum = (uint8_t) checksum + inb(port: ha->io_addr + IPS_REG_FLDP); |
6432 | } |
6433 | |
6434 | if (checksum != 0) |
6435 | /* failure */ |
6436 | return (1); |
6437 | else |
6438 | /* success */ |
6439 | return (0); |
6440 | } |
6441 | |
6442 | /****************************************************************************/ |
6443 | /* */ |
6444 | /* Routine Name: ips_verify_bios_memio */ |
6445 | /* */ |
6446 | /* Routine Description: */ |
6447 | /* Verify the BIOS on the adapter */ |
6448 | /* */ |
6449 | /****************************************************************************/ |
6450 | static int |
6451 | ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize, |
6452 | uint32_t offset) |
6453 | { |
6454 | uint8_t checksum; |
6455 | int i; |
6456 | |
6457 | METHOD_TRACE("ips_verify_bios_memio" , 1); |
6458 | |
6459 | /* test 1st byte */ |
6460 | writel(val: 0, addr: ha->mem_ptr + IPS_REG_FLAP); |
6461 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6462 | udelay(25); /* 25 us */ |
6463 | |
6464 | if (readb(addr: ha->mem_ptr + IPS_REG_FLDP) != 0x55) |
6465 | return (1); |
6466 | |
6467 | writel(val: 1, addr: ha->mem_ptr + IPS_REG_FLAP); |
6468 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6469 | udelay(25); /* 25 us */ |
6470 | if (readb(addr: ha->mem_ptr + IPS_REG_FLDP) != 0xAA) |
6471 | return (1); |
6472 | |
6473 | checksum = 0xff; |
6474 | for (i = 2; i < buffersize; i++) { |
6475 | |
6476 | writel(val: i + offset, addr: ha->mem_ptr + IPS_REG_FLAP); |
6477 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6478 | udelay(25); /* 25 us */ |
6479 | |
6480 | checksum = |
6481 | (uint8_t) checksum + readb(addr: ha->mem_ptr + IPS_REG_FLDP); |
6482 | } |
6483 | |
6484 | if (checksum != 0) |
6485 | /* failure */ |
6486 | return (1); |
6487 | else |
6488 | /* success */ |
6489 | return (0); |
6490 | } |
6491 | |
6492 | /****************************************************************************/ |
6493 | /* */ |
6494 | /* Routine Name: ips_abort_init */ |
6495 | /* */ |
6496 | /* Routine Description: */ |
6497 | /* cleanup routine for a failed adapter initialization */ |
6498 | /****************************************************************************/ |
6499 | static int |
6500 | ips_abort_init(ips_ha_t * ha, int index) |
6501 | { |
6502 | ha->active = 0; |
6503 | ips_free(ha); |
6504 | ips_ha[index] = NULL; |
6505 | ips_sh[index] = NULL; |
6506 | return -1; |
6507 | } |
6508 | |
6509 | /****************************************************************************/ |
6510 | /* */ |
6511 | /* Routine Name: ips_shift_controllers */ |
6512 | /* */ |
6513 | /* Routine Description: */ |
6514 | /* helper function for ordering adapters */ |
6515 | /****************************************************************************/ |
6516 | static void |
6517 | ips_shift_controllers(int lowindex, int highindex) |
6518 | { |
6519 | ips_ha_t *ha_sav = ips_ha[highindex]; |
6520 | struct Scsi_Host *sh_sav = ips_sh[highindex]; |
6521 | int i; |
6522 | |
6523 | for (i = highindex; i > lowindex; i--) { |
6524 | ips_ha[i] = ips_ha[i - 1]; |
6525 | ips_sh[i] = ips_sh[i - 1]; |
6526 | ips_ha[i]->host_num = i; |
6527 | } |
6528 | ha_sav->host_num = lowindex; |
6529 | ips_ha[lowindex] = ha_sav; |
6530 | ips_sh[lowindex] = sh_sav; |
6531 | } |
6532 | |
6533 | /****************************************************************************/ |
6534 | /* */ |
6535 | /* Routine Name: ips_order_controllers */ |
6536 | /* */ |
6537 | /* Routine Description: */ |
6538 | /* place controllers is the "proper" boot order */ |
6539 | /****************************************************************************/ |
6540 | static void |
6541 | ips_order_controllers(void) |
6542 | { |
6543 | int i, j, tmp, position = 0; |
6544 | IPS_NVRAM_P5 *nvram; |
6545 | if (!ips_ha[0]) |
6546 | return; |
6547 | nvram = ips_ha[0]->nvram; |
6548 | |
6549 | if (nvram->adapter_order[0]) { |
6550 | for (i = 1; i <= nvram->adapter_order[0]; i++) { |
6551 | for (j = position; j < ips_num_controllers; j++) { |
6552 | switch (ips_ha[j]->ad_type) { |
6553 | case IPS_ADTYPE_SERVERAID6M: |
6554 | case IPS_ADTYPE_SERVERAID7M: |
6555 | if (nvram->adapter_order[i] == 'M') { |
6556 | ips_shift_controllers(lowindex: position, |
6557 | highindex: j); |
6558 | position++; |
6559 | } |
6560 | break; |
6561 | case IPS_ADTYPE_SERVERAID4L: |
6562 | case IPS_ADTYPE_SERVERAID4M: |
6563 | case IPS_ADTYPE_SERVERAID4MX: |
6564 | case IPS_ADTYPE_SERVERAID4LX: |
6565 | if (nvram->adapter_order[i] == 'N') { |
6566 | ips_shift_controllers(lowindex: position, |
6567 | highindex: j); |
6568 | position++; |
6569 | } |
6570 | break; |
6571 | case IPS_ADTYPE_SERVERAID6I: |
6572 | case IPS_ADTYPE_SERVERAID5I2: |
6573 | case IPS_ADTYPE_SERVERAID5I1: |
6574 | case IPS_ADTYPE_SERVERAID7k: |
6575 | if (nvram->adapter_order[i] == 'S') { |
6576 | ips_shift_controllers(lowindex: position, |
6577 | highindex: j); |
6578 | position++; |
6579 | } |
6580 | break; |
6581 | case IPS_ADTYPE_SERVERAID: |
6582 | case IPS_ADTYPE_SERVERAID2: |
6583 | case IPS_ADTYPE_NAVAJO: |
6584 | case IPS_ADTYPE_KIOWA: |
6585 | case IPS_ADTYPE_SERVERAID3L: |
6586 | case IPS_ADTYPE_SERVERAID3: |
6587 | case IPS_ADTYPE_SERVERAID4H: |
6588 | if (nvram->adapter_order[i] == 'A') { |
6589 | ips_shift_controllers(lowindex: position, |
6590 | highindex: j); |
6591 | position++; |
6592 | } |
6593 | break; |
6594 | default: |
6595 | break; |
6596 | } |
6597 | } |
6598 | } |
6599 | /* if adapter_order[0], then ordering is complete */ |
6600 | return; |
6601 | } |
6602 | /* old bios, use older ordering */ |
6603 | tmp = 0; |
6604 | for (i = position; i < ips_num_controllers; i++) { |
6605 | if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I2 || |
6606 | ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I1) { |
6607 | ips_shift_controllers(lowindex: position, highindex: i); |
6608 | position++; |
6609 | tmp = 1; |
6610 | } |
6611 | } |
6612 | /* if there were no 5I cards, then don't do any extra ordering */ |
6613 | if (!tmp) |
6614 | return; |
6615 | for (i = position; i < ips_num_controllers; i++) { |
6616 | if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4L || |
6617 | ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4M || |
6618 | ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4LX || |
6619 | ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4MX) { |
6620 | ips_shift_controllers(lowindex: position, highindex: i); |
6621 | position++; |
6622 | } |
6623 | } |
6624 | |
6625 | return; |
6626 | } |
6627 | |
6628 | /****************************************************************************/ |
6629 | /* */ |
6630 | /* Routine Name: ips_register_scsi */ |
6631 | /* */ |
6632 | /* Routine Description: */ |
6633 | /* perform any registration and setup with the scsi layer */ |
6634 | /****************************************************************************/ |
6635 | static int |
6636 | ips_register_scsi(int index) |
6637 | { |
6638 | struct Scsi_Host *sh; |
6639 | ips_ha_t *ha, *oldha = ips_ha[index]; |
6640 | sh = scsi_host_alloc(&ips_driver_template, sizeof (ips_ha_t)); |
6641 | if (!sh) { |
6642 | IPS_PRINTK(KERN_WARNING, oldha->pcidev, |
6643 | "Unable to register controller with SCSI subsystem\n" ); |
6644 | return -1; |
6645 | } |
6646 | ha = IPS_HA(sh); |
6647 | memcpy(ha, oldha, sizeof (ips_ha_t)); |
6648 | free_irq(oldha->pcidev->irq, oldha); |
6649 | /* Install the interrupt handler with the new ha */ |
6650 | if (request_irq(irq: ha->pcidev->irq, handler: do_ipsintr, IRQF_SHARED, name: ips_name, dev: ha)) { |
6651 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
6652 | "Unable to install interrupt handler\n" ); |
6653 | goto err_out_sh; |
6654 | } |
6655 | |
6656 | kfree(objp: oldha); |
6657 | |
6658 | /* Store away needed values for later use */ |
6659 | sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr; |
6660 | sh->sg_tablesize = sh->hostt->sg_tablesize; |
6661 | sh->can_queue = sh->hostt->can_queue; |
6662 | sh->cmd_per_lun = sh->hostt->cmd_per_lun; |
6663 | sh->max_sectors = 128; |
6664 | |
6665 | sh->max_id = ha->ntargets; |
6666 | sh->max_lun = ha->nlun; |
6667 | sh->max_channel = ha->nbus - 1; |
6668 | sh->can_queue = ha->max_cmds - 1; |
6669 | |
6670 | if (scsi_add_host(host: sh, dev: &ha->pcidev->dev)) |
6671 | goto err_out; |
6672 | |
6673 | ips_sh[index] = sh; |
6674 | ips_ha[index] = ha; |
6675 | |
6676 | scsi_scan_host(sh); |
6677 | |
6678 | return 0; |
6679 | |
6680 | err_out: |
6681 | free_irq(ha->pcidev->irq, ha); |
6682 | err_out_sh: |
6683 | scsi_host_put(t: sh); |
6684 | return -1; |
6685 | } |
6686 | |
6687 | /*---------------------------------------------------------------------------*/ |
6688 | /* Routine Name: ips_remove_device */ |
6689 | /* */ |
6690 | /* Routine Description: */ |
6691 | /* Remove one Adapter ( Hot Plugging ) */ |
6692 | /*---------------------------------------------------------------------------*/ |
6693 | static void |
6694 | ips_remove_device(struct pci_dev *pci_dev) |
6695 | { |
6696 | struct Scsi_Host *sh = pci_get_drvdata(pdev: pci_dev); |
6697 | |
6698 | pci_set_drvdata(pdev: pci_dev, NULL); |
6699 | |
6700 | ips_release(sh); |
6701 | |
6702 | pci_release_regions(pci_dev); |
6703 | pci_disable_device(dev: pci_dev); |
6704 | } |
6705 | |
6706 | /****************************************************************************/ |
6707 | /* */ |
6708 | /* Routine Name: ips_module_init */ |
6709 | /* */ |
6710 | /* Routine Description: */ |
6711 | /* function called on module load */ |
6712 | /****************************************************************************/ |
6713 | static int __init |
6714 | ips_module_init(void) |
6715 | { |
6716 | #if !defined(__i386__) && !defined(__ia64__) && !defined(__x86_64__) |
6717 | printk(KERN_ERR "ips: This driver has only been tested on the x86/ia64/x86_64 platforms\n" ); |
6718 | add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); |
6719 | #endif |
6720 | |
6721 | if (pci_register_driver(&ips_pci_driver) < 0) |
6722 | return -ENODEV; |
6723 | ips_driver_template.module = THIS_MODULE; |
6724 | ips_order_controllers(); |
6725 | if (!ips_detect(SHT: &ips_driver_template)) { |
6726 | pci_unregister_driver(dev: &ips_pci_driver); |
6727 | return -ENODEV; |
6728 | } |
6729 | register_reboot_notifier(&ips_notifier); |
6730 | return 0; |
6731 | } |
6732 | |
6733 | /****************************************************************************/ |
6734 | /* */ |
6735 | /* Routine Name: ips_module_exit */ |
6736 | /* */ |
6737 | /* Routine Description: */ |
6738 | /* function called on module unload */ |
6739 | /****************************************************************************/ |
6740 | static void __exit |
6741 | ips_module_exit(void) |
6742 | { |
6743 | pci_unregister_driver(dev: &ips_pci_driver); |
6744 | unregister_reboot_notifier(&ips_notifier); |
6745 | } |
6746 | |
6747 | module_init(ips_module_init); |
6748 | module_exit(ips_module_exit); |
6749 | |
6750 | /*---------------------------------------------------------------------------*/ |
6751 | /* Routine Name: ips_insert_device */ |
6752 | /* */ |
6753 | /* Routine Description: */ |
6754 | /* Add One Adapter ( Hot Plug ) */ |
6755 | /* */ |
6756 | /* Return Value: */ |
6757 | /* 0 if Successful, else non-zero */ |
6758 | /*---------------------------------------------------------------------------*/ |
6759 | static int |
6760 | ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent) |
6761 | { |
6762 | int index = -1; |
6763 | int rc; |
6764 | |
6765 | METHOD_TRACE("ips_insert_device" , 1); |
6766 | rc = pci_enable_device(dev: pci_dev); |
6767 | if (rc) |
6768 | return rc; |
6769 | |
6770 | rc = pci_request_regions(pci_dev, "ips" ); |
6771 | if (rc) |
6772 | goto err_out; |
6773 | |
6774 | rc = ips_init_phase1(pci_dev, indexPtr: &index); |
6775 | if (rc == SUCCESS) |
6776 | rc = ips_init_phase2(index); |
6777 | |
6778 | if (ips_hotplug) |
6779 | if (ips_register_scsi(index)) { |
6780 | ips_free(ha: ips_ha[index]); |
6781 | rc = -1; |
6782 | } |
6783 | |
6784 | if (rc == SUCCESS) |
6785 | ips_num_controllers++; |
6786 | |
6787 | ips_next_controller = ips_num_controllers; |
6788 | |
6789 | if (rc < 0) { |
6790 | rc = -ENODEV; |
6791 | goto err_out_regions; |
6792 | } |
6793 | |
6794 | pci_set_drvdata(pdev: pci_dev, data: ips_sh[index]); |
6795 | return 0; |
6796 | |
6797 | err_out_regions: |
6798 | pci_release_regions(pci_dev); |
6799 | err_out: |
6800 | pci_disable_device(dev: pci_dev); |
6801 | return rc; |
6802 | } |
6803 | |
6804 | /*---------------------------------------------------------------------------*/ |
6805 | /* Routine Name: ips_init_phase1 */ |
6806 | /* */ |
6807 | /* Routine Description: */ |
6808 | /* Adapter Initialization */ |
6809 | /* */ |
6810 | /* Return Value: */ |
6811 | /* 0 if Successful, else non-zero */ |
6812 | /*---------------------------------------------------------------------------*/ |
6813 | static int |
6814 | ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr) |
6815 | { |
6816 | ips_ha_t *ha; |
6817 | uint32_t io_addr; |
6818 | uint32_t mem_addr; |
6819 | uint32_t io_len; |
6820 | uint32_t mem_len; |
6821 | int j; |
6822 | int index; |
6823 | dma_addr_t dma_address; |
6824 | char __iomem *ioremap_ptr; |
6825 | char __iomem *mem_ptr; |
6826 | uint32_t IsDead; |
6827 | |
6828 | METHOD_TRACE("ips_init_phase1" , 1); |
6829 | index = IPS_MAX_ADAPTERS; |
6830 | for (j = 0; j < IPS_MAX_ADAPTERS; j++) { |
6831 | if (ips_ha[j] == NULL) { |
6832 | index = j; |
6833 | break; |
6834 | } |
6835 | } |
6836 | |
6837 | if (index >= IPS_MAX_ADAPTERS) |
6838 | return -1; |
6839 | |
6840 | /* Init MEM/IO addresses to 0 */ |
6841 | mem_addr = 0; |
6842 | io_addr = 0; |
6843 | mem_len = 0; |
6844 | io_len = 0; |
6845 | |
6846 | for (j = 0; j < 2; j++) { |
6847 | if (!pci_resource_start(pci_dev, j)) |
6848 | break; |
6849 | |
6850 | if (pci_resource_flags(pci_dev, j) & IORESOURCE_IO) { |
6851 | io_addr = pci_resource_start(pci_dev, j); |
6852 | io_len = pci_resource_len(pci_dev, j); |
6853 | } else { |
6854 | mem_addr = pci_resource_start(pci_dev, j); |
6855 | mem_len = pci_resource_len(pci_dev, j); |
6856 | } |
6857 | } |
6858 | |
6859 | /* setup memory mapped area (if applicable) */ |
6860 | if (mem_addr) { |
6861 | uint32_t base; |
6862 | uint32_t offs; |
6863 | |
6864 | base = mem_addr & PAGE_MASK; |
6865 | offs = mem_addr - base; |
6866 | ioremap_ptr = ioremap(offset: base, PAGE_SIZE); |
6867 | if (!ioremap_ptr) |
6868 | return -1; |
6869 | mem_ptr = ioremap_ptr + offs; |
6870 | } else { |
6871 | ioremap_ptr = NULL; |
6872 | mem_ptr = NULL; |
6873 | } |
6874 | |
6875 | /* found a controller */ |
6876 | ha = kzalloc(size: sizeof (ips_ha_t), GFP_KERNEL); |
6877 | if (ha == NULL) { |
6878 | IPS_PRINTK(KERN_WARNING, pci_dev, |
6879 | "Unable to allocate temporary ha struct\n" ); |
6880 | return -1; |
6881 | } |
6882 | |
6883 | ips_sh[index] = NULL; |
6884 | ips_ha[index] = ha; |
6885 | ha->active = 1; |
6886 | |
6887 | /* Store info in HA structure */ |
6888 | ha->io_addr = io_addr; |
6889 | ha->io_len = io_len; |
6890 | ha->mem_addr = mem_addr; |
6891 | ha->mem_len = mem_len; |
6892 | ha->mem_ptr = mem_ptr; |
6893 | ha->ioremap_ptr = ioremap_ptr; |
6894 | ha->host_num = (uint32_t) index; |
6895 | ha->slot_num = PCI_SLOT(pci_dev->devfn); |
6896 | ha->pcidev = pci_dev; |
6897 | |
6898 | /* |
6899 | * Set the pci_dev's dma_mask. Not all adapters support 64bit |
6900 | * addressing so don't enable it if the adapter can't support |
6901 | * it! Also, don't use 64bit addressing if dma addresses |
6902 | * are guaranteed to be < 4G. |
6903 | */ |
6904 | if (sizeof(dma_addr_t) > 4 && IPS_HAS_ENH_SGLIST(ha) && |
6905 | !dma_set_mask(dev: &ha->pcidev->dev, DMA_BIT_MASK(64))) { |
6906 | (ha)->flags |= IPS_HA_ENH_SG; |
6907 | } else { |
6908 | if (dma_set_mask(dev: &ha->pcidev->dev, DMA_BIT_MASK(32)) != 0) { |
6909 | printk(KERN_WARNING "Unable to set DMA Mask\n" ); |
6910 | return ips_abort_init(ha, index); |
6911 | } |
6912 | } |
6913 | if(ips_cd_boot && !ips_FlashData){ |
6914 | ips_FlashData = dma_alloc_coherent(dev: &pci_dev->dev, |
6915 | PAGE_SIZE << 7, dma_handle: &ips_flashbusaddr, GFP_KERNEL); |
6916 | } |
6917 | |
6918 | ha->enq = dma_alloc_coherent(dev: &pci_dev->dev, size: sizeof (IPS_ENQ), |
6919 | dma_handle: &ha->enq_busaddr, GFP_KERNEL); |
6920 | if (!ha->enq) { |
6921 | IPS_PRINTK(KERN_WARNING, pci_dev, |
6922 | "Unable to allocate host inquiry structure\n" ); |
6923 | return ips_abort_init(ha, index); |
6924 | } |
6925 | |
6926 | ha->adapt = dma_alloc_coherent(dev: &pci_dev->dev, |
6927 | size: sizeof (IPS_ADAPTER) + sizeof (IPS_IO_CMD), |
6928 | dma_handle: &dma_address, GFP_KERNEL); |
6929 | if (!ha->adapt) { |
6930 | IPS_PRINTK(KERN_WARNING, pci_dev, |
6931 | "Unable to allocate host adapt & dummy structures\n" ); |
6932 | return ips_abort_init(ha, index); |
6933 | } |
6934 | ha->adapt->hw_status_start = dma_address; |
6935 | ha->dummy = (void *) (ha->adapt + 1); |
6936 | |
6937 | |
6938 | |
6939 | ha->logical_drive_info = dma_alloc_coherent(dev: &pci_dev->dev, |
6940 | size: sizeof (IPS_LD_INFO), dma_handle: &dma_address, GFP_KERNEL); |
6941 | if (!ha->logical_drive_info) { |
6942 | IPS_PRINTK(KERN_WARNING, pci_dev, |
6943 | "Unable to allocate logical drive info structure\n" ); |
6944 | return ips_abort_init(ha, index); |
6945 | } |
6946 | ha->logical_drive_info_dma_addr = dma_address; |
6947 | |
6948 | |
6949 | ha->conf = kmalloc(size: sizeof (IPS_CONF), GFP_KERNEL); |
6950 | |
6951 | if (!ha->conf) { |
6952 | IPS_PRINTK(KERN_WARNING, pci_dev, |
6953 | "Unable to allocate host conf structure\n" ); |
6954 | return ips_abort_init(ha, index); |
6955 | } |
6956 | |
6957 | ha->nvram = kmalloc(size: sizeof (IPS_NVRAM_P5), GFP_KERNEL); |
6958 | |
6959 | if (!ha->nvram) { |
6960 | IPS_PRINTK(KERN_WARNING, pci_dev, |
6961 | "Unable to allocate host NVRAM structure\n" ); |
6962 | return ips_abort_init(ha, index); |
6963 | } |
6964 | |
6965 | ha->subsys = kmalloc(size: sizeof (IPS_SUBSYS), GFP_KERNEL); |
6966 | |
6967 | if (!ha->subsys) { |
6968 | IPS_PRINTK(KERN_WARNING, pci_dev, |
6969 | "Unable to allocate host subsystem structure\n" ); |
6970 | return ips_abort_init(ha, index); |
6971 | } |
6972 | |
6973 | /* the ioctl buffer is now used during adapter initialization, so its |
6974 | * successful allocation is now required */ |
6975 | if (ips_ioctlsize < PAGE_SIZE) |
6976 | ips_ioctlsize = PAGE_SIZE; |
6977 | |
6978 | ha->ioctl_data = dma_alloc_coherent(dev: &pci_dev->dev, size: ips_ioctlsize, |
6979 | dma_handle: &ha->ioctl_busaddr, GFP_KERNEL); |
6980 | ha->ioctl_len = ips_ioctlsize; |
6981 | if (!ha->ioctl_data) { |
6982 | IPS_PRINTK(KERN_WARNING, pci_dev, |
6983 | "Unable to allocate IOCTL data\n" ); |
6984 | return ips_abort_init(ha, index); |
6985 | } |
6986 | |
6987 | /* |
6988 | * Setup Functions |
6989 | */ |
6990 | ips_setup_funclist(ha); |
6991 | |
6992 | if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) { |
6993 | /* If Morpheus appears dead, reset it */ |
6994 | IsDead = readl(addr: ha->mem_ptr + IPS_REG_I960_MSG1); |
6995 | if (IsDead == 0xDEADBEEF) { |
6996 | ips_reset_morpheus(ha); |
6997 | } |
6998 | } |
6999 | |
7000 | /* |
7001 | * Initialize the card if it isn't already |
7002 | */ |
7003 | |
7004 | if (!(*ha->func.isinit) (ha)) { |
7005 | if (!(*ha->func.init) (ha)) { |
7006 | /* |
7007 | * Initialization failed |
7008 | */ |
7009 | IPS_PRINTK(KERN_WARNING, pci_dev, |
7010 | "Unable to initialize controller\n" ); |
7011 | return ips_abort_init(ha, index); |
7012 | } |
7013 | } |
7014 | |
7015 | *indexPtr = index; |
7016 | return SUCCESS; |
7017 | } |
7018 | |
7019 | /*---------------------------------------------------------------------------*/ |
7020 | /* Routine Name: ips_init_phase2 */ |
7021 | /* */ |
7022 | /* Routine Description: */ |
7023 | /* Adapter Initialization Phase 2 */ |
7024 | /* */ |
7025 | /* Return Value: */ |
7026 | /* 0 if Successful, else non-zero */ |
7027 | /*---------------------------------------------------------------------------*/ |
7028 | static int |
7029 | ips_init_phase2(int index) |
7030 | { |
7031 | ips_ha_t *ha; |
7032 | |
7033 | ha = ips_ha[index]; |
7034 | |
7035 | METHOD_TRACE("ips_init_phase2" , 1); |
7036 | if (!ha->active) { |
7037 | ips_ha[index] = NULL; |
7038 | return -1; |
7039 | } |
7040 | |
7041 | /* Install the interrupt handler */ |
7042 | if (request_irq(irq: ha->pcidev->irq, handler: do_ipsintr, IRQF_SHARED, name: ips_name, dev: ha)) { |
7043 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
7044 | "Unable to install interrupt handler\n" ); |
7045 | return ips_abort_init(ha, index); |
7046 | } |
7047 | |
7048 | /* |
7049 | * Allocate a temporary SCB for initialization |
7050 | */ |
7051 | ha->max_cmds = 1; |
7052 | if (!ips_allocatescbs(ha)) { |
7053 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
7054 | "Unable to allocate a CCB\n" ); |
7055 | free_irq(ha->pcidev->irq, ha); |
7056 | return ips_abort_init(ha, index); |
7057 | } |
7058 | |
7059 | if (!ips_hainit(ha)) { |
7060 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
7061 | "Unable to initialize controller\n" ); |
7062 | free_irq(ha->pcidev->irq, ha); |
7063 | return ips_abort_init(ha, index); |
7064 | } |
7065 | /* Free the temporary SCB */ |
7066 | ips_deallocatescbs(ha, cmds: 1); |
7067 | |
7068 | /* allocate CCBs */ |
7069 | if (!ips_allocatescbs(ha)) { |
7070 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
7071 | "Unable to allocate CCBs\n" ); |
7072 | free_irq(ha->pcidev->irq, ha); |
7073 | return ips_abort_init(ha, index); |
7074 | } |
7075 | |
7076 | return SUCCESS; |
7077 | } |
7078 | |
7079 | MODULE_LICENSE("GPL" ); |
7080 | MODULE_DESCRIPTION("IBM ServeRAID Adapter Driver " IPS_VER_STRING); |
7081 | MODULE_VERSION(IPS_VER_STRING); |
7082 | |