1 | /* |
2 | * Workbit NinjaSCSI-32Bi/UDE PCI/CardBus SCSI Host Bus Adapter driver |
3 | * I/O routine |
4 | * |
5 | * This software may be used and distributed according to the terms of |
6 | * the GNU General Public License. |
7 | */ |
8 | |
9 | #ifndef _NSP32_IO_H |
10 | #define _NSP32_IO_H |
11 | |
12 | static inline void nsp32_write1(unsigned int base, |
13 | unsigned int index, |
14 | unsigned char val) |
15 | { |
16 | outb(value: val, port: (base + index)); |
17 | } |
18 | |
19 | static inline unsigned char nsp32_read1(unsigned int base, |
20 | unsigned int index) |
21 | { |
22 | return inb(port: base + index); |
23 | } |
24 | |
25 | static inline void nsp32_write2(unsigned int base, |
26 | unsigned int index, |
27 | unsigned short val) |
28 | { |
29 | outw(value: val, port: (base + index)); |
30 | } |
31 | |
32 | static inline unsigned short nsp32_read2(unsigned int base, |
33 | unsigned int index) |
34 | { |
35 | return inw(port: base + index); |
36 | } |
37 | |
38 | static inline void nsp32_write4(unsigned int base, |
39 | unsigned int index, |
40 | unsigned long val) |
41 | { |
42 | outl(value: val, port: (base + index)); |
43 | } |
44 | |
45 | static inline unsigned long nsp32_read4(unsigned int base, |
46 | unsigned int index) |
47 | { |
48 | return inl(port: base + index); |
49 | } |
50 | |
51 | /*==============================================*/ |
52 | |
53 | static inline void nsp32_mmio_write1(unsigned long base, |
54 | unsigned int index, |
55 | unsigned char val) |
56 | { |
57 | volatile unsigned char *ptr; |
58 | |
59 | ptr = (unsigned char *)(base + NSP32_MMIO_OFFSET + index); |
60 | |
61 | writeb(val, addr: ptr); |
62 | } |
63 | |
64 | static inline unsigned char nsp32_mmio_read1(unsigned long base, |
65 | unsigned int index) |
66 | { |
67 | volatile unsigned char *ptr; |
68 | |
69 | ptr = (unsigned char *)(base + NSP32_MMIO_OFFSET + index); |
70 | |
71 | return readb(addr: ptr); |
72 | } |
73 | |
74 | static inline void nsp32_mmio_write2(unsigned long base, |
75 | unsigned int index, |
76 | unsigned short val) |
77 | { |
78 | volatile unsigned short *ptr; |
79 | |
80 | ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + index); |
81 | |
82 | writew(cpu_to_le16(val), addr: ptr); |
83 | } |
84 | |
85 | static inline unsigned short nsp32_mmio_read2(unsigned long base, |
86 | unsigned int index) |
87 | { |
88 | volatile unsigned short *ptr; |
89 | |
90 | ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + index); |
91 | |
92 | return le16_to_cpu(readw(ptr)); |
93 | } |
94 | |
95 | static inline void nsp32_mmio_write4(unsigned long base, |
96 | unsigned int index, |
97 | unsigned long val) |
98 | { |
99 | volatile unsigned long *ptr; |
100 | |
101 | ptr = (unsigned long *)(base + NSP32_MMIO_OFFSET + index); |
102 | |
103 | writel(cpu_to_le32(val), addr: ptr); |
104 | } |
105 | |
106 | static inline unsigned long nsp32_mmio_read4(unsigned long base, |
107 | unsigned int index) |
108 | { |
109 | volatile unsigned long *ptr; |
110 | |
111 | ptr = (unsigned long *)(base + NSP32_MMIO_OFFSET + index); |
112 | |
113 | return le32_to_cpu(readl(ptr)); |
114 | } |
115 | |
116 | /*==============================================*/ |
117 | |
118 | static inline unsigned char nsp32_index_read1(unsigned int base, |
119 | unsigned int reg) |
120 | { |
121 | outb(value: reg, port: base + INDEX_REG); |
122 | return inb(port: base + DATA_REG_LOW); |
123 | } |
124 | |
125 | static inline void nsp32_index_write1(unsigned int base, |
126 | unsigned int reg, |
127 | unsigned char val) |
128 | { |
129 | outb(value: reg, port: base + INDEX_REG ); |
130 | outb(value: val, port: base + DATA_REG_LOW); |
131 | } |
132 | |
133 | static inline unsigned short nsp32_index_read2(unsigned int base, |
134 | unsigned int reg) |
135 | { |
136 | outb(value: reg, port: base + INDEX_REG); |
137 | return inw(port: base + DATA_REG_LOW); |
138 | } |
139 | |
140 | static inline void nsp32_index_write2(unsigned int base, |
141 | unsigned int reg, |
142 | unsigned short val) |
143 | { |
144 | outb(value: reg, port: base + INDEX_REG ); |
145 | outw(value: val, port: base + DATA_REG_LOW); |
146 | } |
147 | |
148 | static inline unsigned long nsp32_index_read4(unsigned int base, |
149 | unsigned int reg) |
150 | { |
151 | unsigned long h,l; |
152 | |
153 | outb(value: reg, port: base + INDEX_REG); |
154 | l = inw(port: base + DATA_REG_LOW); |
155 | h = inw(port: base + DATA_REG_HI ); |
156 | |
157 | return ((h << 16) | l); |
158 | } |
159 | |
160 | static inline void nsp32_index_write4(unsigned int base, |
161 | unsigned int reg, |
162 | unsigned long val) |
163 | { |
164 | unsigned long h,l; |
165 | |
166 | h = (val & 0xffff0000) >> 16; |
167 | l = (val & 0x0000ffff) >> 0; |
168 | |
169 | outb(value: reg, port: base + INDEX_REG ); |
170 | outw(value: l, port: base + DATA_REG_LOW); |
171 | outw(value: h, port: base + DATA_REG_HI ); |
172 | } |
173 | |
174 | /*==============================================*/ |
175 | |
176 | static inline unsigned char nsp32_mmio_index_read1(unsigned long base, |
177 | unsigned int reg) |
178 | { |
179 | volatile unsigned short *index_ptr, *data_ptr; |
180 | |
181 | index_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + INDEX_REG); |
182 | data_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + DATA_REG_LOW); |
183 | |
184 | writeb(val: reg, addr: index_ptr); |
185 | return readb(addr: data_ptr); |
186 | } |
187 | |
188 | static inline void nsp32_mmio_index_write1(unsigned long base, |
189 | unsigned int reg, |
190 | unsigned char val) |
191 | { |
192 | volatile unsigned short *index_ptr, *data_ptr; |
193 | |
194 | index_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + INDEX_REG); |
195 | data_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + DATA_REG_LOW); |
196 | |
197 | writeb(val: reg, addr: index_ptr); |
198 | writeb(val, addr: data_ptr ); |
199 | } |
200 | |
201 | static inline unsigned short nsp32_mmio_index_read2(unsigned long base, |
202 | unsigned int reg) |
203 | { |
204 | volatile unsigned short *index_ptr, *data_ptr; |
205 | |
206 | index_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + INDEX_REG); |
207 | data_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + DATA_REG_LOW); |
208 | |
209 | writeb(val: reg, addr: index_ptr); |
210 | return le16_to_cpu(readw(data_ptr)); |
211 | } |
212 | |
213 | static inline void nsp32_mmio_index_write2(unsigned long base, |
214 | unsigned int reg, |
215 | unsigned short val) |
216 | { |
217 | volatile unsigned short *index_ptr, *data_ptr; |
218 | |
219 | index_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + INDEX_REG); |
220 | data_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + DATA_REG_LOW); |
221 | |
222 | writeb(val: reg, addr: index_ptr); |
223 | writew(cpu_to_le16(val), addr: data_ptr ); |
224 | } |
225 | |
226 | /*==============================================*/ |
227 | |
228 | static inline void nsp32_multi_read4(unsigned int base, |
229 | unsigned int reg, |
230 | void *buf, |
231 | unsigned long count) |
232 | { |
233 | insl(port: base + reg, addr: buf, count); |
234 | } |
235 | |
236 | static inline void nsp32_fifo_read(unsigned int base, |
237 | void *buf, |
238 | unsigned long count) |
239 | { |
240 | nsp32_multi_read4(base, FIFO_DATA_LOW, buf, count); |
241 | } |
242 | |
243 | static inline void nsp32_multi_write4(unsigned int base, |
244 | unsigned int reg, |
245 | void *buf, |
246 | unsigned long count) |
247 | { |
248 | outsl(port: base + reg, addr: buf, count); |
249 | } |
250 | |
251 | static inline void nsp32_fifo_write(unsigned int base, |
252 | void *buf, |
253 | unsigned long count) |
254 | { |
255 | nsp32_multi_write4(base, FIFO_DATA_LOW, buf, count); |
256 | } |
257 | |
258 | #endif /* _NSP32_IO_H */ |
259 | /* end */ |
260 | |