1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | #ifndef __SPI_CAVIUM_H |
3 | #define __SPI_CAVIUM_H |
4 | |
5 | #include <linux/clk.h> |
6 | |
7 | #define OCTEON_SPI_MAX_BYTES 9 |
8 | #define OCTEON_SPI_MAX_CLOCK_HZ 16000000 |
9 | |
10 | struct octeon_spi_regs { |
11 | int config; |
12 | int status; |
13 | int tx; |
14 | int data; |
15 | }; |
16 | |
17 | struct octeon_spi { |
18 | void __iomem *register_base; |
19 | u64 last_cfg; |
20 | u64 cs_enax; |
21 | int sys_freq; |
22 | struct octeon_spi_regs regs; |
23 | struct clk *clk; |
24 | }; |
25 | |
26 | #define OCTEON_SPI_CFG(x) (x->regs.config) |
27 | #define OCTEON_SPI_STS(x) (x->regs.status) |
28 | #define OCTEON_SPI_TX(x) (x->regs.tx) |
29 | #define OCTEON_SPI_DAT0(x) (x->regs.data) |
30 | |
31 | int octeon_spi_transfer_one_message(struct spi_controller *ctlr, |
32 | struct spi_message *msg); |
33 | |
34 | /* MPI register descriptions */ |
35 | |
36 | #define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull)) |
37 | #define CVMX_MPI_DATX(offset) (CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8) |
38 | #define CVMX_MPI_STS (CVMX_ADD_IO_SEG(0x0001070000001008ull)) |
39 | #define CVMX_MPI_TX (CVMX_ADD_IO_SEG(0x0001070000001010ull)) |
40 | |
41 | union cvmx_mpi_cfg { |
42 | uint64_t u64; |
43 | struct cvmx_mpi_cfg_s { |
44 | #ifdef __BIG_ENDIAN_BITFIELD |
45 | uint64_t reserved_29_63:35; |
46 | uint64_t clkdiv:13; |
47 | uint64_t csena3:1; |
48 | uint64_t csena2:1; |
49 | uint64_t csena1:1; |
50 | uint64_t csena0:1; |
51 | uint64_t cslate:1; |
52 | uint64_t tritx:1; |
53 | uint64_t idleclks:2; |
54 | uint64_t cshi:1; |
55 | uint64_t csena:1; |
56 | uint64_t int_ena:1; |
57 | uint64_t lsbfirst:1; |
58 | uint64_t wireor:1; |
59 | uint64_t clk_cont:1; |
60 | uint64_t idlelo:1; |
61 | uint64_t enable:1; |
62 | #else |
63 | uint64_t enable:1; |
64 | uint64_t idlelo:1; |
65 | uint64_t clk_cont:1; |
66 | uint64_t wireor:1; |
67 | uint64_t lsbfirst:1; |
68 | uint64_t int_ena:1; |
69 | uint64_t csena:1; |
70 | uint64_t cshi:1; |
71 | uint64_t idleclks:2; |
72 | uint64_t tritx:1; |
73 | uint64_t cslate:1; |
74 | uint64_t csena0:1; |
75 | uint64_t csena1:1; |
76 | uint64_t csena2:1; |
77 | uint64_t csena3:1; |
78 | uint64_t clkdiv:13; |
79 | uint64_t reserved_29_63:35; |
80 | #endif |
81 | } s; |
82 | struct cvmx_mpi_cfg_cn30xx { |
83 | #ifdef __BIG_ENDIAN_BITFIELD |
84 | uint64_t reserved_29_63:35; |
85 | uint64_t clkdiv:13; |
86 | uint64_t reserved_12_15:4; |
87 | uint64_t cslate:1; |
88 | uint64_t tritx:1; |
89 | uint64_t idleclks:2; |
90 | uint64_t cshi:1; |
91 | uint64_t csena:1; |
92 | uint64_t int_ena:1; |
93 | uint64_t lsbfirst:1; |
94 | uint64_t wireor:1; |
95 | uint64_t clk_cont:1; |
96 | uint64_t idlelo:1; |
97 | uint64_t enable:1; |
98 | #else |
99 | uint64_t enable:1; |
100 | uint64_t idlelo:1; |
101 | uint64_t clk_cont:1; |
102 | uint64_t wireor:1; |
103 | uint64_t lsbfirst:1; |
104 | uint64_t int_ena:1; |
105 | uint64_t csena:1; |
106 | uint64_t cshi:1; |
107 | uint64_t idleclks:2; |
108 | uint64_t tritx:1; |
109 | uint64_t cslate:1; |
110 | uint64_t reserved_12_15:4; |
111 | uint64_t clkdiv:13; |
112 | uint64_t reserved_29_63:35; |
113 | #endif |
114 | } cn30xx; |
115 | struct cvmx_mpi_cfg_cn31xx { |
116 | #ifdef __BIG_ENDIAN_BITFIELD |
117 | uint64_t reserved_29_63:35; |
118 | uint64_t clkdiv:13; |
119 | uint64_t reserved_11_15:5; |
120 | uint64_t tritx:1; |
121 | uint64_t idleclks:2; |
122 | uint64_t cshi:1; |
123 | uint64_t csena:1; |
124 | uint64_t int_ena:1; |
125 | uint64_t lsbfirst:1; |
126 | uint64_t wireor:1; |
127 | uint64_t clk_cont:1; |
128 | uint64_t idlelo:1; |
129 | uint64_t enable:1; |
130 | #else |
131 | uint64_t enable:1; |
132 | uint64_t idlelo:1; |
133 | uint64_t clk_cont:1; |
134 | uint64_t wireor:1; |
135 | uint64_t lsbfirst:1; |
136 | uint64_t int_ena:1; |
137 | uint64_t csena:1; |
138 | uint64_t cshi:1; |
139 | uint64_t idleclks:2; |
140 | uint64_t tritx:1; |
141 | uint64_t reserved_11_15:5; |
142 | uint64_t clkdiv:13; |
143 | uint64_t reserved_29_63:35; |
144 | #endif |
145 | } cn31xx; |
146 | struct cvmx_mpi_cfg_cn30xx cn50xx; |
147 | struct cvmx_mpi_cfg_cn61xx { |
148 | #ifdef __BIG_ENDIAN_BITFIELD |
149 | uint64_t reserved_29_63:35; |
150 | uint64_t clkdiv:13; |
151 | uint64_t reserved_14_15:2; |
152 | uint64_t csena1:1; |
153 | uint64_t csena0:1; |
154 | uint64_t cslate:1; |
155 | uint64_t tritx:1; |
156 | uint64_t idleclks:2; |
157 | uint64_t cshi:1; |
158 | uint64_t reserved_6_6:1; |
159 | uint64_t int_ena:1; |
160 | uint64_t lsbfirst:1; |
161 | uint64_t wireor:1; |
162 | uint64_t clk_cont:1; |
163 | uint64_t idlelo:1; |
164 | uint64_t enable:1; |
165 | #else |
166 | uint64_t enable:1; |
167 | uint64_t idlelo:1; |
168 | uint64_t clk_cont:1; |
169 | uint64_t wireor:1; |
170 | uint64_t lsbfirst:1; |
171 | uint64_t int_ena:1; |
172 | uint64_t reserved_6_6:1; |
173 | uint64_t cshi:1; |
174 | uint64_t idleclks:2; |
175 | uint64_t tritx:1; |
176 | uint64_t cslate:1; |
177 | uint64_t csena0:1; |
178 | uint64_t csena1:1; |
179 | uint64_t reserved_14_15:2; |
180 | uint64_t clkdiv:13; |
181 | uint64_t reserved_29_63:35; |
182 | #endif |
183 | } cn61xx; |
184 | struct cvmx_mpi_cfg_cn66xx { |
185 | #ifdef __BIG_ENDIAN_BITFIELD |
186 | uint64_t reserved_29_63:35; |
187 | uint64_t clkdiv:13; |
188 | uint64_t csena3:1; |
189 | uint64_t csena2:1; |
190 | uint64_t reserved_12_13:2; |
191 | uint64_t cslate:1; |
192 | uint64_t tritx:1; |
193 | uint64_t idleclks:2; |
194 | uint64_t cshi:1; |
195 | uint64_t reserved_6_6:1; |
196 | uint64_t int_ena:1; |
197 | uint64_t lsbfirst:1; |
198 | uint64_t wireor:1; |
199 | uint64_t clk_cont:1; |
200 | uint64_t idlelo:1; |
201 | uint64_t enable:1; |
202 | #else |
203 | uint64_t enable:1; |
204 | uint64_t idlelo:1; |
205 | uint64_t clk_cont:1; |
206 | uint64_t wireor:1; |
207 | uint64_t lsbfirst:1; |
208 | uint64_t int_ena:1; |
209 | uint64_t reserved_6_6:1; |
210 | uint64_t cshi:1; |
211 | uint64_t idleclks:2; |
212 | uint64_t tritx:1; |
213 | uint64_t cslate:1; |
214 | uint64_t reserved_12_13:2; |
215 | uint64_t csena2:1; |
216 | uint64_t csena3:1; |
217 | uint64_t clkdiv:13; |
218 | uint64_t reserved_29_63:35; |
219 | #endif |
220 | } cn66xx; |
221 | struct cvmx_mpi_cfg_cn61xx cnf71xx; |
222 | }; |
223 | |
224 | union cvmx_mpi_datx { |
225 | uint64_t u64; |
226 | struct cvmx_mpi_datx_s { |
227 | #ifdef __BIG_ENDIAN_BITFIELD |
228 | uint64_t reserved_8_63:56; |
229 | uint64_t data:8; |
230 | #else |
231 | uint64_t data:8; |
232 | uint64_t reserved_8_63:56; |
233 | #endif |
234 | } s; |
235 | struct cvmx_mpi_datx_s cn30xx; |
236 | struct cvmx_mpi_datx_s cn31xx; |
237 | struct cvmx_mpi_datx_s cn50xx; |
238 | struct cvmx_mpi_datx_s cn61xx; |
239 | struct cvmx_mpi_datx_s cn66xx; |
240 | struct cvmx_mpi_datx_s cnf71xx; |
241 | }; |
242 | |
243 | union cvmx_mpi_sts { |
244 | uint64_t u64; |
245 | struct cvmx_mpi_sts_s { |
246 | #ifdef __BIG_ENDIAN_BITFIELD |
247 | uint64_t reserved_13_63:51; |
248 | uint64_t rxnum:5; |
249 | uint64_t reserved_1_7:7; |
250 | uint64_t busy:1; |
251 | #else |
252 | uint64_t busy:1; |
253 | uint64_t reserved_1_7:7; |
254 | uint64_t rxnum:5; |
255 | uint64_t reserved_13_63:51; |
256 | #endif |
257 | } s; |
258 | struct cvmx_mpi_sts_s cn30xx; |
259 | struct cvmx_mpi_sts_s cn31xx; |
260 | struct cvmx_mpi_sts_s cn50xx; |
261 | struct cvmx_mpi_sts_s cn61xx; |
262 | struct cvmx_mpi_sts_s cn66xx; |
263 | struct cvmx_mpi_sts_s cnf71xx; |
264 | }; |
265 | |
266 | union cvmx_mpi_tx { |
267 | uint64_t u64; |
268 | struct cvmx_mpi_tx_s { |
269 | #ifdef __BIG_ENDIAN_BITFIELD |
270 | uint64_t reserved_22_63:42; |
271 | uint64_t csid:2; |
272 | uint64_t reserved_17_19:3; |
273 | uint64_t leavecs:1; |
274 | uint64_t reserved_13_15:3; |
275 | uint64_t txnum:5; |
276 | uint64_t reserved_5_7:3; |
277 | uint64_t totnum:5; |
278 | #else |
279 | uint64_t totnum:5; |
280 | uint64_t reserved_5_7:3; |
281 | uint64_t txnum:5; |
282 | uint64_t reserved_13_15:3; |
283 | uint64_t leavecs:1; |
284 | uint64_t reserved_17_19:3; |
285 | uint64_t csid:2; |
286 | uint64_t reserved_22_63:42; |
287 | #endif |
288 | } s; |
289 | struct cvmx_mpi_tx_cn30xx { |
290 | #ifdef __BIG_ENDIAN_BITFIELD |
291 | uint64_t reserved_17_63:47; |
292 | uint64_t leavecs:1; |
293 | uint64_t reserved_13_15:3; |
294 | uint64_t txnum:5; |
295 | uint64_t reserved_5_7:3; |
296 | uint64_t totnum:5; |
297 | #else |
298 | uint64_t totnum:5; |
299 | uint64_t reserved_5_7:3; |
300 | uint64_t txnum:5; |
301 | uint64_t reserved_13_15:3; |
302 | uint64_t leavecs:1; |
303 | uint64_t reserved_17_63:47; |
304 | #endif |
305 | } cn30xx; |
306 | struct cvmx_mpi_tx_cn30xx cn31xx; |
307 | struct cvmx_mpi_tx_cn30xx cn50xx; |
308 | struct cvmx_mpi_tx_cn61xx { |
309 | #ifdef __BIG_ENDIAN_BITFIELD |
310 | uint64_t reserved_21_63:43; |
311 | uint64_t csid:1; |
312 | uint64_t reserved_17_19:3; |
313 | uint64_t leavecs:1; |
314 | uint64_t reserved_13_15:3; |
315 | uint64_t txnum:5; |
316 | uint64_t reserved_5_7:3; |
317 | uint64_t totnum:5; |
318 | #else |
319 | uint64_t totnum:5; |
320 | uint64_t reserved_5_7:3; |
321 | uint64_t txnum:5; |
322 | uint64_t reserved_13_15:3; |
323 | uint64_t leavecs:1; |
324 | uint64_t reserved_17_19:3; |
325 | uint64_t csid:1; |
326 | uint64_t reserved_21_63:43; |
327 | #endif |
328 | } cn61xx; |
329 | struct cvmx_mpi_tx_s cn66xx; |
330 | struct cvmx_mpi_tx_cn61xx cnf71xx; |
331 | }; |
332 | |
333 | #endif /* __SPI_CAVIUM_H */ |
334 | |