1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | #ifndef __LINUX_FOTG210_H |
3 | #define __LINUX_FOTG210_H |
4 | |
5 | #include <linux/usb/ehci-dbgp.h> |
6 | |
7 | /* definitions used for the EHCI driver */ |
8 | |
9 | /* |
10 | * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to |
11 | * __leXX (normally) or __beXX (given FOTG210_BIG_ENDIAN_DESC), depending on |
12 | * the host controller implementation. |
13 | * |
14 | * To facilitate the strongest possible byte-order checking from "sparse" |
15 | * and so on, we use __leXX unless that's not practical. |
16 | */ |
17 | #define __hc32 __le32 |
18 | #define __hc16 __le16 |
19 | |
20 | /* statistics can be kept for tuning/monitoring */ |
21 | struct fotg210_stats { |
22 | /* irq usage */ |
23 | unsigned long normal; |
24 | unsigned long error; |
25 | unsigned long iaa; |
26 | unsigned long lost_iaa; |
27 | |
28 | /* termination of urbs from core */ |
29 | unsigned long complete; |
30 | unsigned long unlink; |
31 | }; |
32 | |
33 | /* fotg210_hcd->lock guards shared data against other CPUs: |
34 | * fotg210_hcd: async, unlink, periodic (and shadow), ... |
35 | * usb_host_endpoint: hcpriv |
36 | * fotg210_qh: qh_next, qtd_list |
37 | * fotg210_qtd: qtd_list |
38 | * |
39 | * Also, hold this lock when talking to HC registers or |
40 | * when updating hw_* fields in shared qh/qtd/... structures. |
41 | */ |
42 | |
43 | #define FOTG210_MAX_ROOT_PORTS 1 /* see HCS_N_PORTS */ |
44 | |
45 | /* |
46 | * fotg210_rh_state values of FOTG210_RH_RUNNING or above mean that the |
47 | * controller may be doing DMA. Lower values mean there's no DMA. |
48 | */ |
49 | enum fotg210_rh_state { |
50 | FOTG210_RH_HALTED, |
51 | FOTG210_RH_SUSPENDED, |
52 | FOTG210_RH_RUNNING, |
53 | FOTG210_RH_STOPPING |
54 | }; |
55 | |
56 | /* |
57 | * Timer events, ordered by increasing delay length. |
58 | * Always update event_delays_ns[] and event_handlers[] (defined in |
59 | * ehci-timer.c) in parallel with this list. |
60 | */ |
61 | enum fotg210_hrtimer_event { |
62 | FOTG210_HRTIMER_POLL_ASS, /* Poll for async schedule off */ |
63 | FOTG210_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */ |
64 | FOTG210_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */ |
65 | FOTG210_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */ |
66 | FOTG210_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */ |
67 | FOTG210_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */ |
68 | FOTG210_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */ |
69 | FOTG210_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */ |
70 | FOTG210_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */ |
71 | FOTG210_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */ |
72 | FOTG210_HRTIMER_NUM_EVENTS /* Must come last */ |
73 | }; |
74 | #define FOTG210_HRTIMER_NO_EVENT 99 |
75 | |
76 | struct fotg210_hcd { /* one per controller */ |
77 | /* timing support */ |
78 | enum fotg210_hrtimer_event next_hrtimer_event; |
79 | unsigned enabled_hrtimer_events; |
80 | ktime_t hr_timeouts[FOTG210_HRTIMER_NUM_EVENTS]; |
81 | struct hrtimer hrtimer; |
82 | |
83 | int PSS_poll_count; |
84 | int ASS_poll_count; |
85 | int died_poll_count; |
86 | |
87 | /* glue to PCI and HCD framework */ |
88 | struct fotg210_caps __iomem *caps; |
89 | struct fotg210_regs __iomem *regs; |
90 | struct ehci_dbg_port __iomem *debug; |
91 | |
92 | __u32 hcs_params; /* cached register copy */ |
93 | spinlock_t lock; |
94 | enum fotg210_rh_state rh_state; |
95 | |
96 | /* general schedule support */ |
97 | bool scanning:1; |
98 | bool need_rescan:1; |
99 | bool intr_unlinking:1; |
100 | bool async_unlinking:1; |
101 | bool shutdown:1; |
102 | struct fotg210_qh *qh_scan_next; |
103 | |
104 | /* async schedule support */ |
105 | struct fotg210_qh *async; |
106 | struct fotg210_qh *dummy; /* For AMD quirk use */ |
107 | struct fotg210_qh *async_unlink; |
108 | struct fotg210_qh *async_unlink_last; |
109 | struct fotg210_qh *async_iaa; |
110 | unsigned async_unlink_cycle; |
111 | unsigned async_count; /* async activity count */ |
112 | |
113 | /* periodic schedule support */ |
114 | #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ |
115 | unsigned periodic_size; |
116 | __hc32 *periodic; /* hw periodic table */ |
117 | dma_addr_t periodic_dma; |
118 | struct list_head intr_qh_list; |
119 | unsigned i_thresh; /* uframes HC might cache */ |
120 | |
121 | union fotg210_shadow *pshadow; /* mirror hw periodic table */ |
122 | struct fotg210_qh *intr_unlink; |
123 | struct fotg210_qh *intr_unlink_last; |
124 | unsigned intr_unlink_cycle; |
125 | unsigned now_frame; /* frame from HC hardware */ |
126 | unsigned next_frame; /* scan periodic, start here */ |
127 | unsigned intr_count; /* intr activity count */ |
128 | unsigned isoc_count; /* isoc activity count */ |
129 | unsigned periodic_count; /* periodic activity count */ |
130 | /* max periodic time per uframe */ |
131 | unsigned uframe_periodic_max; |
132 | |
133 | |
134 | /* list of itds completed while now_frame was still active */ |
135 | struct list_head cached_itd_list; |
136 | struct fotg210_itd *last_itd_to_free; |
137 | |
138 | /* per root hub port */ |
139 | unsigned long reset_done[FOTG210_MAX_ROOT_PORTS]; |
140 | |
141 | /* bit vectors (one bit per port) |
142 | * which ports were already suspended at the start of a bus suspend |
143 | */ |
144 | unsigned long bus_suspended; |
145 | |
146 | /* which ports are edicated to the companion controller */ |
147 | unsigned long companion_ports; |
148 | |
149 | /* which ports are owned by the companion during a bus suspend */ |
150 | unsigned long owned_ports; |
151 | |
152 | /* which ports have the change-suspend feature turned on */ |
153 | unsigned long port_c_suspend; |
154 | |
155 | /* which ports are suspended */ |
156 | unsigned long suspended_ports; |
157 | |
158 | /* which ports have started to resume */ |
159 | unsigned long resuming_ports; |
160 | |
161 | /* per-HC memory pools (could be per-bus, but ...) */ |
162 | struct dma_pool *qh_pool; /* qh per active urb */ |
163 | struct dma_pool *qtd_pool; /* one or more per qh */ |
164 | struct dma_pool *itd_pool; /* itd per iso urb */ |
165 | |
166 | unsigned random_frame; |
167 | unsigned long next_statechange; |
168 | ktime_t last_periodic_enable; |
169 | u32 command; |
170 | |
171 | /* SILICON QUIRKS */ |
172 | unsigned need_io_watchdog:1; |
173 | unsigned fs_i_thresh:1; /* Intel iso scheduling */ |
174 | |
175 | u8 sbrn; /* packed release number */ |
176 | |
177 | /* irq statistics */ |
178 | #ifdef FOTG210_STATS |
179 | struct fotg210_stats stats; |
180 | # define INCR(x) ((x)++) |
181 | #else |
182 | # define INCR(x) do {} while (0) |
183 | #endif |
184 | |
185 | struct fotg210 *fotg; /* Overarching FOTG210 device */ |
186 | /* silicon clock */ |
187 | struct clk *pclk; |
188 | }; |
189 | |
190 | /* convert between an HCD pointer and the corresponding FOTG210_HCD */ |
191 | static inline struct fotg210_hcd *hcd_to_fotg210(struct usb_hcd *hcd) |
192 | { |
193 | return (struct fotg210_hcd *)(hcd->hcd_priv); |
194 | } |
195 | static inline struct usb_hcd *fotg210_to_hcd(struct fotg210_hcd *fotg210) |
196 | { |
197 | return container_of((void *) fotg210, struct usb_hcd, hcd_priv); |
198 | } |
199 | |
200 | /*-------------------------------------------------------------------------*/ |
201 | |
202 | /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ |
203 | |
204 | /* Section 2.2 Host Controller Capability Registers */ |
205 | struct fotg210_caps { |
206 | /* these fields are specified as 8 and 16 bit registers, |
207 | * but some hosts can't perform 8 or 16 bit PCI accesses. |
208 | * some hosts treat caplength and hciversion as parts of a 32-bit |
209 | * register, others treat them as two separate registers, this |
210 | * affects the memory map for big endian controllers. |
211 | */ |
212 | u32 hc_capbase; |
213 | #define HC_LENGTH(fotg210, p) (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \ |
214 | (fotg210_big_endian_capbase(fotg210) ? 24 : 0))) |
215 | #define HC_VERSION(fotg210, p) (0xffff&((p) >> /* bits 31:16 / offset 02h */ \ |
216 | (fotg210_big_endian_capbase(fotg210) ? 0 : 16))) |
217 | u32 hcs_params; /* HCSPARAMS - offset 0x4 */ |
218 | #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ |
219 | |
220 | u32 hcc_params; /* HCCPARAMS - offset 0x8 */ |
221 | #define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */ |
222 | #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/ |
223 | u8 portroute[8]; /* nibbles for routing - offset 0xC */ |
224 | }; |
225 | |
226 | |
227 | /* Section 2.3 Host Controller Operational Registers */ |
228 | struct fotg210_regs { |
229 | |
230 | /* USBCMD: offset 0x00 */ |
231 | u32 command; |
232 | |
233 | /* EHCI 1.1 addendum */ |
234 | /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */ |
235 | #define CMD_PARK (1<<11) /* enable "park" on async qh */ |
236 | #define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */ |
237 | #define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */ |
238 | #define CMD_ASE (1<<5) /* async schedule enable */ |
239 | #define CMD_PSE (1<<4) /* periodic schedule enable */ |
240 | /* 3:2 is periodic frame list size */ |
241 | #define CMD_RESET (1<<1) /* reset HC not bus */ |
242 | #define CMD_RUN (1<<0) /* start/stop HC */ |
243 | |
244 | /* USBSTS: offset 0x04 */ |
245 | u32 status; |
246 | #define STS_ASS (1<<15) /* Async Schedule Status */ |
247 | #define STS_PSS (1<<14) /* Periodic Schedule Status */ |
248 | #define STS_RECL (1<<13) /* Reclamation */ |
249 | #define STS_HALT (1<<12) /* Not running (any reason) */ |
250 | /* some bits reserved */ |
251 | /* these STS_* flags are also intr_enable bits (USBINTR) */ |
252 | #define STS_IAA (1<<5) /* Interrupted on async advance */ |
253 | #define STS_FATAL (1<<4) /* such as some PCI access errors */ |
254 | #define STS_FLR (1<<3) /* frame list rolled over */ |
255 | #define STS_PCD (1<<2) /* port change detect */ |
256 | #define STS_ERR (1<<1) /* "error" completion (overflow, ...) */ |
257 | #define STS_INT (1<<0) /* "normal" completion (short, ...) */ |
258 | |
259 | /* USBINTR: offset 0x08 */ |
260 | u32 intr_enable; |
261 | |
262 | /* FRINDEX: offset 0x0C */ |
263 | u32 frame_index; /* current microframe number */ |
264 | /* CTRLDSSEGMENT: offset 0x10 */ |
265 | u32 segment; /* address bits 63:32 if needed */ |
266 | /* PERIODICLISTBASE: offset 0x14 */ |
267 | u32 frame_list; /* points to periodic list */ |
268 | /* ASYNCLISTADDR: offset 0x18 */ |
269 | u32 async_next; /* address of next async queue head */ |
270 | |
271 | u32 reserved1; |
272 | /* PORTSC: offset 0x20 */ |
273 | u32 port_status; |
274 | /* 31:23 reserved */ |
275 | #define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */ |
276 | #define PORT_RESET (1<<8) /* reset port */ |
277 | #define PORT_SUSPEND (1<<7) /* suspend port */ |
278 | #define PORT_RESUME (1<<6) /* resume it */ |
279 | #define PORT_PEC (1<<3) /* port enable change */ |
280 | #define PORT_PE (1<<2) /* port enable */ |
281 | #define PORT_CSC (1<<1) /* connect status change */ |
282 | #define PORT_CONNECT (1<<0) /* device connected */ |
283 | #define PORT_RWC_BITS (PORT_CSC | PORT_PEC) |
284 | u32 reserved2[19]; |
285 | |
286 | /* OTGCSR: offet 0x70 */ |
287 | u32 otgcsr; |
288 | #define OTGCSR_HOST_SPD_TYP (3 << 22) |
289 | #define OTGCSR_A_BUS_DROP (1 << 5) |
290 | #define OTGCSR_A_BUS_REQ (1 << 4) |
291 | |
292 | /* OTGISR: offset 0x74 */ |
293 | u32 otgisr; |
294 | #define OTGISR_OVC (1 << 10) |
295 | |
296 | u32 reserved3[15]; |
297 | |
298 | /* GMIR: offset 0xB4 */ |
299 | u32 gmir; |
300 | #define GMIR_INT_POLARITY (1 << 3) /*Active High*/ |
301 | #define GMIR_MHC_INT (1 << 2) |
302 | #define GMIR_MOTG_INT (1 << 1) |
303 | #define GMIR_MDEV_INT (1 << 0) |
304 | }; |
305 | |
306 | /*-------------------------------------------------------------------------*/ |
307 | |
308 | #define QTD_NEXT(fotg210, dma) cpu_to_hc32(fotg210, (u32)dma) |
309 | |
310 | /* |
311 | * EHCI Specification 0.95 Section 3.5 |
312 | * QTD: describe data transfer components (buffer, direction, ...) |
313 | * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". |
314 | * |
315 | * These are associated only with "QH" (Queue Head) structures, |
316 | * used with control, bulk, and interrupt transfers. |
317 | */ |
318 | struct fotg210_qtd { |
319 | /* first part defined by EHCI spec */ |
320 | __hc32 hw_next; /* see EHCI 3.5.1 */ |
321 | __hc32 hw_alt_next; /* see EHCI 3.5.2 */ |
322 | __hc32 hw_token; /* see EHCI 3.5.3 */ |
323 | #define QTD_TOGGLE (1 << 31) /* data toggle */ |
324 | #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) |
325 | #define QTD_IOC (1 << 15) /* interrupt on complete */ |
326 | #define QTD_CERR(tok) (((tok)>>10) & 0x3) |
327 | #define QTD_PID(tok) (((tok)>>8) & 0x3) |
328 | #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ |
329 | #define QTD_STS_HALT (1 << 6) /* halted on error */ |
330 | #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ |
331 | #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ |
332 | #define QTD_STS_XACT (1 << 3) /* device gave illegal response */ |
333 | #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ |
334 | #define QTD_STS_STS (1 << 1) /* split transaction state */ |
335 | #define QTD_STS_PING (1 << 0) /* issue PING? */ |
336 | |
337 | #define ACTIVE_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_ACTIVE) |
338 | #define HALT_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_HALT) |
339 | #define STATUS_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_STS) |
340 | |
341 | __hc32 hw_buf[5]; /* see EHCI 3.5.4 */ |
342 | __hc32 hw_buf_hi[5]; /* Appendix B */ |
343 | |
344 | /* the rest is HCD-private */ |
345 | dma_addr_t qtd_dma; /* qtd address */ |
346 | struct list_head qtd_list; /* sw qtd list */ |
347 | struct urb *urb; /* qtd's urb */ |
348 | size_t length; /* length of buffer */ |
349 | } __aligned(32); |
350 | |
351 | /* mask NakCnt+T in qh->hw_alt_next */ |
352 | #define QTD_MASK(fotg210) cpu_to_hc32(fotg210, ~0x1f) |
353 | |
354 | #define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1) |
355 | |
356 | /*-------------------------------------------------------------------------*/ |
357 | |
358 | /* type tag from {qh,itd,fstn}->hw_next */ |
359 | #define Q_NEXT_TYPE(fotg210, dma) ((dma) & cpu_to_hc32(fotg210, 3 << 1)) |
360 | |
361 | /* |
362 | * Now the following defines are not converted using the |
363 | * cpu_to_le32() macro anymore, since we have to support |
364 | * "dynamic" switching between be and le support, so that the driver |
365 | * can be used on one system with SoC EHCI controller using big-endian |
366 | * descriptors as well as a normal little-endian PCI EHCI controller. |
367 | */ |
368 | /* values for that type tag */ |
369 | #define Q_TYPE_ITD (0 << 1) |
370 | #define Q_TYPE_QH (1 << 1) |
371 | #define Q_TYPE_SITD (2 << 1) |
372 | #define Q_TYPE_FSTN (3 << 1) |
373 | |
374 | /* next async queue entry, or pointer to interrupt/periodic QH */ |
375 | #define QH_NEXT(fotg210, dma) \ |
376 | (cpu_to_hc32(fotg210, (((u32)dma)&~0x01f)|Q_TYPE_QH)) |
377 | |
378 | /* for periodic/async schedules and qtd lists, mark end of list */ |
379 | #define FOTG210_LIST_END(fotg210) \ |
380 | cpu_to_hc32(fotg210, 1) /* "null pointer" to hw */ |
381 | |
382 | /* |
383 | * Entries in periodic shadow table are pointers to one of four kinds |
384 | * of data structure. That's dictated by the hardware; a type tag is |
385 | * encoded in the low bits of the hardware's periodic schedule. Use |
386 | * Q_NEXT_TYPE to get the tag. |
387 | * |
388 | * For entries in the async schedule, the type tag always says "qh". |
389 | */ |
390 | union fotg210_shadow { |
391 | struct fotg210_qh *qh; /* Q_TYPE_QH */ |
392 | struct fotg210_itd *itd; /* Q_TYPE_ITD */ |
393 | struct fotg210_fstn *fstn; /* Q_TYPE_FSTN */ |
394 | __hc32 *hw_next; /* (all types) */ |
395 | void *ptr; |
396 | }; |
397 | |
398 | /*-------------------------------------------------------------------------*/ |
399 | |
400 | /* |
401 | * EHCI Specification 0.95 Section 3.6 |
402 | * QH: describes control/bulk/interrupt endpoints |
403 | * See Fig 3-7 "Queue Head Structure Layout". |
404 | * |
405 | * These appear in both the async and (for interrupt) periodic schedules. |
406 | */ |
407 | |
408 | /* first part defined by EHCI spec */ |
409 | struct fotg210_qh_hw { |
410 | __hc32 hw_next; /* see EHCI 3.6.1 */ |
411 | __hc32 hw_info1; /* see EHCI 3.6.2 */ |
412 | #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */ |
413 | #define QH_HEAD (1 << 15) /* Head of async reclamation list */ |
414 | #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */ |
415 | #define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */ |
416 | #define QH_LOW_SPEED (1 << 12) |
417 | #define QH_FULL_SPEED (0 << 12) |
418 | #define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */ |
419 | __hc32 hw_info2; /* see EHCI 3.6.2 */ |
420 | #define QH_SMASK 0x000000ff |
421 | #define QH_CMASK 0x0000ff00 |
422 | #define QH_HUBADDR 0x007f0000 |
423 | #define QH_HUBPORT 0x3f800000 |
424 | #define QH_MULT 0xc0000000 |
425 | __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ |
426 | |
427 | /* qtd overlay (hardware parts of a struct fotg210_qtd) */ |
428 | __hc32 hw_qtd_next; |
429 | __hc32 hw_alt_next; |
430 | __hc32 hw_token; |
431 | __hc32 hw_buf[5]; |
432 | __hc32 hw_buf_hi[5]; |
433 | } __aligned(32); |
434 | |
435 | struct fotg210_qh { |
436 | struct fotg210_qh_hw *hw; /* Must come first */ |
437 | /* the rest is HCD-private */ |
438 | dma_addr_t qh_dma; /* address of qh */ |
439 | union fotg210_shadow qh_next; /* ptr to qh; or periodic */ |
440 | struct list_head qtd_list; /* sw qtd list */ |
441 | struct list_head intr_node; /* list of intr QHs */ |
442 | struct fotg210_qtd *dummy; |
443 | struct fotg210_qh *unlink_next; /* next on unlink list */ |
444 | |
445 | unsigned unlink_cycle; |
446 | |
447 | u8 needs_rescan; /* Dequeue during giveback */ |
448 | u8 qh_state; |
449 | #define QH_STATE_LINKED 1 /* HC sees this */ |
450 | #define QH_STATE_UNLINK 2 /* HC may still see this */ |
451 | #define QH_STATE_IDLE 3 /* HC doesn't see this */ |
452 | #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */ |
453 | #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ |
454 | |
455 | u8 xacterrs; /* XactErr retry counter */ |
456 | #define QH_XACTERR_MAX 32 /* XactErr retry limit */ |
457 | |
458 | /* periodic schedule info */ |
459 | u8 usecs; /* intr bandwidth */ |
460 | u8 gap_uf; /* uframes split/csplit gap */ |
461 | u8 c_usecs; /* ... split completion bw */ |
462 | u16 tt_usecs; /* tt downstream bandwidth */ |
463 | unsigned short period; /* polling interval */ |
464 | unsigned short start; /* where polling starts */ |
465 | #define NO_FRAME ((unsigned short)~0) /* pick new start */ |
466 | |
467 | struct usb_device *dev; /* access to TT */ |
468 | unsigned is_out:1; /* bulk or intr OUT */ |
469 | unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ |
470 | }; |
471 | |
472 | /*-------------------------------------------------------------------------*/ |
473 | |
474 | /* description of one iso transaction (up to 3 KB data if highspeed) */ |
475 | struct fotg210_iso_packet { |
476 | /* These will be copied to iTD when scheduling */ |
477 | u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ |
478 | __hc32 transaction; /* itd->hw_transaction[i] |= */ |
479 | u8 cross; /* buf crosses pages */ |
480 | /* for full speed OUT splits */ |
481 | u32 buf1; |
482 | }; |
483 | |
484 | /* temporary schedule data for packets from iso urbs (both speeds) |
485 | * each packet is one logical usb transaction to the device (not TT), |
486 | * beginning at stream->next_uframe |
487 | */ |
488 | struct fotg210_iso_sched { |
489 | struct list_head td_list; |
490 | unsigned span; |
491 | struct fotg210_iso_packet packet[]; |
492 | }; |
493 | |
494 | /* |
495 | * fotg210_iso_stream - groups all (s)itds for this endpoint. |
496 | * acts like a qh would, if EHCI had them for ISO. |
497 | */ |
498 | struct fotg210_iso_stream { |
499 | /* first field matches fotg210_hq, but is NULL */ |
500 | struct fotg210_qh_hw *hw; |
501 | |
502 | u8 bEndpointAddress; |
503 | u8 highspeed; |
504 | struct list_head td_list; /* queued itds */ |
505 | struct list_head free_list; /* list of unused itds */ |
506 | struct usb_device *udev; |
507 | struct usb_host_endpoint *ep; |
508 | |
509 | /* output of (re)scheduling */ |
510 | int next_uframe; |
511 | __hc32 splits; |
512 | |
513 | /* the rest is derived from the endpoint descriptor, |
514 | * trusting urb->interval == f(epdesc->bInterval) and |
515 | * including the extra info for hw_bufp[0..2] |
516 | */ |
517 | u8 usecs, c_usecs; |
518 | u16 interval; |
519 | u16 tt_usecs; |
520 | u16 maxp; |
521 | u16 raw_mask; |
522 | unsigned bandwidth; |
523 | |
524 | /* This is used to initialize iTD's hw_bufp fields */ |
525 | __hc32 buf0; |
526 | __hc32 buf1; |
527 | __hc32 buf2; |
528 | |
529 | /* this is used to initialize sITD's tt info */ |
530 | __hc32 address; |
531 | }; |
532 | |
533 | /*-------------------------------------------------------------------------*/ |
534 | |
535 | /* |
536 | * EHCI Specification 0.95 Section 3.3 |
537 | * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" |
538 | * |
539 | * Schedule records for high speed iso xfers |
540 | */ |
541 | struct fotg210_itd { |
542 | /* first part defined by EHCI spec */ |
543 | __hc32 hw_next; /* see EHCI 3.3.1 */ |
544 | __hc32 hw_transaction[8]; /* see EHCI 3.3.2 */ |
545 | #define FOTG210_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ |
546 | #define FOTG210_ISOC_BUF_ERR (1<<30) /* Data buffer error */ |
547 | #define FOTG210_ISOC_BABBLE (1<<29) /* babble detected */ |
548 | #define FOTG210_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ |
549 | #define FOTG210_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) |
550 | #define FOTG210_ITD_IOC (1 << 15) /* interrupt on complete */ |
551 | |
552 | #define ITD_ACTIVE(fotg210) cpu_to_hc32(fotg210, FOTG210_ISOC_ACTIVE) |
553 | |
554 | __hc32 hw_bufp[7]; /* see EHCI 3.3.3 */ |
555 | __hc32 hw_bufp_hi[7]; /* Appendix B */ |
556 | |
557 | /* the rest is HCD-private */ |
558 | dma_addr_t itd_dma; /* for this itd */ |
559 | union fotg210_shadow itd_next; /* ptr to periodic q entry */ |
560 | |
561 | struct urb *urb; |
562 | struct fotg210_iso_stream *stream; /* endpoint's queue */ |
563 | struct list_head itd_list; /* list of stream's itds */ |
564 | |
565 | /* any/all hw_transactions here may be used by that urb */ |
566 | unsigned frame; /* where scheduled */ |
567 | unsigned pg; |
568 | unsigned index[8]; /* in urb->iso_frame_desc */ |
569 | } __aligned(32); |
570 | |
571 | /*-------------------------------------------------------------------------*/ |
572 | |
573 | /* |
574 | * EHCI Specification 0.96 Section 3.7 |
575 | * Periodic Frame Span Traversal Node (FSTN) |
576 | * |
577 | * Manages split interrupt transactions (using TT) that span frame boundaries |
578 | * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN |
579 | * makes the HC jump (back) to a QH to scan for fs/ls QH completions until |
580 | * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. |
581 | */ |
582 | struct fotg210_fstn { |
583 | __hc32 hw_next; /* any periodic q entry */ |
584 | __hc32 hw_prev; /* qh or FOTG210_LIST_END */ |
585 | |
586 | /* the rest is HCD-private */ |
587 | dma_addr_t fstn_dma; |
588 | union fotg210_shadow fstn_next; /* ptr to periodic q entry */ |
589 | } __aligned(32); |
590 | |
591 | /*-------------------------------------------------------------------------*/ |
592 | |
593 | /* Prepare the PORTSC wakeup flags during controller suspend/resume */ |
594 | |
595 | #define fotg210_prepare_ports_for_controller_suspend(fotg210, do_wakeup) \ |
596 | fotg210_adjust_port_wakeup_flags(fotg210, true, do_wakeup) |
597 | |
598 | #define fotg210_prepare_ports_for_controller_resume(fotg210) \ |
599 | fotg210_adjust_port_wakeup_flags(fotg210, false, false) |
600 | |
601 | /*-------------------------------------------------------------------------*/ |
602 | |
603 | /* |
604 | * Some EHCI controllers have a Transaction Translator built into the |
605 | * root hub. This is a non-standard feature. Each controller will need |
606 | * to add code to the following inline functions, and call them as |
607 | * needed (mostly in root hub code). |
608 | */ |
609 | |
610 | static inline unsigned int |
611 | fotg210_get_speed(struct fotg210_hcd *fotg210, unsigned int portsc) |
612 | { |
613 | return (readl(addr: &fotg210->regs->otgcsr) |
614 | & OTGCSR_HOST_SPD_TYP) >> 22; |
615 | } |
616 | |
617 | /* Returns the speed of a device attached to a port on the root hub. */ |
618 | static inline unsigned int |
619 | fotg210_port_speed(struct fotg210_hcd *fotg210, unsigned int portsc) |
620 | { |
621 | switch (fotg210_get_speed(fotg210, portsc)) { |
622 | case 0: |
623 | return 0; |
624 | case 1: |
625 | return USB_PORT_STAT_LOW_SPEED; |
626 | case 2: |
627 | default: |
628 | return USB_PORT_STAT_HIGH_SPEED; |
629 | } |
630 | } |
631 | |
632 | /*-------------------------------------------------------------------------*/ |
633 | |
634 | #define fotg210_has_fsl_portno_bug(e) (0) |
635 | |
636 | /* |
637 | * While most USB host controllers implement their registers in |
638 | * little-endian format, a minority (celleb companion chip) implement |
639 | * them in big endian format. |
640 | * |
641 | * This attempts to support either format at compile time without a |
642 | * runtime penalty, or both formats with the additional overhead |
643 | * of checking a flag bit. |
644 | * |
645 | */ |
646 | |
647 | #define fotg210_big_endian_mmio(e) 0 |
648 | #define fotg210_big_endian_capbase(e) 0 |
649 | |
650 | static inline unsigned int fotg210_readl(const struct fotg210_hcd *fotg210, |
651 | __u32 __iomem *regs) |
652 | { |
653 | return readl(addr: regs); |
654 | } |
655 | |
656 | static inline void fotg210_writel(const struct fotg210_hcd *fotg210, |
657 | const unsigned int val, __u32 __iomem *regs) |
658 | { |
659 | writel(val, addr: regs); |
660 | } |
661 | |
662 | /* cpu to fotg210 */ |
663 | static inline __hc32 cpu_to_hc32(const struct fotg210_hcd *fotg210, const u32 x) |
664 | { |
665 | return cpu_to_le32(x); |
666 | } |
667 | |
668 | /* fotg210 to cpu */ |
669 | static inline u32 hc32_to_cpu(const struct fotg210_hcd *fotg210, const __hc32 x) |
670 | { |
671 | return le32_to_cpu(x); |
672 | } |
673 | |
674 | static inline u32 hc32_to_cpup(const struct fotg210_hcd *fotg210, |
675 | const __hc32 *x) |
676 | { |
677 | return le32_to_cpup(p: x); |
678 | } |
679 | |
680 | /*-------------------------------------------------------------------------*/ |
681 | |
682 | static inline unsigned fotg210_read_frame_index(struct fotg210_hcd *fotg210) |
683 | { |
684 | return fotg210_readl(fotg210, regs: &fotg210->regs->frame_index); |
685 | } |
686 | |
687 | /*-------------------------------------------------------------------------*/ |
688 | |
689 | #endif /* __LINUX_FOTG210_H */ |
690 | |