1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | |
3 | /* |
4 | * xHCI host controller driver |
5 | * |
6 | * Copyright (C) 2008 Intel Corp. |
7 | * |
8 | * Author: Sarah Sharp |
9 | * Some code borrowed from the Linux EHCI driver. |
10 | */ |
11 | |
12 | #ifndef __LINUX_XHCI_HCD_H |
13 | #define __LINUX_XHCI_HCD_H |
14 | |
15 | #include <linux/usb.h> |
16 | #include <linux/timer.h> |
17 | #include <linux/kernel.h> |
18 | #include <linux/usb/hcd.h> |
19 | #include <linux/io-64-nonatomic-lo-hi.h> |
20 | |
21 | /* Code sharing between pci-quirks and xhci hcd */ |
22 | #include "xhci-ext-caps.h" |
23 | #include "pci-quirks.h" |
24 | |
25 | #include "xhci-port.h" |
26 | #include "xhci-caps.h" |
27 | |
28 | /* max buffer size for trace and debug messages */ |
29 | #define XHCI_MSG_MAX 500 |
30 | |
31 | /* xHCI PCI Configuration Registers */ |
32 | #define XHCI_SBRN_OFFSET (0x60) |
33 | |
34 | /* Max number of USB devices for any host controller - limit in section 6.1 */ |
35 | #define MAX_HC_SLOTS 256 |
36 | /* Section 5.3.3 - MaxPorts */ |
37 | #define MAX_HC_PORTS 127 |
38 | |
39 | /* |
40 | * xHCI register interface. |
41 | * This corresponds to the eXtensible Host Controller Interface (xHCI) |
42 | * Revision 0.95 specification |
43 | */ |
44 | |
45 | /** |
46 | * struct xhci_cap_regs - xHCI Host Controller Capability Registers. |
47 | * @hc_capbase: length of the capabilities register and HC version number |
48 | * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 |
49 | * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 |
50 | * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 |
51 | * @hcc_params: HCCPARAMS - Capability Parameters |
52 | * @db_off: DBOFF - Doorbell array offset |
53 | * @run_regs_off: RTSOFF - Runtime register space offset |
54 | * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only |
55 | */ |
56 | struct xhci_cap_regs { |
57 | __le32 hc_capbase; |
58 | __le32 hcs_params1; |
59 | __le32 hcs_params2; |
60 | __le32 hcs_params3; |
61 | __le32 hcc_params; |
62 | __le32 db_off; |
63 | __le32 run_regs_off; |
64 | __le32 hcc_params2; /* xhci 1.1 */ |
65 | /* Reserved up to (CAPLENGTH - 0x1C) */ |
66 | }; |
67 | |
68 | /* Number of registers per port */ |
69 | #define NUM_PORT_REGS 4 |
70 | |
71 | #define PORTSC 0 |
72 | #define PORTPMSC 1 |
73 | #define PORTLI 2 |
74 | #define PORTHLPMC 3 |
75 | |
76 | /** |
77 | * struct xhci_op_regs - xHCI Host Controller Operational Registers. |
78 | * @command: USBCMD - xHC command register |
79 | * @status: USBSTS - xHC status register |
80 | * @page_size: This indicates the page size that the host controller |
81 | * supports. If bit n is set, the HC supports a page size |
82 | * of 2^(n+12), up to a 128MB page size. |
83 | * 4K is the minimum page size. |
84 | * @cmd_ring: CRP - 64-bit Command Ring Pointer |
85 | * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer |
86 | * @config_reg: CONFIG - Configure Register |
87 | * @port_status_base: PORTSCn - base address for Port Status and Control |
88 | * Each port has a Port Status and Control register, |
89 | * followed by a Port Power Management Status and Control |
90 | * register, a Port Link Info register, and a reserved |
91 | * register. |
92 | * @port_power_base: PORTPMSCn - base address for |
93 | * Port Power Management Status and Control |
94 | * @port_link_base: PORTLIn - base address for Port Link Info (current |
95 | * Link PM state and control) for USB 2.1 and USB 3.0 |
96 | * devices. |
97 | */ |
98 | struct xhci_op_regs { |
99 | __le32 command; |
100 | __le32 status; |
101 | __le32 page_size; |
102 | __le32 reserved1; |
103 | __le32 reserved2; |
104 | __le32 dev_notification; |
105 | __le64 cmd_ring; |
106 | /* rsvd: offset 0x20-2F */ |
107 | __le32 reserved3[4]; |
108 | __le64 dcbaa_ptr; |
109 | __le32 config_reg; |
110 | /* rsvd: offset 0x3C-3FF */ |
111 | __le32 reserved4[241]; |
112 | /* port 1 registers, which serve as a base address for other ports */ |
113 | __le32 port_status_base; |
114 | __le32 port_power_base; |
115 | __le32 port_link_base; |
116 | __le32 reserved5; |
117 | /* registers for ports 2-255 */ |
118 | __le32 reserved6[NUM_PORT_REGS*254]; |
119 | }; |
120 | |
121 | /* USBCMD - USB command - command bitmasks */ |
122 | /* start/stop HC execution - do not write unless HC is halted*/ |
123 | #define CMD_RUN XHCI_CMD_RUN |
124 | /* Reset HC - resets internal HC state machine and all registers (except |
125 | * PCI config regs). HC does NOT drive a USB reset on the downstream ports. |
126 | * The xHCI driver must reinitialize the xHC after setting this bit. |
127 | */ |
128 | #define CMD_RESET (1 << 1) |
129 | /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ |
130 | #define CMD_EIE XHCI_CMD_EIE |
131 | /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ |
132 | #define CMD_HSEIE XHCI_CMD_HSEIE |
133 | /* bits 4:6 are reserved (and should be preserved on writes). */ |
134 | /* light reset (port status stays unchanged) - reset completed when this is 0 */ |
135 | #define CMD_LRESET (1 << 7) |
136 | /* host controller save/restore state. */ |
137 | #define CMD_CSS (1 << 8) |
138 | #define CMD_CRS (1 << 9) |
139 | /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ |
140 | #define CMD_EWE XHCI_CMD_EWE |
141 | /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root |
142 | * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. |
143 | * '0' means the xHC can power it off if all ports are in the disconnect, |
144 | * disabled, or powered-off state. |
145 | */ |
146 | #define CMD_PM_INDEX (1 << 11) |
147 | /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */ |
148 | #define CMD_ETE (1 << 14) |
149 | /* bits 15:31 are reserved (and should be preserved on writes). */ |
150 | |
151 | #define XHCI_RESET_LONG_USEC (10 * 1000 * 1000) |
152 | #define XHCI_RESET_SHORT_USEC (250 * 1000) |
153 | |
154 | /* IMAN - Interrupt Management Register */ |
155 | #define IMAN_IE (1 << 1) |
156 | #define IMAN_IP (1 << 0) |
157 | |
158 | /* USBSTS - USB status - status bitmasks */ |
159 | /* HC not running - set to 1 when run/stop bit is cleared. */ |
160 | #define STS_HALT XHCI_STS_HALT |
161 | /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ |
162 | #define STS_FATAL (1 << 2) |
163 | /* event interrupt - clear this prior to clearing any IP flags in IR set*/ |
164 | #define STS_EINT (1 << 3) |
165 | /* port change detect */ |
166 | #define STS_PORT (1 << 4) |
167 | /* bits 5:7 reserved and zeroed */ |
168 | /* save state status - '1' means xHC is saving state */ |
169 | #define STS_SAVE (1 << 8) |
170 | /* restore state status - '1' means xHC is restoring state */ |
171 | #define STS_RESTORE (1 << 9) |
172 | /* true: save or restore error */ |
173 | #define STS_SRE (1 << 10) |
174 | /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ |
175 | #define STS_CNR XHCI_STS_CNR |
176 | /* true: internal Host Controller Error - SW needs to reset and reinitialize */ |
177 | #define STS_HCE (1 << 12) |
178 | /* bits 13:31 reserved and should be preserved */ |
179 | |
180 | /* |
181 | * DNCTRL - Device Notification Control Register - dev_notification bitmasks |
182 | * Generate a device notification event when the HC sees a transaction with a |
183 | * notification type that matches a bit set in this bit field. |
184 | */ |
185 | #define DEV_NOTE_MASK (0xffff) |
186 | #define ENABLE_DEV_NOTE(x) (1 << (x)) |
187 | /* Most of the device notification types should only be used for debug. |
188 | * SW does need to pay attention to function wake notifications. |
189 | */ |
190 | #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) |
191 | |
192 | /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ |
193 | /* bit 0 is the command ring cycle state */ |
194 | /* stop ring operation after completion of the currently executing command */ |
195 | #define CMD_RING_PAUSE (1 << 1) |
196 | /* stop ring immediately - abort the currently executing command */ |
197 | #define CMD_RING_ABORT (1 << 2) |
198 | /* true: command ring is running */ |
199 | #define CMD_RING_RUNNING (1 << 3) |
200 | /* bits 4:5 reserved and should be preserved */ |
201 | /* Command Ring pointer - bit mask for the lower 32 bits. */ |
202 | #define CMD_RING_RSVD_BITS (0x3f) |
203 | |
204 | /* CONFIG - Configure Register - config_reg bitmasks */ |
205 | /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ |
206 | #define MAX_DEVS(p) ((p) & 0xff) |
207 | /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */ |
208 | #define CONFIG_U3E (1 << 8) |
209 | /* bit 9: Configuration Information Enable, xhci 1.1 */ |
210 | #define CONFIG_CIE (1 << 9) |
211 | /* bits 10:31 - reserved and should be preserved */ |
212 | |
213 | /** |
214 | * struct xhci_intr_reg - Interrupt Register Set |
215 | * @irq_pending: IMAN - Interrupt Management Register. Used to enable |
216 | * interrupts and check for pending interrupts. |
217 | * @irq_control: IMOD - Interrupt Moderation Register. |
218 | * Used to throttle interrupts. |
219 | * @erst_size: Number of segments in the Event Ring Segment Table (ERST). |
220 | * @erst_base: ERST base address. |
221 | * @erst_dequeue: Event ring dequeue pointer. |
222 | * |
223 | * Each interrupter (defined by a MSI-X vector) has an event ring and an Event |
224 | * Ring Segment Table (ERST) associated with it. The event ring is comprised of |
225 | * multiple segments of the same size. The HC places events on the ring and |
226 | * "updates the Cycle bit in the TRBs to indicate to software the current |
227 | * position of the Enqueue Pointer." The HCD (Linux) processes those events and |
228 | * updates the dequeue pointer. |
229 | */ |
230 | struct xhci_intr_reg { |
231 | __le32 irq_pending; |
232 | __le32 irq_control; |
233 | __le32 erst_size; |
234 | __le32 rsvd; |
235 | __le64 erst_base; |
236 | __le64 erst_dequeue; |
237 | }; |
238 | |
239 | /* irq_pending bitmasks */ |
240 | #define ER_IRQ_PENDING(p) ((p) & 0x1) |
241 | /* bits 2:31 need to be preserved */ |
242 | /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ |
243 | #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) |
244 | #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) |
245 | #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) |
246 | |
247 | /* irq_control bitmasks */ |
248 | /* Minimum interval between interrupts (in 250ns intervals). The interval |
249 | * between interrupts will be longer if there are no events on the event ring. |
250 | * Default is 4000 (1 ms). |
251 | */ |
252 | #define ER_IRQ_INTERVAL_MASK (0xffff) |
253 | /* Counter used to count down the time to the next interrupt - HW use only */ |
254 | #define ER_IRQ_COUNTER_MASK (0xffff << 16) |
255 | |
256 | /* erst_size bitmasks */ |
257 | /* Preserve bits 16:31 of erst_size */ |
258 | #define ERST_SIZE_MASK (0xffff << 16) |
259 | |
260 | /* erst_base bitmasks */ |
261 | #define ERST_BASE_RSVDP (GENMASK_ULL(5, 0)) |
262 | |
263 | /* erst_dequeue bitmasks */ |
264 | /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) |
265 | * where the current dequeue pointer lies. This is an optional HW hint. |
266 | */ |
267 | #define ERST_DESI_MASK (0x7) |
268 | /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by |
269 | * a work queue (or delayed service routine)? |
270 | */ |
271 | #define ERST_EHB (1 << 3) |
272 | #define ERST_PTR_MASK (GENMASK_ULL(63, 4)) |
273 | |
274 | /** |
275 | * struct xhci_run_regs |
276 | * @microframe_index: |
277 | * MFINDEX - current microframe number |
278 | * |
279 | * Section 5.5 Host Controller Runtime Registers: |
280 | * "Software should read and write these registers using only Dword (32 bit) |
281 | * or larger accesses" |
282 | */ |
283 | struct xhci_run_regs { |
284 | __le32 microframe_index; |
285 | __le32 rsvd[7]; |
286 | struct xhci_intr_reg ir_set[128]; |
287 | }; |
288 | |
289 | /** |
290 | * struct doorbell_array |
291 | * |
292 | * Bits 0 - 7: Endpoint target |
293 | * Bits 8 - 15: RsvdZ |
294 | * Bits 16 - 31: Stream ID |
295 | * |
296 | * Section 5.6 |
297 | */ |
298 | struct xhci_doorbell_array { |
299 | __le32 doorbell[256]; |
300 | }; |
301 | |
302 | #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) |
303 | #define DB_VALUE_HOST 0x00000000 |
304 | |
305 | #define PLT_MASK (0x03 << 6) |
306 | #define PLT_SYM (0x00 << 6) |
307 | #define PLT_ASYM_RX (0x02 << 6) |
308 | #define PLT_ASYM_TX (0x03 << 6) |
309 | |
310 | /** |
311 | * struct xhci_container_ctx |
312 | * @type: Type of context. Used to calculated offsets to contained contexts. |
313 | * @size: Size of the context data |
314 | * @bytes: The raw context data given to HW |
315 | * @dma: dma address of the bytes |
316 | * |
317 | * Represents either a Device or Input context. Holds a pointer to the raw |
318 | * memory used for the context (bytes) and dma address of it (dma). |
319 | */ |
320 | struct xhci_container_ctx { |
321 | unsigned type; |
322 | #define XHCI_CTX_TYPE_DEVICE 0x1 |
323 | #define XHCI_CTX_TYPE_INPUT 0x2 |
324 | |
325 | int size; |
326 | |
327 | u8 *bytes; |
328 | dma_addr_t dma; |
329 | }; |
330 | |
331 | /** |
332 | * struct xhci_slot_ctx |
333 | * @dev_info: Route string, device speed, hub info, and last valid endpoint |
334 | * @dev_info2: Max exit latency for device number, root hub port number |
335 | * @tt_info: tt_info is used to construct split transaction tokens |
336 | * @dev_state: slot state and device address |
337 | * |
338 | * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context |
339 | * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes |
340 | * reserved at the end of the slot context for HC internal use. |
341 | */ |
342 | struct xhci_slot_ctx { |
343 | __le32 dev_info; |
344 | __le32 dev_info2; |
345 | __le32 tt_info; |
346 | __le32 dev_state; |
347 | /* offset 0x10 to 0x1f reserved for HC internal use */ |
348 | __le32 reserved[4]; |
349 | }; |
350 | |
351 | /* dev_info bitmasks */ |
352 | /* Route String - 0:19 */ |
353 | #define ROUTE_STRING_MASK (0xfffff) |
354 | /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ |
355 | #define DEV_SPEED (0xf << 20) |
356 | #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20) |
357 | /* bit 24 reserved */ |
358 | /* Is this LS/FS device connected through a HS hub? - bit 25 */ |
359 | #define DEV_MTT (0x1 << 25) |
360 | /* Set if the device is a hub - bit 26 */ |
361 | #define DEV_HUB (0x1 << 26) |
362 | /* Index of the last valid endpoint context in this device context - 27:31 */ |
363 | #define LAST_CTX_MASK (0x1f << 27) |
364 | #define LAST_CTX(p) ((p) << 27) |
365 | #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) |
366 | #define SLOT_FLAG (1 << 0) |
367 | #define EP0_FLAG (1 << 1) |
368 | |
369 | /* dev_info2 bitmasks */ |
370 | /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ |
371 | #define MAX_EXIT (0xffff) |
372 | /* Root hub port number that is needed to access the USB device */ |
373 | #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) |
374 | #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) |
375 | /* Maximum number of ports under a hub device */ |
376 | #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) |
377 | #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24) |
378 | |
379 | /* tt_info bitmasks */ |
380 | /* |
381 | * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub |
382 | * The Slot ID of the hub that isolates the high speed signaling from |
383 | * this low or full-speed device. '0' if attached to root hub port. |
384 | */ |
385 | #define TT_SLOT (0xff) |
386 | /* |
387 | * The number of the downstream facing port of the high-speed hub |
388 | * '0' if the device is not low or full speed. |
389 | */ |
390 | #define TT_PORT (0xff << 8) |
391 | #define TT_THINK_TIME(p) (((p) & 0x3) << 16) |
392 | #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16) |
393 | |
394 | /* dev_state bitmasks */ |
395 | /* USB device address - assigned by the HC */ |
396 | #define DEV_ADDR_MASK (0xff) |
397 | /* bits 8:26 reserved */ |
398 | /* Slot state */ |
399 | #define SLOT_STATE (0x1f << 27) |
400 | #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) |
401 | |
402 | #define SLOT_STATE_DISABLED 0 |
403 | #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED |
404 | #define SLOT_STATE_DEFAULT 1 |
405 | #define SLOT_STATE_ADDRESSED 2 |
406 | #define SLOT_STATE_CONFIGURED 3 |
407 | |
408 | /** |
409 | * struct xhci_ep_ctx |
410 | * @ep_info: endpoint state, streams, mult, and interval information. |
411 | * @ep_info2: information on endpoint type, max packet size, max burst size, |
412 | * error count, and whether the HC will force an event for all |
413 | * transactions. |
414 | * @deq: 64-bit ring dequeue pointer address. If the endpoint only |
415 | * defines one stream, this points to the endpoint transfer ring. |
416 | * Otherwise, it points to a stream context array, which has a |
417 | * ring pointer for each flow. |
418 | * @tx_info: |
419 | * Average TRB lengths for the endpoint ring and |
420 | * max payload within an Endpoint Service Interval Time (ESIT). |
421 | * |
422 | * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context |
423 | * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes |
424 | * reserved at the end of the endpoint context for HC internal use. |
425 | */ |
426 | struct xhci_ep_ctx { |
427 | __le32 ep_info; |
428 | __le32 ep_info2; |
429 | __le64 deq; |
430 | __le32 tx_info; |
431 | /* offset 0x14 - 0x1f reserved for HC internal use */ |
432 | __le32 reserved[3]; |
433 | }; |
434 | |
435 | /* ep_info bitmasks */ |
436 | /* |
437 | * Endpoint State - bits 0:2 |
438 | * 0 - disabled |
439 | * 1 - running |
440 | * 2 - halted due to halt condition - ok to manipulate endpoint ring |
441 | * 3 - stopped |
442 | * 4 - TRB error |
443 | * 5-7 - reserved |
444 | */ |
445 | #define EP_STATE_MASK (0x7) |
446 | #define EP_STATE_DISABLED 0 |
447 | #define EP_STATE_RUNNING 1 |
448 | #define EP_STATE_HALTED 2 |
449 | #define EP_STATE_STOPPED 3 |
450 | #define EP_STATE_ERROR 4 |
451 | #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK) |
452 | |
453 | /* Mult - Max number of burtst within an interval, in EP companion desc. */ |
454 | #define EP_MULT(p) (((p) & 0x3) << 8) |
455 | #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) |
456 | /* bits 10:14 are Max Primary Streams */ |
457 | /* bit 15 is Linear Stream Array */ |
458 | /* Interval - period between requests to an endpoint - 125u increments. */ |
459 | #define EP_INTERVAL(p) (((p) & 0xff) << 16) |
460 | #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) |
461 | #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) |
462 | #define EP_MAXPSTREAMS_MASK (0x1f << 10) |
463 | #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) |
464 | #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10) |
465 | /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ |
466 | #define EP_HAS_LSA (1 << 15) |
467 | /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */ |
468 | #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff) |
469 | |
470 | /* ep_info2 bitmasks */ |
471 | /* |
472 | * Force Event - generate transfer events for all TRBs for this endpoint |
473 | * This will tell the HC to ignore the IOC and ISP flags (for debugging only). |
474 | */ |
475 | #define FORCE_EVENT (0x1) |
476 | #define ERROR_COUNT(p) (((p) & 0x3) << 1) |
477 | #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) |
478 | #define EP_TYPE(p) ((p) << 3) |
479 | #define ISOC_OUT_EP 1 |
480 | #define BULK_OUT_EP 2 |
481 | #define INT_OUT_EP 3 |
482 | #define CTRL_EP 4 |
483 | #define ISOC_IN_EP 5 |
484 | #define BULK_IN_EP 6 |
485 | #define INT_IN_EP 7 |
486 | /* bit 6 reserved */ |
487 | /* bit 7 is Host Initiate Disable - for disabling stream selection */ |
488 | #define MAX_BURST(p) (((p)&0xff) << 8) |
489 | #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) |
490 | #define MAX_PACKET(p) (((p)&0xffff) << 16) |
491 | #define MAX_PACKET_MASK (0xffff << 16) |
492 | #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) |
493 | |
494 | /* tx_info bitmasks */ |
495 | #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff) |
496 | #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16) |
497 | #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24) |
498 | #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) |
499 | |
500 | /* deq bitmasks */ |
501 | #define EP_CTX_CYCLE_MASK (1 << 0) |
502 | #define SCTX_DEQ_MASK (~0xfL) |
503 | |
504 | |
505 | /** |
506 | * struct xhci_input_control_context |
507 | * Input control context; see section 6.2.5. |
508 | * |
509 | * @drop_context: set the bit of the endpoint context you want to disable |
510 | * @add_context: set the bit of the endpoint context you want to enable |
511 | */ |
512 | struct xhci_input_control_ctx { |
513 | __le32 drop_flags; |
514 | __le32 add_flags; |
515 | __le32 rsvd2[6]; |
516 | }; |
517 | |
518 | #define EP_IS_ADDED(ctrl_ctx, i) \ |
519 | (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) |
520 | #define EP_IS_DROPPED(ctrl_ctx, i) \ |
521 | (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) |
522 | |
523 | /* Represents everything that is needed to issue a command on the command ring. |
524 | * It's useful to pre-allocate these for commands that cannot fail due to |
525 | * out-of-memory errors, like freeing streams. |
526 | */ |
527 | struct xhci_command { |
528 | /* Input context for changing device state */ |
529 | struct xhci_container_ctx *in_ctx; |
530 | u32 status; |
531 | int slot_id; |
532 | /* If completion is null, no one is waiting on this command |
533 | * and the structure can be freed after the command completes. |
534 | */ |
535 | struct completion *completion; |
536 | union xhci_trb *command_trb; |
537 | struct list_head cmd_list; |
538 | /* xHCI command response timeout in milliseconds */ |
539 | unsigned int timeout_ms; |
540 | }; |
541 | |
542 | /* drop context bitmasks */ |
543 | #define DROP_EP(x) (0x1 << x) |
544 | /* add context bitmasks */ |
545 | #define ADD_EP(x) (0x1 << x) |
546 | |
547 | struct xhci_stream_ctx { |
548 | /* 64-bit stream ring address, cycle state, and stream type */ |
549 | __le64 stream_ring; |
550 | /* offset 0x14 - 0x1f reserved for HC internal use */ |
551 | __le32 reserved[2]; |
552 | }; |
553 | |
554 | /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ |
555 | #define SCT_FOR_CTX(p) (((p) & 0x7) << 1) |
556 | /* Secondary stream array type, dequeue pointer is to a transfer ring */ |
557 | #define SCT_SEC_TR 0 |
558 | /* Primary stream array type, dequeue pointer is to a transfer ring */ |
559 | #define SCT_PRI_TR 1 |
560 | /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ |
561 | #define SCT_SSA_8 2 |
562 | #define SCT_SSA_16 3 |
563 | #define SCT_SSA_32 4 |
564 | #define SCT_SSA_64 5 |
565 | #define SCT_SSA_128 6 |
566 | #define SCT_SSA_256 7 |
567 | |
568 | /* Assume no secondary streams for now */ |
569 | struct xhci_stream_info { |
570 | struct xhci_ring **stream_rings; |
571 | /* Number of streams, including stream 0 (which drivers can't use) */ |
572 | unsigned int num_streams; |
573 | /* The stream context array may be bigger than |
574 | * the number of streams the driver asked for |
575 | */ |
576 | struct xhci_stream_ctx *stream_ctx_array; |
577 | unsigned int num_stream_ctxs; |
578 | dma_addr_t ctx_array_dma; |
579 | /* For mapping physical TRB addresses to segments in stream rings */ |
580 | struct radix_tree_root trb_address_map; |
581 | struct xhci_command *free_streams_command; |
582 | }; |
583 | |
584 | #define SMALL_STREAM_ARRAY_SIZE 256 |
585 | #define MEDIUM_STREAM_ARRAY_SIZE 1024 |
586 | |
587 | /* Some Intel xHCI host controllers need software to keep track of the bus |
588 | * bandwidth. Keep track of endpoint info here. Each root port is allocated |
589 | * the full bus bandwidth. We must also treat TTs (including each port under a |
590 | * multi-TT hub) as a separate bandwidth domain. The direct memory interface |
591 | * (DMI) also limits the total bandwidth (across all domains) that can be used. |
592 | */ |
593 | struct xhci_bw_info { |
594 | /* ep_interval is zero-based */ |
595 | unsigned int ep_interval; |
596 | /* mult and num_packets are one-based */ |
597 | unsigned int mult; |
598 | unsigned int num_packets; |
599 | unsigned int max_packet_size; |
600 | unsigned int max_esit_payload; |
601 | unsigned int type; |
602 | }; |
603 | |
604 | /* "Block" sizes in bytes the hardware uses for different device speeds. |
605 | * The logic in this part of the hardware limits the number of bits the hardware |
606 | * can use, so must represent bandwidth in a less precise manner to mimic what |
607 | * the scheduler hardware computes. |
608 | */ |
609 | #define FS_BLOCK 1 |
610 | #define HS_BLOCK 4 |
611 | #define SS_BLOCK 16 |
612 | #define DMI_BLOCK 32 |
613 | |
614 | /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated |
615 | * with each byte transferred. SuperSpeed devices have an initial overhead to |
616 | * set up bursts. These are in blocks, see above. LS overhead has already been |
617 | * translated into FS blocks. |
618 | */ |
619 | #define DMI_OVERHEAD 8 |
620 | #define DMI_OVERHEAD_BURST 4 |
621 | #define SS_OVERHEAD 8 |
622 | #define SS_OVERHEAD_BURST 32 |
623 | #define HS_OVERHEAD 26 |
624 | #define FS_OVERHEAD 20 |
625 | #define LS_OVERHEAD 128 |
626 | /* The TTs need to claim roughly twice as much bandwidth (94 bytes per |
627 | * microframe ~= 24Mbps) of the HS bus as the devices can actually use because |
628 | * of overhead associated with split transfers crossing microframe boundaries. |
629 | * 31 blocks is pure protocol overhead. |
630 | */ |
631 | #define TT_HS_OVERHEAD (31 + 94) |
632 | #define TT_DMI_OVERHEAD (25 + 12) |
633 | |
634 | /* Bandwidth limits in blocks */ |
635 | #define FS_BW_LIMIT 1285 |
636 | #define TT_BW_LIMIT 1320 |
637 | #define HS_BW_LIMIT 1607 |
638 | #define SS_BW_LIMIT_IN 3906 |
639 | #define DMI_BW_LIMIT_IN 3906 |
640 | #define SS_BW_LIMIT_OUT 3906 |
641 | #define DMI_BW_LIMIT_OUT 3906 |
642 | |
643 | /* Percentage of bus bandwidth reserved for non-periodic transfers */ |
644 | #define FS_BW_RESERVED 10 |
645 | #define HS_BW_RESERVED 20 |
646 | #define SS_BW_RESERVED 10 |
647 | |
648 | struct xhci_virt_ep { |
649 | struct xhci_virt_device *vdev; /* parent */ |
650 | unsigned int ep_index; |
651 | struct xhci_ring *ring; |
652 | /* Related to endpoints that are configured to use stream IDs only */ |
653 | struct xhci_stream_info *stream_info; |
654 | /* Temporary storage in case the configure endpoint command fails and we |
655 | * have to restore the device state to the previous state |
656 | */ |
657 | struct xhci_ring *new_ring; |
658 | unsigned int err_count; |
659 | unsigned int ep_state; |
660 | #define SET_DEQ_PENDING (1 << 0) |
661 | #define EP_HALTED (1 << 1) /* For stall handling */ |
662 | #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */ |
663 | /* Transitioning the endpoint to using streams, don't enqueue URBs */ |
664 | #define EP_GETTING_STREAMS (1 << 3) |
665 | #define EP_HAS_STREAMS (1 << 4) |
666 | /* Transitioning the endpoint to not using streams, don't enqueue URBs */ |
667 | #define EP_GETTING_NO_STREAMS (1 << 5) |
668 | #define EP_HARD_CLEAR_TOGGLE (1 << 6) |
669 | #define EP_SOFT_CLEAR_TOGGLE (1 << 7) |
670 | /* usb_hub_clear_tt_buffer is in progress */ |
671 | #define EP_CLEARING_TT (1 << 8) |
672 | /* ---- Related to URB cancellation ---- */ |
673 | struct list_head cancelled_td_list; |
674 | struct xhci_hcd *xhci; |
675 | /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue |
676 | * command. We'll need to update the ring's dequeue segment and dequeue |
677 | * pointer after the command completes. |
678 | */ |
679 | struct xhci_segment *queued_deq_seg; |
680 | union xhci_trb *queued_deq_ptr; |
681 | /* |
682 | * Sometimes the xHC can not process isochronous endpoint ring quickly |
683 | * enough, and it will miss some isoc tds on the ring and generate |
684 | * a Missed Service Error Event. |
685 | * Set skip flag when receive a Missed Service Error Event and |
686 | * process the missed tds on the endpoint ring. |
687 | */ |
688 | bool skip; |
689 | /* Bandwidth checking storage */ |
690 | struct xhci_bw_info bw_info; |
691 | struct list_head bw_endpoint_list; |
692 | /* Isoch Frame ID checking storage */ |
693 | int next_frame_id; |
694 | /* Use new Isoch TRB layout needed for extended TBC support */ |
695 | bool use_extended_tbc; |
696 | }; |
697 | |
698 | enum xhci_overhead_type { |
699 | LS_OVERHEAD_TYPE = 0, |
700 | FS_OVERHEAD_TYPE, |
701 | HS_OVERHEAD_TYPE, |
702 | }; |
703 | |
704 | struct xhci_interval_bw { |
705 | unsigned int num_packets; |
706 | /* Sorted by max packet size. |
707 | * Head of the list is the greatest max packet size. |
708 | */ |
709 | struct list_head endpoints; |
710 | /* How many endpoints of each speed are present. */ |
711 | unsigned int overhead[3]; |
712 | }; |
713 | |
714 | #define XHCI_MAX_INTERVAL 16 |
715 | |
716 | struct xhci_interval_bw_table { |
717 | unsigned int interval0_esit_payload; |
718 | struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL]; |
719 | /* Includes reserved bandwidth for async endpoints */ |
720 | unsigned int bw_used; |
721 | unsigned int ss_bw_in; |
722 | unsigned int ss_bw_out; |
723 | }; |
724 | |
725 | #define EP_CTX_PER_DEV 31 |
726 | |
727 | struct xhci_virt_device { |
728 | int slot_id; |
729 | struct usb_device *udev; |
730 | /* |
731 | * Commands to the hardware are passed an "input context" that |
732 | * tells the hardware what to change in its data structures. |
733 | * The hardware will return changes in an "output context" that |
734 | * software must allocate for the hardware. We need to keep |
735 | * track of input and output contexts separately because |
736 | * these commands might fail and we don't trust the hardware. |
737 | */ |
738 | struct xhci_container_ctx *out_ctx; |
739 | /* Used for addressing devices and configuration changes */ |
740 | struct xhci_container_ctx *in_ctx; |
741 | struct xhci_virt_ep eps[EP_CTX_PER_DEV]; |
742 | struct xhci_port *rhub_port; |
743 | struct xhci_interval_bw_table *bw_table; |
744 | struct xhci_tt_bw_info *tt_info; |
745 | /* |
746 | * flags for state tracking based on events and issued commands. |
747 | * Software can not rely on states from output contexts because of |
748 | * latency between events and xHC updating output context values. |
749 | * See xhci 1.1 section 4.8.3 for more details |
750 | */ |
751 | unsigned long flags; |
752 | #define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */ |
753 | |
754 | /* The current max exit latency for the enabled USB3 link states. */ |
755 | u16 current_mel; |
756 | /* Used for the debugfs interfaces. */ |
757 | void *debugfs_private; |
758 | }; |
759 | |
760 | /* |
761 | * For each roothub, keep track of the bandwidth information for each periodic |
762 | * interval. |
763 | * |
764 | * If a high speed hub is attached to the roothub, each TT associated with that |
765 | * hub is a separate bandwidth domain. The interval information for the |
766 | * endpoints on the devices under that TT will appear in the TT structure. |
767 | */ |
768 | struct xhci_root_port_bw_info { |
769 | struct list_head tts; |
770 | unsigned int num_active_tts; |
771 | struct xhci_interval_bw_table bw_table; |
772 | }; |
773 | |
774 | struct xhci_tt_bw_info { |
775 | struct list_head tt_list; |
776 | int slot_id; |
777 | int ttport; |
778 | struct xhci_interval_bw_table bw_table; |
779 | int active_eps; |
780 | }; |
781 | |
782 | |
783 | /** |
784 | * struct xhci_device_context_array |
785 | * @dev_context_ptr array of 64-bit DMA addresses for device contexts |
786 | */ |
787 | struct xhci_device_context_array { |
788 | /* 64-bit device addresses; we only write 32-bit addresses */ |
789 | __le64 dev_context_ptrs[MAX_HC_SLOTS]; |
790 | /* private xHCD pointers */ |
791 | dma_addr_t dma; |
792 | }; |
793 | /* TODO: write function to set the 64-bit device DMA address */ |
794 | /* |
795 | * TODO: change this to be dynamically sized at HC mem init time since the HC |
796 | * might not be able to handle the maximum number of devices possible. |
797 | */ |
798 | |
799 | |
800 | struct xhci_transfer_event { |
801 | /* 64-bit buffer address, or immediate data */ |
802 | __le64 buffer; |
803 | __le32 transfer_len; |
804 | /* This field is interpreted differently based on the type of TRB */ |
805 | __le32 flags; |
806 | }; |
807 | |
808 | /* Transfer event TRB length bit mask */ |
809 | /* bits 0:23 */ |
810 | #define EVENT_TRB_LEN(p) ((p) & 0xffffff) |
811 | |
812 | /** Transfer Event bit fields **/ |
813 | #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) |
814 | |
815 | /* Completion Code - only applicable for some types of TRBs */ |
816 | #define COMP_CODE_MASK (0xff << 24) |
817 | #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) |
818 | #define COMP_INVALID 0 |
819 | #define COMP_SUCCESS 1 |
820 | #define COMP_DATA_BUFFER_ERROR 2 |
821 | #define COMP_BABBLE_DETECTED_ERROR 3 |
822 | #define COMP_USB_TRANSACTION_ERROR 4 |
823 | #define COMP_TRB_ERROR 5 |
824 | #define COMP_STALL_ERROR 6 |
825 | #define COMP_RESOURCE_ERROR 7 |
826 | #define COMP_BANDWIDTH_ERROR 8 |
827 | #define COMP_NO_SLOTS_AVAILABLE_ERROR 9 |
828 | #define COMP_INVALID_STREAM_TYPE_ERROR 10 |
829 | #define COMP_SLOT_NOT_ENABLED_ERROR 11 |
830 | #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12 |
831 | #define COMP_SHORT_PACKET 13 |
832 | #define COMP_RING_UNDERRUN 14 |
833 | #define COMP_RING_OVERRUN 15 |
834 | #define COMP_VF_EVENT_RING_FULL_ERROR 16 |
835 | #define COMP_PARAMETER_ERROR 17 |
836 | #define COMP_BANDWIDTH_OVERRUN_ERROR 18 |
837 | #define COMP_CONTEXT_STATE_ERROR 19 |
838 | #define COMP_NO_PING_RESPONSE_ERROR 20 |
839 | #define COMP_EVENT_RING_FULL_ERROR 21 |
840 | #define COMP_INCOMPATIBLE_DEVICE_ERROR 22 |
841 | #define COMP_MISSED_SERVICE_ERROR 23 |
842 | #define COMP_COMMAND_RING_STOPPED 24 |
843 | #define COMP_COMMAND_ABORTED 25 |
844 | #define COMP_STOPPED 26 |
845 | #define COMP_STOPPED_LENGTH_INVALID 27 |
846 | #define COMP_STOPPED_SHORT_PACKET 28 |
847 | #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29 |
848 | #define COMP_ISOCH_BUFFER_OVERRUN 31 |
849 | #define COMP_EVENT_LOST_ERROR 32 |
850 | #define COMP_UNDEFINED_ERROR 33 |
851 | #define COMP_INVALID_STREAM_ID_ERROR 34 |
852 | #define COMP_SECONDARY_BANDWIDTH_ERROR 35 |
853 | #define COMP_SPLIT_TRANSACTION_ERROR 36 |
854 | |
855 | static inline const char *xhci_trb_comp_code_string(u8 status) |
856 | { |
857 | switch (status) { |
858 | case COMP_INVALID: |
859 | return "Invalid" ; |
860 | case COMP_SUCCESS: |
861 | return "Success" ; |
862 | case COMP_DATA_BUFFER_ERROR: |
863 | return "Data Buffer Error" ; |
864 | case COMP_BABBLE_DETECTED_ERROR: |
865 | return "Babble Detected" ; |
866 | case COMP_USB_TRANSACTION_ERROR: |
867 | return "USB Transaction Error" ; |
868 | case COMP_TRB_ERROR: |
869 | return "TRB Error" ; |
870 | case COMP_STALL_ERROR: |
871 | return "Stall Error" ; |
872 | case COMP_RESOURCE_ERROR: |
873 | return "Resource Error" ; |
874 | case COMP_BANDWIDTH_ERROR: |
875 | return "Bandwidth Error" ; |
876 | case COMP_NO_SLOTS_AVAILABLE_ERROR: |
877 | return "No Slots Available Error" ; |
878 | case COMP_INVALID_STREAM_TYPE_ERROR: |
879 | return "Invalid Stream Type Error" ; |
880 | case COMP_SLOT_NOT_ENABLED_ERROR: |
881 | return "Slot Not Enabled Error" ; |
882 | case COMP_ENDPOINT_NOT_ENABLED_ERROR: |
883 | return "Endpoint Not Enabled Error" ; |
884 | case COMP_SHORT_PACKET: |
885 | return "Short Packet" ; |
886 | case COMP_RING_UNDERRUN: |
887 | return "Ring Underrun" ; |
888 | case COMP_RING_OVERRUN: |
889 | return "Ring Overrun" ; |
890 | case COMP_VF_EVENT_RING_FULL_ERROR: |
891 | return "VF Event Ring Full Error" ; |
892 | case COMP_PARAMETER_ERROR: |
893 | return "Parameter Error" ; |
894 | case COMP_BANDWIDTH_OVERRUN_ERROR: |
895 | return "Bandwidth Overrun Error" ; |
896 | case COMP_CONTEXT_STATE_ERROR: |
897 | return "Context State Error" ; |
898 | case COMP_NO_PING_RESPONSE_ERROR: |
899 | return "No Ping Response Error" ; |
900 | case COMP_EVENT_RING_FULL_ERROR: |
901 | return "Event Ring Full Error" ; |
902 | case COMP_INCOMPATIBLE_DEVICE_ERROR: |
903 | return "Incompatible Device Error" ; |
904 | case COMP_MISSED_SERVICE_ERROR: |
905 | return "Missed Service Error" ; |
906 | case COMP_COMMAND_RING_STOPPED: |
907 | return "Command Ring Stopped" ; |
908 | case COMP_COMMAND_ABORTED: |
909 | return "Command Aborted" ; |
910 | case COMP_STOPPED: |
911 | return "Stopped" ; |
912 | case COMP_STOPPED_LENGTH_INVALID: |
913 | return "Stopped - Length Invalid" ; |
914 | case COMP_STOPPED_SHORT_PACKET: |
915 | return "Stopped - Short Packet" ; |
916 | case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR: |
917 | return "Max Exit Latency Too Large Error" ; |
918 | case COMP_ISOCH_BUFFER_OVERRUN: |
919 | return "Isoch Buffer Overrun" ; |
920 | case COMP_EVENT_LOST_ERROR: |
921 | return "Event Lost Error" ; |
922 | case COMP_UNDEFINED_ERROR: |
923 | return "Undefined Error" ; |
924 | case COMP_INVALID_STREAM_ID_ERROR: |
925 | return "Invalid Stream ID Error" ; |
926 | case COMP_SECONDARY_BANDWIDTH_ERROR: |
927 | return "Secondary Bandwidth Error" ; |
928 | case COMP_SPLIT_TRANSACTION_ERROR: |
929 | return "Split Transaction Error" ; |
930 | default: |
931 | return "Unknown!!" ; |
932 | } |
933 | } |
934 | |
935 | struct xhci_link_trb { |
936 | /* 64-bit segment pointer*/ |
937 | __le64 segment_ptr; |
938 | __le32 intr_target; |
939 | __le32 control; |
940 | }; |
941 | |
942 | /* control bitfields */ |
943 | #define LINK_TOGGLE (0x1<<1) |
944 | |
945 | /* Command completion event TRB */ |
946 | struct xhci_event_cmd { |
947 | /* Pointer to command TRB, or the value passed by the event data trb */ |
948 | __le64 cmd_trb; |
949 | __le32 status; |
950 | __le32 flags; |
951 | }; |
952 | |
953 | /* flags bitmasks */ |
954 | |
955 | /* Address device - disable SetAddress */ |
956 | #define TRB_BSR (1<<9) |
957 | |
958 | /* Configure Endpoint - Deconfigure */ |
959 | #define TRB_DC (1<<9) |
960 | |
961 | /* Stop Ring - Transfer State Preserve */ |
962 | #define TRB_TSP (1<<9) |
963 | |
964 | enum xhci_ep_reset_type { |
965 | EP_HARD_RESET, |
966 | EP_SOFT_RESET, |
967 | }; |
968 | |
969 | /* Force Event */ |
970 | #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22) |
971 | #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16) |
972 | |
973 | /* Set Latency Tolerance Value */ |
974 | #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16) |
975 | |
976 | /* Get Port Bandwidth */ |
977 | #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16) |
978 | |
979 | /* Force Header */ |
980 | #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f) |
981 | #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24) |
982 | |
983 | enum xhci_setup_dev { |
984 | SETUP_CONTEXT_ONLY, |
985 | SETUP_CONTEXT_ADDRESS, |
986 | }; |
987 | |
988 | /* bits 16:23 are the virtual function ID */ |
989 | /* bits 24:31 are the slot ID */ |
990 | #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) |
991 | #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) |
992 | |
993 | /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ |
994 | #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) |
995 | #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) |
996 | |
997 | #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) |
998 | #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) |
999 | #define LAST_EP_INDEX 30 |
1000 | |
1001 | /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */ |
1002 | #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) |
1003 | #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) |
1004 | #define SCT_FOR_TRB(p) (((p) << 1) & 0x7) |
1005 | |
1006 | /* Link TRB specific fields */ |
1007 | #define TRB_TC (1<<1) |
1008 | |
1009 | /* Port Status Change Event TRB fields */ |
1010 | /* Port ID - bits 31:24 */ |
1011 | #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) |
1012 | |
1013 | #define EVENT_DATA (1 << 2) |
1014 | |
1015 | /* Normal TRB fields */ |
1016 | /* transfer_len bitmasks - bits 0:16 */ |
1017 | #define TRB_LEN(p) ((p) & 0x1ffff) |
1018 | /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */ |
1019 | #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) |
1020 | #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17) |
1021 | /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */ |
1022 | #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17) |
1023 | /* Interrupter Target - which MSI-X vector to target the completion event at */ |
1024 | #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) |
1025 | #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) |
1026 | /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */ |
1027 | #define TRB_TBC(p) (((p) & 0x3) << 7) |
1028 | #define TRB_TLBPC(p) (((p) & 0xf) << 16) |
1029 | |
1030 | /* Cycle bit - indicates TRB ownership by HC or HCD */ |
1031 | #define TRB_CYCLE (1<<0) |
1032 | /* |
1033 | * Force next event data TRB to be evaluated before task switch. |
1034 | * Used to pass OS data back after a TD completes. |
1035 | */ |
1036 | #define TRB_ENT (1<<1) |
1037 | /* Interrupt on short packet */ |
1038 | #define TRB_ISP (1<<2) |
1039 | /* Set PCIe no snoop attribute */ |
1040 | #define TRB_NO_SNOOP (1<<3) |
1041 | /* Chain multiple TRBs into a TD */ |
1042 | #define TRB_CHAIN (1<<4) |
1043 | /* Interrupt on completion */ |
1044 | #define TRB_IOC (1<<5) |
1045 | /* The buffer pointer contains immediate data */ |
1046 | #define TRB_IDT (1<<6) |
1047 | /* TDs smaller than this might use IDT */ |
1048 | #define TRB_IDT_MAX_SIZE 8 |
1049 | |
1050 | /* Block Event Interrupt */ |
1051 | #define TRB_BEI (1<<9) |
1052 | |
1053 | /* Control transfer TRB specific fields */ |
1054 | #define TRB_DIR_IN (1<<16) |
1055 | #define TRB_TX_TYPE(p) ((p) << 16) |
1056 | #define TRB_DATA_OUT 2 |
1057 | #define TRB_DATA_IN 3 |
1058 | |
1059 | /* Isochronous TRB specific fields */ |
1060 | #define TRB_SIA (1<<31) |
1061 | #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20) |
1062 | |
1063 | /* TRB cache size for xHC with TRB cache */ |
1064 | #define TRB_CACHE_SIZE_HS 8 |
1065 | #define TRB_CACHE_SIZE_SS 16 |
1066 | |
1067 | struct xhci_generic_trb { |
1068 | __le32 field[4]; |
1069 | }; |
1070 | |
1071 | union xhci_trb { |
1072 | struct xhci_link_trb link; |
1073 | struct xhci_transfer_event trans_event; |
1074 | struct xhci_event_cmd event_cmd; |
1075 | struct xhci_generic_trb generic; |
1076 | }; |
1077 | |
1078 | /* TRB bit mask */ |
1079 | #define TRB_TYPE_BITMASK (0xfc00) |
1080 | #define TRB_TYPE(p) ((p) << 10) |
1081 | #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) |
1082 | /* TRB type IDs */ |
1083 | /* bulk, interrupt, isoc scatter/gather, and control data stage */ |
1084 | #define TRB_NORMAL 1 |
1085 | /* setup stage for control transfers */ |
1086 | #define TRB_SETUP 2 |
1087 | /* data stage for control transfers */ |
1088 | #define TRB_DATA 3 |
1089 | /* status stage for control transfers */ |
1090 | #define TRB_STATUS 4 |
1091 | /* isoc transfers */ |
1092 | #define TRB_ISOC 5 |
1093 | /* TRB for linking ring segments */ |
1094 | #define TRB_LINK 6 |
1095 | #define TRB_EVENT_DATA 7 |
1096 | /* Transfer Ring No-op (not for the command ring) */ |
1097 | #define TRB_TR_NOOP 8 |
1098 | /* Command TRBs */ |
1099 | /* Enable Slot Command */ |
1100 | #define TRB_ENABLE_SLOT 9 |
1101 | /* Disable Slot Command */ |
1102 | #define TRB_DISABLE_SLOT 10 |
1103 | /* Address Device Command */ |
1104 | #define TRB_ADDR_DEV 11 |
1105 | /* Configure Endpoint Command */ |
1106 | #define TRB_CONFIG_EP 12 |
1107 | /* Evaluate Context Command */ |
1108 | #define TRB_EVAL_CONTEXT 13 |
1109 | /* Reset Endpoint Command */ |
1110 | #define TRB_RESET_EP 14 |
1111 | /* Stop Transfer Ring Command */ |
1112 | #define TRB_STOP_RING 15 |
1113 | /* Set Transfer Ring Dequeue Pointer Command */ |
1114 | #define TRB_SET_DEQ 16 |
1115 | /* Reset Device Command */ |
1116 | #define TRB_RESET_DEV 17 |
1117 | /* Force Event Command (opt) */ |
1118 | #define TRB_FORCE_EVENT 18 |
1119 | /* Negotiate Bandwidth Command (opt) */ |
1120 | #define TRB_NEG_BANDWIDTH 19 |
1121 | /* Set Latency Tolerance Value Command (opt) */ |
1122 | #define TRB_SET_LT 20 |
1123 | /* Get port bandwidth Command */ |
1124 | #define TRB_GET_BW 21 |
1125 | /* Force Header Command - generate a transaction or link management packet */ |
1126 | #define 22 |
1127 | /* No-op Command - not for transfer rings */ |
1128 | #define TRB_CMD_NOOP 23 |
1129 | /* TRB IDs 24-31 reserved */ |
1130 | /* Event TRBS */ |
1131 | /* Transfer Event */ |
1132 | #define TRB_TRANSFER 32 |
1133 | /* Command Completion Event */ |
1134 | #define TRB_COMPLETION 33 |
1135 | /* Port Status Change Event */ |
1136 | #define TRB_PORT_STATUS 34 |
1137 | /* Bandwidth Request Event (opt) */ |
1138 | #define TRB_BANDWIDTH_EVENT 35 |
1139 | /* Doorbell Event (opt) */ |
1140 | #define TRB_DOORBELL 36 |
1141 | /* Host Controller Event */ |
1142 | #define TRB_HC_EVENT 37 |
1143 | /* Device Notification Event - device sent function wake notification */ |
1144 | #define TRB_DEV_NOTE 38 |
1145 | /* MFINDEX Wrap Event - microframe counter wrapped */ |
1146 | #define TRB_MFINDEX_WRAP 39 |
1147 | /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ |
1148 | #define TRB_VENDOR_DEFINED_LOW 48 |
1149 | /* Nec vendor-specific command completion event. */ |
1150 | #define TRB_NEC_CMD_COMP 48 |
1151 | /* Get NEC firmware revision. */ |
1152 | #define TRB_NEC_GET_FW 49 |
1153 | |
1154 | static inline const char *xhci_trb_type_string(u8 type) |
1155 | { |
1156 | switch (type) { |
1157 | case TRB_NORMAL: |
1158 | return "Normal" ; |
1159 | case TRB_SETUP: |
1160 | return "Setup Stage" ; |
1161 | case TRB_DATA: |
1162 | return "Data Stage" ; |
1163 | case TRB_STATUS: |
1164 | return "Status Stage" ; |
1165 | case TRB_ISOC: |
1166 | return "Isoch" ; |
1167 | case TRB_LINK: |
1168 | return "Link" ; |
1169 | case TRB_EVENT_DATA: |
1170 | return "Event Data" ; |
1171 | case TRB_TR_NOOP: |
1172 | return "No-Op" ; |
1173 | case TRB_ENABLE_SLOT: |
1174 | return "Enable Slot Command" ; |
1175 | case TRB_DISABLE_SLOT: |
1176 | return "Disable Slot Command" ; |
1177 | case TRB_ADDR_DEV: |
1178 | return "Address Device Command" ; |
1179 | case TRB_CONFIG_EP: |
1180 | return "Configure Endpoint Command" ; |
1181 | case TRB_EVAL_CONTEXT: |
1182 | return "Evaluate Context Command" ; |
1183 | case TRB_RESET_EP: |
1184 | return "Reset Endpoint Command" ; |
1185 | case TRB_STOP_RING: |
1186 | return "Stop Ring Command" ; |
1187 | case TRB_SET_DEQ: |
1188 | return "Set TR Dequeue Pointer Command" ; |
1189 | case TRB_RESET_DEV: |
1190 | return "Reset Device Command" ; |
1191 | case TRB_FORCE_EVENT: |
1192 | return "Force Event Command" ; |
1193 | case TRB_NEG_BANDWIDTH: |
1194 | return "Negotiate Bandwidth Command" ; |
1195 | case TRB_SET_LT: |
1196 | return "Set Latency Tolerance Value Command" ; |
1197 | case TRB_GET_BW: |
1198 | return "Get Port Bandwidth Command" ; |
1199 | case TRB_FORCE_HEADER: |
1200 | return "Force Header Command" ; |
1201 | case TRB_CMD_NOOP: |
1202 | return "No-Op Command" ; |
1203 | case TRB_TRANSFER: |
1204 | return "Transfer Event" ; |
1205 | case TRB_COMPLETION: |
1206 | return "Command Completion Event" ; |
1207 | case TRB_PORT_STATUS: |
1208 | return "Port Status Change Event" ; |
1209 | case TRB_BANDWIDTH_EVENT: |
1210 | return "Bandwidth Request Event" ; |
1211 | case TRB_DOORBELL: |
1212 | return "Doorbell Event" ; |
1213 | case TRB_HC_EVENT: |
1214 | return "Host Controller Event" ; |
1215 | case TRB_DEV_NOTE: |
1216 | return "Device Notification Event" ; |
1217 | case TRB_MFINDEX_WRAP: |
1218 | return "MFINDEX Wrap Event" ; |
1219 | case TRB_NEC_CMD_COMP: |
1220 | return "NEC Command Completion Event" ; |
1221 | case TRB_NEC_GET_FW: |
1222 | return "NET Get Firmware Revision Command" ; |
1223 | default: |
1224 | return "UNKNOWN" ; |
1225 | } |
1226 | } |
1227 | |
1228 | #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) |
1229 | /* Above, but for __le32 types -- can avoid work by swapping constants: */ |
1230 | #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ |
1231 | cpu_to_le32(TRB_TYPE(TRB_LINK))) |
1232 | #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ |
1233 | cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) |
1234 | |
1235 | #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) |
1236 | #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) |
1237 | |
1238 | /* |
1239 | * TRBS_PER_SEGMENT must be a multiple of 4, |
1240 | * since the command ring is 64-byte aligned. |
1241 | * It must also be greater than 16. |
1242 | */ |
1243 | #define TRBS_PER_SEGMENT 256 |
1244 | /* Allow two commands + a link TRB, along with any reserved command TRBs */ |
1245 | #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) |
1246 | #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) |
1247 | #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE)) |
1248 | /* TRB buffer pointers can't cross 64KB boundaries */ |
1249 | #define TRB_MAX_BUFF_SHIFT 16 |
1250 | #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) |
1251 | /* How much data is left before the 64KB boundary? */ |
1252 | #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \ |
1253 | (addr & (TRB_MAX_BUFF_SIZE - 1))) |
1254 | #define MAX_SOFT_RETRY 3 |
1255 | /* |
1256 | * Limits of consecutive isoc trbs that can Block Event Interrupt (BEI) if |
1257 | * XHCI_AVOID_BEI quirk is in use. |
1258 | */ |
1259 | #define AVOID_BEI_INTERVAL_MIN 8 |
1260 | #define AVOID_BEI_INTERVAL_MAX 32 |
1261 | |
1262 | struct xhci_segment { |
1263 | union xhci_trb *trbs; |
1264 | /* private to HCD */ |
1265 | struct xhci_segment *next; |
1266 | unsigned int num; |
1267 | dma_addr_t dma; |
1268 | /* Max packet sized bounce buffer for td-fragmant alignment */ |
1269 | dma_addr_t bounce_dma; |
1270 | void *bounce_buf; |
1271 | unsigned int bounce_offs; |
1272 | unsigned int bounce_len; |
1273 | }; |
1274 | |
1275 | enum xhci_cancelled_td_status { |
1276 | TD_DIRTY = 0, |
1277 | TD_HALTED, |
1278 | TD_CLEARING_CACHE, |
1279 | TD_CLEARED, |
1280 | }; |
1281 | |
1282 | struct xhci_td { |
1283 | struct list_head td_list; |
1284 | struct list_head cancelled_td_list; |
1285 | int status; |
1286 | enum xhci_cancelled_td_status cancel_status; |
1287 | struct urb *urb; |
1288 | struct xhci_segment *start_seg; |
1289 | union xhci_trb *first_trb; |
1290 | union xhci_trb *last_trb; |
1291 | struct xhci_segment *last_trb_seg; |
1292 | struct xhci_segment *bounce_seg; |
1293 | /* actual_length of the URB has already been set */ |
1294 | bool urb_length_set; |
1295 | bool error_mid_td; |
1296 | unsigned int num_trbs; |
1297 | }; |
1298 | |
1299 | /* |
1300 | * xHCI command default timeout value in milliseconds. |
1301 | * USB 3.2 spec, section 9.2.6.1 |
1302 | */ |
1303 | #define XHCI_CMD_DEFAULT_TIMEOUT 5000 |
1304 | |
1305 | /* command descriptor */ |
1306 | struct xhci_cd { |
1307 | struct xhci_command *command; |
1308 | union xhci_trb *cmd_trb; |
1309 | }; |
1310 | |
1311 | enum xhci_ring_type { |
1312 | TYPE_CTRL = 0, |
1313 | TYPE_ISOC, |
1314 | TYPE_BULK, |
1315 | TYPE_INTR, |
1316 | TYPE_STREAM, |
1317 | TYPE_COMMAND, |
1318 | TYPE_EVENT, |
1319 | }; |
1320 | |
1321 | static inline const char *xhci_ring_type_string(enum xhci_ring_type type) |
1322 | { |
1323 | switch (type) { |
1324 | case TYPE_CTRL: |
1325 | return "CTRL" ; |
1326 | case TYPE_ISOC: |
1327 | return "ISOC" ; |
1328 | case TYPE_BULK: |
1329 | return "BULK" ; |
1330 | case TYPE_INTR: |
1331 | return "INTR" ; |
1332 | case TYPE_STREAM: |
1333 | return "STREAM" ; |
1334 | case TYPE_COMMAND: |
1335 | return "CMD" ; |
1336 | case TYPE_EVENT: |
1337 | return "EVENT" ; |
1338 | } |
1339 | |
1340 | return "UNKNOWN" ; |
1341 | } |
1342 | |
1343 | struct xhci_ring { |
1344 | struct xhci_segment *first_seg; |
1345 | struct xhci_segment *last_seg; |
1346 | union xhci_trb *enqueue; |
1347 | struct xhci_segment *enq_seg; |
1348 | union xhci_trb *dequeue; |
1349 | struct xhci_segment *deq_seg; |
1350 | struct list_head td_list; |
1351 | /* |
1352 | * Write the cycle state into the TRB cycle field to give ownership of |
1353 | * the TRB to the host controller (if we are the producer), or to check |
1354 | * if we own the TRB (if we are the consumer). See section 4.9.1. |
1355 | */ |
1356 | u32 cycle_state; |
1357 | unsigned int stream_id; |
1358 | unsigned int num_segs; |
1359 | unsigned int num_trbs_free; /* used only by xhci DbC */ |
1360 | unsigned int bounce_buf_len; |
1361 | enum xhci_ring_type type; |
1362 | bool last_td_was_short; |
1363 | struct radix_tree_root *trb_address_map; |
1364 | }; |
1365 | |
1366 | struct xhci_erst_entry { |
1367 | /* 64-bit event ring segment address */ |
1368 | __le64 seg_addr; |
1369 | __le32 seg_size; |
1370 | /* Set to zero */ |
1371 | __le32 rsvd; |
1372 | }; |
1373 | |
1374 | struct xhci_erst { |
1375 | struct xhci_erst_entry *entries; |
1376 | unsigned int num_entries; |
1377 | /* xhci->event_ring keeps track of segment dma addresses */ |
1378 | dma_addr_t erst_dma_addr; |
1379 | /* Num entries the ERST can contain */ |
1380 | unsigned int erst_size; |
1381 | }; |
1382 | |
1383 | struct xhci_scratchpad { |
1384 | u64 *sp_array; |
1385 | dma_addr_t sp_dma; |
1386 | void **sp_buffers; |
1387 | }; |
1388 | |
1389 | struct urb_priv { |
1390 | int num_tds; |
1391 | int num_tds_done; |
1392 | struct xhci_td td[] __counted_by(num_tds); |
1393 | }; |
1394 | |
1395 | /* Reasonable limit for number of Event Ring segments (spec allows 32k) */ |
1396 | #define ERST_MAX_SEGS 2 |
1397 | /* Poll every 60 seconds */ |
1398 | #define POLL_TIMEOUT 60 |
1399 | /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ |
1400 | #define XHCI_STOP_EP_CMD_TIMEOUT 5 |
1401 | /* XXX: Make these module parameters */ |
1402 | |
1403 | struct s3_save { |
1404 | u32 command; |
1405 | u32 dev_nt; |
1406 | u64 dcbaa_ptr; |
1407 | u32 config_reg; |
1408 | }; |
1409 | |
1410 | /* Use for lpm */ |
1411 | struct dev_info { |
1412 | u32 dev_id; |
1413 | struct list_head list; |
1414 | }; |
1415 | |
1416 | struct xhci_bus_state { |
1417 | unsigned long bus_suspended; |
1418 | unsigned long next_statechange; |
1419 | |
1420 | /* Port suspend arrays are indexed by the portnum of the fake roothub */ |
1421 | /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ |
1422 | u32 port_c_suspend; |
1423 | u32 suspended_ports; |
1424 | u32 port_remote_wakeup; |
1425 | /* which ports have started to resume */ |
1426 | unsigned long resuming_ports; |
1427 | }; |
1428 | |
1429 | struct xhci_interrupter { |
1430 | struct xhci_ring *event_ring; |
1431 | struct xhci_erst erst; |
1432 | struct xhci_intr_reg __iomem *ir_set; |
1433 | unsigned int intr_num; |
1434 | bool ip_autoclear; |
1435 | u32 isoc_bei_interval; |
1436 | /* For interrupter registers save and restore over suspend/resume */ |
1437 | u32 s3_irq_pending; |
1438 | u32 s3_irq_control; |
1439 | u32 s3_erst_size; |
1440 | u64 s3_erst_base; |
1441 | u64 s3_erst_dequeue; |
1442 | }; |
1443 | /* |
1444 | * It can take up to 20 ms to transition from RExit to U0 on the |
1445 | * Intel Lynx Point LP xHCI host. |
1446 | */ |
1447 | #define XHCI_MAX_REXIT_TIMEOUT_MS 20 |
1448 | struct xhci_port_cap { |
1449 | u32 *psi; /* array of protocol speed ID entries */ |
1450 | u8 psi_count; |
1451 | u8 psi_uid_count; |
1452 | u8 maj_rev; |
1453 | u8 min_rev; |
1454 | }; |
1455 | |
1456 | struct xhci_port { |
1457 | __le32 __iomem *addr; |
1458 | int hw_portnum; |
1459 | int hcd_portnum; |
1460 | struct xhci_hub *rhub; |
1461 | struct xhci_port_cap *port_cap; |
1462 | unsigned int lpm_incapable:1; |
1463 | unsigned long resume_timestamp; |
1464 | bool rexit_active; |
1465 | /* Slot ID is the index of the device directly connected to the port */ |
1466 | int slot_id; |
1467 | struct completion rexit_done; |
1468 | struct completion u3exit_done; |
1469 | }; |
1470 | |
1471 | struct xhci_hub { |
1472 | struct xhci_port **ports; |
1473 | unsigned int num_ports; |
1474 | struct usb_hcd *hcd; |
1475 | /* keep track of bus suspend info */ |
1476 | struct xhci_bus_state bus_state; |
1477 | /* supported prococol extended capabiliy values */ |
1478 | u8 maj_rev; |
1479 | u8 min_rev; |
1480 | }; |
1481 | |
1482 | /* There is one xhci_hcd structure per controller */ |
1483 | struct xhci_hcd { |
1484 | struct usb_hcd *main_hcd; |
1485 | struct usb_hcd *shared_hcd; |
1486 | /* glue to PCI and HCD framework */ |
1487 | struct xhci_cap_regs __iomem *cap_regs; |
1488 | struct xhci_op_regs __iomem *op_regs; |
1489 | struct xhci_run_regs __iomem *run_regs; |
1490 | struct xhci_doorbell_array __iomem *dba; |
1491 | |
1492 | /* Cached register copies of read-only HC data */ |
1493 | __u32 hcs_params1; |
1494 | __u32 hcs_params2; |
1495 | __u32 hcs_params3; |
1496 | __u32 hcc_params; |
1497 | __u32 hcc_params2; |
1498 | |
1499 | spinlock_t lock; |
1500 | |
1501 | /* packed release number */ |
1502 | u8 sbrn; |
1503 | u16 hci_version; |
1504 | u8 max_slots; |
1505 | u16 max_interrupters; |
1506 | u8 max_ports; |
1507 | u8 isoc_threshold; |
1508 | /* imod_interval in ns (I * 250ns) */ |
1509 | u32 imod_interval; |
1510 | int event_ring_max; |
1511 | /* 4KB min, 128MB max */ |
1512 | int page_size; |
1513 | /* Valid values are 12 to 20, inclusive */ |
1514 | int page_shift; |
1515 | /* MSI-X/MSI vectors */ |
1516 | int nvecs; |
1517 | /* optional clocks */ |
1518 | struct clk *clk; |
1519 | struct clk *reg_clk; |
1520 | /* optional reset controller */ |
1521 | struct reset_control *reset; |
1522 | /* data structures */ |
1523 | struct xhci_device_context_array *dcbaa; |
1524 | struct xhci_interrupter **interrupters; |
1525 | struct xhci_ring *cmd_ring; |
1526 | unsigned int cmd_ring_state; |
1527 | #define CMD_RING_STATE_RUNNING (1 << 0) |
1528 | #define CMD_RING_STATE_ABORTED (1 << 1) |
1529 | #define CMD_RING_STATE_STOPPED (1 << 2) |
1530 | struct list_head cmd_list; |
1531 | unsigned int cmd_ring_reserved_trbs; |
1532 | struct delayed_work cmd_timer; |
1533 | struct completion cmd_ring_stop_completion; |
1534 | struct xhci_command *current_cmd; |
1535 | |
1536 | /* Scratchpad */ |
1537 | struct xhci_scratchpad *scratchpad; |
1538 | |
1539 | /* slot enabling and address device helpers */ |
1540 | /* these are not thread safe so use mutex */ |
1541 | struct mutex mutex; |
1542 | /* Internal mirror of the HW's dcbaa */ |
1543 | struct xhci_virt_device *devs[MAX_HC_SLOTS]; |
1544 | /* For keeping track of bandwidth domains per roothub. */ |
1545 | struct xhci_root_port_bw_info *rh_bw; |
1546 | |
1547 | /* DMA pools */ |
1548 | struct dma_pool *device_pool; |
1549 | struct dma_pool *segment_pool; |
1550 | struct dma_pool *small_streams_pool; |
1551 | struct dma_pool *medium_streams_pool; |
1552 | |
1553 | /* Host controller watchdog timer structures */ |
1554 | unsigned int xhc_state; |
1555 | unsigned long run_graceperiod; |
1556 | struct s3_save s3; |
1557 | /* Host controller is dying - not responding to commands. "I'm not dead yet!" |
1558 | * |
1559 | * xHC interrupts have been disabled and a watchdog timer will (or has already) |
1560 | * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code |
1561 | * that sees this status (other than the timer that set it) should stop touching |
1562 | * hardware immediately. Interrupt handlers should return immediately when |
1563 | * they see this status (any time they drop and re-acquire xhci->lock). |
1564 | * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without |
1565 | * putting the TD on the canceled list, etc. |
1566 | * |
1567 | * There are no reports of xHCI host controllers that display this issue. |
1568 | */ |
1569 | #define XHCI_STATE_DYING (1 << 0) |
1570 | #define XHCI_STATE_HALTED (1 << 1) |
1571 | #define XHCI_STATE_REMOVING (1 << 2) |
1572 | unsigned long long quirks; |
1573 | #define XHCI_LINK_TRB_QUIRK BIT_ULL(0) |
1574 | #define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */ |
1575 | #define XHCI_NEC_HOST BIT_ULL(2) |
1576 | #define XHCI_AMD_PLL_FIX BIT_ULL(3) |
1577 | #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4) |
1578 | /* |
1579 | * Certain Intel host controllers have a limit to the number of endpoint |
1580 | * contexts they can handle. Ideally, they would signal that they can't handle |
1581 | * anymore endpoint contexts by returning a Resource Error for the Configure |
1582 | * Endpoint command, but they don't. Instead they expect software to keep track |
1583 | * of the number of active endpoints for them, across configure endpoint |
1584 | * commands, reset device commands, disable slot commands, and address device |
1585 | * commands. |
1586 | */ |
1587 | #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5) |
1588 | #define XHCI_BROKEN_MSI BIT_ULL(6) |
1589 | #define XHCI_RESET_ON_RESUME BIT_ULL(7) |
1590 | #define XHCI_SW_BW_CHECKING BIT_ULL(8) |
1591 | #define XHCI_AMD_0x96_HOST BIT_ULL(9) |
1592 | #define XHCI_TRUST_TX_LENGTH BIT_ULL(10) |
1593 | #define XHCI_LPM_SUPPORT BIT_ULL(11) |
1594 | #define XHCI_INTEL_HOST BIT_ULL(12) |
1595 | #define XHCI_SPURIOUS_REBOOT BIT_ULL(13) |
1596 | #define XHCI_COMP_MODE_QUIRK BIT_ULL(14) |
1597 | #define XHCI_AVOID_BEI BIT_ULL(15) |
1598 | #define XHCI_PLAT BIT_ULL(16) /* Deprecated */ |
1599 | #define XHCI_SLOW_SUSPEND BIT_ULL(17) |
1600 | #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18) |
1601 | /* For controllers with a broken beyond repair streams implementation */ |
1602 | #define XHCI_BROKEN_STREAMS BIT_ULL(19) |
1603 | #define XHCI_PME_STUCK_QUIRK BIT_ULL(20) |
1604 | #define XHCI_MTK_HOST BIT_ULL(21) |
1605 | #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22) |
1606 | #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23) |
1607 | #define XHCI_MISSING_CAS BIT_ULL(24) |
1608 | /* For controller with a broken Port Disable implementation */ |
1609 | #define XHCI_BROKEN_PORT_PED BIT_ULL(25) |
1610 | #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26) |
1611 | #define XHCI_U2_DISABLE_WAKE BIT_ULL(27) |
1612 | #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28) |
1613 | #define XHCI_HW_LPM_DISABLE BIT_ULL(29) |
1614 | #define XHCI_SUSPEND_DELAY BIT_ULL(30) |
1615 | #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31) |
1616 | #define XHCI_ZERO_64B_REGS BIT_ULL(32) |
1617 | #define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33) |
1618 | #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34) |
1619 | #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35) |
1620 | #define XHCI_RENESAS_FW_QUIRK BIT_ULL(36) |
1621 | #define XHCI_SKIP_PHY_INIT BIT_ULL(37) |
1622 | #define XHCI_DISABLE_SPARSE BIT_ULL(38) |
1623 | #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39) |
1624 | #define XHCI_NO_SOFT_RETRY BIT_ULL(40) |
1625 | #define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41) |
1626 | #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42) |
1627 | #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43) |
1628 | #define XHCI_RESET_TO_DEFAULT BIT_ULL(44) |
1629 | #define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45) |
1630 | #define XHCI_ZHAOXIN_HOST BIT_ULL(46) |
1631 | |
1632 | unsigned int num_active_eps; |
1633 | unsigned int limit_active_eps; |
1634 | struct xhci_port *hw_ports; |
1635 | struct xhci_hub usb2_rhub; |
1636 | struct xhci_hub usb3_rhub; |
1637 | /* support xHCI 1.0 spec USB2 hardware LPM */ |
1638 | unsigned hw_lpm_support:1; |
1639 | /* Broken Suspend flag for SNPS Suspend resume issue */ |
1640 | unsigned broken_suspend:1; |
1641 | /* Indicates that omitting hcd is supported if root hub has no ports */ |
1642 | unsigned allow_single_roothub:1; |
1643 | /* cached usb2 extened protocol capabilites */ |
1644 | u32 *ext_caps; |
1645 | unsigned int num_ext_caps; |
1646 | /* cached extended protocol port capabilities */ |
1647 | struct xhci_port_cap *port_caps; |
1648 | unsigned int num_port_caps; |
1649 | /* Compliance Mode Recovery Data */ |
1650 | struct timer_list comp_mode_recovery_timer; |
1651 | u32 port_status_u0; |
1652 | u16 test_mode; |
1653 | /* Compliance Mode Timer Triggered every 2 seconds */ |
1654 | #define COMP_MODE_RCVRY_MSECS 2000 |
1655 | |
1656 | struct dentry *debugfs_root; |
1657 | struct dentry *debugfs_slots; |
1658 | struct list_head regset_list; |
1659 | |
1660 | void *dbc; |
1661 | /* platform-specific data -- must come last */ |
1662 | unsigned long priv[] __aligned(sizeof(s64)); |
1663 | }; |
1664 | |
1665 | /* Platform specific overrides to generic XHCI hc_driver ops */ |
1666 | struct xhci_driver_overrides { |
1667 | size_t ; |
1668 | int (*reset)(struct usb_hcd *hcd); |
1669 | int (*start)(struct usb_hcd *hcd); |
1670 | int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, |
1671 | struct usb_host_endpoint *ep); |
1672 | int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, |
1673 | struct usb_host_endpoint *ep); |
1674 | int (*check_bandwidth)(struct usb_hcd *, struct usb_device *); |
1675 | void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *); |
1676 | int (*update_hub_device)(struct usb_hcd *hcd, struct usb_device *hdev, |
1677 | struct usb_tt *tt, gfp_t mem_flags); |
1678 | int (*hub_control)(struct usb_hcd *hcd, u16 typeReq, u16 wValue, |
1679 | u16 wIndex, char *buf, u16 wLength); |
1680 | }; |
1681 | |
1682 | #define XHCI_CFC_DELAY 10 |
1683 | |
1684 | /* convert between an HCD pointer and the corresponding EHCI_HCD */ |
1685 | static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) |
1686 | { |
1687 | struct usb_hcd *primary_hcd; |
1688 | |
1689 | if (usb_hcd_is_primary_hcd(hcd)) |
1690 | primary_hcd = hcd; |
1691 | else |
1692 | primary_hcd = hcd->primary_hcd; |
1693 | |
1694 | return (struct xhci_hcd *) (primary_hcd->hcd_priv); |
1695 | } |
1696 | |
1697 | static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) |
1698 | { |
1699 | return xhci->main_hcd; |
1700 | } |
1701 | |
1702 | static inline struct usb_hcd *xhci_get_usb3_hcd(struct xhci_hcd *xhci) |
1703 | { |
1704 | if (xhci->shared_hcd) |
1705 | return xhci->shared_hcd; |
1706 | |
1707 | if (!xhci->usb2_rhub.num_ports) |
1708 | return xhci->main_hcd; |
1709 | |
1710 | return NULL; |
1711 | } |
1712 | |
1713 | static inline bool xhci_hcd_is_usb3(struct usb_hcd *hcd) |
1714 | { |
1715 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
1716 | |
1717 | return hcd == xhci_get_usb3_hcd(xhci); |
1718 | } |
1719 | |
1720 | static inline bool xhci_has_one_roothub(struct xhci_hcd *xhci) |
1721 | { |
1722 | return xhci->allow_single_roothub && |
1723 | (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports); |
1724 | } |
1725 | |
1726 | #define xhci_dbg(xhci, fmt, args...) \ |
1727 | dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args) |
1728 | #define xhci_err(xhci, fmt, args...) \ |
1729 | dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) |
1730 | #define xhci_warn(xhci, fmt, args...) \ |
1731 | dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) |
1732 | #define xhci_warn_ratelimited(xhci, fmt, args...) \ |
1733 | dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args) |
1734 | #define xhci_info(xhci, fmt, args...) \ |
1735 | dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args) |
1736 | |
1737 | /* |
1738 | * Registers should always be accessed with double word or quad word accesses. |
1739 | * |
1740 | * Some xHCI implementations may support 64-bit address pointers. Registers |
1741 | * with 64-bit address pointers should be written to with dword accesses by |
1742 | * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. |
1743 | * xHCI implementations that do not support 64-bit address pointers will ignore |
1744 | * the high dword, and write order is irrelevant. |
1745 | */ |
1746 | static inline u64 xhci_read_64(const struct xhci_hcd *xhci, |
1747 | __le64 __iomem *regs) |
1748 | { |
1749 | return lo_hi_readq(addr: regs); |
1750 | } |
1751 | static inline void xhci_write_64(struct xhci_hcd *xhci, |
1752 | const u64 val, __le64 __iomem *regs) |
1753 | { |
1754 | lo_hi_writeq(val, addr: regs); |
1755 | } |
1756 | |
1757 | static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) |
1758 | { |
1759 | return xhci->quirks & XHCI_LINK_TRB_QUIRK; |
1760 | } |
1761 | |
1762 | /* xHCI debugging */ |
1763 | char *xhci_get_slot_state(struct xhci_hcd *xhci, |
1764 | struct xhci_container_ctx *ctx); |
1765 | void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), |
1766 | const char *fmt, ...); |
1767 | |
1768 | /* xHCI memory management */ |
1769 | void xhci_mem_cleanup(struct xhci_hcd *xhci); |
1770 | int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); |
1771 | void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); |
1772 | int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); |
1773 | int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); |
1774 | void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, |
1775 | struct usb_device *udev); |
1776 | unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); |
1777 | unsigned int xhci_last_valid_endpoint(u32 added_ctxs); |
1778 | void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); |
1779 | void xhci_update_tt_active_eps(struct xhci_hcd *xhci, |
1780 | struct xhci_virt_device *virt_dev, |
1781 | int old_active_eps); |
1782 | void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info); |
1783 | void xhci_update_bw_info(struct xhci_hcd *xhci, |
1784 | struct xhci_container_ctx *in_ctx, |
1785 | struct xhci_input_control_ctx *ctrl_ctx, |
1786 | struct xhci_virt_device *virt_dev); |
1787 | void xhci_endpoint_copy(struct xhci_hcd *xhci, |
1788 | struct xhci_container_ctx *in_ctx, |
1789 | struct xhci_container_ctx *out_ctx, |
1790 | unsigned int ep_index); |
1791 | void xhci_slot_copy(struct xhci_hcd *xhci, |
1792 | struct xhci_container_ctx *in_ctx, |
1793 | struct xhci_container_ctx *out_ctx); |
1794 | int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, |
1795 | struct usb_device *udev, struct usb_host_endpoint *ep, |
1796 | gfp_t mem_flags); |
1797 | struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, |
1798 | unsigned int num_segs, unsigned int cycle_state, |
1799 | enum xhci_ring_type type, unsigned int max_packet, gfp_t flags); |
1800 | void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); |
1801 | int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, |
1802 | unsigned int num_trbs, gfp_t flags); |
1803 | void xhci_initialize_ring_info(struct xhci_ring *ring, |
1804 | unsigned int cycle_state); |
1805 | void xhci_free_endpoint_ring(struct xhci_hcd *xhci, |
1806 | struct xhci_virt_device *virt_dev, |
1807 | unsigned int ep_index); |
1808 | struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, |
1809 | unsigned int num_stream_ctxs, |
1810 | unsigned int num_streams, |
1811 | unsigned int max_packet, gfp_t flags); |
1812 | void xhci_free_stream_info(struct xhci_hcd *xhci, |
1813 | struct xhci_stream_info *stream_info); |
1814 | void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, |
1815 | struct xhci_ep_ctx *ep_ctx, |
1816 | struct xhci_stream_info *stream_info); |
1817 | void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, |
1818 | struct xhci_virt_ep *ep); |
1819 | void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, |
1820 | struct xhci_virt_device *virt_dev, bool drop_control_ep); |
1821 | struct xhci_ring *xhci_dma_to_transfer_ring( |
1822 | struct xhci_virt_ep *ep, |
1823 | u64 address); |
1824 | struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, |
1825 | bool allocate_completion, gfp_t mem_flags); |
1826 | struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci, |
1827 | bool allocate_completion, gfp_t mem_flags); |
1828 | void xhci_urb_free_priv(struct urb_priv *urb_priv); |
1829 | void xhci_free_command(struct xhci_hcd *xhci, |
1830 | struct xhci_command *command); |
1831 | struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci, |
1832 | int type, gfp_t flags); |
1833 | void xhci_free_container_ctx(struct xhci_hcd *xhci, |
1834 | struct xhci_container_ctx *ctx); |
1835 | struct xhci_interrupter * |
1836 | xhci_create_secondary_interrupter(struct usb_hcd *hcd, int num_seg); |
1837 | void xhci_remove_secondary_interrupter(struct usb_hcd |
1838 | *hcd, struct xhci_interrupter *ir); |
1839 | |
1840 | /* xHCI host controller glue */ |
1841 | typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); |
1842 | int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us); |
1843 | int xhci_handshake_check_state(struct xhci_hcd *xhci, void __iomem *ptr, |
1844 | u32 mask, u32 done, int usec, unsigned int exit_state); |
1845 | void xhci_quiesce(struct xhci_hcd *xhci); |
1846 | int xhci_halt(struct xhci_hcd *xhci); |
1847 | int xhci_start(struct xhci_hcd *xhci); |
1848 | int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us); |
1849 | int xhci_run(struct usb_hcd *hcd); |
1850 | int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); |
1851 | void xhci_shutdown(struct usb_hcd *hcd); |
1852 | void xhci_stop(struct usb_hcd *hcd); |
1853 | void xhci_init_driver(struct hc_driver *drv, |
1854 | const struct xhci_driver_overrides *over); |
1855 | int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, |
1856 | struct usb_host_endpoint *ep); |
1857 | int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, |
1858 | struct usb_host_endpoint *ep); |
1859 | int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); |
1860 | void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); |
1861 | int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, |
1862 | struct usb_tt *tt, gfp_t mem_flags); |
1863 | int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id); |
1864 | int xhci_ext_cap_init(struct xhci_hcd *xhci); |
1865 | |
1866 | int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup); |
1867 | int xhci_resume(struct xhci_hcd *xhci, pm_message_t msg); |
1868 | |
1869 | irqreturn_t xhci_irq(struct usb_hcd *hcd); |
1870 | irqreturn_t xhci_msi_irq(int irq, void *hcd); |
1871 | int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); |
1872 | int xhci_alloc_tt_info(struct xhci_hcd *xhci, |
1873 | struct xhci_virt_device *virt_dev, |
1874 | struct usb_device *hdev, |
1875 | struct usb_tt *tt, gfp_t mem_flags); |
1876 | |
1877 | /* xHCI ring, segment, TRB, and TD functions */ |
1878 | dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); |
1879 | struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, |
1880 | struct xhci_segment *start_seg, union xhci_trb *start_trb, |
1881 | union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug); |
1882 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); |
1883 | void xhci_ring_cmd_db(struct xhci_hcd *xhci); |
1884 | int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, |
1885 | u32 trb_type, u32 slot_id); |
1886 | int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
1887 | dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev); |
1888 | int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
1889 | u32 field1, u32 field2, u32 field3, u32 field4); |
1890 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, |
1891 | int slot_id, unsigned int ep_index, int suspend); |
1892 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, |
1893 | int slot_id, unsigned int ep_index); |
1894 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, |
1895 | int slot_id, unsigned int ep_index); |
1896 | int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, |
1897 | int slot_id, unsigned int ep_index); |
1898 | int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, |
1899 | struct urb *urb, int slot_id, unsigned int ep_index); |
1900 | int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, |
1901 | struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id, |
1902 | bool command_must_succeed); |
1903 | int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, |
1904 | dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed); |
1905 | int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, |
1906 | int slot_id, unsigned int ep_index, |
1907 | enum xhci_ep_reset_type reset_type); |
1908 | int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
1909 | u32 slot_id); |
1910 | void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id, |
1911 | unsigned int ep_index, unsigned int stream_id, |
1912 | struct xhci_td *td); |
1913 | void xhci_stop_endpoint_command_watchdog(struct timer_list *t); |
1914 | void xhci_handle_command_timeout(struct work_struct *work); |
1915 | |
1916 | void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, |
1917 | unsigned int ep_index, unsigned int stream_id); |
1918 | void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci, |
1919 | unsigned int slot_id, |
1920 | unsigned int ep_index); |
1921 | void xhci_cleanup_command_queue(struct xhci_hcd *xhci); |
1922 | void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring); |
1923 | unsigned int count_trbs(u64 addr, u64 len); |
1924 | |
1925 | /* xHCI roothub code */ |
1926 | void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port, |
1927 | u32 link_state); |
1928 | void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port, |
1929 | u32 port_bit); |
1930 | int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, |
1931 | char *buf, u16 wLength); |
1932 | int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); |
1933 | int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1); |
1934 | struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd); |
1935 | |
1936 | void xhci_hc_died(struct xhci_hcd *xhci); |
1937 | |
1938 | #ifdef CONFIG_PM |
1939 | int xhci_bus_suspend(struct usb_hcd *hcd); |
1940 | int xhci_bus_resume(struct usb_hcd *hcd); |
1941 | unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd); |
1942 | #else |
1943 | #define xhci_bus_suspend NULL |
1944 | #define xhci_bus_resume NULL |
1945 | #define xhci_get_resuming_ports NULL |
1946 | #endif /* CONFIG_PM */ |
1947 | |
1948 | u32 xhci_port_state_to_neutral(u32 state); |
1949 | void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); |
1950 | |
1951 | /* xHCI contexts */ |
1952 | struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); |
1953 | struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); |
1954 | struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); |
1955 | |
1956 | struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, |
1957 | unsigned int slot_id, unsigned int ep_index, |
1958 | unsigned int stream_id); |
1959 | |
1960 | static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, |
1961 | struct urb *urb) |
1962 | { |
1963 | return xhci_triad_to_transfer_ring(xhci, slot_id: urb->dev->slot_id, |
1964 | ep_index: xhci_get_endpoint_index(desc: &urb->ep->desc), |
1965 | stream_id: urb->stream_id); |
1966 | } |
1967 | |
1968 | /* |
1969 | * TODO: As per spec Isochronous IDT transmissions are supported. We bypass |
1970 | * them anyways as we where unable to find a device that matches the |
1971 | * constraints. |
1972 | */ |
1973 | static inline bool xhci_urb_suitable_for_idt(struct urb *urb) |
1974 | { |
1975 | if (!usb_endpoint_xfer_isoc(epd: &urb->ep->desc) && usb_urb_dir_out(urb) && |
1976 | usb_endpoint_maxp(epd: &urb->ep->desc) >= TRB_IDT_MAX_SIZE && |
1977 | urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE && |
1978 | !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) && |
1979 | !urb->num_sgs) |
1980 | return true; |
1981 | |
1982 | return false; |
1983 | } |
1984 | |
1985 | static inline char *xhci_slot_state_string(u32 state) |
1986 | { |
1987 | switch (state) { |
1988 | case SLOT_STATE_ENABLED: |
1989 | return "enabled/disabled" ; |
1990 | case SLOT_STATE_DEFAULT: |
1991 | return "default" ; |
1992 | case SLOT_STATE_ADDRESSED: |
1993 | return "addressed" ; |
1994 | case SLOT_STATE_CONFIGURED: |
1995 | return "configured" ; |
1996 | default: |
1997 | return "reserved" ; |
1998 | } |
1999 | } |
2000 | |
2001 | static inline const char *xhci_decode_trb(char *str, size_t size, |
2002 | u32 field0, u32 field1, u32 field2, u32 field3) |
2003 | { |
2004 | int type = TRB_FIELD_TO_TYPE(field3); |
2005 | |
2006 | switch (type) { |
2007 | case TRB_LINK: |
2008 | snprintf(buf: str, size, |
2009 | fmt: "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c" , |
2010 | field1, field0, GET_INTR_TARGET(field2), |
2011 | xhci_trb_type_string(type), |
2012 | field3 & TRB_IOC ? 'I' : 'i', |
2013 | field3 & TRB_CHAIN ? 'C' : 'c', |
2014 | field3 & TRB_TC ? 'T' : 't', |
2015 | field3 & TRB_CYCLE ? 'C' : 'c'); |
2016 | break; |
2017 | case TRB_TRANSFER: |
2018 | case TRB_COMPLETION: |
2019 | case TRB_PORT_STATUS: |
2020 | case TRB_BANDWIDTH_EVENT: |
2021 | case TRB_DOORBELL: |
2022 | case TRB_HC_EVENT: |
2023 | case TRB_DEV_NOTE: |
2024 | case TRB_MFINDEX_WRAP: |
2025 | snprintf(buf: str, size, |
2026 | fmt: "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c" , |
2027 | field1, field0, |
2028 | xhci_trb_comp_code_string(GET_COMP_CODE(field2)), |
2029 | EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3), |
2030 | /* Macro decrements 1, maybe it shouldn't?!? */ |
2031 | TRB_TO_EP_INDEX(field3) + 1, |
2032 | xhci_trb_type_string(type), |
2033 | field3 & EVENT_DATA ? 'E' : 'e', |
2034 | field3 & TRB_CYCLE ? 'C' : 'c'); |
2035 | |
2036 | break; |
2037 | case TRB_SETUP: |
2038 | snprintf(buf: str, size, |
2039 | fmt: "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c" , |
2040 | field0 & 0xff, |
2041 | (field0 & 0xff00) >> 8, |
2042 | (field0 & 0xff000000) >> 24, |
2043 | (field0 & 0xff0000) >> 16, |
2044 | (field1 & 0xff00) >> 8, |
2045 | field1 & 0xff, |
2046 | (field1 & 0xff000000) >> 16 | |
2047 | (field1 & 0xff0000) >> 16, |
2048 | TRB_LEN(field2), GET_TD_SIZE(field2), |
2049 | GET_INTR_TARGET(field2), |
2050 | xhci_trb_type_string(type), |
2051 | field3 & TRB_IDT ? 'I' : 'i', |
2052 | field3 & TRB_IOC ? 'I' : 'i', |
2053 | field3 & TRB_CYCLE ? 'C' : 'c'); |
2054 | break; |
2055 | case TRB_DATA: |
2056 | snprintf(buf: str, size, |
2057 | fmt: "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c" , |
2058 | field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), |
2059 | GET_INTR_TARGET(field2), |
2060 | xhci_trb_type_string(type), |
2061 | field3 & TRB_IDT ? 'I' : 'i', |
2062 | field3 & TRB_IOC ? 'I' : 'i', |
2063 | field3 & TRB_CHAIN ? 'C' : 'c', |
2064 | field3 & TRB_NO_SNOOP ? 'S' : 's', |
2065 | field3 & TRB_ISP ? 'I' : 'i', |
2066 | field3 & TRB_ENT ? 'E' : 'e', |
2067 | field3 & TRB_CYCLE ? 'C' : 'c'); |
2068 | break; |
2069 | case TRB_STATUS: |
2070 | snprintf(buf: str, size, |
2071 | fmt: "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c" , |
2072 | field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), |
2073 | GET_INTR_TARGET(field2), |
2074 | xhci_trb_type_string(type), |
2075 | field3 & TRB_IOC ? 'I' : 'i', |
2076 | field3 & TRB_CHAIN ? 'C' : 'c', |
2077 | field3 & TRB_ENT ? 'E' : 'e', |
2078 | field3 & TRB_CYCLE ? 'C' : 'c'); |
2079 | break; |
2080 | case TRB_NORMAL: |
2081 | case TRB_ISOC: |
2082 | case TRB_EVENT_DATA: |
2083 | case TRB_TR_NOOP: |
2084 | snprintf(buf: str, size, |
2085 | fmt: "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c" , |
2086 | field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), |
2087 | GET_INTR_TARGET(field2), |
2088 | xhci_trb_type_string(type), |
2089 | field3 & TRB_BEI ? 'B' : 'b', |
2090 | field3 & TRB_IDT ? 'I' : 'i', |
2091 | field3 & TRB_IOC ? 'I' : 'i', |
2092 | field3 & TRB_CHAIN ? 'C' : 'c', |
2093 | field3 & TRB_NO_SNOOP ? 'S' : 's', |
2094 | field3 & TRB_ISP ? 'I' : 'i', |
2095 | field3 & TRB_ENT ? 'E' : 'e', |
2096 | field3 & TRB_CYCLE ? 'C' : 'c'); |
2097 | break; |
2098 | |
2099 | case TRB_CMD_NOOP: |
2100 | case TRB_ENABLE_SLOT: |
2101 | snprintf(buf: str, size, |
2102 | fmt: "%s: flags %c" , |
2103 | xhci_trb_type_string(type), |
2104 | field3 & TRB_CYCLE ? 'C' : 'c'); |
2105 | break; |
2106 | case TRB_DISABLE_SLOT: |
2107 | case TRB_NEG_BANDWIDTH: |
2108 | snprintf(buf: str, size, |
2109 | fmt: "%s: slot %d flags %c" , |
2110 | xhci_trb_type_string(type), |
2111 | TRB_TO_SLOT_ID(field3), |
2112 | field3 & TRB_CYCLE ? 'C' : 'c'); |
2113 | break; |
2114 | case TRB_ADDR_DEV: |
2115 | snprintf(buf: str, size, |
2116 | fmt: "%s: ctx %08x%08x slot %d flags %c:%c" , |
2117 | xhci_trb_type_string(type), |
2118 | field1, field0, |
2119 | TRB_TO_SLOT_ID(field3), |
2120 | field3 & TRB_BSR ? 'B' : 'b', |
2121 | field3 & TRB_CYCLE ? 'C' : 'c'); |
2122 | break; |
2123 | case TRB_CONFIG_EP: |
2124 | snprintf(buf: str, size, |
2125 | fmt: "%s: ctx %08x%08x slot %d flags %c:%c" , |
2126 | xhci_trb_type_string(type), |
2127 | field1, field0, |
2128 | TRB_TO_SLOT_ID(field3), |
2129 | field3 & TRB_DC ? 'D' : 'd', |
2130 | field3 & TRB_CYCLE ? 'C' : 'c'); |
2131 | break; |
2132 | case TRB_EVAL_CONTEXT: |
2133 | snprintf(buf: str, size, |
2134 | fmt: "%s: ctx %08x%08x slot %d flags %c" , |
2135 | xhci_trb_type_string(type), |
2136 | field1, field0, |
2137 | TRB_TO_SLOT_ID(field3), |
2138 | field3 & TRB_CYCLE ? 'C' : 'c'); |
2139 | break; |
2140 | case TRB_RESET_EP: |
2141 | snprintf(buf: str, size, |
2142 | fmt: "%s: ctx %08x%08x slot %d ep %d flags %c:%c" , |
2143 | xhci_trb_type_string(type), |
2144 | field1, field0, |
2145 | TRB_TO_SLOT_ID(field3), |
2146 | /* Macro decrements 1, maybe it shouldn't?!? */ |
2147 | TRB_TO_EP_INDEX(field3) + 1, |
2148 | field3 & TRB_TSP ? 'T' : 't', |
2149 | field3 & TRB_CYCLE ? 'C' : 'c'); |
2150 | break; |
2151 | case TRB_STOP_RING: |
2152 | snprintf(buf: str, size, |
2153 | fmt: "%s: slot %d sp %d ep %d flags %c" , |
2154 | xhci_trb_type_string(type), |
2155 | TRB_TO_SLOT_ID(field3), |
2156 | TRB_TO_SUSPEND_PORT(field3), |
2157 | /* Macro decrements 1, maybe it shouldn't?!? */ |
2158 | TRB_TO_EP_INDEX(field3) + 1, |
2159 | field3 & TRB_CYCLE ? 'C' : 'c'); |
2160 | break; |
2161 | case TRB_SET_DEQ: |
2162 | snprintf(buf: str, size, |
2163 | fmt: "%s: deq %08x%08x stream %d slot %d ep %d flags %c" , |
2164 | xhci_trb_type_string(type), |
2165 | field1, field0, |
2166 | TRB_TO_STREAM_ID(field2), |
2167 | TRB_TO_SLOT_ID(field3), |
2168 | /* Macro decrements 1, maybe it shouldn't?!? */ |
2169 | TRB_TO_EP_INDEX(field3) + 1, |
2170 | field3 & TRB_CYCLE ? 'C' : 'c'); |
2171 | break; |
2172 | case TRB_RESET_DEV: |
2173 | snprintf(buf: str, size, |
2174 | fmt: "%s: slot %d flags %c" , |
2175 | xhci_trb_type_string(type), |
2176 | TRB_TO_SLOT_ID(field3), |
2177 | field3 & TRB_CYCLE ? 'C' : 'c'); |
2178 | break; |
2179 | case TRB_FORCE_EVENT: |
2180 | snprintf(buf: str, size, |
2181 | fmt: "%s: event %08x%08x vf intr %d vf id %d flags %c" , |
2182 | xhci_trb_type_string(type), |
2183 | field1, field0, |
2184 | TRB_TO_VF_INTR_TARGET(field2), |
2185 | TRB_TO_VF_ID(field3), |
2186 | field3 & TRB_CYCLE ? 'C' : 'c'); |
2187 | break; |
2188 | case TRB_SET_LT: |
2189 | snprintf(buf: str, size, |
2190 | fmt: "%s: belt %d flags %c" , |
2191 | xhci_trb_type_string(type), |
2192 | TRB_TO_BELT(field3), |
2193 | field3 & TRB_CYCLE ? 'C' : 'c'); |
2194 | break; |
2195 | case TRB_GET_BW: |
2196 | snprintf(buf: str, size, |
2197 | fmt: "%s: ctx %08x%08x slot %d speed %d flags %c" , |
2198 | xhci_trb_type_string(type), |
2199 | field1, field0, |
2200 | TRB_TO_SLOT_ID(field3), |
2201 | TRB_TO_DEV_SPEED(field3), |
2202 | field3 & TRB_CYCLE ? 'C' : 'c'); |
2203 | break; |
2204 | case TRB_FORCE_HEADER: |
2205 | snprintf(buf: str, size, |
2206 | fmt: "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c" , |
2207 | xhci_trb_type_string(type), |
2208 | field2, field1, field0 & 0xffffffe0, |
2209 | TRB_TO_PACKET_TYPE(field0), |
2210 | TRB_TO_ROOTHUB_PORT(field3), |
2211 | field3 & TRB_CYCLE ? 'C' : 'c'); |
2212 | break; |
2213 | default: |
2214 | snprintf(buf: str, size, |
2215 | fmt: "type '%s' -> raw %08x %08x %08x %08x" , |
2216 | xhci_trb_type_string(type), |
2217 | field0, field1, field2, field3); |
2218 | } |
2219 | |
2220 | return str; |
2221 | } |
2222 | |
2223 | static inline const char *xhci_decode_ctrl_ctx(char *str, |
2224 | unsigned long drop, unsigned long add) |
2225 | { |
2226 | unsigned int bit; |
2227 | int ret = 0; |
2228 | |
2229 | str[0] = '\0'; |
2230 | |
2231 | if (drop) { |
2232 | ret = sprintf(buf: str, fmt: "Drop:" ); |
2233 | for_each_set_bit(bit, &drop, 32) |
2234 | ret += sprintf(buf: str + ret, fmt: " %d%s" , |
2235 | bit / 2, |
2236 | bit % 2 ? "in" :"out" ); |
2237 | ret += sprintf(buf: str + ret, fmt: ", " ); |
2238 | } |
2239 | |
2240 | if (add) { |
2241 | ret += sprintf(buf: str + ret, fmt: "Add:%s%s" , |
2242 | (add & SLOT_FLAG) ? " slot" :"" , |
2243 | (add & EP0_FLAG) ? " ep0" :"" ); |
2244 | add &= ~(SLOT_FLAG | EP0_FLAG); |
2245 | for_each_set_bit(bit, &add, 32) |
2246 | ret += sprintf(buf: str + ret, fmt: " %d%s" , |
2247 | bit / 2, |
2248 | bit % 2 ? "in" :"out" ); |
2249 | } |
2250 | return str; |
2251 | } |
2252 | |
2253 | static inline const char *xhci_decode_slot_context(char *str, |
2254 | u32 info, u32 info2, u32 tt_info, u32 state) |
2255 | { |
2256 | u32 speed; |
2257 | u32 hub; |
2258 | u32 mtt; |
2259 | int ret = 0; |
2260 | |
2261 | speed = info & DEV_SPEED; |
2262 | hub = info & DEV_HUB; |
2263 | mtt = info & DEV_MTT; |
2264 | |
2265 | ret = sprintf(buf: str, fmt: "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d" , |
2266 | info & ROUTE_STRING_MASK, |
2267 | ({ char *s; |
2268 | switch (speed) { |
2269 | case SLOT_SPEED_FS: |
2270 | s = "full-speed" ; |
2271 | break; |
2272 | case SLOT_SPEED_LS: |
2273 | s = "low-speed" ; |
2274 | break; |
2275 | case SLOT_SPEED_HS: |
2276 | s = "high-speed" ; |
2277 | break; |
2278 | case SLOT_SPEED_SS: |
2279 | s = "super-speed" ; |
2280 | break; |
2281 | case SLOT_SPEED_SSP: |
2282 | s = "super-speed plus" ; |
2283 | break; |
2284 | default: |
2285 | s = "UNKNOWN speed" ; |
2286 | } s; }), |
2287 | mtt ? " multi-TT" : "" , |
2288 | hub ? " Hub" : "" , |
2289 | (info & LAST_CTX_MASK) >> 27, |
2290 | info2 & MAX_EXIT, |
2291 | DEVINFO_TO_ROOT_HUB_PORT(info2), |
2292 | DEVINFO_TO_MAX_PORTS(info2)); |
2293 | |
2294 | ret += sprintf(buf: str + ret, fmt: " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s" , |
2295 | tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8, |
2296 | GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info), |
2297 | state & DEV_ADDR_MASK, |
2298 | xhci_slot_state_string(GET_SLOT_STATE(state))); |
2299 | |
2300 | return str; |
2301 | } |
2302 | |
2303 | |
2304 | static inline const char *xhci_portsc_link_state_string(u32 portsc) |
2305 | { |
2306 | switch (portsc & PORT_PLS_MASK) { |
2307 | case XDEV_U0: |
2308 | return "U0" ; |
2309 | case XDEV_U1: |
2310 | return "U1" ; |
2311 | case XDEV_U2: |
2312 | return "U2" ; |
2313 | case XDEV_U3: |
2314 | return "U3" ; |
2315 | case XDEV_DISABLED: |
2316 | return "Disabled" ; |
2317 | case XDEV_RXDETECT: |
2318 | return "RxDetect" ; |
2319 | case XDEV_INACTIVE: |
2320 | return "Inactive" ; |
2321 | case XDEV_POLLING: |
2322 | return "Polling" ; |
2323 | case XDEV_RECOVERY: |
2324 | return "Recovery" ; |
2325 | case XDEV_HOT_RESET: |
2326 | return "Hot Reset" ; |
2327 | case XDEV_COMP_MODE: |
2328 | return "Compliance mode" ; |
2329 | case XDEV_TEST_MODE: |
2330 | return "Test mode" ; |
2331 | case XDEV_RESUME: |
2332 | return "Resume" ; |
2333 | default: |
2334 | break; |
2335 | } |
2336 | return "Unknown" ; |
2337 | } |
2338 | |
2339 | static inline const char *xhci_decode_portsc(char *str, u32 portsc) |
2340 | { |
2341 | int ret; |
2342 | |
2343 | ret = sprintf(buf: str, fmt: "%s %s %s Link:%s PortSpeed:%d " , |
2344 | portsc & PORT_POWER ? "Powered" : "Powered-off" , |
2345 | portsc & PORT_CONNECT ? "Connected" : "Not-connected" , |
2346 | portsc & PORT_PE ? "Enabled" : "Disabled" , |
2347 | xhci_portsc_link_state_string(portsc), |
2348 | DEV_PORT_SPEED(portsc)); |
2349 | |
2350 | if (portsc & PORT_OC) |
2351 | ret += sprintf(buf: str + ret, fmt: "OverCurrent " ); |
2352 | if (portsc & PORT_RESET) |
2353 | ret += sprintf(buf: str + ret, fmt: "In-Reset " ); |
2354 | |
2355 | ret += sprintf(buf: str + ret, fmt: "Change: " ); |
2356 | if (portsc & PORT_CSC) |
2357 | ret += sprintf(buf: str + ret, fmt: "CSC " ); |
2358 | if (portsc & PORT_PEC) |
2359 | ret += sprintf(buf: str + ret, fmt: "PEC " ); |
2360 | if (portsc & PORT_WRC) |
2361 | ret += sprintf(buf: str + ret, fmt: "WRC " ); |
2362 | if (portsc & PORT_OCC) |
2363 | ret += sprintf(buf: str + ret, fmt: "OCC " ); |
2364 | if (portsc & PORT_RC) |
2365 | ret += sprintf(buf: str + ret, fmt: "PRC " ); |
2366 | if (portsc & PORT_PLC) |
2367 | ret += sprintf(buf: str + ret, fmt: "PLC " ); |
2368 | if (portsc & PORT_CEC) |
2369 | ret += sprintf(buf: str + ret, fmt: "CEC " ); |
2370 | if (portsc & PORT_CAS) |
2371 | ret += sprintf(buf: str + ret, fmt: "CAS " ); |
2372 | |
2373 | ret += sprintf(buf: str + ret, fmt: "Wake: " ); |
2374 | if (portsc & PORT_WKCONN_E) |
2375 | ret += sprintf(buf: str + ret, fmt: "WCE " ); |
2376 | if (portsc & PORT_WKDISC_E) |
2377 | ret += sprintf(buf: str + ret, fmt: "WDE " ); |
2378 | if (portsc & PORT_WKOC_E) |
2379 | ret += sprintf(buf: str + ret, fmt: "WOE " ); |
2380 | |
2381 | return str; |
2382 | } |
2383 | |
2384 | static inline const char *xhci_decode_usbsts(char *str, u32 usbsts) |
2385 | { |
2386 | int ret = 0; |
2387 | |
2388 | ret = sprintf(buf: str, fmt: " 0x%08x" , usbsts); |
2389 | |
2390 | if (usbsts == ~(u32)0) |
2391 | return str; |
2392 | |
2393 | if (usbsts & STS_HALT) |
2394 | ret += sprintf(buf: str + ret, fmt: " HCHalted" ); |
2395 | if (usbsts & STS_FATAL) |
2396 | ret += sprintf(buf: str + ret, fmt: " HSE" ); |
2397 | if (usbsts & STS_EINT) |
2398 | ret += sprintf(buf: str + ret, fmt: " EINT" ); |
2399 | if (usbsts & STS_PORT) |
2400 | ret += sprintf(buf: str + ret, fmt: " PCD" ); |
2401 | if (usbsts & STS_SAVE) |
2402 | ret += sprintf(buf: str + ret, fmt: " SSS" ); |
2403 | if (usbsts & STS_RESTORE) |
2404 | ret += sprintf(buf: str + ret, fmt: " RSS" ); |
2405 | if (usbsts & STS_SRE) |
2406 | ret += sprintf(buf: str + ret, fmt: " SRE" ); |
2407 | if (usbsts & STS_CNR) |
2408 | ret += sprintf(buf: str + ret, fmt: " CNR" ); |
2409 | if (usbsts & STS_HCE) |
2410 | ret += sprintf(buf: str + ret, fmt: " HCE" ); |
2411 | |
2412 | return str; |
2413 | } |
2414 | |
2415 | static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell) |
2416 | { |
2417 | u8 ep; |
2418 | u16 stream; |
2419 | int ret; |
2420 | |
2421 | ep = (doorbell & 0xff); |
2422 | stream = doorbell >> 16; |
2423 | |
2424 | if (slot == 0) { |
2425 | sprintf(buf: str, fmt: "Command Ring %d" , doorbell); |
2426 | return str; |
2427 | } |
2428 | ret = sprintf(buf: str, fmt: "Slot %d " , slot); |
2429 | if (ep > 0 && ep < 32) |
2430 | ret = sprintf(buf: str + ret, fmt: "ep%d%s" , |
2431 | ep / 2, |
2432 | ep % 2 ? "in" : "out" ); |
2433 | else if (ep == 0 || ep < 248) |
2434 | ret = sprintf(buf: str + ret, fmt: "Reserved %d" , ep); |
2435 | else |
2436 | ret = sprintf(buf: str + ret, fmt: "Vendor Defined %d" , ep); |
2437 | if (stream) |
2438 | ret = sprintf(buf: str + ret, fmt: " Stream %d" , stream); |
2439 | |
2440 | return str; |
2441 | } |
2442 | |
2443 | static inline const char *xhci_ep_state_string(u8 state) |
2444 | { |
2445 | switch (state) { |
2446 | case EP_STATE_DISABLED: |
2447 | return "disabled" ; |
2448 | case EP_STATE_RUNNING: |
2449 | return "running" ; |
2450 | case EP_STATE_HALTED: |
2451 | return "halted" ; |
2452 | case EP_STATE_STOPPED: |
2453 | return "stopped" ; |
2454 | case EP_STATE_ERROR: |
2455 | return "error" ; |
2456 | default: |
2457 | return "INVALID" ; |
2458 | } |
2459 | } |
2460 | |
2461 | static inline const char *xhci_ep_type_string(u8 type) |
2462 | { |
2463 | switch (type) { |
2464 | case ISOC_OUT_EP: |
2465 | return "Isoc OUT" ; |
2466 | case BULK_OUT_EP: |
2467 | return "Bulk OUT" ; |
2468 | case INT_OUT_EP: |
2469 | return "Int OUT" ; |
2470 | case CTRL_EP: |
2471 | return "Ctrl" ; |
2472 | case ISOC_IN_EP: |
2473 | return "Isoc IN" ; |
2474 | case BULK_IN_EP: |
2475 | return "Bulk IN" ; |
2476 | case INT_IN_EP: |
2477 | return "Int IN" ; |
2478 | default: |
2479 | return "INVALID" ; |
2480 | } |
2481 | } |
2482 | |
2483 | static inline const char *xhci_decode_ep_context(char *str, u32 info, |
2484 | u32 info2, u64 deq, u32 tx_info) |
2485 | { |
2486 | int ret; |
2487 | |
2488 | u32 esit; |
2489 | u16 maxp; |
2490 | u16 avg; |
2491 | |
2492 | u8 max_pstr; |
2493 | u8 ep_state; |
2494 | u8 interval; |
2495 | u8 ep_type; |
2496 | u8 burst; |
2497 | u8 cerr; |
2498 | u8 mult; |
2499 | |
2500 | bool lsa; |
2501 | bool hid; |
2502 | |
2503 | esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 | |
2504 | CTX_TO_MAX_ESIT_PAYLOAD(tx_info); |
2505 | |
2506 | ep_state = info & EP_STATE_MASK; |
2507 | max_pstr = CTX_TO_EP_MAXPSTREAMS(info); |
2508 | interval = CTX_TO_EP_INTERVAL(info); |
2509 | mult = CTX_TO_EP_MULT(info) + 1; |
2510 | lsa = !!(info & EP_HAS_LSA); |
2511 | |
2512 | cerr = (info2 & (3 << 1)) >> 1; |
2513 | ep_type = CTX_TO_EP_TYPE(info2); |
2514 | hid = !!(info2 & (1 << 7)); |
2515 | burst = CTX_TO_MAX_BURST(info2); |
2516 | maxp = MAX_PACKET_DECODED(info2); |
2517 | |
2518 | avg = EP_AVG_TRB_LENGTH(tx_info); |
2519 | |
2520 | ret = sprintf(buf: str, fmt: "State %s mult %d max P. Streams %d %s" , |
2521 | xhci_ep_state_string(state: ep_state), mult, |
2522 | max_pstr, lsa ? "LSA " : "" ); |
2523 | |
2524 | ret += sprintf(buf: str + ret, fmt: "interval %d us max ESIT payload %d CErr %d " , |
2525 | (1 << interval) * 125, esit, cerr); |
2526 | |
2527 | ret += sprintf(buf: str + ret, fmt: "Type %s %sburst %d maxp %d deq %016llx " , |
2528 | xhci_ep_type_string(type: ep_type), hid ? "HID" : "" , |
2529 | burst, maxp, deq); |
2530 | |
2531 | ret += sprintf(buf: str + ret, fmt: "avg trb len %d" , avg); |
2532 | |
2533 | return str; |
2534 | } |
2535 | |
2536 | #endif /* __LINUX_XHCI_HCD_H */ |
2537 | |